From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Thu, 23 Jan 2020 16:10:22 -0800 Subject: Merge FPGA repository back into UHD repository MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams Co-authored-by: Andrej Rode Co-authored-by: Ashish Chaudhari Co-authored-by: Ben Hilburn Co-authored-by: Ciro Nishiguchi Co-authored-by: Daniel Jepson Co-authored-by: Derek Kozel Co-authored-by: EJ Kreinar Co-authored-by: Humberto Jimenez Co-authored-by: Ian Buckley Co-authored-by: Jörg Hofrichter Co-authored-by: Jon Kiser Co-authored-by: Josh Blum Co-authored-by: Jonathon Pendlum Co-authored-by: Martin Braun Co-authored-by: Matt Ettus Co-authored-by: Michael West Co-authored-by: Moritz Fischer Co-authored-by: Nick Foster Co-authored-by: Nicolas Cuervo Co-authored-by: Paul Butler Co-authored-by: Paul David Co-authored-by: Ryan Marlow Co-authored-by: Sugandha Gupta Co-authored-by: Sylvain Munaut Co-authored-by: Trung Tran Co-authored-by: Vidush Vishwanath Co-authored-by: Wade Fife --- fpga/usrp3/top/n3xx/.gitignore | 8 + fpga/usrp3/top/n3xx/Makefile | 191 + fpga/usrp3/top/n3xx/Makefile.n3xx.inc | 161 + fpga/usrp3/top/n3xx/WrapBufg.vhd | 172 + fpga/usrp3/top/n3xx/build_n3xx.tcl | 39 + fpga/usrp3/top/n3xx/coregen_dsp/.gitignore | 4 + fpga/usrp3/top/n3xx/coregen_dsp/.lso | 1 + fpga/usrp3/top/n3xx/coregen_dsp/Makefile.srcs | 17 + fpga/usrp3/top/n3xx/coregen_dsp/hbdec1.ngc | 3 + fpga/usrp3/top/n3xx/coregen_dsp/hbdec1.v | 39998 +++++++++++++++++++ fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.ngc | 3 + fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.v | 24109 +++++++++++ fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.ngc | 3 + fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.v | 20014 ++++++++++ fpga/usrp3/top/n3xx/dboards/common/Makefile.srcs | 18 + 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National Instruments Company +# Copyright 2019 Ettus Research, a National Instruments Brand +# + +# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target +##------------------- +##USRP N3XX FPGA Help +##------------------- +##Usage: +## make +## +##Output: +## build/usrp__fpga_.bit: Configuration bitstream with header +## build/usrp__fpga_.dts: Device tree source file +## build/usrp__fpga_.rpt: Build report (includes utilization and timing summary) + +# Debug Options +# Uncomment this line or add to make arg to omit radio_clk (sourced from db) and use bus_clk as radio_clk +# OPTIONS += NO_DB=1 +# Uncomment this line to add two example Aurora loopback lanes on the general NPIO bus. +# OPTIONS += NPIO_LANES=2 +# Uncomment this line to add four example Aurora loopback lanes on the QSFP NPIO bus. +# OPTIONS += QSFP_LANES=4 + +# Additional definitions specific to the various targets: +WX_DEFS=SFP0_WR=1 SFP1_10GBE=1 USE_REPLAY=1 BUILD_WR=1 BUILD_10G=1 $(OPTIONS) +HG_DEFS=SFP0_1GBE=1 SFP1_10GBE=1 USE_REPLAY=1 BUILD_1G=1 BUILD_10G=1 $(OPTIONS) +XG_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 USE_REPLAY=1 BUILD_10G=1 $(OPTIONS) +HA_DEFS=SFP0_1GBE=1 SFP1_AURORA=1 USE_REPLAY=1 BUILD_1G=1 BUILD_AURORA=1 $(OPTIONS) +XA_DEFS=SFP0_10GBE=1 SFP1_AURORA=1 USE_REPLAY=1 BUILD_10G=1 BUILD_AURORA=1 $(OPTIONS) +AA_DEFS=SFP0_AURORA=1 SFP1_AURORA=1 BUILD_AURORA=1 $(OPTIONS) +XQ_DEFS=SFP0_WR=1 QSFP_10GBE=1 USE_REPLAY=1 BUILD_WR=1 BUILD_10G=1 QSFP_LANES=2 $(OPTIONS) +AQ_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 QSFP_AURORA=1 USE_REPLAY=1 BUILD_10G=1 BUILD_AURORA=1 QSFP_LANES=4 $(OPTIONS) + +# Defaults specific to the various targets: +N300_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n300_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath n300_static_router.hex) +N310_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n310_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath n310_static_router.hex) +N320_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n320_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath n320_static_router.hex) +N300AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n300_bist_image_core.v DEFAULT_EDGE_FILE=$(abspath n300_bist_static_router.hex) +N310AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n310_bist_image_core.v DEFAULT_EDGE_FILE=$(abspath n310_bist_static_router.hex) + +# Set build option (check RTL, run synthesis, or do a full build) +ifndef TARGET + ifdef CHECK + TARGET = rtl + else ifdef SYNTH + TARGET = synth + else + TARGET = bin + endif +endif +TOP ?= n3xx + +# vivado_build($1=Device, $2=Definitions, $3=Defaults) +# Device: N300, N310, or N320 +# Definitions: See above (*_DEFS) +# Defaults: See above (*_DEFAULTS) +vivado_build = make -f Makefile.n3xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3 + +# post_build($1=Device, $2=Option) +ifeq ($(TARGET),bin) + post_build = @\ + mkdir -p build; \ + echo "Exporting bitstream file..."; \ + cp build-$(1)_$(2)/n3xx.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \ + echo "Exporting build report..."; \ + cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \ + echo "Build DONE ... $(1)_$(2)"; +else + post_build = @echo "Skipping bitfile export." +endif + +## +##Supported Targets +##----------------- + +all: N300_HG N300_XG N310_HG N310_XG N320_HG N320_XG ##(Default target) + +##N310_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1. +N310_WX: build/usrp_n310_fpga_WX.dts + $(call vivado_build,N310,$(WX_DEFS) N310=1,$(N310_DEFAULTS)) + $(call post_build,N310,WX) + +##N310_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. +N310_HG: build/usrp_n310_fpga_HG.dts + $(call vivado_build,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS)) + $(call post_build,N310,HG) + +##N310_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1. +N310_XG: build/usrp_n310_fpga_XG.dts + $(call vivado_build,N310,$(XG_DEFS) N310=1,$(N310_DEFAULTS)) + $(call post_build,N310,XG) + +##N310_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1. +N310_HA: build/usrp_n310_fpga_HA.dts + $(call vivado_build,N310,$(HA_DEFS) N310=1,$(N310_DEFAULTS)) + $(call post_build,N310,HA) + +##N310_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1. +N310_XA: build/usrp_n310_fpga_XA.dts + $(call vivado_build,N310,$(XA_DEFS) N310=1,$(N310_DEFAULTS)) + $(call post_build,N310,XA) + +##N310_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1. +N310_AA: build/usrp_n310_fpga_AA.dts + $(call vivado_build,N310,$(AA_DEFS) N310=1,$(N310AA_DEFAULTS)) + $(call post_build,N310,AA) + +##N300_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1. +N300_WX: build/usrp_n300_fpga_WX.dts + $(call vivado_build,N300,$(WX_DEFS) N300=1,$(N300_DEFAULTS)) + $(call post_build,N300,WX) + +##N300_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. +N300_HG: build/usrp_n300_fpga_HG.dts + $(call vivado_build,N300,$(HG_DEFS) N300=1,$(N300_DEFAULTS)) + $(call post_build,N300,HG) + +##N300_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1. +N300_XG: build/usrp_n300_fpga_XG.dts + $(call vivado_build,N300,$(XG_DEFS) N300=1,$(N300_DEFAULTS)) + $(call post_build,N300,XG) + +##N300_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1. +N300_HA: build/usrp_n300_fpga_HA.dts + $(call vivado_build,N300,$(HA_DEFS) N300=1,$(N300_DEFAULTS)) + $(call post_build,N300,HA) + +##N300_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1. +N300_XA: build/usrp_n300_fpga_XA.dts + $(call vivado_build,N300,$(XA_DEFS) N300=1,$(N300_DEFAULTS)) + $(call post_build,N300,XA) + +##N300_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1. +N300_AA: build/usrp_n300_fpga_AA.dts + $(call vivado_build,N300,$(AA_DEFS) N300=1,$(N300AA_DEFAULTS)) + $(call post_build,N300,AA) + +##N320_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1. +N320_WX: build/usrp_n320_fpga_WX.dts + $(call vivado_build,N320,$(WX_DEFS) N320=1,$(N320_DEFAULTS)) + $(call post_build,N320,WX) + +##N320_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. +N320_HG: build/usrp_n320_fpga_HG.dts + $(call vivado_build,N320,$(HG_DEFS) N320=1,$(N320_DEFAULTS)) + $(call post_build,N320,HG) + +##N320_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1. +N320_XG: build/usrp_n320_fpga_XG.dts + $(call vivado_build,N320,$(XG_DEFS) N320=1,$(N320_DEFAULTS)) + $(call post_build,N320,XG) + +##N320_XQ: WR on SFP+ Port0, 10Gig on QSFP+ Port0,1. +N320_XQ: build/usrp_n320_fpga_XQ.dts + $(call vivado_build,N320,$(XQ_DEFS) N320=1,$(N320_DEFAULTS)) + $(call post_build,N320,XQ) + +##N320_AQ: 10Gig on SFP+ Port0,1 Aurora on QSFP+ Port0,1,2,3. +N320_AQ: build/usrp_n320_fpga_AQ.dts + $(call vivado_build,N320,$(AQ_DEFS) N320=1,$(N320_DEFAULTS)) + $(call post_build,N320,AQ) + +build/%.dts: dts/%.dts dts/*.dtsi + -mkdir -p build + ${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $< + +clean: ##Clean up all target build outputs. + @echo "Cleaning targets..." + @rm -rf build-N3*_* + @rm -rf build + +cleanall: ##Clean up all target and ip build outputs. + @echo "Cleaning targets and IP..." + @rm -rf build-ip + @rm -rf build-N3*_* + @rm -rf build + +help: ##Show this help message. + @grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' + +## +##Supported Options +##----------------- +##GUI=1 Launch the build in the Vivado GUI. +##CHECK=1 Launch the syntax checker instead of building a bitfile. +##SYNTH=1 Launch the build but stop after synthesis. +##TOP= Specify a top module for syntax checking. (Optional. Default is the bitfile top) + +.PHONY: all clean cleanall help diff --git a/fpga/usrp3/top/n3xx/Makefile.n3xx.inc b/fpga/usrp3/top/n3xx/Makefile.n3xx.inc new file mode 100644 index 000000000..aea75a69a --- /dev/null +++ b/fpga/usrp3/top/n3xx/Makefile.n3xx.inc @@ -0,0 +1,161 @@ +# +# Copyright 2008-2019 Ettus Research, a National Instruments Brand +# + +################################################## +# Project Setup +################################################## +# TOP_MODULE = +# NAME = +# PART_ID = +# ARCH = + +################################################## +# Include other makefiles +################################################## + +BASE_DIR = $(abspath ..) +IP_DIR = $(abspath ./ip) +include $(BASE_DIR)/../tools/make/viv_design_builder.mak + +include $(IP_DIR)/Makefile.inc +include coregen_dsp/Makefile.srcs +include $(LIB_DIR)/ip/Makefile.inc +include $(LIB_DIR)/hls/Makefile.inc +include $(LIB_DIR)/control/Makefile.srcs +include $(LIB_DIR)/fifo/Makefile.srcs +include $(LIB_DIR)/simple_gemac/Makefile.srcs +include $(LIB_DIR)/axi/Makefile.srcs +include $(LIB_DIR)/timing/Makefile.srcs +include $(LIB_DIR)/packet_proc/Makefile.srcs +include $(LIB_DIR)/xge/Makefile.srcs +include $(LIB_DIR)/xge_interface/Makefile.srcs +include $(LIB_DIR)/dsp/Makefile.srcs +include $(LIB_DIR)/axi/Makefile.srcs +include $(LIB_DIR)/white_rabbit/wr_cores_v4_2/Makefile.srcs +include $(LIB_DIR)/rfnoc/Makefile.srcs +include $(BASE_DIR)/n3xx/dboards/rh/Makefile.srcs +include $(BASE_DIR)/n3xx/dboards/mg/Makefile.srcs +include $(BASE_DIR)/n3xx/dboards/common/Makefile.srcs +# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and +# DUC, and of course the radio. Any other block needs to use the +# RFNOC_OOT_MAKEFILE_SRCS variable (see below). +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs +# If out-of-tree modules want to be compiled into this image, then they need to +# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files. +# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual +# source files. +include $(RFNOC_OOT_MAKEFILE_SRCS) + +IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE) +EDGE_FILE ?= $(DEFAULT_EDGE_FILE) + +################################################## +# Sources +################################################## +TOP_SRCS = \ +n3xx_core.v \ +n3xx_mgt_channel_wrapper.v \ +n3xx_mgt_wrapper.v \ +n3xx_mgt_io_core.v \ +n3xx_clocking.v \ +n3xx_db_fe_core.v \ +WrapBufg.vhd \ +$(IMAGE_CORE) + +MB_CLOCKS_XDC = $(abspath mb_clocks.xdc) + +MB_XDC = \ +mb_timing.xdc \ +mb_pins.xdc + +ifdef BUILD_WR +MB_XDC += $(abspath n3xx_wr.xdc) +TOP_SRCS += \ +n3xx_wr_top.vhd \ +n3xx_serial_dac.vhd \ +n3xx_serial_dac_arb.vhd +endif + +ifdef BUILD_10G +MB_XDC += $(abspath n310_10ge.xdc) +endif + +ifdef BUILD_1G +MB_XDC += $(abspath n310_1ge.xdc) +endif + +ifdef BUILD_AURORA +MB_XDC += $(abspath n310_aurora.xdc) +endif + +ifndef NO_DRAM_FIFOS +DRAM_SRCS = $(IP_DRAM_XCI_SRCS) $(abspath n310_dram.xdc) +else +DRAM_SRCS = +endif + +ifdef N300 +DB_CLOCKS_XDC = +DB_SRCS = $(MAGNESIUM_DB_TIMING_XDC) \ +$(MAGNESIUM_DB0_XDC) \ +$(MAGNESIUM_TOP_SRCS) $(MAGNESIUM_DB_SRCS) +endif + +ifdef N310 +DB_CLOCKS_XDC = +DB_SRCS = $(MAGNESIUM_DB_TIMING_XDC) \ +$(MAGNESIUM_DB0_XDC) $(MAGNESIUM_DB1_XDC) \ +$(MAGNESIUM_TOP_SRCS) $(MAGNESIUM_DB_SRCS) +endif + +ifdef N320 +DB_CLOCKS_XDC = $(RHODIUM_DB_CLOCKS_XDC) +DB_SRCS = $(RHODIUM_DB_XDC) \ +$(RHODIUM_TOP_SRCS) $(RHODIUM_DB_SRCS) +endif + +DB_SRCS += $(DB_COMMON_SRCS) + +# The XDC files must be read in a specific order, motherboard first and then daughterboard, +# and the clocking XDC files must be before other XDC files. +# Outside of that, all the other sources can be read in any order desired. +DESIGN_SRCS = $(MB_CLOCKS_XDC) $(DB_CLOCKS_XDC) $(abspath $(MB_XDC)) $(DB_SRCS) \ +$(abspath $(TOP_SRCS)) $(AXI_SRCS) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \ +$(UDP_SRCS) $(EXTRAM_SRCS) $(WISHBONE_SRCS) \ +$(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(AURORA_PHY_SRCS) \ +$(TEN_GIGE_PHY_SRCS) $(ONE_GIGE_PHY_SRCS) \ +$(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \ +$(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \ +$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) \ +$(WHITE_RABBIT_SRCS) \ +$(RFNOC_FRAMEWORK_SRCS) \ +$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \ +$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \ +$(RFNOC_BLOCK_RADIO_SRCS) + +EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(EDGE_FILE)" + +################################################## +# Dependency Targets +################################################## +.SECONDEXPANSION: + +VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) + +# DESIGN_SRCS and VERILOG_DEFS must be defined +bin: .prereqs $$(DESIGN_SRCS) ip + $(call BUILD_VIVADO_DESIGN,$(abspath ./build_n3xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID)) + +synth: .prereqs $$(DESIGN_SRCS) ip + $(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) + +rtl: .prereqs $$(DESIGN_SRCS) ip + $(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) + +.PHONY: bin rtl diff --git a/fpga/usrp3/top/n3xx/WrapBufg.vhd b/fpga/usrp3/top/n3xx/WrapBufg.vhd new file mode 100644 index 000000000..1f3417658 --- /dev/null +++ b/fpga/usrp3/top/n3xx/WrapBufg.vhd @@ -0,0 +1,172 @@ +-------------------------------------------------------------------------------- +-- +-- File: WrapBufg.vhd +-- Author: Robert Atkinson +-- Original Project: RF-RIO +-- Date: 13 January 2012 +-- +-------------------------------------------------------------------------------- +-- Copyright 2012 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +-------------------------------------------------------------------------------- +-- +-- Purpose: This is a simple wrapper around a BUFG to make instantiating BUFGCTRLs +-- easier without a headache to relearn the port usage each time. This +-- wrapper only supports a single input clock. When disabled, the BUFG +-- output is zero. +-- +-------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library UNISIM; + use UNISIM.vcomponents.all; + + +entity WrapBufg is + generic( + -- ClkIn is selected by default if set to true, otherwise zero. + kEnableByDefault : boolean := false; + -- If kIgnore is set to true, then the BUFG will switch inputs whenever + -- the aCe signal changes as opposed to waiting for ClkIn to transition low. + kIgnore : boolean := false; + -- If aCe is asynchronous to ClkIn, set this generic to true and the select + -- lines of the BUFGCTRL will be used. If aCe is synchronous to ClkIn, then the CE pins + -- will be used - note that this requires that setup and hold times be met! If aCe is + -- synchronous to ClkIn but no timing relationship is really needed then set this to true. + kEnableIsAsync : boolean := false + ); + port( + -- Input clock + ClkIn : in std_logic; + -- Enable to the BUFG - this signal is treated either asynchronously + -- or synchronously based on the value of the kEnableIsAsync generic. + aCe : in std_logic; + -- Clock output + ClkOut : out std_logic + ); +end WrapBufg; + + +architecture rtl of WrapBufg is + + signal iCe0, + iCe1, + aSel0, + aSel1, + kIgnore0 : std_logic; + +begin + + -- From Data Sheet: + -- The BUFGCTRL is designed to switch between two clock inputs without the possibility of a + -- glitch. When the presently selected clock transitions from High to Low after S0 and S1 + -- changes, the output is kept Low until the other (to-be-selected) clock has transitioned from + -- High to Low. Then the new clock starts driving the output. The default configuration for + -- BUFGCTRL is falling edge sensitive and held at Low prior to the input switching. + -- BUFGCTRL can also be rising edge sensitive and held at High prior to the input switching + -- by using the INIT_OUT attribute. + -- In some applications the conditions previously described are not desirable. Asserting the + -- IGNORE pins will bypass the BUFGCTRL from detecting the conditions for switching + -- between two clock inputs. In other words, asserting IGNORE causes the MUX to switch + -- the inputs at the instant the select pin changes. IGNORE0 causes the output to switch away + -- from the I0 input immediately when the select pin changes, while IGNORE1 causes the + -- output to switch away from the I1 input immediately when the select pin changes. + -- Selection of an input clock requires a "select" pair (S0 and CE0, or S1 and CE1) to be + -- asserted High. If either S or CE is not asserted High, the desired input will not be selected. + -- In normal operation, both S and CE pairs (all four select lines) are not expected to be + -- asserted High simultaneously. Typically only one pin of a "select" pair is used as a select + -- line, while the other pin is tied High. + + -- If the aCe input is async to the I clock, then use the select pins + -- of the BUFGCTRL since setup and hold times at the S* pins do not have + -- to be met. Enable both Select pins if the aCe signal is synchronous to the I clock. + aSel0 <= aCe when kEnableIsAsync else + '1'; + aSel1 <= not aCe when kEnableIsAsync else + '1'; + + -- Only use the CE pins when the input aCe signal is synchronous to the I clock. + iCe0 <= '1' when kEnableIsAsync else + aCe; + iCe1 <= '1' when kEnableIsAsync else + not aCe; + + -- No PkgNiUtilities for me. + kIgnore0 <= '1' when kIgnore else + '0'; + + --vhook_i BUFGCTRL GlobalBuffer + --vhook_a {^IS_(.*)} '0' + --vhook_a INIT_OUT 0 + --vhook_a PRESELECT_I0 kEnableByDefault + --vhook_a PRESELECT_I1 not kEnableByDefault + --vhook_a O ClkOut + --vhook_a CE0 iCe0 + --vhook_a CE1 iCe1 + --vhook_a I0 ClkIn + --vhook_a I1 '0' + --vhook_a IGNORE0 kIgnore0 + --vhook_a IGNORE1 '1' + --vhook_a S0 aSel0 + --vhook_a S1 aSel1 + GlobalBuffer: BUFGCTRL + generic map ( + INIT_OUT => 0, --integer:=0 + IS_CE0_INVERTED => '0', --bit:='0' + IS_CE1_INVERTED => '0', --bit:='0' + IS_I0_INVERTED => '0', --bit:='0' + IS_I1_INVERTED => '0', --bit:='0' + IS_IGNORE0_INVERTED => '0', --bit:='0' + IS_IGNORE1_INVERTED => '0', --bit:='0' + IS_S0_INVERTED => '0', --bit:='0' + IS_S1_INVERTED => '0', --bit:='0' + PRESELECT_I0 => kEnableByDefault, --boolean:=false + PRESELECT_I1 => not kEnableByDefault) --boolean:=false + port map ( + O => ClkOut, --out std_ulogic + CE0 => iCe0, --in std_ulogic + CE1 => iCe1, --in std_ulogic + I0 => ClkIn, --in std_ulogic + I1 => '0', --in std_ulogic + IGNORE0 => kIgnore0, --in std_ulogic + IGNORE1 => '1', --in std_ulogic + S0 => aSel0, --in std_ulogic + S1 => aSel1); --in std_ulogic + + + --vscan Begin Add Explain Clock + --vscan # These are the outputs of the BUFGCTRLs in the WrapBufg module. VScan + --vscan # sees the output as glitchy but the clocks are guaranteed to switch + --vscan # in a glitchless fashion provided that either setup and hold times + --vscan # are met at the CE pins of the BUFGCTRL (these paths are analyzed by the + --vscan # tools for timing) or the CE pins are hardwired and the S pins are used + --vscan # which require no timing relationship to the input clocks. + --vscan *[WrapBufg]GlobalBuffer/[BUFGCTRL]O + --vscan End Add Explain Clock + + + -- Check that enable lines match up with the generics of the BUFGCTRL + --vscan vscan_off + --synthesis translate_off + SimProcess: process + begin + wait for 1 ns; + if kEnableIsAsync then + assert kEnableByDefault = (aSel0 = '1') + report "Initial condition on enable lines do not match between" & LF + & "the BUFGCTRL generic and the SEL line" + severity error; + else + assert kEnableByDefault = (iCe0 = '1') + report "Initial condition on enable lines do not match between" & LF + & "the BUFGCTRL generic and the CE line" + severity error; + end if; + wait; + end process SimProcess; + --synthesis translate_on + --vscan vscan_on + +end rtl; diff --git a/fpga/usrp3/top/n3xx/build_n3xx.tcl b/fpga/usrp3/top/n3xx/build_n3xx.tcl new file mode 100644 index 000000000..45ba102c3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/build_n3xx.tcl @@ -0,0 +1,39 @@ +# +# Copyright 2016 Ettus Research +# + +source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl +source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl + +# STEP#1: Create project, add sources, refresh IP +vivado_utils::initialize_project + +# STEP#2: Run synthesis +vivado_utils::synthesize_design +vivado_utils::generate_post_synth_reports + +# STEP#3: Run implementation strategy +set n3xx_strategy [dict create] +dict set n3xx_strategy "opt_design.is_enabled" 1 +dict set n3xx_strategy "opt_design.directive" "NoBramPowerOpt" +dict set n3xx_strategy "post_opt_power_opt_design.is_enabled" 0 +dict set n3xx_strategy "place_design.directive" "ExtraNetDelay_high" +dict set n3xx_strategy "post_place_power_opt_design.is_enabled" 0 +dict set n3xx_strategy "post_place_phys_opt_design.is_enabled" 1 +dict set n3xx_strategy "post_place_phys_opt_design.directive" "AggressiveExplore" +dict set n3xx_strategy "route_design.directive" "Explore" +dict set n3xx_strategy "route_design.more_options" "-tns_cleanup" +dict set n3xx_strategy "post_route_phys_opt_design.is_enabled" 1 +dict set n3xx_strategy "post_route_phys_opt_design.directive" "Explore" +vivado_strategies::implement_design $n3xx_strategy + +# STEP#4: Generate reports +vivado_utils::generate_post_route_reports + +# STEP#5: Generate a bitstream, netlist and debug probes +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [get_designs *] +set byte_swap_bin 1 +vivado_utils::write_implementation_outputs $byte_swap_bin + +# Cleanup +vivado_utils::close_batch_project diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/.gitignore b/fpga/usrp3/top/n3xx/coregen_dsp/.gitignore new file mode 100644 index 000000000..dbc4e5588 --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/.gitignore @@ -0,0 +1,4 @@ +_xmsgs +*.log +*.ncf + diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/.lso b/fpga/usrp3/top/n3xx/coregen_dsp/.lso new file mode 100644 index 000000000..9d9a4a3aa --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/.lso @@ -0,0 +1 @@ +fir_compiler_v5_0 diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/Makefile.srcs b/fpga/usrp3/top/n3xx/coregen_dsp/Makefile.srcs new file mode 100644 index 000000000..6717ac611 --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/Makefile.srcs @@ -0,0 +1,17 @@ +# +# Copyright 2012 Ettus Research LLC +# + +################################################## +# Coregen Sources +################################################## + +COREGEN_DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/n3xx/coregen_dsp/, \ +hbdec1.v \ +hbdec1.ngc \ +hbdec2.v \ +hbdec2.ngc \ +hbdec3.v \ +hbdec3.ngc \ +)) + diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/hbdec1.ngc b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec1.ngc new file mode 100644 index 000000000..5c09a6253 --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec1.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$22g6~753-Xnzd}foo8#5+421).97 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174289io6`;138b?>i6;hk1<7*;12827geh39;0n76a>3`494?"39:0:?om4n531>c=5$530>45ek2d?=?4>0:9l56g4290/8<=512``?k26:3;:76a>3`094?"39:0:?om4n531>44<3f;8m<4?:%627?74jj1e8<<51298k45f83:1(9?<:01ag>h39;0:865`12;e>5<#<891=>ll;o626?7232e:?4k50;&756<6;ki0b9?=:048?j741m0;6):>3;30ff=i<881=:54o01:g?6=,=;86<=mc:l757<6021d=>7m:18'045=9:hh7c:>2;3:?>i6;0k1<7*;12827ge:?7?=h9:3=6=4+401956dd3g>:>7?k;:m27<3=83.?=>4>3ca8j17528o07b?<9583>!26;3;8nn5a40095c=5$530>45ek2d?=?4=0:9l56?5290/8<=512``?k26:38:76a>38394?"39:0:?om4n531>74<3f;85=4?:%627?74jj1e8<<52298k45?n3:1(9?<:01ag>h39;09865`12`a>5<#<891=>ll;o626?4232e:?oo50;&756<6;ki0b9?=:348?j74j00;6):>3;30ff=i<881>:54o01al8:18'045=9:hh7c:>2;0:?>i6;hl1<7*;12827ge:?7?=h9:2n6=4+401956dd3g>:>74>3ca8j1752;o07b?!26;3;8in5a40094>=h9:o>6=4+401956cd3g>:>7?4;n30a1<72->:?7?k<:18'045=9:oh7c:>2;18?j74m;0;6):>3;30af=i<881865`12g2>5<#<891=>kl;o626?3<3f;8i=4?:%627?74mj1e8<<56:9l56bb290/8<=512g`?k26:3=07b?!26;3;8in5a4009<>=h9:nh6=4+401956cd3g>:>774;n30`g<72->:?7?jn:18'045=9:oh7c:>2;`8?j74l00;6):>3;30af=i<881o65`12f;>5<#<891=>kl;o626?b<3f;8h:4?:%627?74mj1e8<<5e:9l56b1290/8<=512g`?k26:3l07b?!26;3;8in5a400955=5$530>45bk2d?=?4>1:9l56b5290/8<=512g`?k26:3;976a>3e394?"39:0:?hm4n531>45<3f;8h=4?:%627?74mj1e8<<51598k45dn3:1(9?<:01fg>h39;0:965`12af>5<#<891=>kl;o626?7132e:?nj50;&756<6;li0b9?=:058?j74kj0;6):>3;30af=i<881=554o01`f?6=,=;86<=jc:l757<6121d=>mn:18'045=9:oh7c:>2;3b?>i6;j21<7*;12827`e:?7?=h9:i>6=4+401956cd3g>:>7?j;:m27f2=83.?=>4>3da8j17528l07b?!26;3;8in5a400965=7>5$530>45bk2d?=?4=1:9l56e6290/8<=512g`?k26:38976a>3b294?"39:0:?hm4n531>75<3f;8nk4?:%627?74mj1e8<<52598k45bj3:1(9?<:01fg>h39;09965`12gb>5<#<891=>kl;o626?4132e:?h750;&756<6;li0b9?=:358?j74m10;6):>3;30af=i<881>554o01f3?6=,=;86<=jc:l757<5121d=>ji:18'045=9:oh7c:>2;0b?>i6;m>1<7*;12827`e:?7?=h9:ho6=4+401956cd3g>:>74>40a8j1752910c<:>5;29 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1742:n27c:>2;00?>o4j;0;6):>3;1g=>h39;09865f3c394?"39:08h45a400960=j6;o626?4032c8hh4?:%627?5c12d?=?4=8:9j7ab=83.?=>4jl:18'045=;m30b9?=:3c8?l5cj3:1(9?<:2f:?k26:38i76g!26;39o56`;1381g>=n;j<1<7*;1280`<=i<881>i54i2`a>5<#<891?i74n531>7c<3`9i<7>5$530>6b>3g>:>75=h39;0:76gic;29 1742oo0b9?=:398mcd=83.?=>4ie:l757<432c::n4?:%627?71j2d?=?4?;:k22d<72->:?7?9b:l757<632c::44?:%627?71j2d?=?4=;:k22=<72->:?7?9b:l757<432c:::4?:%627?71j2d?=?4;;:k223<72->:?7?9b:l757<232c::84?:%627?71j2d?=?49;:k221<72->:?7?9b:l757<032c::?4?:%627?71j2d?=?47;:k224<72->:?7?9b:l757<>32c::=4?:%627?71j2d?=?4n;:k21c<72->:?7?9b:l757:?7?9b:l757:?7?9b:l7570:9j50?=83.?=>4>6c9m044=9810e<;8:18'045=9?h0b9?=:008?l72>3:1(9?<:04a?k26:3;876g>5483>!26;3;=n6`;13820>=n9<>1<7*;12822g=i<881=854i070>5<#<891=;l4n531>40<3`;>>7>5$530>40e3g>:>7?8;:k214<72->:?7?9b:l757<6021b=8>50;&756<6>k1e8<<51898m42a290/8<=517`8j17528k07d?;e;29 174282;3a?>o63;35f>h39;0:o65f15`94?"39:0::o5a40095a=j6=4+401953d4>6c9m044=:810e<:9:18'045=9?h0b9?=:308?l73=3:1(9?<:04a?k26:38876g>4583>!26;3;=n6`;13810>=n9=91<7*;12822g=i<881>854i051>5<#<891=;l4n531>70<3`;<=7>5$530>40e3g>:>7<8;:k235<72->:?7?9b:l757<5021b=;h50;&756<6>k1e8<<52898m40b290/8<=517`8j1752;k07d?9d;29 174282;0a?>o6>:0;6):>3;35f>h39;09o65f14:94?"39:0::o5a40096a=o6=4+401953d:?7?8f:l757<632e:;i4?:%627?70n2d?=?4=;:m23f<72->:?7?8f:l757<432c9m:4?:%627?4f>2d?=?4?;:k1e0<72->:?72d?=?4=;:k1e6<72->:?72d?=?4;;:k264<72->:?7?=0:l757<732c:=k4?:%627?7582d?=?4>;:k25`<72->:?7?=0:l757<532c:=i4?:%627?7582d?=?4<;:k25f<72->:?7?=0:l757<332c:=o4?:%627?7582d?=?4:;:k25d<72->:?7?=0:l757<132c:=44?:%627?7582d?=?48;:k26d<72->:?7?=0:l75744?:%627?7582d?=?46;:k26=<72->:?7?=0:l757:4?:%627?7582d?=?4m;:k263<72->:?7?=0:l75784?:%627?7582d?=?4k;:k261<72->:?7?=0:l757>4?:%627?7582d?=?4i;:k267<72->:?7?=0:l757<6821b=<650;&756<6:91e8<<51098m46c290/8<=511a8j1752910e<>m:18'045=99i0b9?=:098m46f290/8<=511a8j1752;10e<>6:18'045=99i0b9?=:298m46?290/8<=511a8j1752=10e<>8:18'045=99i0b9?=:498m461290/8<=511a8j1752?10e<>::18'045=99i0b9?=:698m471290/8<=511a8j1752110e:18'045=99i0b9?=:e98m477290/8<=511a8j1752l10e<>i:18'045=99i0b9?=:g98m46b290/8<=511a8j17528:07d??4;29 17428:h7c:>2;32?>i6;=0;6):>3;307>h39;0;76a>3383>!26;3;8?6`;1382?>i6;80;6):>3;307>h39;0976a>3183>!26;3;8?6`;1380?>i6:o0;6):>3;307>h39;0?76a>2d83>!26;3;8?6`;1386?>i6:m0;6):>3;307>h39;0=76a>2b83>!26;3;8?6`;1384?>i6;m0;6):>3;307>h39;0376a>3b83>!26;3;8?6`;138:?>i6;k0;6):>3;307>h39;0j76a>3`83>!26;3;8?6`;138a?>i6;00;6):>3;307>h39;0h76a>3983>!26;3;8?6`;138g?>i6;>0;6):>3;307>h39;0n76a>3783>!26;3;8?6`;138e?>i6;<0;6):>3;307>h39;0:<65`13`94?"39:0:?>5a400954=5<#<891=l74n531>4=5<#<891=l74n531>6=6=4+40195d?5<#<891=l74n531>0=5<#<891=l74n531>2=5<#<891=l74n531><=5<#<891=l74n531>g=5<#<891=l74n531>a=5<#<891=l74n531>c=4;h3a4?6=,=;862:9j5dc=83.?=>4>a89m044=9:10e76g>ac83>!26;3;j56`;13822>=n9h>1<7*;1282e<=i<881=:54i0;:>5<#<891=l74n531>4><3f9j97>5$530>6g33g>:>7>4;n1b7?6=,=;86>o;;o626?7<3f9j>7>5$530>6g33g>:>7<4;n1b5?6=,=;86>o;;o626?5<3f9j<7>5$530>6g33g>:>7:4;n1:b?6=,=;86>o;;o626?3<3f92i7>5$530>6g33g>:>784;n1:`?6=,=;86>o;;o626?1<3f92n7>5$530>6g33g>:>764;n1:e?6=,=;86>o;;o626??<3f9257>5$530>6g33g>:>7o4;n1:o;;o626?d<3f92;7>5$530>6g33g>:>7m4;n1:2?6=,=;86>o;;o626?b<3f9297>5$530>6g33g>:>7k4;n1:0?6=,=;86>o;;o626?`<3f92?7>5$530>6g33g>:>7??;:m0=7<72->:?7=n4:l757<6921d?4>50;&756<4i=1e8<<51398k6>a290/8<=53`68j17528907b=7e;29 1742:k?7c:>2;37?>i40m0;6):>3;1b0>h39;0:965`39a94?"39:08m95a400953=o;;o626?7?32e8444?:%627?5f<2d?=?4>9:9l7=>=83.?=>468:18'045=;h>0b9?=:0`8?j5?=3:1(9?<:2c7?k26:3;h76a<8583>!26;39j86`;1382`>=h;191<7*;1280e1=i<881=h54o2:1>5<#<891?l:4n531>4`<3f93=7>5$530>6g33g>:>7:?7=n4:l757<5921d?:h50;&756<4i=1e8<<52398k61b290/8<=53`68j1752;907b=8d;29 1742:k?7c:>2;07?>i4?j0;6):>3;1b0>h39;09965`3``94?"39:08m95a400963=o;;o626?4?32e8m54?:%627?5f<2d?=?4=9:9l7d1=83.?=>4o9:18'045=;h>0b9?=:3`8?j5>k3:1(9?<:2c7?k26:38h76a<9083>!26;39j86`;1381`>=h;1<1<7*;1280e1=i<881>h54o25a>5<#<891?l:4n531>7`<3`k?6=4+4019e6=i<881<65fa383>!26;3k87c:>2;38?lg6290/8<=5a29m044=:21bm=4?:%627?g43g>:>7=4;h;e>5<#<891m>5a40090>=n1l0;6):>3;c0?k26:3?07d7k:18'045=i:1e8<<56:9j=f<72->:?7o<;o626?1<3`3i6=4+4019e6=i<881465f9`83>!26;3k87c:>2;;8?l??290/8<=5a29m044=i21b5:4?:%627?g43g>:>7l4;h;5>5<#<891m>5a4009g>=n1<0;6):>3;c0?k26:3n07d7;:18'045=i:1e8<<5e:9j=6<72->:?7o<;o626?`<3`396=4+4019e6=i<881==54i8394?"39:0j?6`;13825>=n190;6):>3;c0?k26:3;976g7f;29 1742h90b9?=:018?lgd290/8<=5a29m044=9=10ell50;&7565:9jed<72->:?7o<;o626?7132cj57>5$530>d55<#<891m>5a40095==h39;0:565fa783>!26;3k87c:>2;3b?>of=3:1(9?<:`18j17528h07d76:18'045=i:1e8<<51b98m=c=83.?=>4n3:l757<6l21d8=l50;&756<38h1e8<<50:9l05?=83.?=>4;0`9m044=921d8=650;&756<38h1e8<<52:9l051=83.?=>4;0`9m044=;21d8=850;&756<38h1e8<<54:9l053=83.?=>4;0`9m044==21d8=:50;&756<38h1e8<<56:9l055=83.?=>4;0`9m044=?21d8=?50;&756<38h1e8<<58:9l056=83.?=>4;0`9m044=121d?kh50;&756<38h1e8<<5a:9l7cc=83.?=>4;0`9m044=j21d?kj50;&756<38h1e8<<5c:9l7ce=83.?=>4;0`9m044=l21d?kl50;&756<38h1e8<<5e:9l7cg=83.?=>4;0`9m044=n21d?k750;&756<38h1e8<<51198k6`?290/8<=541c8j17528;07b=i6;29 1742=:j7c:>2;31?>i4n<0;6):>3;63e>h39;0:?65`3g694?"39:0?n;o626?7132e8j<4?:%627?27i2d?=?4>7:9l7c6=83.?=>4;0`9m044=9110c>ki:18'045=<9k0b9?=:0;8?j5bm3:1(9?<:52b?k26:3;j76a!26;3>;m6`;1382f>=h;lh1<7*;12874d=i<881=n54o2gb>5<#<8918=o4n531>4b<3f9n57>5$530>16f3g>:>7?j;:m0a=<72->:?7:?a:l757<6n21d?h950;&756<38h1e8<<52198k6c1290/8<=541c8j1752;;07b=j5;29 1742=:j7c:>2;01?>i4m=0;6):>3;63e>h39;09?65`3d194?"39:0?n;o626?4132e?==4?:%627?27i2d?=?4=7:9l05`=83.?=>4;0`9m044=:110c9>j:18'045=<9k0b9?=:3;8?j27l3:1(9?<:52b?k26:38j76a;0b83>!26;3>;m6`;1381f>=h<981<7*;12874d=i<881>n54o2d4>5<#<8918=o4n531>7b<3f9no7>5$530>16f3g>:>7:?7:?a:l757<5n21bo94?:%627?e43g>:>7>4;ha1>5<#<891o>5a40095>=nk80;6):>3;a0?k26:3807dm?:18'045=k:1e8<<53:9jfc<72->:?7m<;o626?2<3`hn6=4+4019g6=i<881965fbe83>!26;3i87c:>2;48?ldd290/8<=5c29m044=?21bno4?:%627?e43g>:>764;h`b>5<#<891o>5a4009=>=nj10;6):>3;a0?k26:3k07dl8:18'045=k:1e8<<5b:9jf3<72->:?7m<;o626?e<3`h>6=4+4019g6=i<881h65fb583>!26;3i87c:>2;g8?ld4290/8<=5c29m044=n21bn?4?:%627?e43g>:>7??;:ka5?6=,=;86n=4n531>47<3`h;6=4+4019g6=i<881=?54i`d94?"39:0h?6`;13827>=nkj0;6):>3;a0?k26:3;?76glb;29 1742j90b9?=:078?lef290/8<=5c29m044=9?10en750;&7567:9jg=<72->:?7m<;o626?7?32ch;7>5$530>f55<#<891o>5a40095d=h39;0:n65fb883>!26;3i87c:>2;3`?>ofm3:1(9?<:b18j17528n07d?8a;29 17428=27c:>2;28?l7003:1(9?<:05:?k26:3;07d?87;29 17428=27c:>2;08?xd3>10;684?:1y'07c=:k30D9=k;I605>"4?>0:mh94i0;2>5<5<5<=57>55;294~"3:l09585G42f8L1563-9<;7?ne69'6d7=k2c:8<4?::k2<4<722c:5:4?::k761<722e?=;4?::a03g=83?1<7>t$50f>7?33A>8h6F;309'721=9ho<7):188m4?02900e9?7:188k1712900qo:9b;291?6=8r.?>h4=959K06b<@=9:7)=87;3ba2=#:h;1>6g>4083>>o6080;66g>9683>>o3910;66a;1783>>{e6g>4083>>o6080;66g>9683>>i39?0;66sm47f94?3=83:p(95<5<5<=i7>55;294~"3:l09595G42f8L1563-9<;7?ne69'6d7=:2c:8<4?::k2<4<722c:5:4?::k75=<722e?=;4?::a03`=83?1<7>t$50f>7?33A>8h6F;309'721=9ho<7):188m4?02900e9?7:188k1712900qo:80;291?6=8r.?>h4=959K06b<@=9:7)=87;3ba2=#:h;1>6g>4083>>o6080;66g>9683>>o3910;66a;1783>>{e<>;1<7;50;2x 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1742=:j7c:>2;3`?>i4mh0;6):>3;63e>h39;0:h65`3d;94?"39:0?n;o626?4732e8i;4?:%627?27i2d?=?4=1:9l7`3=83.?=>4;0`9m044=:;10c>k;:18'045=<9k0b9?=:318?j5b;3:1(9?<:52b?k26:38?76a!26;3>;m6`;13811>=h<8;1<7*;12874d=i<881>;54o533>5<#<8918=o4n531>71<3f>;j7>5$530>16f3g>:>7<7;:m74`<72->:?7:?a:l757<5121d8=j50;&756<38h1e8<<52`98k16d290/8<=541c8j1752;h07b:?2;29 1742=:j7c:>2;0`?>i4n>0;6):>3;63e>h39;09h65`3da94?"39:0?5<#<891o>5a40094>=nk;0;6):>3;a0?k26:3;07dm>:18'045=k:1e8<<52:9jg5<72->:?7m<;o626?5<3`hm6=4+4019g6=i<881865fbd83>!26;3i87c:>2;78?ldc290/8<=5c29m044=>21bnn4?:%627?e43g>:>794;h`a>5<#<891o>5a4009<>=njh0;6):>3;a0?k26:3307dl7:18'045=k:1e8<<5a:9jf2<72->:?7m<;o626?d<3`h=6=4+4019g6=i<881o65fb483>!26;3i87c:>2;f8?ld3290/8<=5c29m044=m21bn>4?:%627?e43g>:>7h4;h`1>5<#<891o>5a400955=h39;0:=65fb183>!26;3i87c:>2;31?>ofn3:1(9?<:b18j17528907dml:18'045=k:1e8<<51598mfd=83.?=>4l3:l757<6=21bol4?:%627?e43g>:>7?9;:k`=?6=,=;86n=4n531>41<3`i36=4+4019g6=i<881=554ib594?"39:0h?6`;1382=>=nk?0;6):>3;a0?k26:3;j76gl5;29 1742j90b9?=:0`8?ld>290/8<=5c29m044=9j10elk50;&756d:9j52g=83.?=>4>789m044=821b=:650;&756<6?01e8<<51:9j521=83.?=>4>789m044=:21vn8=n:182e4<729q/8?k52958L15c3A>8=6T>3g824~2c2>21;:473;5`>1g=9=0<:79=:0390<<083;;69;57487=1=lk8;ocg>4=inh0:7c??0;28j466281/==<537c8 4642;=m7c?>7;38j45b281/=9>526d8j411281e=:l51:l2=3<63g83:7?4n3c;>4=#:k91>464n3`7>4=i;><1<6*o;4$517>60>3->897=9d:m0e`<722c?=h4?::k2<3<722c:494?::m1f2<722c:454?::k767<722c9n;4?::k2<2<722c?=k4?::k2=4?::k2<0<722c:4>4?::k2=7<722c:4?4?::k75a<722e8;54?::k24?::k764<722c:4i4?::k766<722en?7>5$530>`46`;1382?>ib83:1(9?<:d08j1752;10cih50;&7561=h39;0>76akc;29 1742l80b9?=:798kad=83.?=>4j2:l757<032eom7>5$530>`46`;138:?>ic?3:1(9?<:d08j1752h10ci850;&756f=1<7*;128f6>h39;0o76ak3;29 1742l80b9?=:d98ka4=83.?=>4j2:l7575$530>`44;nf3>5<#<891i?5a400954=h39;0:>65`cd83>!26;3o97c:>2;30?>ibj3:1(9?<:d08j17528>07bkn:18'045=m;1e8<<51498k`?=83.?=>4j2:l757<6>21di54?:%627?c53g>:>7?8;:mf3?6=,=;86h<4n531>4><3fo=6=4+4019a7=i<881=454od794?"39:0n>6`;1382e>=hm=0;6):>3;g1?k26:3;i76ak8;29 1742l80b9?=:0a8?jec290/8<=5e39m044=9m10e>9::18'045=;>>0b9?=:198m614290/8<=53668j1752810e>9=:18'045=;>>0b9?=:398m616290/8<=53668j1752:10e>9?:18'045=;>>0b9?=:598m60a290/8<=53668j1752<10e>8j:18'045=;>>0b9?=:798m6bf290/8<=53e;8j1752910e>j7:18'045=;m30b9?=:098m6b0290/8<=53e;8j1752;10e>j9:18'045=;m30b9?=:298m6b2290/8<=53e;8j1752=10e>j;:18'045=;m30b9?=:498m6b4290/8<=53e;8j1752?10e>j=:18'045=;m30b9?=:698m6b7290/8<=53e;8j1752110e>mi:18'045=;m30b9?=:898m6eb290/8<=53e;8j1752h10e>mk:18'045=;m30b9?=:c98m6ed290/8<=53e;8j1752j10e>mm:18'045=;m30b9?=:e98m6ef290/8<=53e;8j1752l10e>m6:18'045=;m30b9?=:g98m6e?290/8<=53e;8j17528:07d=l7;29 1742:n27c:>2;32?>o4k<0;6):>3;1g=>h39;0:>65f3b694?"39:08h45a400956=j6;o626?7232c8o<4?:%627?5c12d?=?4>6:9j7f6=83.?=>410e>li:18'045=;m30b9?=:0:8?l5em3:1(9?<:2f:?k26:3;276g!26;39o56`;1382e>=n;ki1<7*;1280`<=i<881=o54i2`b>5<#<891?i74n531>4e<3`9i57>5$530>6b>3g>:>7?k;:k0f=<72->:?7=k9:l757<6m21b?o950;&756<4l01e8<<51g98m6d1290/8<=53e;8j1752;:07d=m5;29 1742:n27c:>2;02?>o4j=0;6):>3;1g=>h39;09>65f3c194?"39:08h45a400966=j6;o626?4232c8i=4?:%627?5c12d?=?4=6:9j7a`=83.?=>410e>jj:18'045=;m30b9?=:3:8?l5cl3:1(9?<:2f:?k26:38276g!26;39o56`;1381e>=n;mh1<7*;1280`<=i<881>o54i2f2>5<#<891?i74n531>7e<3`9h:7>5$530>6b>3g>:>7:?7=k9:l757<5m21b?o>50;&756<4l01e8<<52g98mc`=83.?=>4ie:l757<732cmh7>5$530>ccoaj3:1(9?<:gg8j1752:10e<8l:18'045=9?h0b9?=:198m40f290/8<=517`8j1752810e<86:18'045=9?h0b9?=:398m40?290/8<=517`8j1752:10e<88:18'045=9?h0b9?=:598m401290/8<=517`8j1752<10e<8::18'045=9?h0b9?=:798m403290/8<=517`8j1752>10e<8=:18'045=9?h0b9?=:998m406290/8<=517`8j1752010e<8?:18'045=9?h0b9?=:`98m43a290/8<=517`8j1752k10e<;j:18'045=9?h0b9?=:b98m43c290/8<=517`8j1752m10e<;l:18'045=9?h0b9?=:d98m43e290/8<=517`8j1752o10e<;n:18'045=9?h0b9?=:028?l7213:1(9?<:04a?k26:3;:76g>5683>!26;3;=n6`;13826>=n9<<1<7*;12822g=i<881=>54i076>5<#<891=;l4n531>42<3`;>87>5$530>40e3g>:>7?:;:k216<72->:?7?9b:l757<6>21b=8<50;&756<6>k1e8<<51698m436290/8<=517`8j17528207d?:0;29 174282;3:?>o63;35f>h39;0:m65f15g94?"39:0::o5a40095g=h6=4+401953de:9j51?=83.?=>4>6c9m044=9o10e<:7:18'045=9?h0b9?=:328?l73?3:1(9?<:04a?k26:38:76g>4783>!26;3;=n6`;13816>=n9=?1<7*;12822g=i<881>>54i067>5<#<891=;l4n531>72<3`;??7>5$530>40e3g>:>7<:;:k237<72->:?7?9b:l757<5>21b=:?50;&756<6>k1e8<<52698m417290/8<=517`8j1752;207d?9f;29 174282;0:?>o6>l0;6):>3;35f>h39;09m65f17f94?"39:0::o5a40096g=4>6c9m044=:o10c<6?:18'045=9>l0b9?=:198k41b290/8<=516d8j1752810c<9k:18'045=9>l0b9?=:398k41d290/8<=516d8j1752:10e?o8:18'045=:h<0b9?=:198m7g2290/8<=52`48j1752810e?o;:18'045=:h<0b9?=:398m7g4290/8<=52`48j1752:10e?o=:18'045=:h<0b9?=:598m446290/8<=51328j1752910e8;29 174288;7c:>2;32?>o68m0;6):>3;33g>h39;0;76g>0c83>!26;3;;o6`;1382?>o68h0;6):>3;33g>h39;0976g>0883>!26;3;;o6`;1380?>o6810;6):>3;33g>h39;0?76g>0683>!26;3;;o6`;1386?>o68?0;6):>3;33g>h39;0=76g>0483>!26;3;;o6`;1384?>o69?0;6):>3;33g>h39;0376g>1483>!26;3;;o6`;138:?>o69=0;6):>3;33g>h39;0j76g>1283>!26;3;;o6`;138a?>o69;0;6):>3;33g>h39;0h76g>1083>!26;3;;o6`;138g?>o6990;6):>3;33g>h39;0n76g>0g83>!26;3;;o6`;138e?>o68l0;6):>3;33g>h39;0:<65f11694?"39:0:5<#<891=>=4n531>4=5<#<891=>=4n531>6=5<#<891=>=4n531>0=5<#<891=>=4n531>2=5<#<891=>=4n531><=5<#<891=>=4n531>g=5<#<891=>=4n531>a=5<#<891=>=4n531>c=6=4+40195654;n31f?6=,=;86<=<;o626?7632c:ml4?:%627?7f12d?=?4?;:k2e=<72->:?7?n9:l757<632c:m:4?:%627?7f12d?=?4=;:k2e3<72->:?7?n9:l757<432c:m84?:%627?7f12d?=?4;;:k2e6<72->:?7?n9:l757<232c:m?4?:%627?7f12d?=?49;:k2e4<72->:?7?n9:l757<032c:m=4?:%627?7f12d?=?47;:k2=c<72->:?7?n9:l757<>32c:5h4?:%627?7f12d?=?4n;:k2=a<72->:?7?n9:l757:?7?n9:l757:?7?n9:l7570:9j5g6=83.?=>4>a89m044=9810eae83>!26;3;j56`;13820>=n9hi1<7*;1282e<=i<881=854i0ca>5<#<891=l74n531>40<3`;j87>5$530>4g>3g>:>7?8;:k2=<<72->:?7?n9:l757<6021d?l;50;&756<4i=1e8<<50:9l7d5=83.?=>4450;&756<4i=1e8<<54:9l7<`=83.?=>444=83.?=>4442;31?>i40o0;6):>3;1b0>h39;0:?65`39g94?"39:08m95a400951=o;;o626?7132e84o4?:%627?5f<2d?=?4>7:9l7=g=83.?=>466:18'045=;h>0b9?=:0;8?j5?03:1(9?<:2c7?k26:3;j76a<8683>!26;39j86`;1382f>=h;1?1<7*;1280e1=i<881=n54o2:7>5<#<891?l:4n531>4b<3f93?7>5$530>6g33g>:>7?j;:m0<7<72->:?7=n4:l757<6n21d?5?50;&756<4i=1e8<<52198k6>7290/8<=53`68j1752;;07b=8f;29 1742:k?7c:>2;01?>i4?l0;6):>3;1b0>h39;09?65`36f94?"39:08m95a400961=o;;o626?4132e8ml4?:%627?5f<2d?=?4=7:9l7d?=83.?=>4o7:18'045=;h>0b9?=:3;8?j5f?3:1(9?<:2c7?k26:38j76a!26;39j86`;1381f>=h;0i1<7*;1280e1=i<881>n54o2;2>5<#<891?l:4n531>7b<3f93:7>5$530>6g33g>:>7:?7=n4:l757<5n21bm94?:%627?g43g>:>7>4;hc1>5<#<891m>5a40095>=ni80;6):>3;c0?k26:3807do?:18'045=i:1e8<<53:9j=c<72->:?7o<;o626?2<3`3n6=4+4019e6=i<881965f9e83>!26;3k87c:>2;48?l?d290/8<=5a29m044=?21b5o4?:%627?g43g>:>764;h;b>5<#<891m>5a4009=>=n110;6):>3;c0?k26:3k07d78:18'045=i:1e8<<5b:9j=3<72->:?7o<;o626?e<3`3>6=4+4019e6=i<881h65f9583>!26;3k87c:>2;g8?l?4290/8<=5a29m044=n21b5?4?:%627?g43g>:>7??;:k:5?6=,=;86l=4n531>47<3`3;6=4+4019e6=i<881=?54i9d94?"39:0j?6`;13827>=nij0;6):>3;c0?k26:3;?76gnb;29 1742h90b9?=:078?lgf290/8<=5a29m044=9?10el750;&7567:9je=<72->:?7o<;o626?7?32cj;7>5$530>d55<#<891m>5a40095d=h39;0:n65f9883>!26;3k87c:>2;3`?>o?m3:1(9?<:`18j17528n07b:?b;29 1742=:j7c:>2;28?j2713:1(9?<:52b?k26:3;07b:?8;29 1742=:j7c:>2;08?j27?3:1(9?<:52b?k26:3907b:?6;29 1742=:j7c:>2;68?j27=3:1(9?<:52b?k26:3?07b:?4;29 1742=:j7c:>2;48?j27;3:1(9?<:52b?k26:3=07b:?1;29 1742=:j7c:>2;:8?j2783:1(9?<:52b?k26:3307b=if;29 1742=:j7c:>2;c8?j5am3:1(9?<:52b?k26:3h07b=id;29 1742=:j7c:>2;a8?j5ak3:1(9?<:52b?k26:3n07b=ib;29 1742=:j7c:>2;g8?j5ai3:1(9?<:52b?k26:3l07b=i9;29 1742=:j7c:>2;33?>i4n10;6):>3;63e>h39;0:=65`3g494?"39:0?6=4+401905gn;o626?7332e8j>4?:%627?27i2d?=?4>5:9l7c4=83.?=>4;0`9m044=9?10c>h>:18'045=<9k0b9?=:058?j5a83:1(9?<:52b?k26:3;376a!26;3>;m6`;1382=>=h;lo1<7*;12874d=i<881=l54o2gg>5<#<8918=o4n531>4d<3f9nn7>5$530>16f3g>:>7?l;:m0ad<72->:?7:?a:l757<6l21d?h750;&756<38h1e8<<51d98k6c?290/8<=541c8j17528l07b=j7;29 1742=:j7c:>2;03?>i4m?0;6):>3;63e>h39;09=65`3d794?"39:0?n;o626?4332e8i?4?:%627?27i2d?=?4=5:9l047=83.?=>4;0`9m044=:?10c9??:18'045=<9k0b9?=:358?j27n3:1(9?<:52b?k26:38376a;0d83>!26;3>;m6`;1381=>=h<9n1<7*;12874d=i<881>l54o52`>5<#<8918=o4n531>7d<3f>;>7>5$530>16f3g>:>7:?7:?a:l757<5l21d?hm50;&756<38h1e8<<52d98k6c6290/8<=541c8j1752;l07dm;:18'045=k:1e8<<50:9jg7<72->:?7m<;o626?7<3`i:6=4+4019g6=i<881>65fc183>!26;3i87c:>2;18?lda290/8<=5c29m044=<21bnh4?:%627?e43g>:>7;4;h`g>5<#<891o>5a40092>=njj0;6):>3;a0?k26:3=07dlm:18'045=k:1e8<<58:9jfd<72->:?7m<;o626??<3`h36=4+4019g6=i<881m65fb683>!26;3i87c:>2;`8?ld1290/8<=5c29m044=k21bn84?:%627?e43g>:>7j4;h`7>5<#<891o>5a4009a>=nj:0;6):>3;a0?k26:3l07dl=:18'045=k:1e8<<51198mg7=83.?=>4l3:l757<6921bn=4?:%627?e43g>:>7?=;:kbb?6=,=;86n=4n531>45<3`ih6=4+4019g6=i<881=954ib`94?"39:0h?6`;13821>=nkh0;6):>3;a0?k26:3;=76gl9;29 1742j90b9?=:058?le?290/8<=5c29m044=9110en950;&7569:9jg3<72->:?7m<;o626?7f32ch97>5$530>f55<#<891o>5a40095f=h39;0:h65f16c94?"39:0:;45a40094>=n9>21<7*;12823<=i<881=65f16594?"39:0:;45a40096>=zj<9i6=4>a083>5}#<;o1>594H51g?M2492P:?k4>0z6g>2>=?>03?79l:5c951<0>3=964n022>4=#9981?;o4$020>71a3g;:;7?4n01f>4=#9=:1>:h4n055>4=i9>h1=6`>9782?k4?>3;0b?o7:09'6g5=:020b?l;:09m720=82.8mi4:;o621?7<,=8=6?l<;%613?5fl2.???4;2e9'065=:k?0(9=;:24:?!24=39=h6a>o39l0;66g>8783>>o60=0;66a=b683>>o6010;66g;2383>>o5j?0;66g>8683>>o39o0;66g>8g83>>i6?=0;66g;1`83>>o6000;66a;2g83>>i4io0;66g;1b83>>o39k0;66g>8c83>>o3:90;66g>8483>>o60:0;66g>9383>>o60;0;66g;1e83>>i4?10;66g>8`83>>o60l0;66g>7483>>o6?:0;66g;2083>>o60m0;66g;2283>>ib;3:1(9?<:d08j1752910ch?50;&756;:mf4?6=,=;86h<4n531>7=h39;0876ake;29 1742l80b9?=:598kab=83.?=>4j2:l757<232eoo7>5$530>`46`;1384?>ici3:1(9?<:d08j1752110ci750;&756d=h39;0i76ak5;29 1742l80b9?=:b98ka2=83.?=>4j2:l7575$530>`46`;138e?>ic93:1(9?<:d08j17528:07bj?:18'045=m;1e8<<51098kf`=83.?=>4j2:l757<6:21doh4?:%627?c53g>:>7?<;:mff?6=,=;86h<4n531>42<3foj6=4+4019a7=i<881=854od;94?"39:0n>6`;13822>=hm10;6):>3;g1?k26:3;<76aj7;29 1742l80b9?=:0:8?jc1290/8<=5e39m044=9010ch;50;&756a:9la1<72->:?7k=;o626?7e32eo47>5$530>`45<#<891i?5a40095a=6=4+40197225<#<891?::4n531>4=5<#<891?::4n531>6=5<#<891?::4n531>0=5<#<891?i74n531>5=5<#<891?i74n531>7=54i2f6>5<#<891?i74n531>1=5<#<891?i74n531>3=5<#<891?i74n531>==5<#<891?i74n531>d=5<#<891?i74n531>f=5<#<891?i74n531>`=5<#<891?i74n531>46<3`9h;7>5$530>6b>3g>:>7?>;:k0g0<72->:?7=k9:l757<6:21b?n:50;&756<4l01e8<<51298m6e4290/8<=53e;8j17528>07d=l2;29 1742:n27c:>2;36?>o4k80;6):>3;1g=>h39;0::65f3b294?"39:08h45a400952=j6;o626?7>32c8ni4?:%627?5c12d?=?4>a:9j7ge=83.?=>4ln:18'045=;m30b9?=:0a8?l5e13:1(9?<:2f:?k26:3;o76g!26;39o56`;1382a>=n;k=1<7*;1280`<=i<881=k54i2`5>5<#<891?i74n531>76<3`9i97>5$530>6b>3g>:>7<>;:k0f1<72->:?7=k9:l757<5:21b?o=50;&756<4l01e8<<52298m6d5290/8<=53e;8j1752;>07d=m1;29 1742:n27c:>2;06?>o4m90;6):>3;1g=>h39;09:65f3ed94?"39:08h45a400962=j6;o626?4>32c8hn4?:%627?5c12d?=?4=a:9j7ad=83.?=>4j>:18'045=;m30b9?=:3a8?l5d>3:1(9?<:2f:?k26:38o76g!26;39o56`;1381a>=n;k:1<7*;1280`<=i<881>k54igd94?"39:0mi6`;1383?>oal3:1(9?<:gg8j1752810ekm50;&7566=5<#<891=;l4n531>4=5<#<891=;l4n531>6=5<#<891=;l4n531>0=6=4+401953d5<#<891=;l4n531>2=5<#<891=;l4n531><=5<#<891=;l4n531>g=5<#<891=;l4n531>a=5<#<891=;l4n531>c=4;h36=?6=,=;86<8m;o626?7632c:9:4?:%627?71j2d?=?4>2:9j500=83.?=>4>6c9m044=9:10e<;::18'045=9?h0b9?=:068?l72<3:1(9?<:04a?k26:3;>76g>5283>!26;3;=n6`;13822>=n9<81<7*;12822g=i<881=:54i072>5<#<891=;l4n531>4><3`;><7>5$530>40e3g>:>7?6;:k20c<72->:?7?9b:l757<6i21b=9k50;&756<6>k1e8<<51c98m42d290/8<=517`8j17528i07d?;b;29 174282;3g?>o63;35f>h39;0:i65f15;94?"39:0::o5a40095c=36=4+401953d4;h373?6=,=;86<8m;o626?4632c:8;4?:%627?71j2d?=?4=2:9j513=83.?=>4>6c9m044=::10e<:;:18'045=9?h0b9?=:368?l73;3:1(9?<:04a?k26:38>76g>7383>!26;3;=n6`;13812>=n9>;1<7*;12822g=i<881>:54i053>5<#<891=;l4n531>7><3`;=j7>5$530>40e3g>:>7<6;:k22`<72->:?7?9b:l757<5i21b=;j50;&756<6>k1e8<<52c98m404290/8<=517`8j1752;i07d?:8;29 174282;0g?>o63;35f>h39;09i65f15094?"39:0::o5a40096c=5<#<891=:h4n531>4=5<#<891=:h4n531>6=5<#<891>l84n531>4=5<#<891>l84n531>6=5<#<891=?>4n531>5=5<#<891=?>4n531>7=54i03`>5<#<891=?>4n531>1=5<#<891=?>4n531>3=5<#<891=?>4n531>==5<#<891=?>4n531>d=5<#<891=?>4n531>f=6=4+40195765<#<891=?>4n531>`=5<#<891=?>4n531>46<3`;:47>5$530>4473g>:>7?>;:k24a<72->:?7??c:l757<732c:;:k24d<72->:?7??c:l757<532c:<44?:%627?77k2d?=?4<;:k24=<72->:?7??c:l757<332c:<:4?:%627?77k2d?=?4:;:k243<72->:?7??c:l757<132c:<84?:%627?77k2d?=?48;:k253<72->:?7??c:l757:?7??c:l7574?:%627?77k2d?=?4m;:k257<72->:?7??c:l757:?7??c:l757:?7??c:l757<6821b==:50;&756<68j1e8<<51098k453290/8<=51218j1752910c<==:18'045=9:90b9?=:098k456290/8<=51218j1752;10c<=?:18'045=9:90b9?=:298k44a290/8<=51218j1752=10c<290/8<=51218j1752j10c<=7:18'045=9:90b9?=:e98k450290/8<=51218j1752l10c<=9:18'045=9:90b9?=:g98k452290/8<=51218j17528:07b?=b;29 17428987c:>2;32?>o6ih0;6):>3;3b=>h39;0;76g>a983>!26;3;j56`;1382?>o6i>0;6):>3;3b=>h39;0976g>a783>!26;3;j56`;1380?>o6i<0;6):>3;3b=>h39;0?76g>a283>!26;3;j56`;1386?>o6i;0;6):>3;3b=>h39;0=76g>a083>!26;3;j56`;1384?>o6i90;6):>3;3b=>h39;0376g>9g83>!26;3;j56`;138:?>o61l0;6):>3;3b=>h39;0j76g>9e83>!26;3;j56`;138a?>o61j0;6):>3;3b=>h39;0h76g>9c83>!26;3;j56`;138g?>o61h0;6):>3;3b=>h39;0n76g>b383>!26;3;j56`;138e?>o6j80;6):>3;3b=>h39;0:<65f1c294?"39:0:m45a400954=4:9j5de=83.?=>4>a89m044=9<10e9883>!26;3;j56`;1382<>=h;h?1<7*;1280e1=i<881<65`3`194?"39:08m95a40095>=h;h81<7*;1280e1=i<881>65`3`394?"39:08m95a40097>=h;h:1<7*;1280e1=i<881865`38d94?"39:08m95a40091>=h;0o1<7*;1280e1=i<881:65`38f94?"39:08m95a40093>=h;0h1<7*;1280e1=i<881465`38c94?"39:08m95a4009=>=h;031<7*;1280e1=i<881m65`38:94?"39:08m95a4009f>=h;0=1<7*;1280e1=i<881o65`38494?"39:08m95a4009`>=h;0?1<7*;1280e1=i<881i65`38694?"39:08m95a4009b>=h;091<7*;1280e1=i<881==54o2;1>5<#<891?l:4n531>47<3f92<7>5$530>6g33g>:>7?=;:m0:?7=n4:l757<6;21d?5k50;&756<4i=1e8<<51598k6>c290/8<=53`68j17528?07b=7c;29 1742:k?7c:>2;35?>i40k0;6):>3;1b0>h39;0:;65`39c94?"39:08m95a40095==o;;o626?7f32e84:4?:%627?5f<2d?=?4>b:9l7=3=83.?=>46;:18'045=;h>0b9?=:0f8?j5?;3:1(9?<:2c7?k26:3;n76a<8383>!26;39j86`;1382b>=h;1;1<7*;1280e1=i<881>=54o2:3>5<#<891?l:4n531>77<3f95$530>6g33g>:>7<=;:m03`<72->:?7=n4:l757<5;21d?:j50;&756<4i=1e8<<52598k61d290/8<=53`68j1752;?07b=nb;29 1742:k?7c:>2;05?>i4ih0;6):>3;1b0>h39;09;65`3`;94?"39:08m95a40096==o;;o626?4f32e8m;4?:%627?5f<2d?=?4=b:9l747>:18'045=;h>0b9?=:3f8?j5?>3:1(9?<:2c7?k26:38n76a<7c83>!26;39j86`;1381b>=ni=0;6):>3;c0?k26:3:07do=:18'045=i:1e8<<51:9je4<72->:?7o<;o626?4<3`k;6=4+4019e6=i<881?65f9g83>!26;3k87c:>2;68?l?b290/8<=5a29m044==21b5i4?:%627?g43g>:>784;h;`>5<#<891m>5a40093>=n1k0;6):>3;c0?k26:3207d7n:18'045=i:1e8<<59:9j==<72->:?7o<;o626?g<3`3<6=4+4019e6=i<881n65f9783>!26;3k87c:>2;a8?l?2290/8<=5a29m044=l21b594?:%627?g43g>:>7k4;h;0>5<#<891m>5a4009b>=n1;0;6):>3;c0?k26:3;;76g61;29 1742h90b9?=:038?l?7290/8<=5a29m044=9;10e5h50;&7563:9jef<72->:?7o<;o626?7332cjn7>5$530>d55<#<891m>5a400953=h39;0:;65fa983>!26;3k87c:>2;3;?>of?3:1(9?<:`18j17528307do9:18'045=i:1e8<<51`98md3=83.?=>4n3:l757<6j21b544?:%627?g43g>:>7?l;:k;a?6=,=;86l=4n531>4b<3f>;n7>5$530>16f3g>:>7>4;n63=?6=,=;869>n;o626?7<3f>;47>5$530>16f3g>:>7<4;n633?6=,=;869>n;o626?5<3f>;:7>5$530>16f3g>:>7:4;n631?6=,=;869>n;o626?3<3f>;87>5$530>16f3g>:>784;n637?6=,=;869>n;o626?1<3f>;=7>5$530>16f3g>:>764;n634?6=,=;869>n;o626??<3f9mj7>5$530>16f3g>:>7o4;n1ea?6=,=;869>n;o626?d<3f9mh7>5$530>16f3g>:>7m4;n1eg?6=,=;869>n;o626?b<3f9mn7>5$530>16f3g>:>7k4;n1ee?6=,=;869>n;o626?`<3f9m57>5$530>16f3g>:>7??;:m0b=<72->:?7:?a:l757<6921d?k850;&756<38h1e8<<51398k6`2290/8<=541c8j17528907b=i4;29 1742=:j7c:>2;37?>i4n:0;6):>3;63e>h39;0:965`3g094?"39:0?n;o626?7?32e8ik4?:%627?27i2d?=?4>9:9l7`c=83.?=>4;0`9m044=9h10c>kk:18'045=<9k0b9?=:0`8?j5bj3:1(9?<:52b?k26:3;h76a!26;3>;m6`;1382`>=h;l31<7*;12874d=i<881=h54o2g;>5<#<8918=o4n531>4`<3f9n;7>5$530>16f3g>:>7:?7:?a:l757<5921d?h;50;&756<38h1e8<<52398k6c3290/8<=541c8j1752;907b=j3;29 1742=:j7c:>2;07?>i4m;0;6):>3;63e>h39;09965`40394?"39:0?n;o626?4?32e?4;0`9m044=:h10c9>l:18'045=<9k0b9?=:3`8?j27:3:1(9?<:52b?k26:38h76a!26;3>;m6`;1381`>=h;li1<7*;12874d=i<881>h54o2g2>5<#<8918=o4n531>7`<3`i?6=4+4019g6=i<881<65fc383>!26;3i87c:>2;38?le6290/8<=5c29m044=:21bo=4?:%627?e43g>:>7=4;h`e>5<#<891o>5a40090>=njl0;6):>3;a0?k26:3?07dlk:18'045=k:1e8<<56:9jff<72->:?7m<;o626?1<3`hi6=4+4019g6=i<881465fb`83>!26;3i87c:>2;;8?ld?290/8<=5c29m044=i21bn:4?:%627?e43g>:>7l4;h`5>5<#<891o>5a4009g>=nj<0;6):>3;a0?k26:3n07dl;:18'045=k:1e8<<5e:9jf6<72->:?7m<;o626?`<3`h96=4+4019g6=i<881==54ic394?"39:0h?6`;13825>=nj90;6):>3;a0?k26:3;976gnf;29 1742j90b9?=:018?led290/8<=5c29m044=9=10enl50;&7565:9jgd<72->:?7m<;o626?7132ch57>5$530>f55<#<891o>5a40095==h39;0:565fc783>!26;3i87c:>2;3b?>od=3:1(9?<:b18j17528h07dl6:18'045=k:1e8<<51b98mdc=83.?=>4l3:l757<6l21b=:o50;&756<6?01e8<<50:9j52>=83.?=>4>789m044=921b=:950;&756<6?01e8<<52:9~f05d290:m<4?:1y'07c=:1=0D9=k;I605>\6;o0:13=?<0?47s+36595dc03gko6<5af`82?k7783:0b<>>:09'554=;?k0(<><:35e?k76?3;0b<=j:09'516=:>l0b<99:09m52d=92d:5;4>;o0;2?7"4im0>7c:>5;38 1412;h87):=7;1b`>"3;;0?>i5+42196g3<,=9?6>86;%601?51l2e8mh4?::k75`<722c:4;4?::k2<1<722e9n:4?::k2<=<722c?>?4?::k1f3<722c:4:4?::k75c<722c:4k4?::m231<722c?=l4?::k2<<<722e?>k4?::m0ec<722c?=n4?::k75g<722c:4o4?::k765<722c:484?::k2<6<722c:5?4?::k2<7<722c?=i4?::m03=<722c:4l4?::k2<`<722c:;84?::k236<722c?><4?::k2>4?::mf7?6=,=;86h<4n531>5=h39;0:76aj0;29 1742l80b9?=:398ka`=83.?=>4j2:l757<432eoi7>5$530>`46`;1386?>ick3:1(9?<:d08j1752?10cil50;&756==h39;0276ak7;29 1742l80b9?=:`98ka0=83.?=>4j2:l7575$530>`46`;138g?>ic;3:1(9?<:d08j1752l10ci<50;&75646<3fn;6=4+4019a7=i<881=<54obd94?"39:0n>6`;13826>=hkl0;6):>3;g1?k26:3;876ajb;29 1742l80b9?=:068?jcf290/8<=5e39m044=9<10ch750;&7566:9la=<72->:?7k=;o626?7032en;7>5$530>`45<#<891i?5a40095<=h39;0:m65`e583>!26;3o97c:>2;3a?>ic03:1(9?<:d08j17528i07bmk:18'045=m;1e8<<51e98m612290/8<=53668j1752910e>9<:18'045=;>>0b9?=:098m615290/8<=53668j1752;10e>9>:18'045=;>>0b9?=:298m617290/8<=53668j1752=10e>8i:18'045=;>>0b9?=:498m60b290/8<=53668j1752?10e>jn:18'045=;m30b9?=:198m6b?290/8<=53e;8j1752810e>j8:18'045=;m30b9?=:398m6b1290/8<=53e;8j1752:10e>j::18'045=;m30b9?=:598m6b3290/8<=53e;8j1752<10e>j<:18'045=;m30b9?=:798m6b5290/8<=53e;8j1752>10e>j?:18'045=;m30b9?=:998m6ea290/8<=53e;8j1752010e>mj:18'045=;m30b9?=:`98m6ec290/8<=53e;8j1752k10e>ml:18'045=;m30b9?=:b98m6ee290/8<=53e;8j1752m10e>mn:18'045=;m30b9?=:d98m6e>290/8<=53e;8j1752o10e>m7:18'045=;m30b9?=:028?l5d?3:1(9?<:2f:?k26:3;:76g!26;39o56`;13826>=n;j>1<7*;1280`<=i<881=>54i2a0>5<#<891?i74n531>42<3`9h>7>5$530>6b>3g>:>7?:;:k0g4<72->:?7=k9:l757<6>21b?n>50;&756<4l01e8<<51698m6da290/8<=53e;8j17528207d=me;29 1742:n27c:>2;3:?>o4jm0;6):>3;1g=>h39;0:m65f3ca94?"39:08h45a40095g=j6;o626?7c32c8n54?:%627?5c12d?=?4>e:9j7g1=83.?=>4l9:18'045=;m30b9?=:328?l5e=3:1(9?<:2f:?k26:38:76g!26;39o56`;13816>=n;k91<7*;1280`<=i<881>>54i2`1>5<#<891?i74n531>72<3`9i=7>5$530>6b>3g>:>7<:;:k0a5<72->:?7=k9:l757<5>21b?ih50;&756<4l01e8<<52698m6bb290/8<=53e;8j1752;207d=kd;29 1742:n27c:>2;0:?>o4lj0;6):>3;1g=>h39;09m65f3e`94?"39:08h45a40096g=j6;o626?4c32c8no4?:%627?5c12d?=?4=e:9j7g6=83.?=>44=h39;0976gib;29 1742oo0b9?=:298m40d290/8<=517`8j1752910e<8n:18'045=9?h0b9?=:098m40>290/8<=517`8j1752;10e<87:18'045=9?h0b9?=:298m400290/8<=517`8j1752=10e<89:18'045=9?h0b9?=:498m402290/8<=517`8j1752?10e<8;:18'045=9?h0b9?=:698m405290/8<=517`8j1752110e<8>:18'045=9?h0b9?=:898m407290/8<=517`8j1752h10e<;i:18'045=9?h0b9?=:c98m43b290/8<=517`8j1752j10e<;k:18'045=9?h0b9?=:e98m43d290/8<=517`8j1752l10e<;m:18'045=9?h0b9?=:g98m43f290/8<=517`8j17528:07d?:9;29 174282;32?>o6=>0;6):>3;35f>h39;0:>65f14494?"39:0::o5a400956=6=4+401953d4?:%627?71j2d?=?4>6:9j504=83.?=>4>6c9m044=9>10e<;>:18'045=9?h0b9?=:0:8?l7283:1(9?<:04a?k26:3;276g>4g83>!26;3;=n6`;1382e>=n9=o1<7*;12822g=i<881=o54i06`>5<#<891=;l4n531>4e<3`;?n7>5$530>40e3g>:>7?k;:k20d<72->:?7?9b:l757<6m21b=9750;&756<6>k1e8<<51g98m42?290/8<=517`8j1752;:07d?;7;29 174282;02?>o63;35f>h39;09>65f15794?"39:0::o5a400966=?6=4+401953d4>6c9m044=:>10e<9?:18'045=9?h0b9?=:3:8?l71n3:1(9?<:04a?k26:38276g>6d83>!26;3;=n6`;1381e>=n9?n1<7*;12822g=i<881>o54i040>5<#<891=;l4n531>7e<3`;>47>5$530>40e3g>:>7:?7?9b:l757<5m21b=9<50;&756<6>k1e8<<52g98k4>7290/8<=516d8j1752910c<9j:18'045=9>l0b9?=:098k41c290/8<=516d8j1752;10c<9l:18'045=9>l0b9?=:298m7g0290/8<=52`48j1752910e?o::18'045=:h<0b9?=:098m7g3290/8<=52`48j1752;10e?o<:18'045=:h<0b9?=:298m7g5290/8<=52`48j1752=10e<<>:18'045=9;:0b9?=:198m47a290/8<=51328j1752810e290/8<=51328j1752>10e<290/8<=51328j1752010e<<7:18'045=9;:0b9?=:`98m440290/8<=51328j1752k10e<<9:18'045=9;:0b9?=:b98m442290/8<=51328j1752m10e<<;:18'045=9;:0b9?=:d98m444290/8<=51328j1752o10e<<=:18'045=9;:0b9?=:028?l7603:1(9?<:003?k26:3;:76g>0e83>!26;3;;o6`;1383?>o68k0;6):>3;33g>h39;0:76g>0`83>!26;3;;o6`;1381?>o6800;6):>3;33g>h39;0876g>0983>!26;3;;o6`;1387?>o68>0;6):>3;33g>h39;0>76g>0783>!26;3;;o6`;1385?>o68<0;6):>3;33g>h39;0<76g>1783>!26;3;;o6`;138;?>o69<0;6):>3;33g>h39;0276g>1583>!26;3;;o6`;138b?>o69:0;6):>3;33g>h39;0i76g>1383>!26;3;;o6`;138`?>o6980;6):>3;33g>h39;0o76g>1183>!26;3;;o6`;138f?>o68o0;6):>3;33g>h39;0m76g>0d83>!26;3;;o6`;13824>=n99>1<7*;12824f=i<881=<54o017>5<#<891=>=4n531>5=5<#<891=>=4n531>7=54o00e>5<#<891=>=4n531>1=5<#<891=>=4n531>3=5<#<891=>=4n531>==5<#<891=>=4n531>d=5<#<891=>=4n531>f=5<#<891=>=4n531>`=5<#<891=>=4n531>46<3f;9n7>5$530>4543g>:>7?>;:k2ed<72->:?7?n9:l757<732c:m54?:%627?7f12d?=?4>;:k2e2<72->:?7?n9:l757<532c:m;4?:%627?7f12d?=?4<;:k2e0<72->:?7?n9:l757<332c:m>4?:%627?7f12d?=?4:;:k2e7<72->:?7?n9:l757<132c:m<4?:%627?7f12d?=?48;:k2e5<72->:?7?n9:l757:?7?n9:l757:?7?n9:l757:?7?n9:l757:?7?n9:l757<6821b=o>50;&756<6i01e8<<51098m4ga290/8<=51`;8j17528807d?ne;29 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17428k27c:>2;34?>o6100;6):>3;3b=>h39;0:465`3`794?"39:08m95a40094>=h;h91<7*;1280e1=i<881=65`3`094?"39:08m95a40096>=h;h;1<7*;1280e1=i<881?65`3`294?"39:08m95a40090>=h;0l1<7*;1280e1=i<881965`38g94?"39:08m95a40092>=h;0n1<7*;1280e1=i<881;65`38`94?"39:08m95a4009<>=h;0k1<7*;1280e1=i<881565`38;94?"39:08m95a4009e>=h;021<7*;1280e1=i<881n65`38594?"39:08m95a4009g>=h;0<1<7*;1280e1=i<881h65`38794?"39:08m95a4009a>=h;0>1<7*;1280e1=i<881j65`38194?"39:08m95a400955=o;;o626?7532e84k4?:%627?5f<2d?=?4>3:9l7=c=83.?=>46k:18'045=;h>0b9?=:078?j5?k3:1(9?<:2c7?k26:3;=76a<8c83>!26;39j86`;13823>=h;1k1<7*;1280e1=i<881=554o2::>5<#<891?l:4n531>4?<3f9347>5$530>6g33g>:>7?n;:m0<2<72->:?7=n4:l757<6j21d?5;50;&756<4i=1e8<<51b98k6>3290/8<=53`68j17528n07b=73;29 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1742h90b9?=:0;8?lg1290/8<=5a29m044=9h10el;50;&756b:9j=<<72->:?7o<;o626?7d32c3i7>5$530>d5n;o626?6<3f>;57>5$530>16f3g>:>7?4;n63n;o626?4<3f>;;7>5$530>16f3g>:>7=4;n632?6=,=;869>n;o626?2<3f>;97>5$530>16f3g>:>7;4;n630?6=,=;869>n;o626?0<3f>;?7>5$530>16f3g>:>794;n635?6=,=;869>n;o626?><3f>;<7>5$530>16f3g>:>774;n1eb?6=,=;869>n;o626?g<3f9mi7>5$530>16f3g>:>7l4;n1e`?6=,=;869>n;o626?e<3f9mo7>5$530>16f3g>:>7j4;n1ef?6=,=;869>n;o626?c<3f9mm7>5$530>16f3g>:>7h4;n1e=?6=,=;869>n;o626?7732e8j54?:%627?27i2d?=?4>1:9l7c0=83.?=>4;0`9m044=9;10c>h::18'045=<9k0b9?=:018?j5a<3:1(9?<:52b?k26:3;?76a!26;3>;m6`;13821>=h;o81<7*;12874d=i<881=;54o2d2>5<#<8918=o4n531>41<3f9m<7>5$530>16f3g>:>7?7;:m0ac<72->:?7:?a:l757<6121d?hk50;&756<38h1e8<<51`98k6cc290/8<=541c8j17528h07b=jb;29 1742=:j7c:>2;3`?>i4mh0;6):>3;63e>h39;0:h65`3d;94?"39:0?n;o626?4732e8i;4?:%627?27i2d?=?4=1:9l7`3=83.?=>4;0`9m044=:;10c>k;:18'045=<9k0b9?=:318?j5b;3:1(9?<:52b?k26:38?76a!26;3>;m6`;13811>=h<8;1<7*;12874d=i<881>;54o533>5<#<8918=o4n531>71<3f>;j7>5$530>16f3g>:>7<7;:m74`<72->:?7:?a:l757<5121d8=j50;&756<38h1e8<<52`98k16d290/8<=541c8j1752;h07b:?2;29 1742=:j7c:>2;0`?>i4n>0;6):>3;63e>h39;09h65`3da94?"39:0?5<#<891o>5a40094>=nk;0;6):>3;a0?k26:3;07dm>:18'045=k:1e8<<52:9jg5<72->:?7m<;o626?5<3`hm6=4+4019g6=i<881865fbd83>!26;3i87c:>2;78?ldc290/8<=5c29m044=>21bnn4?:%627?e43g>:>794;h`a>5<#<891o>5a4009<>=njh0;6):>3;a0?k26:3307dl7:18'045=k:1e8<<5a:9jf2<72->:?7m<;o626?d<3`h=6=4+4019g6=i<881o65fb483>!26;3i87c:>2;f8?ld3290/8<=5c29m044=m21bn>4?:%627?e43g>:>7h4;h`1>5<#<891o>5a400955=h39;0:=65fb183>!26;3i87c:>2;31?>ofn3:1(9?<:b18j17528907dml:18'045=k:1e8<<51598mfd=83.?=>4l3:l757<6=21bol4?:%627?e43g>:>7?9;:k`=?6=,=;86n=4n531>41<3`i36=4+4019g6=i<881=554ib594?"39:0h?6`;1382=>=nk?0;6):>3;a0?k26:3;j76gl5;29 1742j90b9?=:0`8?ld>290/8<=5c29m044=9j10elk50;&756d:9j52g=83.?=>4>789m044=821b=:650;&756<6?01e8<<51:9j521=83.?=>4>789m044=:21vn8=j:182e4<729q/8?k52958L15c3A>8=6T>3g824~2c2>21;:473;5`>1g=9=0<:79=:0390<<083;;69;57487=1=lk8;ocg>4=inh0:7c??0;28j466281/==<537c8 4642;=m7c?>7;38j45b281/=9>526d8j411281e=:l51:l2=3<63g83:7?4n3c;>4=#:k91>464n3`7>4=i;><1<6*o;4$517>60>3->897=9d:m0e`<722c?=h4?::k2<3<722c:494?::m1f2<722c:454?::k767<722c9n;4?::k2<2<722c?=k4?::k2=4?::k2<0<722c:4>4?::k2=7<722c:4?4?::k75a<722e8;54?::k24?::k764<722c:4i4?::k766<722en?7>5$530>`46`;1382?>ib83:1(9?<:d08j1752;10cih50;&7561=h39;0>76akc;29 1742l80b9?=:798kad=83.?=>4j2:l757<032eom7>5$530>`46`;138:?>ic?3:1(9?<:d08j1752h10ci850;&756f=1<7*;128f6>h39;0o76ak3;29 1742l80b9?=:d98ka4=83.?=>4j2:l7575$530>`44;nf3>5<#<891i?5a400954=h39;0:>65`cd83>!26;3o97c:>2;30?>ibj3:1(9?<:d08j17528>07bkn:18'045=m;1e8<<51498k`?=83.?=>4j2:l757<6>21di54?:%627?c53g>:>7?8;:mf3?6=,=;86h<4n531>4><3fo=6=4+4019a7=i<881=454od794?"39:0n>6`;1382e>=hm=0;6):>3;g1?k26:3;i76ak8;29 1742l80b9?=:0a8?jec290/8<=5e39m044=9m10e>9::18'045=;>>0b9?=:198m614290/8<=53668j1752810e>9=:18'045=;>>0b9?=:398m616290/8<=53668j1752:10e>9?:18'045=;>>0b9?=:598m60a290/8<=53668j1752<10e>8j:18'045=;>>0b9?=:798m6bf290/8<=53e;8j1752910e>j7:18'045=;m30b9?=:098m6b0290/8<=53e;8j1752;10e>j9:18'045=;m30b9?=:298m6b2290/8<=53e;8j1752=10e>j;:18'045=;m30b9?=:498m6b4290/8<=53e;8j1752?10e>j=:18'045=;m30b9?=:698m6b7290/8<=53e;8j1752110e>mi:18'045=;m30b9?=:898m6eb290/8<=53e;8j1752h10e>mk:18'045=;m30b9?=:c98m6ed290/8<=53e;8j1752j10e>mm:18'045=;m30b9?=:e98m6ef290/8<=53e;8j1752l10e>m6:18'045=;m30b9?=:g98m6e?290/8<=53e;8j17528:07d=l7;29 1742:n27c:>2;32?>o4k<0;6):>3;1g=>h39;0:>65f3b694?"39:08h45a400956=j6;o626?7232c8o<4?:%627?5c12d?=?4>6:9j7f6=83.?=>410e>li:18'045=;m30b9?=:0:8?l5em3:1(9?<:2f:?k26:3;276g!26;39o56`;1382e>=n;ki1<7*;1280`<=i<881=o54i2`b>5<#<891?i74n531>4e<3`9i57>5$530>6b>3g>:>7?k;:k0f=<72->:?7=k9:l757<6m21b?o950;&756<4l01e8<<51g98m6d1290/8<=53e;8j1752;:07d=m5;29 1742:n27c:>2;02?>o4j=0;6):>3;1g=>h39;09>65f3c194?"39:08h45a400966=j6;o626?4232c8i=4?:%627?5c12d?=?4=6:9j7a`=83.?=>410e>jj:18'045=;m30b9?=:3:8?l5cl3:1(9?<:2f:?k26:38276g!26;39o56`;1381e>=n;mh1<7*;1280`<=i<881>o54i2f2>5<#<891?i74n531>7e<3`9h:7>5$530>6b>3g>:>7:?7=k9:l757<5m21b?o>50;&756<4l01e8<<52g98mc`=83.?=>4ie:l757<732cmh7>5$530>ccoaj3:1(9?<:gg8j1752:10e<8l:18'045=9?h0b9?=:198m40f290/8<=517`8j1752810e<86:18'045=9?h0b9?=:398m40?290/8<=517`8j1752:10e<88:18'045=9?h0b9?=:598m401290/8<=517`8j1752<10e<8::18'045=9?h0b9?=:798m403290/8<=517`8j1752>10e<8=:18'045=9?h0b9?=:998m406290/8<=517`8j1752010e<8?:18'045=9?h0b9?=:`98m43a290/8<=517`8j1752k10e<;j:18'045=9?h0b9?=:b98m43c290/8<=517`8j1752m10e<;l:18'045=9?h0b9?=:d98m43e290/8<=517`8j1752o10e<;n:18'045=9?h0b9?=:028?l7213:1(9?<:04a?k26:3;:76g>5683>!26;3;=n6`;13826>=n9<<1<7*;12822g=i<881=>54i076>5<#<891=;l4n531>42<3`;>87>5$530>40e3g>:>7?:;:k216<72->:?7?9b:l757<6>21b=8<50;&756<6>k1e8<<51698m436290/8<=517`8j17528207d?:0;29 174282;3:?>o63;35f>h39;0:m65f15g94?"39:0::o5a40095g=h6=4+401953de:9j51?=83.?=>4>6c9m044=9o10e<:7:18'045=9?h0b9?=:328?l73?3:1(9?<:04a?k26:38:76g>4783>!26;3;=n6`;13816>=n9=?1<7*;12822g=i<881>>54i067>5<#<891=;l4n531>72<3`;??7>5$530>40e3g>:>7<:;:k237<72->:?7?9b:l757<5>21b=:?50;&756<6>k1e8<<52698m417290/8<=517`8j1752;207d?9f;29 174282;0:?>o6>l0;6):>3;35f>h39;09m65f17f94?"39:0::o5a40096g=4>6c9m044=:o10c<6?:18'045=9>l0b9?=:198k41b290/8<=516d8j1752810c<9k:18'045=9>l0b9?=:398k41d290/8<=516d8j1752:10e?o8:18'045=:h<0b9?=:198m7g2290/8<=52`48j1752810e?o;:18'045=:h<0b9?=:398m7g4290/8<=52`48j1752:10e?o=:18'045=:h<0b9?=:598m446290/8<=51328j1752910e8;29 174288;7c:>2;32?>o68m0;6):>3;33g>h39;0;76g>0c83>!26;3;;o6`;1382?>o68h0;6):>3;33g>h39;0976g>0883>!26;3;;o6`;1380?>o6810;6):>3;33g>h39;0?76g>0683>!26;3;;o6`;1386?>o68?0;6):>3;33g>h39;0=76g>0483>!26;3;;o6`;1384?>o69?0;6):>3;33g>h39;0376g>1483>!26;3;;o6`;138:?>o69=0;6):>3;33g>h39;0j76g>1283>!26;3;;o6`;138a?>o69;0;6):>3;33g>h39;0h76g>1083>!26;3;;o6`;138g?>o6990;6):>3;33g>h39;0n76g>0g83>!26;3;;o6`;138e?>o68l0;6):>3;33g>h39;0:<65f11694?"39:0:5<#<891=>=4n531>4=5<#<891=>=4n531>6=5<#<891=>=4n531>0=5<#<891=>=4n531>2=5<#<891=>=4n531><=5<#<891=>=4n531>g=5<#<891=>=4n531>a=5<#<891=>=4n531>c=6=4+40195654;n31f?6=,=;86<=<;o626?7632c:ml4?:%627?7f12d?=?4?;:k2e=<72->:?7?n9:l757<632c:m:4?:%627?7f12d?=?4=;:k2e3<72->:?7?n9:l757<432c:m84?:%627?7f12d?=?4;;:k2e6<72->:?7?n9:l757<232c:m?4?:%627?7f12d?=?49;:k2e4<72->:?7?n9:l757<032c:m=4?:%627?7f12d?=?47;:k2=c<72->:?7?n9:l757<>32c:5h4?:%627?7f12d?=?4n;:k2=a<72->:?7?n9:l757:?7?n9:l757:?7?n9:l7570:9j5g6=83.?=>4>a89m044=9810eae83>!26;3;j56`;13820>=n9hi1<7*;1282e<=i<881=854i0ca>5<#<891=l74n531>40<3`;j87>5$530>4g>3g>:>7?8;:k2=<<72->:?7?n9:l757<6021d?l;50;&756<4i=1e8<<50:9l7d5=83.?=>4450;&756<4i=1e8<<54:9l7<`=83.?=>444=83.?=>4442;31?>i40o0;6):>3;1b0>h39;0:?65`39g94?"39:08m95a400951=o;;o626?7132e84o4?:%627?5f<2d?=?4>7:9l7=g=83.?=>466:18'045=;h>0b9?=:0;8?j5?03:1(9?<:2c7?k26:3;j76a<8683>!26;39j86`;1382f>=h;1?1<7*;1280e1=i<881=n54o2:7>5<#<891?l:4n531>4b<3f93?7>5$530>6g33g>:>7?j;:m0<7<72->:?7=n4:l757<6n21d?5?50;&756<4i=1e8<<52198k6>7290/8<=53`68j1752;;07b=8f;29 1742:k?7c:>2;01?>i4?l0;6):>3;1b0>h39;09?65`36f94?"39:08m95a400961=o;;o626?4132e8ml4?:%627?5f<2d?=?4=7:9l7d?=83.?=>4o7:18'045=;h>0b9?=:3;8?j5f?3:1(9?<:2c7?k26:38j76a!26;39j86`;1381f>=h;0i1<7*;1280e1=i<881>n54o2;2>5<#<891?l:4n531>7b<3f93:7>5$530>6g33g>:>7:?7=n4:l757<5n21bm94?:%627?g43g>:>7>4;hc1>5<#<891m>5a40095>=ni80;6):>3;c0?k26:3807do?:18'045=i:1e8<<53:9j=c<72->:?7o<;o626?2<3`3n6=4+4019e6=i<881965f9e83>!26;3k87c:>2;48?l?d290/8<=5a29m044=?21b5o4?:%627?g43g>:>764;h;b>5<#<891m>5a4009=>=n110;6):>3;c0?k26:3k07d78:18'045=i:1e8<<5b:9j=3<72->:?7o<;o626?e<3`3>6=4+4019e6=i<881h65f9583>!26;3k87c:>2;g8?l?4290/8<=5a29m044=n21b5?4?:%627?g43g>:>7??;:k:5?6=,=;86l=4n531>47<3`3;6=4+4019e6=i<881=?54i9d94?"39:0j?6`;13827>=nij0;6):>3;c0?k26:3;?76gnb;29 1742h90b9?=:078?lgf290/8<=5a29m044=9?10el750;&7567:9je=<72->:?7o<;o626?7?32cj;7>5$530>d55<#<891m>5a40095d=h39;0:n65f9883>!26;3k87c:>2;3`?>o?m3:1(9?<:`18j17528n07b:?b;29 1742=:j7c:>2;28?j2713:1(9?<:52b?k26:3;07b:?8;29 1742=:j7c:>2;08?j27?3:1(9?<:52b?k26:3907b:?6;29 1742=:j7c:>2;68?j27=3:1(9?<:52b?k26:3?07b:?4;29 1742=:j7c:>2;48?j27;3:1(9?<:52b?k26:3=07b:?1;29 1742=:j7c:>2;:8?j2783:1(9?<:52b?k26:3307b=if;29 1742=:j7c:>2;c8?j5am3:1(9?<:52b?k26:3h07b=id;29 1742=:j7c:>2;a8?j5ak3:1(9?<:52b?k26:3n07b=ib;29 1742=:j7c:>2;g8?j5ai3:1(9?<:52b?k26:3l07b=i9;29 1742=:j7c:>2;33?>i4n10;6):>3;63e>h39;0:=65`3g494?"39:0?6=4+401905gn;o626?7332e8j>4?:%627?27i2d?=?4>5:9l7c4=83.?=>4;0`9m044=9?10c>h>:18'045=<9k0b9?=:058?j5a83:1(9?<:52b?k26:3;376a!26;3>;m6`;1382=>=h;lo1<7*;12874d=i<881=l54o2gg>5<#<8918=o4n531>4d<3f9nn7>5$530>16f3g>:>7?l;:m0ad<72->:?7:?a:l757<6l21d?h750;&756<38h1e8<<51d98k6c?290/8<=541c8j17528l07b=j7;29 1742=:j7c:>2;03?>i4m?0;6):>3;63e>h39;09=65`3d794?"39:0?n;o626?4332e8i?4?:%627?27i2d?=?4=5:9l047=83.?=>4;0`9m044=:?10c9??:18'045=<9k0b9?=:358?j27n3:1(9?<:52b?k26:38376a;0d83>!26;3>;m6`;1381=>=h<9n1<7*;12874d=i<881>l54o52`>5<#<8918=o4n531>7d<3f>;>7>5$530>16f3g>:>7:?7:?a:l757<5l21d?hm50;&756<38h1e8<<52d98k6c6290/8<=541c8j1752;l07dm;:18'045=k:1e8<<50:9jg7<72->:?7m<;o626?7<3`i:6=4+4019g6=i<881>65fc183>!26;3i87c:>2;18?lda290/8<=5c29m044=<21bnh4?:%627?e43g>:>7;4;h`g>5<#<891o>5a40092>=njj0;6):>3;a0?k26:3=07dlm:18'045=k:1e8<<58:9jfd<72->:?7m<;o626??<3`h36=4+4019g6=i<881m65fb683>!26;3i87c:>2;`8?ld1290/8<=5c29m044=k21bn84?:%627?e43g>:>7j4;h`7>5<#<891o>5a4009a>=nj:0;6):>3;a0?k26:3l07dl=:18'045=k:1e8<<51198mg7=83.?=>4l3:l757<6921bn=4?:%627?e43g>:>7?=;:kbb?6=,=;86n=4n531>45<3`ih6=4+4019g6=i<881=954ib`94?"39:0h?6`;13821>=nkh0;6):>3;a0?k26:3;=76gl9;29 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1742l80b9?=:b98ka2=83.?=>4j2:l7575$530>`46`;138e?>ic93:1(9?<:d08j17528:07bj?:18'045=m;1e8<<51098kf`=83.?=>4j2:l757<6:21doh4?:%627?c53g>:>7?<;:mff?6=,=;86h<4n531>42<3foj6=4+4019a7=i<881=854od;94?"39:0n>6`;13822>=hm10;6):>3;g1?k26:3;<76aj7;29 1742l80b9?=:0:8?jc1290/8<=5e39m044=9010ch;50;&756a:9la1<72->:?7k=;o626?7e32eo47>5$530>`45<#<891i?5a40095a=6=4+40197225<#<891?::4n531>4=5<#<891?::4n531>6=5<#<891?::4n531>0=5<#<891?i74n531>5=5<#<891?i74n531>7=54i2f6>5<#<891?i74n531>1=5<#<891?i74n531>3=5<#<891?i74n531>==5<#<891?i74n531>d=5<#<891?i74n531>f=5<#<891?i74n531>`=5<#<891?i74n531>46<3`9h;7>5$530>6b>3g>:>7?>;:k0g0<72->:?7=k9:l757<6:21b?n:50;&756<4l01e8<<51298m6e4290/8<=53e;8j17528>07d=l2;29 1742:n27c:>2;36?>o4k80;6):>3;1g=>h39;0::65f3b294?"39:08h45a400952=j6;o626?7>32c8ni4?:%627?5c12d?=?4>a:9j7ge=83.?=>4ln:18'045=;m30b9?=:0a8?l5e13:1(9?<:2f:?k26:3;o76g!26;39o56`;1382a>=n;k=1<7*;1280`<=i<881=k54i2`5>5<#<891?i74n531>76<3`9i97>5$530>6b>3g>:>7<>;:k0f1<72->:?7=k9:l757<5:21b?o=50;&756<4l01e8<<52298m6d5290/8<=53e;8j1752;>07d=m1;29 1742:n27c:>2;06?>o4m90;6):>3;1g=>h39;09:65f3ed94?"39:08h45a400962=j6;o626?4>32c8hn4?:%627?5c12d?=?4=a:9j7ad=83.?=>4j>:18'045=;m30b9?=:3a8?l5d>3:1(9?<:2f:?k26:38o76g!26;39o56`;1381a>=n;k:1<7*;1280`<=i<881>k54igd94?"39:0mi6`;1383?>oal3:1(9?<:gg8j1752810ekm50;&7566=5<#<891=;l4n531>4=5<#<891=;l4n531>6=5<#<891=;l4n531>0=6=4+401953d5<#<891=;l4n531>2=5<#<891=;l4n531><=5<#<891=;l4n531>g=5<#<891=;l4n531>a=5<#<891=;l4n531>c=4;h36=?6=,=;86<8m;o626?7632c:9:4?:%627?71j2d?=?4>2:9j500=83.?=>4>6c9m044=9:10e<;::18'045=9?h0b9?=:068?l72<3:1(9?<:04a?k26:3;>76g>5283>!26;3;=n6`;13822>=n9<81<7*;12822g=i<881=:54i072>5<#<891=;l4n531>4><3`;><7>5$530>40e3g>:>7?6;:k20c<72->:?7?9b:l757<6i21b=9k50;&756<6>k1e8<<51c98m42d290/8<=517`8j17528i07d?;b;29 174282;3g?>o63;35f>h39;0:i65f15;94?"39:0::o5a40095c=36=4+401953d4;h373?6=,=;86<8m;o626?4632c:8;4?:%627?71j2d?=?4=2:9j513=83.?=>4>6c9m044=::10e<:;:18'045=9?h0b9?=:368?l73;3:1(9?<:04a?k26:38>76g>7383>!26;3;=n6`;13812>=n9>;1<7*;12822g=i<881>:54i053>5<#<891=;l4n531>7><3`;=j7>5$530>40e3g>:>7<6;:k22`<72->:?7?9b:l757<5i21b=;j50;&756<6>k1e8<<52c98m404290/8<=517`8j1752;i07d?:8;29 174282;0g?>o63;35f>h39;09i65f15094?"39:0::o5a40096c=5<#<891=:h4n531>4=5<#<891=:h4n531>6=5<#<891>l84n531>4=5<#<891>l84n531>6=5<#<891=?>4n531>5=5<#<891=?>4n531>7=54i03`>5<#<891=?>4n531>1=5<#<891=?>4n531>3=5<#<891=?>4n531>==5<#<891=?>4n531>d=5<#<891=?>4n531>f=6=4+40195765<#<891=?>4n531>`=5<#<891=?>4n531>46<3`;:47>5$530>4473g>:>7?>;:k24a<72->:?7??c:l757<732c:;:k24d<72->:?7??c:l757<532c:<44?:%627?77k2d?=?4<;:k24=<72->:?7??c:l757<332c:<:4?:%627?77k2d?=?4:;:k243<72->:?7??c:l757<132c:<84?:%627?77k2d?=?48;:k253<72->:?7??c:l757:?7??c:l7574?:%627?77k2d?=?4m;:k257<72->:?7??c:l757:?7??c:l757:?7??c:l757<6821b==:50;&756<68j1e8<<51098k453290/8<=51218j1752910c<==:18'045=9:90b9?=:098k456290/8<=51218j1752;10c<=?:18'045=9:90b9?=:298k44a290/8<=51218j1752=10c<290/8<=51218j1752j10c<=7:18'045=9:90b9?=:e98k450290/8<=51218j1752l10c<=9:18'045=9:90b9?=:g98k452290/8<=51218j17528:07b?=b;29 17428987c:>2;32?>o6ih0;6):>3;3b=>h39;0;76g>a983>!26;3;j56`;1382?>o6i>0;6):>3;3b=>h39;0976g>a783>!26;3;j56`;1380?>o6i<0;6):>3;3b=>h39;0?76g>a283>!26;3;j56`;1386?>o6i;0;6):>3;3b=>h39;0=76g>a083>!26;3;j56`;1384?>o6i90;6):>3;3b=>h39;0376g>9g83>!26;3;j56`;138:?>o61l0;6):>3;3b=>h39;0j76g>9e83>!26;3;j56`;138a?>o61j0;6):>3;3b=>h39;0h76g>9c83>!26;3;j56`;138g?>o61h0;6):>3;3b=>h39;0n76g>b383>!26;3;j56`;138e?>o6j80;6):>3;3b=>h39;0:<65f1c294?"39:0:m45a400954=4:9j5de=83.?=>4>a89m044=9<10e9883>!26;3;j56`;1382<>=h;h?1<7*;1280e1=i<881<65`3`194?"39:08m95a40095>=h;h81<7*;1280e1=i<881>65`3`394?"39:08m95a40097>=h;h:1<7*;1280e1=i<881865`38d94?"39:08m95a40091>=h;0o1<7*;1280e1=i<881:65`38f94?"39:08m95a40093>=h;0h1<7*;1280e1=i<881465`38c94?"39:08m95a4009=>=h;031<7*;1280e1=i<881m65`38:94?"39:08m95a4009f>=h;0=1<7*;1280e1=i<881o65`38494?"39:08m95a4009`>=h;0?1<7*;1280e1=i<881i65`38694?"39:08m95a4009b>=h;091<7*;1280e1=i<881==54o2;1>5<#<891?l:4n531>47<3f92<7>5$530>6g33g>:>7?=;:m0:?7=n4:l757<6;21d?5k50;&756<4i=1e8<<51598k6>c290/8<=53`68j17528?07b=7c;29 1742:k?7c:>2;35?>i40k0;6):>3;1b0>h39;0:;65`39c94?"39:08m95a40095==o;;o626?7f32e84:4?:%627?5f<2d?=?4>b:9l7=3=83.?=>46;:18'045=;h>0b9?=:0f8?j5?;3:1(9?<:2c7?k26:3;n76a<8383>!26;39j86`;1382b>=h;1;1<7*;1280e1=i<881>=54o2:3>5<#<891?l:4n531>77<3f95$530>6g33g>:>7<=;:m03`<72->:?7=n4:l757<5;21d?:j50;&756<4i=1e8<<52598k61d290/8<=53`68j1752;?07b=nb;29 1742:k?7c:>2;05?>i4ih0;6):>3;1b0>h39;09;65`3`;94?"39:08m95a40096==o;;o626?4f32e8m;4?:%627?5f<2d?=?4=b:9l747>:18'045=;h>0b9?=:3f8?j5?>3:1(9?<:2c7?k26:38n76a<7c83>!26;39j86`;1381b>=ni=0;6):>3;c0?k26:3:07do=:18'045=i:1e8<<51:9je4<72->:?7o<;o626?4<3`k;6=4+4019e6=i<881?65f9g83>!26;3k87c:>2;68?l?b290/8<=5a29m044==21b5i4?:%627?g43g>:>784;h;`>5<#<891m>5a40093>=n1k0;6):>3;c0?k26:3207d7n:18'045=i:1e8<<59:9j==<72->:?7o<;o626?g<3`3<6=4+4019e6=i<881n65f9783>!26;3k87c:>2;a8?l?2290/8<=5a29m044=l21b594?:%627?g43g>:>7k4;h;0>5<#<891m>5a4009b>=n1;0;6):>3;c0?k26:3;;76g61;29 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1742=:j7c:>2;37?>i4n:0;6):>3;63e>h39;0:965`3g094?"39:0?n;o626?7?32e8ik4?:%627?27i2d?=?4>9:9l7`c=83.?=>4;0`9m044=9h10c>kk:18'045=<9k0b9?=:0`8?j5bj3:1(9?<:52b?k26:3;h76a!26;3>;m6`;1382`>=h;l31<7*;12874d=i<881=h54o2g;>5<#<8918=o4n531>4`<3f9n;7>5$530>16f3g>:>7:?7:?a:l757<5921d?h;50;&756<38h1e8<<52398k6c3290/8<=541c8j1752;907b=j3;29 1742=:j7c:>2;07?>i4m;0;6):>3;63e>h39;09965`40394?"39:0?n;o626?4?32e?4;0`9m044=:h10c9>l:18'045=<9k0b9?=:3`8?j27:3:1(9?<:52b?k26:38h76a!26;3>;m6`;1381`>=h;li1<7*;12874d=i<881>h54o2g2>5<#<8918=o4n531>7`<3`i?6=4+4019g6=i<881<65fc383>!26;3i87c:>2;38?le6290/8<=5c29m044=:21bo=4?:%627?e43g>:>7=4;h`e>5<#<891o>5a40090>=njl0;6):>3;a0?k26:3?07dlk:18'045=k:1e8<<56:9jff<72->:?7m<;o626?1<3`hi6=4+4019g6=i<881465fb`83>!26;3i87c:>2;;8?ld?290/8<=5c29m044=i21bn:4?:%627?e43g>:>7l4;h`5>5<#<891o>5a4009g>=nj<0;6):>3;a0?k26:3n07dl;:18'045=k:1e8<<5e:9jf6<72->:?7m<;o626?`<3`h96=4+4019g6=i<881==54ic394?"39:0h?6`;13825>=nj90;6):>3;a0?k26:3;976gnf;29 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1742l80b9?=:`98ka0=83.?=>4j2:l7575$530>`46`;138g?>ic;3:1(9?<:d08j1752l10ci<50;&75646<3fn;6=4+4019a7=i<881=<54obd94?"39:0n>6`;13826>=hkl0;6):>3;g1?k26:3;876ajb;29 1742l80b9?=:068?jcf290/8<=5e39m044=9<10ch750;&7566:9la=<72->:?7k=;o626?7032en;7>5$530>`45<#<891i?5a40095<=h39;0:m65`e583>!26;3o97c:>2;3a?>ic03:1(9?<:d08j17528i07bmk:18'045=m;1e8<<51e98m612290/8<=53668j1752910e>9<:18'045=;>>0b9?=:098m615290/8<=53668j1752;10e>9>:18'045=;>>0b9?=:298m617290/8<=53668j1752=10e>8i:18'045=;>>0b9?=:498m60b290/8<=53668j1752?10e>jn:18'045=;m30b9?=:198m6b?290/8<=53e;8j1752810e>j8:18'045=;m30b9?=:398m6b1290/8<=53e;8j1752:10e>j::18'045=;m30b9?=:598m6b3290/8<=53e;8j1752<10e>j<:18'045=;m30b9?=:798m6b5290/8<=53e;8j1752>10e>j?:18'045=;m30b9?=:998m6ea290/8<=53e;8j1752010e>mj:18'045=;m30b9?=:`98m6ec290/8<=53e;8j1752k10e>ml:18'045=;m30b9?=:b98m6ee290/8<=53e;8j1752m10e>mn:18'045=;m30b9?=:d98m6e>290/8<=53e;8j1752o10e>m7:18'045=;m30b9?=:028?l5d?3:1(9?<:2f:?k26:3;:76g!26;39o56`;13826>=n;j>1<7*;1280`<=i<881=>54i2a0>5<#<891?i74n531>42<3`9h>7>5$530>6b>3g>:>7?:;:k0g4<72->:?7=k9:l757<6>21b?n>50;&756<4l01e8<<51698m6da290/8<=53e;8j17528207d=me;29 1742:n27c:>2;3:?>o4jm0;6):>3;1g=>h39;0:m65f3ca94?"39:08h45a40095g=j6;o626?7c32c8n54?:%627?5c12d?=?4>e:9j7g1=83.?=>4l9:18'045=;m30b9?=:328?l5e=3:1(9?<:2f:?k26:38:76g!26;39o56`;13816>=n;k91<7*;1280`<=i<881>>54i2`1>5<#<891?i74n531>72<3`9i=7>5$530>6b>3g>:>7<:;:k0a5<72->:?7=k9:l757<5>21b?ih50;&756<4l01e8<<52698m6bb290/8<=53e;8j1752;207d=kd;29 1742:n27c:>2;0:?>o4lj0;6):>3;1g=>h39;09m65f3e`94?"39:08h45a40096g=j6;o626?4c32c8no4?:%627?5c12d?=?4=e:9j7g6=83.?=>44=h39;0976gib;29 1742oo0b9?=:298m40d290/8<=517`8j1752910e<8n:18'045=9?h0b9?=:098m40>290/8<=517`8j1752;10e<87:18'045=9?h0b9?=:298m400290/8<=517`8j1752=10e<89:18'045=9?h0b9?=:498m402290/8<=517`8j1752?10e<8;:18'045=9?h0b9?=:698m405290/8<=517`8j1752110e<8>:18'045=9?h0b9?=:898m407290/8<=517`8j1752h10e<;i:18'045=9?h0b9?=:c98m43b290/8<=517`8j1752j10e<;k:18'045=9?h0b9?=:e98m43d290/8<=517`8j1752l10e<;m:18'045=9?h0b9?=:g98m43f290/8<=517`8j17528:07d?:9;29 174282;32?>o6=>0;6):>3;35f>h39;0:>65f14494?"39:0::o5a400956=6=4+401953d4?:%627?71j2d?=?4>6:9j504=83.?=>4>6c9m044=9>10e<;>:18'045=9?h0b9?=:0:8?l7283:1(9?<:04a?k26:3;276g>4g83>!26;3;=n6`;1382e>=n9=o1<7*;12822g=i<881=o54i06`>5<#<891=;l4n531>4e<3`;?n7>5$530>40e3g>:>7?k;:k20d<72->:?7?9b:l757<6m21b=9750;&756<6>k1e8<<51g98m42?290/8<=517`8j1752;:07d?;7;29 174282;02?>o63;35f>h39;09>65f15794?"39:0::o5a400966=?6=4+401953d4>6c9m044=:>10e<9?:18'045=9?h0b9?=:3:8?l71n3:1(9?<:04a?k26:38276g>6d83>!26;3;=n6`;1381e>=n9?n1<7*;12822g=i<881>o54i040>5<#<891=;l4n531>7e<3`;>47>5$530>40e3g>:>7:?7?9b:l757<5m21b=9<50;&756<6>k1e8<<52g98k4>7290/8<=516d8j1752910c<9j:18'045=9>l0b9?=:098k41c290/8<=516d8j1752;10c<9l:18'045=9>l0b9?=:298m7g0290/8<=52`48j1752910e?o::18'045=:h<0b9?=:098m7g3290/8<=52`48j1752;10e?o<:18'045=:h<0b9?=:298m7g5290/8<=52`48j1752=10e<<>:18'045=9;:0b9?=:198m47a290/8<=51328j1752810e290/8<=51328j1752>10e<290/8<=51328j1752010e<<7:18'045=9;:0b9?=:`98m440290/8<=51328j1752k10e<<9:18'045=9;:0b9?=:b98m442290/8<=51328j1752m10e<<;:18'045=9;:0b9?=:d98m444290/8<=51328j1752o10e<<=:18'045=9;:0b9?=:028?l7603:1(9?<:003?k26:3;:76g>0e83>!26;3;;o6`;1383?>o68k0;6):>3;33g>h39;0:76g>0`83>!26;3;;o6`;1381?>o6800;6):>3;33g>h39;0876g>0983>!26;3;;o6`;1387?>o68>0;6):>3;33g>h39;0>76g>0783>!26;3;;o6`;1385?>o68<0;6):>3;33g>h39;0<76g>1783>!26;3;;o6`;138;?>o69<0;6):>3;33g>h39;0276g>1583>!26;3;;o6`;138b?>o69:0;6):>3;33g>h39;0i76g>1383>!26;3;;o6`;138`?>o6980;6):>3;33g>h39;0o76g>1183>!26;3;;o6`;138f?>o68o0;6):>3;33g>h39;0m76g>0d83>!26;3;;o6`;13824>=n99>1<7*;12824f=i<881=<54o017>5<#<891=>=4n531>5=5<#<891=>=4n531>7=54o00e>5<#<891=>=4n531>1=5<#<891=>=4n531>3=5<#<891=>=4n531>==5<#<891=>=4n531>d=5<#<891=>=4n531>f=5<#<891=>=4n531>`=5<#<891=>=4n531>46<3f;9n7>5$530>4543g>:>7?>;:k2ed<72->:?7?n9:l757<732c:m54?:%627?7f12d?=?4>;:k2e2<72->:?7?n9:l757<532c:m;4?:%627?7f12d?=?4<;:k2e0<72->:?7?n9:l757<332c:m>4?:%627?7f12d?=?4:;:k2e7<72->:?7?n9:l757<132c:m<4?:%627?7f12d?=?48;:k2e5<72->:?7?n9:l757:?7?n9:l757:?7?n9:l757:?7?n9:l757:?7?n9:l757<6821b=o>50;&756<6i01e8<<51098m4ga290/8<=51`;8j17528807d?ne;29 17428k27c:>2;30?>o6im0;6):>3;3b=>h39;0:865f1`a94?"39:0:m45a400950=8:9l7d3=83.?=>444421d?4j50;&756<4i=1e8<<57:9l7444447=:18'045=;h>0b9?=:038?j5>83:1(9?<:2c7?k26:3;976a<8g83>!26;39j86`;13827>=h;1o1<7*;1280e1=i<881=954o2:g>5<#<891?l:4n531>43<3f93o7>5$530>6g33g>:>7?9;:m0:?7=n4:l757<6?21d?5o50;&756<4i=1e8<<51998k6>>290/8<=53`68j17528307b=78;29 1742:k?7c:>2;3b?>i40>0;6):>3;1b0>h39;0:n65`39794?"39:08m95a40095f=o;;o626?7b32e84?4?:%627?5f<2d?=?4>f:9l7=7=83.?=>46?:18'045=;h>0b9?=:338?j50n3:1(9?<:2c7?k26:38976a<7d83>!26;39j86`;13817>=h;>n1<7*;1280e1=i<881>954o25`>5<#<891?l:4n531>73<3f9jn7>5$530>6g33g>:>7<9;:m0ed<72->:?7=n4:l757<5?21d?l750;&756<4i=1e8<<52998k6g?290/8<=53`68j1752;307b=n7;29 1742:k?7c:>2;0b?>i4i?0;6):>3;1b0>h39;09n65`38a94?"39:08m95a40096f=o;;o626?4b32e8;o4?:%627?5f<2d?=?4=f:9je1<72->:?7o<;o626?6<3`k96=4+4019e6=i<881=65fa083>!26;3k87c:>2;08?lg7290/8<=5a29m044=;21b5k4?:%627?g43g>:>7:4;h;f>5<#<891m>5a40091>=n1m0;6):>3;c0?k26:3<07d7l:18'045=i:1e8<<57:9j=g<72->:?7o<;o626?><3`3j6=4+4019e6=i<881565f9983>!26;3k87c:>2;c8?l?0290/8<=5a29m044=j21b5;4?:%627?g43g>:>7m4;h;6>5<#<891m>5a4009`>=n1=0;6):>3;c0?k26:3o07d7<:18'045=i:1e8<<5f:9j=7<72->:?7o<;o626?7732c2=7>5$530>d55<#<891m>5a400957=h39;0:?65fab83>!26;3k87c:>2;37?>ofj3:1(9?<:`18j17528?07don:18'045=i:1e8<<51798md?=83.?=>4n3:l757<6?21bm54?:%627?g43g>:>7?7;:kb3?6=,=;86l=4n531>4?<3`k=6=4+4019e6=i<881=l54i`794?"39:0j?6`;1382f>=n100;6):>3;c0?k26:3;h76g7e;29 1742h90b9?=:0f8?j27j3:1(9?<:52b?k26:3:07b:?9;29 1742=:j7c:>2;38?j2703:1(9?<:52b?k26:3807b:?7;29 1742=:j7c:>2;18?j27>3:1(9?<:52b?k26:3>07b:?5;29 1742=:j7c:>2;78?j27<3:1(9?<:52b?k26:3<07b:?3;29 1742=:j7c:>2;58?j2793:1(9?<:52b?k26:3207b:?0;29 1742=:j7c:>2;;8?j5an3:1(9?<:52b?k26:3k07b=ie;29 1742=:j7c:>2;`8?j5al3:1(9?<:52b?k26:3i07b=ic;29 1742=:j7c:>2;f8?j5aj3:1(9?<:52b?k26:3o07b=ia;29 1742=:j7c:>2;d8?j5a13:1(9?<:52b?k26:3;;76a!26;3>;m6`;13825>=h;o<1<7*;12874d=i<881=?54o2d6>5<#<8918=o4n531>45<3f9m87>5$530>16f3g>:>7?;;:m0b6<72->:?7:?a:l757<6=21d?k<50;&756<38h1e8<<51798k6`6290/8<=541c8j17528=07b=i0;29 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1742:n27c:>2;3g?>o4j10;6):>3;1g=>h39;0:i65f3c594?"39:08h45a40095c=4;h1a1?6=,=;86>j6;o626?4632c8n94?:%627?5c12d?=?4=2:9j7g5=83.?=>4l=:18'045=;m30b9?=:368?l5e93:1(9?<:2f:?k26:38>76g!26;39o56`;13812>=n;ml1<7*;1280`<=i<881>:54i2ff>5<#<891?i74n531>7><3`9oh7>5$530>6b>3g>:>7<6;:k0`f<72->:?7=k9:l757<5i21b?il50;&756<4l01e8<<52c98m6b6290/8<=53e;8j1752;i07d=l6;29 1742:n27c:>2;0g?>o4jk0;6):>3;1g=>h39;09i65f3c294?"39:08h45a40096c=h39;0;76gid;29 1742oo0b9?=:098mce=83.?=>4ie:l757<532cmn7>5$530>cc54i04`>5<#<891=;l4n531>5=5<#<891=;l4n531>7=54i044>5<#<891=;l4n531>1=5<#<891=;l4n531>3=5<#<891=;l4n531>==5<#<891=;l4n531>d=5<#<891=;l4n531>f=5<#<891=;l4n531>`=5<#<891=;l4n531>46<3`;>57>5$530>40e3g>:>7?>;:k212<72->:?7?9b:l757<6:21b=8850;&756<6>k1e8<<51298m432290/8<=517`8j17528>07d?:4;29 174282;36?>o6=:0;6):>3;35f>h39;0::65f14094?"39:0::o5a400952=32c:8k4?:%627?71j2d?=?4>a:9j51c=83.?=>4>6c9m044=9k10e<:l:18'045=9?h0b9?=:0a8?l73j3:1(9?<:04a?k26:3;o76g>4`83>!26;3;=n6`;1382a>=n9=31<7*;12822g=i<881=k54i06;>5<#<891=;l4n531>76<3`;?;7>5$530>40e3g>:>7<>;:k203<72->:?7?9b:l757<5:21b=9;50;&756<6>k1e8<<52298m423290/8<=517`8j1752;>07d?;3;29 174282;06?>o6?;0;6):>3;35f>h39;09:65f16394?"39:0::o5a400962=32c::h4?:%627?71j2d?=?4=a:9j53b=83.?=>4>6c9m044=:k10e<8<:18'045=9?h0b9?=:3a8?l7203:1(9?<:04a?k26:38o76g>4e83>!26;3;=n6`;1381a>=n9=81<7*;12822g=i<881>k54o0:3>5<#<891=:h4n531>5=5<#<891=:h4n531>7=54i3c4>5<#<891>l84n531>5=6=4+40196d05<#<891>l84n531>7=54i3c1>5<#<891>l84n531>1=5<#<891=?>4n531>4=5<#<891=?>4n531>6=5<#<891=?>4n531>0=5<#<891=?>4n531>2=5<#<891=?>4n531><=5<#<891=?>4n531>g=5<#<891=?>4n531>a=5<#<891=?>4n531>c=4;h32:?7??c:l757<632c::?7??c:l757<432c:<54?:%627?77k2d?=?4;;:k242<72->:?7??c:l757<232c:<;4?:%627?77k2d?=?49;:k240<72->:?7??c:l757<032c:=;4?:%627?77k2d?=?47;:k250<72->:?7??c:l757<>32c:=94?:%627?77k2d?=?4n;:k256<72->:?7??c:l757:?7??c:l757:?7??c:l7570:9j552=83.?=>4>0b9m044=9810c<=;:18'045=9:90b9?=:198k455290/8<=51218j1752810c<=>:18'045=9:90b9?=:398k457290/8<=51218j1752:10c<10c<=k:18'045=9:90b9?=:998k45d290/8<=51218j1752010c<=m:18'045=9:90b9?=:`98k45f290/8<=51218j1752k10c<=6:18'045=9:90b9?=:b98k45?290/8<=51218j1752m10c<=8:18'045=9:90b9?=:d98k451290/8<=51218j1752o10c<=::18'045=9:90b9?=:028?j75j3:1(9?<:010?k26:3;:76g>a`83>!26;3;j56`;1383?>o6i10;6):>3;3b=>h39;0:76g>a683>!26;3;j56`;1381?>o6i?0;6):>3;3b=>h39;0876g>a483>!26;3;j56`;1387?>o6i:0;6):>3;3b=>h39;0>76g>a383>!26;3;j56`;1385?>o6i80;6):>3;3b=>h39;0<76g>a183>!26;3;j56`;138;?>o61o0;6):>3;3b=>h39;0276g>9d83>!26;3;j56`;138b?>o61m0;6):>3;3b=>h39;0i76g>9b83>!26;3;j56`;138`?>o61k0;6):>3;3b=>h39;0o76g>9`83>!26;3;j56`;138f?>o6j;0;6):>3;3b=>h39;0m76g>b083>!26;3;j56`;13824>=n9k:1<7*;1282e<=i<881=<54i0ce>5<#<891=l74n531>44<3`;ji7>5$530>4g>3g>:>7?<;:k2ea<72->:?7?n9:l757<6<21b=lm50;&756<6i01e8<<51498m4ge290/8<=51`;8j17528<07d?n4;29 17428k27c:>2;34?>o6100;6):>3;3b=>h39;0:465`3`794?"39:08m95a40094>=h;h91<7*;1280e1=i<881=65`3`094?"39:08m95a40096>=h;h;1<7*;1280e1=i<881?65`3`294?"39:08m95a40090>=h;0l1<7*;1280e1=i<881965`38g94?"39:08m95a40092>=h;0n1<7*;1280e1=i<881;65`38`94?"39:08m95a4009<>=h;0k1<7*;1280e1=i<881565`38;94?"39:08m95a4009e>=h;021<7*;1280e1=i<881n65`38594?"39:08m95a4009g>=h;0<1<7*;1280e1=i<881h65`38794?"39:08m95a4009a>=h;0>1<7*;1280e1=i<881j65`38194?"39:08m95a400955=o;;o626?7532e84k4?:%627?5f<2d?=?4>3:9l7=c=83.?=>46k:18'045=;h>0b9?=:078?j5?k3:1(9?<:2c7?k26:3;=76a<8c83>!26;39j86`;13823>=h;1k1<7*;1280e1=i<881=554o2::>5<#<891?l:4n531>4?<3f9347>5$530>6g33g>:>7?n;:m0<2<72->:?7=n4:l757<6j21d?5;50;&756<4i=1e8<<51b98k6>3290/8<=53`68j17528n07b=73;29 1742:k?7c:>2;3f?>i40;0;6):>3;1b0>h39;0:j65`39394?"39:08m95a400965=o;;o626?4532e8;h4?:%627?5f<2d?=?4=3:9l72b=83.?=>49l:18'045=;h>0b9?=:378?j5fj3:1(9?<:2c7?k26:38=76a!26;39j86`;13813>=h;h31<7*;1280e1=i<881>554o2c;>5<#<891?l:4n531>7?<3f9j;7>5$530>6g33g>:>7:?7=n4:l757<5j21d?4m50;&756<4i=1e8<<52b98k6?6290/8<=53`68j1752;n07b=76;29 1742:k?7c:>2;0f?>i4?k0;6):>3;1b0>h39;09j65fa583>!26;3k87c:>2;28?lg5290/8<=5a29m044=921bm<4?:%627?g43g>:>7<4;hc3>5<#<891m>5a40097>=n1o0;6):>3;c0?k26:3>07d7j:18'045=i:1e8<<55:9j=a<72->:?7o<;o626?0<3`3h6=4+4019e6=i<881;65f9c83>!26;3k87c:>2;:8?l?f290/8<=5a29m044=121b554?:%627?g43g>:>7o4;h;4>5<#<891m>5a4009f>=n1?0;6):>3;c0?k26:3i07d7::18'045=i:1e8<<5d:9j=1<72->:?7o<;o626?c<3`386=4+4019e6=i<881j65f9383>!26;3k87c:>2;33?>o>93:1(9?<:`18j17528;07d7?:18'045=i:1e8<<51398m=`=83.?=>4n3:l757<6;21bmn4?:%627?g43g>:>7?;;:kbf?6=,=;86l=4n531>43<3`kj6=4+4019e6=i<881=;54i`;94?"39:0j?6`;13823>=ni10;6):>3;c0?k26:3;376gn7;29 1742h90b9?=:0;8?lg1290/8<=5a29m044=9h10el;50;&756b:9j=<<72->:?7o<;o626?7d32c3i7>5$530>d5n;o626?6<3f>;57>5$530>16f3g>:>7?4;n63n;o626?4<3f>;;7>5$530>16f3g>:>7=4;n632?6=,=;869>n;o626?2<3f>;97>5$530>16f3g>:>7;4;n630?6=,=;869>n;o626?0<3f>;?7>5$530>16f3g>:>794;n635?6=,=;869>n;o626?><3f>;<7>5$530>16f3g>:>774;n1eb?6=,=;869>n;o626?g<3f9mi7>5$530>16f3g>:>7l4;n1e`?6=,=;869>n;o626?e<3f9mo7>5$530>16f3g>:>7j4;n1ef?6=,=;869>n;o626?c<3f9mm7>5$530>16f3g>:>7h4;n1e=?6=,=;869>n;o626?7732e8j54?:%627?27i2d?=?4>1:9l7c0=83.?=>4;0`9m044=9;10c>h::18'045=<9k0b9?=:018?j5a<3:1(9?<:52b?k26:3;?76a!26;3>;m6`;13821>=h;o81<7*;12874d=i<881=;54o2d2>5<#<8918=o4n531>41<3f9m<7>5$530>16f3g>:>7?7;:m0ac<72->:?7:?a:l757<6121d?hk50;&756<38h1e8<<51`98k6cc290/8<=541c8j17528h07b=jb;29 1742=:j7c:>2;3`?>i4mh0;6):>3;63e>h39;0:h65`3d;94?"39:0?n;o626?4732e8i;4?:%627?27i2d?=?4=1:9l7`3=83.?=>4;0`9m044=:;10c>k;:18'045=<9k0b9?=:318?j5b;3:1(9?<:52b?k26:38?76a!26;3>;m6`;13811>=h<8;1<7*;12874d=i<881>;54o533>5<#<8918=o4n531>71<3f>;j7>5$530>16f3g>:>7<7;:m74`<72->:?7:?a:l757<5121d8=j50;&756<38h1e8<<52`98k16d290/8<=541c8j1752;h07b:?2;29 1742=:j7c:>2;0`?>i4n>0;6):>3;63e>h39;09h65`3da94?"39:0?5<#<891o>5a40094>=nk;0;6):>3;a0?k26:3;07dm>:18'045=k:1e8<<52:9jg5<72->:?7m<;o626?5<3`hm6=4+4019g6=i<881865fbd83>!26;3i87c:>2;78?ldc290/8<=5c29m044=>21bnn4?:%627?e43g>:>794;h`a>5<#<891o>5a4009<>=njh0;6):>3;a0?k26:3307dl7:18'045=k:1e8<<5a:9jf2<72->:?7m<;o626?d<3`h=6=4+4019g6=i<881o65fb483>!26;3i87c:>2;f8?ld3290/8<=5c29m044=m21bn>4?:%627?e43g>:>7h4;h`1>5<#<891o>5a400955=h39;0:=65fb183>!26;3i87c:>2;31?>ofn3:1(9?<:b18j17528907dml:18'045=k:1e8<<51598mfd=83.?=>4l3:l757<6=21bol4?:%627?e43g>:>7?9;:k`=?6=,=;86n=4n531>41<3`i36=4+4019g6=i<881=554ib594?"39:0h?6`;1382=>=nk?0;6):>3;a0?k26:3;j76gl5;29 1742j90b9?=:0`8?ld>290/8<=5c29m044=9j10elk50;&756d:9j52g=83.?=>4>789m044=821b=:650;&756<6?01e8<<51:9j521=83.?=>4>789m044=:21vn8:=:182e4<729q/8?k52958L15c3A>8=6T>3g824~2c2>21;:473;5`>1g=9=0<:79=:0390<<083;;69;57487=1=lk8;ocg>4=inh0:7c??0;28j466281/==<537c8 4642;=m7c?>7;38j45b281/=9>526d8j411281e=:l51:l2=3<63g83:7?4n3c;>4=#:k91>464n3`7>4=i;><1<6*o;4$517>60>3->897=9d:m0e`<722c?=h4?::k2<3<722c:494?::m1f2<722c:454?::k767<722c9n;4?::k2<2<722c?=k4?::k2=4?::k2<0<722c:4>4?::k2=7<722c:4?4?::k75a<722e8;54?::k24?::k764<722c:4i4?::k766<722en?7>5$530>`46`;1382?>ib83:1(9?<:d08j1752;10cih50;&7561=h39;0>76akc;29 1742l80b9?=:798kad=83.?=>4j2:l757<032eom7>5$530>`46`;138:?>ic?3:1(9?<:d08j1752h10ci850;&756f=1<7*;128f6>h39;0o76ak3;29 1742l80b9?=:d98ka4=83.?=>4j2:l7575$530>`44;nf3>5<#<891i?5a400954=h39;0:>65`cd83>!26;3o97c:>2;30?>ibj3:1(9?<:d08j17528>07bkn:18'045=m;1e8<<51498k`?=83.?=>4j2:l757<6>21di54?:%627?c53g>:>7?8;:mf3?6=,=;86h<4n531>4><3fo=6=4+4019a7=i<881=454od794?"39:0n>6`;1382e>=hm=0;6):>3;g1?k26:3;i76ak8;29 1742l80b9?=:0a8?jec290/8<=5e39m044=9m10e>9::18'045=;>>0b9?=:198m614290/8<=53668j1752810e>9=:18'045=;>>0b9?=:398m616290/8<=53668j1752:10e>9?:18'045=;>>0b9?=:598m60a290/8<=53668j1752<10e>8j:18'045=;>>0b9?=:798m6bf290/8<=53e;8j1752910e>j7:18'045=;m30b9?=:098m6b0290/8<=53e;8j1752;10e>j9:18'045=;m30b9?=:298m6b2290/8<=53e;8j1752=10e>j;:18'045=;m30b9?=:498m6b4290/8<=53e;8j1752?10e>j=:18'045=;m30b9?=:698m6b7290/8<=53e;8j1752110e>mi:18'045=;m30b9?=:898m6eb290/8<=53e;8j1752h10e>mk:18'045=;m30b9?=:c98m6ed290/8<=53e;8j1752j10e>mm:18'045=;m30b9?=:e98m6ef290/8<=53e;8j1752l10e>m6:18'045=;m30b9?=:g98m6e?290/8<=53e;8j17528:07d=l7;29 1742:n27c:>2;32?>o4k<0;6):>3;1g=>h39;0:>65f3b694?"39:08h45a400956=j6;o626?7232c8o<4?:%627?5c12d?=?4>6:9j7f6=83.?=>410e>li:18'045=;m30b9?=:0:8?l5em3:1(9?<:2f:?k26:3;276g!26;39o56`;1382e>=n;ki1<7*;1280`<=i<881=o54i2`b>5<#<891?i74n531>4e<3`9i57>5$530>6b>3g>:>7?k;:k0f=<72->:?7=k9:l757<6m21b?o950;&756<4l01e8<<51g98m6d1290/8<=53e;8j1752;:07d=m5;29 1742:n27c:>2;02?>o4j=0;6):>3;1g=>h39;09>65f3c194?"39:08h45a400966=j6;o626?4232c8i=4?:%627?5c12d?=?4=6:9j7a`=83.?=>410e>jj:18'045=;m30b9?=:3:8?l5cl3:1(9?<:2f:?k26:38276g!26;39o56`;1381e>=n;mh1<7*;1280`<=i<881>o54i2f2>5<#<891?i74n531>7e<3`9h:7>5$530>6b>3g>:>7:?7=k9:l757<5m21b?o>50;&756<4l01e8<<52g98mc`=83.?=>4ie:l757<732cmh7>5$530>ccoaj3:1(9?<:gg8j1752:10e<8l:18'045=9?h0b9?=:198m40f290/8<=517`8j1752810e<86:18'045=9?h0b9?=:398m40?290/8<=517`8j1752:10e<88:18'045=9?h0b9?=:598m401290/8<=517`8j1752<10e<8::18'045=9?h0b9?=:798m403290/8<=517`8j1752>10e<8=:18'045=9?h0b9?=:998m406290/8<=517`8j1752010e<8?:18'045=9?h0b9?=:`98m43a290/8<=517`8j1752k10e<;j:18'045=9?h0b9?=:b98m43c290/8<=517`8j1752m10e<;l:18'045=9?h0b9?=:d98m43e290/8<=517`8j1752o10e<;n:18'045=9?h0b9?=:028?l7213:1(9?<:04a?k26:3;:76g>5683>!26;3;=n6`;13826>=n9<<1<7*;12822g=i<881=>54i076>5<#<891=;l4n531>42<3`;>87>5$530>40e3g>:>7?:;:k216<72->:?7?9b:l757<6>21b=8<50;&756<6>k1e8<<51698m436290/8<=517`8j17528207d?:0;29 174282;3:?>o63;35f>h39;0:m65f15g94?"39:0::o5a40095g=h6=4+401953de:9j51?=83.?=>4>6c9m044=9o10e<:7:18'045=9?h0b9?=:328?l73?3:1(9?<:04a?k26:38:76g>4783>!26;3;=n6`;13816>=n9=?1<7*;12822g=i<881>>54i067>5<#<891=;l4n531>72<3`;??7>5$530>40e3g>:>7<:;:k237<72->:?7?9b:l757<5>21b=:?50;&756<6>k1e8<<52698m417290/8<=517`8j1752;207d?9f;29 174282;0:?>o6>l0;6):>3;35f>h39;09m65f17f94?"39:0::o5a40096g=4>6c9m044=:o10c<6?:18'045=9>l0b9?=:198k41b290/8<=516d8j1752810c<9k:18'045=9>l0b9?=:398k41d290/8<=516d8j1752:10e?o8:18'045=:h<0b9?=:198m7g2290/8<=52`48j1752810e?o;:18'045=:h<0b9?=:398m7g4290/8<=52`48j1752:10e?o=:18'045=:h<0b9?=:598m446290/8<=51328j1752910e8;29 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1742=:j7c:>2;08?j27?3:1(9?<:52b?k26:3907b:?6;29 1742=:j7c:>2;68?j27=3:1(9?<:52b?k26:3?07b:?4;29 1742=:j7c:>2;48?j27;3:1(9?<:52b?k26:3=07b:?1;29 1742=:j7c:>2;:8?j2783:1(9?<:52b?k26:3307b=if;29 1742=:j7c:>2;c8?j5am3:1(9?<:52b?k26:3h07b=id;29 1742=:j7c:>2;a8?j5ak3:1(9?<:52b?k26:3n07b=ib;29 1742=:j7c:>2;g8?j5ai3:1(9?<:52b?k26:3l07b=i9;29 1742=:j7c:>2;33?>i4n10;6):>3;63e>h39;0:=65`3g494?"39:0?6=4+401905gn;o626?7332e8j>4?:%627?27i2d?=?4>5:9l7c4=83.?=>4;0`9m044=9?10c>h>:18'045=<9k0b9?=:058?j5a83:1(9?<:52b?k26:3;376a!26;3>;m6`;1382=>=h;lo1<7*;12874d=i<881=l54o2gg>5<#<8918=o4n531>4d<3f9nn7>5$530>16f3g>:>7?l;:m0ad<72->:?7:?a:l757<6l21d?h750;&756<38h1e8<<51d98k6c?290/8<=541c8j17528l07b=j7;29 1742=:j7c:>2;03?>i4m?0;6):>3;63e>h39;09=65`3d794?"39:0?n;o626?4332e8i?4?:%627?27i2d?=?4=5:9l047=83.?=>4;0`9m044=:?10c9??:18'045=<9k0b9?=:358?j27n3:1(9?<:52b?k26:38376a;0d83>!26;3>;m6`;1381=>=h<9n1<7*;12874d=i<881>l54o52`>5<#<8918=o4n531>7d<3f>;>7>5$530>16f3g>:>7:?7:?a:l757<5l21d?hm50;&756<38h1e8<<52d98k6c6290/8<=541c8j1752;l07dm;:18'045=k:1e8<<50:9jg7<72->:?7m<;o626?7<3`i:6=4+4019g6=i<881>65fc183>!26;3i87c:>2;18?lda290/8<=5c29m044=<21bnh4?:%627?e43g>:>7;4;h`g>5<#<891o>5a40092>=njj0;6):>3;a0?k26:3=07dlm:18'045=k:1e8<<58:9jfd<72->:?7m<;o626??<3`h36=4+4019g6=i<881m65fb683>!26;3i87c:>2;`8?ld1290/8<=5c29m044=k21bn84?:%627?e43g>:>7j4;h`7>5<#<891o>5a4009a>=nj:0;6):>3;a0?k26:3l07dl=:18'045=k:1e8<<51198mg7=83.?=>4l3:l757<6921bn=4?:%627?e43g>:>7?=;:kbb?6=,=;86n=4n531>45<3`ih6=4+4019g6=i<881=954ib`94?"39:0h?6`;13821>=nkh0;6):>3;a0?k26:3;=76gl9;29 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1742l80b9?=:b98ka2=83.?=>4j2:l7575$530>`46`;138e?>ic93:1(9?<:d08j17528:07bj?:18'045=m;1e8<<51098kf`=83.?=>4j2:l757<6:21doh4?:%627?c53g>:>7?<;:mff?6=,=;86h<4n531>42<3foj6=4+4019a7=i<881=854od;94?"39:0n>6`;13822>=hm10;6):>3;g1?k26:3;<76aj7;29 1742l80b9?=:0:8?jc1290/8<=5e39m044=9010ch;50;&756a:9la1<72->:?7k=;o626?7e32eo47>5$530>`45<#<891i?5a40095a=6=4+40197225<#<891?::4n531>4=5<#<891?::4n531>6=5<#<891?::4n531>0=5<#<891?i74n531>5=5<#<891?i74n531>7=54i2f6>5<#<891?i74n531>1=5<#<891?i74n531>3=5<#<891?i74n531>==5<#<891?i74n531>d=5<#<891?i74n531>f=5<#<891?i74n531>`=5<#<891?i74n531>46<3`9h;7>5$530>6b>3g>:>7?>;:k0g0<72->:?7=k9:l757<6:21b?n:50;&756<4l01e8<<51298m6e4290/8<=53e;8j17528>07d=l2;29 1742:n27c:>2;36?>o4k80;6):>3;1g=>h39;0::65f3b294?"39:08h45a400952=j6;o626?7>32c8ni4?:%627?5c12d?=?4>a:9j7ge=83.?=>4ln:18'045=;m30b9?=:0a8?l5e13:1(9?<:2f:?k26:3;o76g!26;39o56`;1382a>=n;k=1<7*;1280`<=i<881=k54i2`5>5<#<891?i74n531>76<3`9i97>5$530>6b>3g>:>7<>;:k0f1<72->:?7=k9:l757<5:21b?o=50;&756<4l01e8<<52298m6d5290/8<=53e;8j1752;>07d=m1;29 1742:n27c:>2;06?>o4m90;6):>3;1g=>h39;09:65f3ed94?"39:08h45a400962=j6;o626?4>32c8hn4?:%627?5c12d?=?4=a:9j7ad=83.?=>4j>:18'045=;m30b9?=:3a8?l5d>3:1(9?<:2f:?k26:38o76g!26;39o56`;1381a>=n;k:1<7*;1280`<=i<881>k54igd94?"39:0mi6`;1383?>oal3:1(9?<:gg8j1752810ekm50;&7566=5<#<891=;l4n531>4=5<#<891=;l4n531>6=5<#<891=;l4n531>0=6=4+401953d5<#<891=;l4n531>2=5<#<891=;l4n531><=5<#<891=;l4n531>g=5<#<891=;l4n531>a=5<#<891=;l4n531>c=4;h36=?6=,=;86<8m;o626?7632c:9:4?:%627?71j2d?=?4>2:9j500=83.?=>4>6c9m044=9:10e<;::18'045=9?h0b9?=:068?l72<3:1(9?<:04a?k26:3;>76g>5283>!26;3;=n6`;13822>=n9<81<7*;12822g=i<881=:54i072>5<#<891=;l4n531>4><3`;><7>5$530>40e3g>:>7?6;:k20c<72->:?7?9b:l757<6i21b=9k50;&756<6>k1e8<<51c98m42d290/8<=517`8j17528i07d?;b;29 174282;3g?>o63;35f>h39;0:i65f15;94?"39:0::o5a40095c=36=4+401953d4;h373?6=,=;86<8m;o626?4632c:8;4?:%627?71j2d?=?4=2:9j513=83.?=>4>6c9m044=::10e<:;:18'045=9?h0b9?=:368?l73;3:1(9?<:04a?k26:38>76g>7383>!26;3;=n6`;13812>=n9>;1<7*;12822g=i<881>:54i053>5<#<891=;l4n531>7><3`;=j7>5$530>40e3g>:>7<6;:k22`<72->:?7?9b:l757<5i21b=;j50;&756<6>k1e8<<52c98m404290/8<=517`8j1752;i07d?:8;29 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78a;295~N3;81vb>78b;295~N3;81vb>78c;295~N3;81vb>78d;295~N3;81vb>78e;295~N3;81vb>78f;295~N3;81vb>770;295~N3;81vb>771;295~N3;81vb>772;295~N3;81vb>773;295~N3;81vb>774;295~N3;81vb>775;295~N3;81vb>776;295~N3;81vb>777;295~N3;81vb>778;295~N3;81vb>779;295~N3;81vb>77a;295~N3;81vb>77b;295~N3;81vb>77c;295~N3;81vb>77d;295~N3;81vb>77e;295~N3;81vb>77f;295~N3;81vb>760;295~N3;81vb>761;295~N3;81vb>762;295~N3;81vb>763;295~N3;81vb>l9c;295~N3;81vb>l9d;295~N3;81vb>l9e;295~N3;81vb>l9f;295~N3;81vb>l80;295~N3;81vb>l81;295~N3;81vb>l82;295~N3;81vb>l83;295~N3;81vb>l84;295~N3;81vb>l85;295~N3;81vb>l86;295~N3;81vb>l87;295~N3;81vb>l88;295~N3;81vb>l89;295~N3;81vb>l8a;295~N3;81vb>l8b;295~N3;81vb>l8c;295~N3;81vb>l8d;295~N3;81vb>l8e;295~N3;81vb>l8f;295~N3;81vb>l70;295~N3;81vb>l71;295~N3;81vb>l72;295~N3;81vb>l73;295~N3;81vb>l74;295~N3;81vb>l75;295~N3;81vb>j:e;295~N3;81vb>j:f;295~N3;81vb>j90;295~N3;81vb>j91;295~N3;81vb>j92;295~N3;81vb>j93;295~N3;81vb>j94;295~N3;81vb>j95;295~N3;81vb>j96;295~N3;81vb>j97;295~N3;81vb>j98;295~N3;81vb>j99;295~N3;81vb>j9a;295~N3;81vb>j9b;295~N3;81vb>j9c;295~N3;81vb>j9d;295~N3;81vb>j9e;295~N3;81vb>j9f;295~N3;81vb>j80;295~N3;81vb>j81;295~N3;81vb>j82;295~N3;81vb>j83;295~N3;81vb>j84;295~N3;81vb>j85;295~N3;81vb>j86;295~N3;81vb>j87;295~N3;81vb>h:0;295~N3;81vb>h:1;295~N3;81vb>h:2;295~N3;81vb>h:3;295~N3;81vb>h:4;295~N3;81vb>h:5;295~N3;81vb>h:6;295~N3;81vb>h:7;295~N3;81vb>h:8;295~N3;81vb>h:9;295~N3;81vb>h:a;295~N3;81vb>h:b;295~N3;81vb>h:c;295~N3;81vb>h:d;295~N3;81vb>h:e;295~N3;81vb>h:f;295~N3;81vb>h90;295~N3;81vb>h91;295~N3;81vb>h92;295~N3;81vb>h93;295~N3;81vb>h94;295~N3;81vb>h95;295~N3;81vb>h96;295~N3;81vb>h97;295~N3;81vb>h98;295~N3;81vb>h99;295~N3;81vb9?;2;295~N3;81vb9?;3;295~N3;81vb9?;4;295~N3;81vb9?;5;295~N3;81vb9?;6;295~N3;81vb9?;7;295~N3;81vb9?;8;295~N3;81vb9?;9;295~N3;81vb9?;a;295~N3;81vb9?;b;295~N3;81vb9?;c;295~N3;81vb9?;d;295~N3;81vb9?;e;295~N3;81vb9?;f;295~N3;81vb9?:0;295~N3;81vb9?:1;295~N3;81vb9?:2;295~N3;81vb9?:3;295~N3;81vb9?:4;295~N3;81vb9?:5;295~N3;81vb9?:6;295~N3;81vb9?:7;295~N3;81vb9?:8;295~N3;81vb9?:9;295~N3;81vb9?:a;295~N3;81vb9?:b;295~N3;81vb9=<4;295~N3;81vb9=<5;295~N3;81vb9=<6;295~N3;81vb9=<7;295~N3;81vb9=<8;295~N3;81vb9=<9;295~N3;81vb9=8;295~N3;81vb99>9;295~N3;81vb99>a;295~N3;81vb99>b;295~N3;81vb99>c;295~N3;81vb99>d;295~N3;81vb99>e;295~N3;81vb99>f;295~N3;81vb99=0;295~N3;81vb99=1;295~N3;81vb99=2;295~N3;81vb99=3;295~N3;81vb99=4;295~N3;81vb99=5;295~N3;81vb99=6;295~N3;81vb99=7;295~N3;81vb99=8;295~N3;81vb99=9;295~N3;81vb99=a;295~N3;81vb99=b;295~N3;81vb99=c;295~N3;81vb99=d;295~N3;81vb99=e;295~N3;81vb99=f;295~N3;81vb99<0;295~N3;81vb99<1;295~N3;81vb97?a;295~N3;81vb97?b;295~N3;81vb97?c;295~N3;81vb97?d;295~N3;81vb97?e;295~N3;81vb97?f;295~N3;81vb97>0;295~N3;81vb97>1;295~N3;81vb97>2;295~N3;81vb97>3;295~N3;81vb97>4;295~N3;81vb97>5;295~N3;81vb97>6;295~N3;81vb97>7;295~N3;81vb97>8;295~N3;81vb97>9;295~N3;81vb97>a;295~N3;81vb97>b;295~N3;81vb97>c;295~N3;81vb97>d;295~N3;81vb97>e;295~N3;81vb97>f;295~N3;81vb97=0;295~N3;81vb97=1;295~N3;81vb97=2;295~N3;81vb97=3;295~N3;81vb9oic;295~N3;81vb9oid;295~N3;81vb9oie;295~N3;81vb9oif;295~N3;81vb9l?0;295~N3;81vb9l?1;295~N3;81vb9l?2;295~N3;81vb9l?3;295~N3;81vb9l?4;295~N3;81vb9l?5;295~N3;81vb9l?6;295~N3;81vb9l?7;295~N3;81vb9l?8;295~N3;81vb9l?9;295~N3;81vb9l?a;295~N3;81vb9l?b;295~N3;81vb9l?c;295~N3;81vb9l?d;295~N3;81vb9l?e;295~N3;81vb9l?f;295~N3;81vb9l>0;295~N3;81vb9l>1;295~N3;81vb9l>2;295~N3;81vb9l>3;295~N3;81vb9l>4;295~N3;81vb9l>5;295~N3;81vb9mje;295~N3;81vb9mjf;295~N3;81vb9mi0;295~N3;81vb9mi1;295~N3;81vb9mi2;295~N3;81vb9mi3;295~N3;81vb9mi4;295~N3;81vb9mi5;295~N3;81vb9mi6;295~N3;81vb9mi7;295~N3;81vb9mi8;295~N3;81vb9mi9;295~N3;81vb9mia;295~N3;81vb9mib;295~N3;81vb9mic;295~N3;81vb9mid;295~N3;81vb9mie;295~N3;81vb9mif;295~N3;81vb9j?0;295~N3;81vb9j?1;295~N3;81vb9j?2;295~N3;81vb9j?3;295~N3;81vb9j?4;295~N3;81vb9j?5;295~N3;81vb9j?6;295~N3;81vb9j?7;295~N3;81vb9kj0;295~N3;81vb9kj1;295~N3;81vb9kj2;295~N3;81vb9kj3;295~N3;81vb9kj4;295~N3;81vb9kj5;295~N3;81vb9kj6;295~N3;81vb9kj7;295~N3;81vb9kj8;295~N3;81vb9kj9;295~N3;81vb9kja;295~N3;81vb9kjb;295~N3;81vb9kjc;295~N3;81vb9kjd;295~N3;81vb9kje;295~N3;81vb9kjf;295~N3;81vb9ki0;295~N3;81vb9ki1;295~N3;81vb9ki2;295~N3;81vb9ki3;295~N3;81vb9ki4;295~N3;81vb9ki5;295~N3;81vb9ki6;295~N3;81vb9ki7;295~N3;81vb9ki8;295~N3;81vb9ki9;295~N3;81vb8>k2;295~N3;81vb8>k3;295~N3;81vb8>k4;295~N3;81vb8>k5;295~N3;81vb8>k6;295~N3;81vb8>k7;295~N3;81vb8>k8;295~N3;81vb8>k9;295~N3;81vb8>ka;295~N3;81vb8>kb;295~N3;81vb8>kc;295~N3;81vb8>kd;295~N3;81vb8>ke;295~N3;81vb8>kf;295~N3;81vb8>j0;295~N3;81vb8>j1;295~N3;81vb8>j2;295~N3;81vb8>j3;295~N3;81vb8>j4;295~N3;81vb8>j5;295~N3;81vb8>j6;295~N3;81vb8>j7;295~N3;81vb8>j8;295~N3;81vb8>j9;295~N3;81vb8>ja;295~N3;81vb8>jb;295~N3;81vb80;295~N3;81vb8l>1;295~N3;81vb8l>2;295~N3;81vb8l>3;295~N3;81vb8l>4;295~N3;81vb8l>5;295~N3;81vb8l>6;295~N3;81vb8l>7;295~N3;81vb8l>8;295~N3;81vb8l>9;295~N3;81vb8l>a;295~N3;81vb8l>b;295~N3;81vb8l>c;295~N3;81vb8l>d;295~N3;81vb8l>e;295~N3;81vb8l>f;295~N3;81vb8l=0;295~N3;81vb8l=1;295~N3;81vb8l=2;295~N3;81vb8l=3;295~N3;81vb8l=4;295~N3;81vb8l=5;295~N3;81vb8l=6;295~N3;81vb8l=7;295~N3;81vb8l=8;295~N3;81vb8l=9;295~N3;81vb8l=a;295~N3;81vb8l=b;295~N3;81vb8l=c;295~N3;81vb8l=d;295~N3;81vb8l=e;295~N3;81vb8l=f;295~N3;81vb8j76;295~N3;81vb8j77;295~N3;81vb8j78;295~N3;81vb8j79;295~N3;81vb8j7a;295~N3;81vb8j7b;295~N3;81vb8j7c;295~N3;81vb8j7d;295~N3;81vb8j7e;295~N3;81vb8j7f;295~N3;81vb8j60;295~N3;81vb8j61;295~N3;81vb8j62;295~N3;81vb8j63;295~N3;81vb8j64;295~N3;81vb8j65;295~N3;81vb8j66;295~N3;81vb8j67;295~N3;81vb8j68;295~N3;81vb8j69;295~N3;81vb8j6a;295~N3;81vb8j6b;295~N3;81vb8j6c;295~N3;81vb8j6d;295~N3;81vb8j6e;295~N3;81vb8j6f;295~N3;81vb8jn0;295~N3;81vb8jn1;295~N3;81vb8jn2;295~N3;81vb8jn3;295~N3;81vb8jn4;295~N3;81vb8jn5;295~N3;81vb8jn6;295~N3;81vb8jn7;295~N3;81vb8jn8;295~N3;81vb8jn9;295~N3;81vb8jna;295~N3;81vb8jnb;295~N3;81vb;>?2;295~N3;81vb;>?3;295~N3;81vb;>?4;295~N3;81vb;>?5;295~N3;81vb;>?6;295~N3;81vb;>?7;295~N3;81vb;>?8;295~N3;81vb;>?9;295~N3;81vb;>?a;295~N3;81vb;>?b;295~N3;81vb;>?c;295~N3;81vb;>?d;295~N3;81vb;>?e;295~N3;81vb;>?f;295~N3;81vb;>>0;295~N3;81vb;>>1;295~N3;81vb;>>2;295~N3;81vb;>>3;295~N3;81vb;>>4;295~N3;81vb;>>5;295~N3;81vb;>>6;295~N3;81vb;>>7;295~N3;81vb;>>8;295~N3;81vb;>>9;295~N3;81vb;>>a;295~N3;81vb;>>b;295~N3;81vb;>>c;295~N3;81vb;>>d;295~N3;81vb;>>e;295~N3;81vb;>>f;295~N3;81vb;>=0;295~N3;81vb;>=1;295~N3;81vb;>=2;295~N3;81vb;>=3;295~N3;81vb;>=4;295~N3;81vb;>=5;295~N3;81vb;>=6;295~N3;81vb;>=7;295~N3;81vb;<8e;295~N3;81vb;<8f;295~N3;81vb;<70;295~N3;81vb;<71;295~N3;81vb;<72;295~N3;81vb;<73;295~N3;81vb;<74;295~N3;81vb;<75;295~N3;81vb;<76;295~N3;81vb;<77;295~N3;81vb;<78;295~N3;81vb;<79;295~N3;81vb;<7a;295~N3;81vb;<7b;295~N3;81vb;<7c;295~N3;81vb;<7d;295~N3;81vb;<7e;295~N3;81vb;<7f;295~N3;81vb;<60;295~N3;81vb;<61;295~N3;81vb;<62;295~N3;81vb;<63;295~N3;81vb;<64;295~N3;81vb;<65;295~N3;81vb;<66;295~N3;81vb;<67;295~N3;81vb;<68;295~N3;81vb;<69;295~N3;81vb;<6a;295~N3;81vb;<6b;295~N3;81vb;<6c;295~N3;81vb;<6d;295~N3;81vb;<6e;295~N3;81vb;<6f;295~N3;81vb;0;295~N3;81vb;;>1;295~N3;81vb;;>2;295~N3;81vb;;>3;295~N3;81vb;;>4;295~N3;81vb;;>5;295~N3;81vb;;>6;295~N3;81vb;;>7;295~N3;81vb;;>8;295~N3;81vb;;>9;295~N3;81vb;;>a;295~N3;81vb;;>b;295~N3;81vb;;>c;295~N3;81vb;;>d;295~N3;81vb;;>e;295~N3;81vb;;>f;295~N3;81vb;9?a;295~N3;81vb;9?b;295~N3;81vb;9?c;295~N3;81vb;9?d;295~N3;81vb;9?e;295~N3;81vb;9?f;295~N3;81vb;9>0;295~N3;81vb;9>1;295~N3;81vb;9>2;295~N3;81vb;9>3;295~N3;81vb;9>4;295~N3;81vb;9>5;295~N3;81vb;9>6;295~N3;81vb;9>7;295~N3;81vb;9>8;295~N3;81vb;9>9;295~N3;81vb;9>a;295~N3;81vb;9>b;295~N3;81vb;9>c;295~N3;81vb;9>d;295~N3;81vb;o=4;295~N3;81vb;o=5;295~N3;81vb;o=6;295~N3;81vb;o=7;295~N3;81vb;o=8;295~N3;81vb;o=9;295~N3;81vb;o=a;295~N3;81vb;o=b;295~N3;81vb;o=c;295~N3;81vb;o=d;295~N3;81vb;o=e;295~N3;81vb;o=f;295~N3;81vb;o<0;295~N3;81vb;o<1;295~N3;81vb;o<2;295~N3;81vb;o<3;295~N3;81vb;o<4;295~N3;81vb;o<5;295~N3;81vb;o<6;295~N3;81vb;o<7;295~N3;81vqpsO@Byb0cb===_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000df_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000df_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dc_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000da_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000da_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d6_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cf_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ce_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cb_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bb_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a4_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a2_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000099_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000098_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000097_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000096_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000094_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000094_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000092_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000091_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000019_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000b_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000b_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000a_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000008d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000008c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000066_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000065_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000064_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000063_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000062_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000061_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000060_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000005f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000005e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000151_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000150_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000149_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000148_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000147_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000146_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000145_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000144_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000143_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000142_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000141_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000140_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000184_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000183_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000182_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000181_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000180_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000179_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000178_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000177_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000176_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000175_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000171_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000170_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000021d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000021c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000021b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000021a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000219_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000218_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000217_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000216_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000215_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000214_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000213_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000212_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000211_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000210_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000209_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000208_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000207_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000206_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000250_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000249_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000248_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000247_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000243_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000242_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000241_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000240_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000239_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000283_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000282_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000281_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000280_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000279_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000278_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000277_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000276_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000275_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000274_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000273_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000272_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000271_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000270_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000026f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000026e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000026d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000026c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk0000029f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000031c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000031b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000031a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000319_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000318_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000317_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000316_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000315_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000314_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000313_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000312_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000311_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000310_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000309_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000308_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000307_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000306_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000305_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000349_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000348_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000347_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000346_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000345_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000344_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000343_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000342_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000341_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000340_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000339_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000338_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000382_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000381_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000380_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000379_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000378_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000377_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000376_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000375_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000374_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000373_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000372_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000371_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000370_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk0000039f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk0000039e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000041b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000041a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000419_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000418_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000417_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000416_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000415_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000414_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000413_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000412_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000411_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000410_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000409_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000408_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000407_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000406_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000405_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000404_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000449_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000448_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000447_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000446_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000445_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000444_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000443_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000442_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000441_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000440_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000439_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000438_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000437_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000481_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000480_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000479_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000478_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000477_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000476_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000475_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000474_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000473_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000472_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000471_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000470_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk0000049f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk0000049e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk0000049d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000051a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000519_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000518_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000517_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000516_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000515_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000514_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000513_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000512_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000511_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000510_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000509_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000508_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000507_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000506_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000505_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000504_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000503_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000054d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000054c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000054b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000054a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000549_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000548_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000547_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000546_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000545_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000544_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000543_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000542_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000541_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000540_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000539_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000538_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000537_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000536_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000580_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000579_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000578_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000577_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000576_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000575_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000574_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000573_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000572_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000571_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000570_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000569_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk0000059f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk0000059e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk0000059d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk0000059c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000072a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000729_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000728_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000727_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000726_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000725_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000724_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000723_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000722_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000721_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000720_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000719_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000781_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000780_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000779_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000778_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000777_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000776_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000775_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000774_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000773_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000772_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000771_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000770_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [46 : 0] NlwRenamedSig_OI_dout_1; + wire [46 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c13 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8e ), + .Q(\blk00000003/sig00000881 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c12 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000839 ), + .Q(\blk00000003/sig00000b8e ), + .Q15(\NLW_blk00000003/blk00000c12_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c11 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8d ), + .Q(\blk00000003/sig00000880 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c10 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000838 ), + .Q(\blk00000003/sig00000b8d ), + .Q15(\NLW_blk00000003/blk00000c10_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0f ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8c ), + .Q(\blk00000003/sig0000087f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000837 ), + .Q(\blk00000003/sig00000b8c ), + .Q15(\NLW_blk00000003/blk00000c0e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0d ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8b ), + .Q(\blk00000003/sig0000087e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000836 ), + .Q(\blk00000003/sig00000b8b ), + .Q15(\NLW_blk00000003/blk00000c0c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0b ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8a ), + .Q(\blk00000003/sig0000087c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000834 ), + .Q(\blk00000003/sig00000b8a ), + .Q15(\NLW_blk00000003/blk00000c0a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c09 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b89 ), + .Q(\blk00000003/sig0000087b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c08 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000833 ), + .Q(\blk00000003/sig00000b89 ), + .Q15(\NLW_blk00000003/blk00000c08_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c07 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b88 ), + .Q(\blk00000003/sig0000087d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c06 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000835 ), + .Q(\blk00000003/sig00000b88 ), + .Q15(\NLW_blk00000003/blk00000c06_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c05 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b87 ), + .Q(\blk00000003/sig00000879 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c04 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000831 ), + .Q(\blk00000003/sig00000b87 ), + .Q15(\NLW_blk00000003/blk00000c04_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c03 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b86 ), + .Q(\blk00000003/sig00000878 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c02 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000830 ), + .Q(\blk00000003/sig00000b86 ), + .Q15(\NLW_blk00000003/blk00000c02_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c01 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b85 ), + .Q(\blk00000003/sig0000087a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c00 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000832 ), + .Q(\blk00000003/sig00000b85 ), + .Q15(\NLW_blk00000003/blk00000c00_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bff ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b84 ), + .Q(\blk00000003/sig00000876 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082e ), + .Q(\blk00000003/sig00000b84 ), + .Q15(\NLW_blk00000003/blk00000bfe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfd ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b83 ), + .Q(\blk00000003/sig00000875 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082d ), + .Q(\blk00000003/sig00000b83 ), + .Q15(\NLW_blk00000003/blk00000bfc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b82 ), + .Q(\blk00000003/sig00000877 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082f ), + .Q(\blk00000003/sig00000b82 ), + .Q15(\NLW_blk00000003/blk00000bfa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b81 ), + .Q(\blk00000003/sig00000873 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082b ), + .Q(\blk00000003/sig00000b81 ), + .Q15(\NLW_blk00000003/blk00000bf8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b80 ), + .Q(\blk00000003/sig00000872 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082a ), + .Q(\blk00000003/sig00000b80 ), + .Q15(\NLW_blk00000003/blk00000bf6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7f ), + .Q(\blk00000003/sig00000874 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082c ), + .Q(\blk00000003/sig00000b7f ), + .Q15(\NLW_blk00000003/blk00000bf4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf3 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7e ), + .Q(\blk00000003/sig00000870 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000828 ), + .Q(\blk00000003/sig00000b7e ), + .Q15(\NLW_blk00000003/blk00000bf2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf1 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7d ), + .Q(\blk00000003/sig0000086f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000827 ), + .Q(\blk00000003/sig00000b7d ), + .Q15(\NLW_blk00000003/blk00000bf0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bef ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7c ), + .Q(\blk00000003/sig00000871 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bee ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000829 ), + .Q(\blk00000003/sig00000b7c ), + .Q15(\NLW_blk00000003/blk00000bee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bed ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7b ), + .Q(\blk00000003/sig0000086d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bec ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000825 ), + .Q(\blk00000003/sig00000b7b ), + .Q15(\NLW_blk00000003/blk00000bec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000beb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7a ), + .Q(\blk00000003/sig0000086c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bea ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000824 ), + .Q(\blk00000003/sig00000b7a ), + .Q15(\NLW_blk00000003/blk00000bea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b79 ), + .Q(\blk00000003/sig0000086e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000826 ), + .Q(\blk00000003/sig00000b79 ), + .Q15(\NLW_blk00000003/blk00000be8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b78 ), + .Q(\blk00000003/sig0000086a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000822 ), + .Q(\blk00000003/sig00000b78 ), + .Q15(\NLW_blk00000003/blk00000be6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b77 ), + .Q(\blk00000003/sig0000086b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000823 ), + .Q(\blk00000003/sig00000b77 ), + .Q15(\NLW_blk00000003/blk00000be4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be3 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b76 ), + .Q(\blk00000003/sig000008b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000851 ), + .Q(\blk00000003/sig00000b76 ), + .Q15(\NLW_blk00000003/blk00000be2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be1 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b75 ), + .Q(\blk00000003/sig000008b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000850 ), + .Q(\blk00000003/sig00000b75 ), + .Q15(\NLW_blk00000003/blk00000be0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdf ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b74 ), + .Q(\blk00000003/sig000008ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bde ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084e ), + .Q(\blk00000003/sig00000b74 ), + .Q15(\NLW_blk00000003/blk00000bde_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdd ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b73 ), + .Q(\blk00000003/sig000008ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bdc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084d ), + .Q(\blk00000003/sig00000b73 ), + .Q15(\NLW_blk00000003/blk00000bdc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b72 ), + .Q(\blk00000003/sig000008af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bda ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084f ), + .Q(\blk00000003/sig00000b72 ), + .Q15(\NLW_blk00000003/blk00000bda_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b71 ), + .Q(\blk00000003/sig000008ab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084b ), + .Q(\blk00000003/sig00000b71 ), + .Q15(\NLW_blk00000003/blk00000bd8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b70 ), + .Q(\blk00000003/sig000008aa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084a ), + .Q(\blk00000003/sig00000b70 ), + .Q15(\NLW_blk00000003/blk00000bd6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6f ), + .Q(\blk00000003/sig000008ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084c ), + .Q(\blk00000003/sig00000b6f ), + .Q15(\NLW_blk00000003/blk00000bd4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd3 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6e ), + .Q(\blk00000003/sig000008a9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000849 ), + .Q(\blk00000003/sig00000b6e ), + .Q15(\NLW_blk00000003/blk00000bd2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd1 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6d ), + .Q(\blk00000003/sig000008a8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000848 ), + .Q(\blk00000003/sig00000b6d ), + .Q15(\NLW_blk00000003/blk00000bd0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcf ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6c ), + .Q(\blk00000003/sig000008a7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bce ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000847 ), + .Q(\blk00000003/sig00000b6c ), + .Q15(\NLW_blk00000003/blk00000bce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcd ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6b ), + .Q(\blk00000003/sig000008a6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bcc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000846 ), + .Q(\blk00000003/sig00000b6b ), + .Q15(\NLW_blk00000003/blk00000bcc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6a ), + .Q(\blk00000003/sig000008a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bca ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000844 ), + .Q(\blk00000003/sig00000b6a ), + .Q15(\NLW_blk00000003/blk00000bca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b69 ), + .Q(\blk00000003/sig000008a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000843 ), + .Q(\blk00000003/sig00000b69 ), + .Q15(\NLW_blk00000003/blk00000bc8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b68 ), + .Q(\blk00000003/sig000008a5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000845 ), + .Q(\blk00000003/sig00000b68 ), + .Q15(\NLW_blk00000003/blk00000bc6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b67 ), + .Q(\blk00000003/sig000008a1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000841 ), + .Q(\blk00000003/sig00000b67 ), + .Q15(\NLW_blk00000003/blk00000bc4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc3 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b66 ), + .Q(\blk00000003/sig000008a0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000840 ), + .Q(\blk00000003/sig00000b66 ), + .Q15(\NLW_blk00000003/blk00000bc2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc1 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b65 ), + .Q(\blk00000003/sig000008a2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000842 ), + .Q(\blk00000003/sig00000b65 ), + .Q15(\NLW_blk00000003/blk00000bc0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbf ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b64 ), + .Q(\blk00000003/sig0000089e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083e ), + .Q(\blk00000003/sig00000b64 ), + .Q15(\NLW_blk00000003/blk00000bbe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbd ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b63 ), + .Q(\blk00000003/sig0000089d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083d ), + .Q(\blk00000003/sig00000b63 ), + .Q15(\NLW_blk00000003/blk00000bbc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b62 ), + .Q(\blk00000003/sig0000089f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bba ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083f ), + .Q(\blk00000003/sig00000b62 ), + .Q15(\NLW_blk00000003/blk00000bba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b61 ), + .Q(\blk00000003/sig0000089c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083c ), + .Q(\blk00000003/sig00000b61 ), + .Q15(\NLW_blk00000003/blk00000bb8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b60 ), + .Q(\blk00000003/sig0000089b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083b ), + .Q(\blk00000003/sig00000b60 ), + .Q15(\NLW_blk00000003/blk00000bb6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b5f ), + .Q(\blk00000003/sig0000089a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083a ), + .Q(\blk00000003/sig00000b5f ), + .Q15(\NLW_blk00000003/blk00000bb4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb3 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5e ), + .Q(\blk00000003/sig00000839 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000809 ), + .Q(\blk00000003/sig00000b5e ), + .Q15(\NLW_blk00000003/blk00000bb2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb1 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5d ), + .Q(\blk00000003/sig00000838 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000808 ), + .Q(\blk00000003/sig00000b5d ), + .Q15(\NLW_blk00000003/blk00000bb0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000baf ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5c ), + .Q(\blk00000003/sig00000837 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bae ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000807 ), + .Q(\blk00000003/sig00000b5c ), + .Q15(\NLW_blk00000003/blk00000bae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bad ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5b ), + .Q(\blk00000003/sig00000836 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bac ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000806 ), + .Q(\blk00000003/sig00000b5b ), + .Q15(\NLW_blk00000003/blk00000bac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bab ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5a ), + .Q(\blk00000003/sig00000835 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000baa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000805 ), + .Q(\blk00000003/sig00000b5a ), + .Q15(\NLW_blk00000003/blk00000baa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba9 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b59 ), + .Q(\blk00000003/sig00000833 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000803 ), + .Q(\blk00000003/sig00000b59 ), + .Q15(\NLW_blk00000003/blk00000ba8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba7 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b58 ), + .Q(\blk00000003/sig00000832 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000802 ), + .Q(\blk00000003/sig00000b58 ), + .Q15(\NLW_blk00000003/blk00000ba6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba5 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b57 ), + .Q(\blk00000003/sig00000834 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000804 ), + .Q(\blk00000003/sig00000b57 ), + .Q15(\NLW_blk00000003/blk00000ba4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba3 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b56 ), + .Q(\blk00000003/sig00000830 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000800 ), + .Q(\blk00000003/sig00000b56 ), + .Q15(\NLW_blk00000003/blk00000ba2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba1 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b55 ), + .Q(\blk00000003/sig0000082f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007ff ), + .Q(\blk00000003/sig00000b55 ), + .Q15(\NLW_blk00000003/blk00000ba0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b54 ), + .Q(\blk00000003/sig00000831 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000801 ), + .Q(\blk00000003/sig00000b54 ), + .Q15(\NLW_blk00000003/blk00000b9e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b53 ), + .Q(\blk00000003/sig0000082d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fd ), + .Q(\blk00000003/sig00000b53 ), + .Q15(\NLW_blk00000003/blk00000b9c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b52 ), + .Q(\blk00000003/sig0000082c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fc ), + .Q(\blk00000003/sig00000b52 ), + .Q15(\NLW_blk00000003/blk00000b9a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b99 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b51 ), + .Q(\blk00000003/sig0000082e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b98 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fe ), + .Q(\blk00000003/sig00000b51 ), + .Q15(\NLW_blk00000003/blk00000b98_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b97 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b50 ), + .Q(\blk00000003/sig0000082b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b96 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fb ), + .Q(\blk00000003/sig00000b50 ), + .Q15(\NLW_blk00000003/blk00000b96_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b95 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4f ), + .Q(\blk00000003/sig0000082a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b94 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fa ), + .Q(\blk00000003/sig00000b4f ), + .Q15(\NLW_blk00000003/blk00000b94_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b93 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4e ), + .Q(\blk00000003/sig00000829 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b92 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f9 ), + .Q(\blk00000003/sig00000b4e ), + .Q15(\NLW_blk00000003/blk00000b92_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b91 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4d ), + .Q(\blk00000003/sig00000828 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b90 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f8 ), + .Q(\blk00000003/sig00000b4d ), + .Q15(\NLW_blk00000003/blk00000b90_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4c ), + .Q(\blk00000003/sig00000826 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f6 ), + .Q(\blk00000003/sig00000b4c ), + .Q15(\NLW_blk00000003/blk00000b8e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4b ), + .Q(\blk00000003/sig00000825 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f5 ), + .Q(\blk00000003/sig00000b4b ), + .Q15(\NLW_blk00000003/blk00000b8c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4a ), + .Q(\blk00000003/sig00000827 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f7 ), + .Q(\blk00000003/sig00000b4a ), + .Q15(\NLW_blk00000003/blk00000b8a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b89 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b49 ), + .Q(\blk00000003/sig00000823 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b88 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f3 ), + .Q(\blk00000003/sig00000b49 ), + .Q15(\NLW_blk00000003/blk00000b88_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b87 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b48 ), + .Q(\blk00000003/sig00000822 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b86 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f2 ), + .Q(\blk00000003/sig00000b48 ), + .Q15(\NLW_blk00000003/blk00000b86_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b85 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b47 ), + .Q(\blk00000003/sig00000824 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b84 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f4 ), + .Q(\blk00000003/sig00000b47 ), + .Q15(\NLW_blk00000003/blk00000b84_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b83 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b46 ), + .Q(\blk00000003/sig00000851 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b82 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000821 ), + .Q(\blk00000003/sig00000b46 ), + .Q15(\NLW_blk00000003/blk00000b82_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b81 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b45 ), + .Q(\blk00000003/sig0000084f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b80 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081f ), + .Q(\blk00000003/sig00000b45 ), + .Q15(\NLW_blk00000003/blk00000b80_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b44 ), + .Q(\blk00000003/sig0000084e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081e ), + .Q(\blk00000003/sig00000b44 ), + .Q15(\NLW_blk00000003/blk00000b7e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b43 ), + .Q(\blk00000003/sig00000850 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000820 ), + .Q(\blk00000003/sig00000b43 ), + .Q15(\NLW_blk00000003/blk00000b7c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b42 ), + .Q(\blk00000003/sig0000084c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081c ), + .Q(\blk00000003/sig00000b42 ), + .Q15(\NLW_blk00000003/blk00000b7a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b79 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b41 ), + .Q(\blk00000003/sig0000084b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b78 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081b ), + .Q(\blk00000003/sig00000b41 ), + .Q15(\NLW_blk00000003/blk00000b78_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b77 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b40 ), + .Q(\blk00000003/sig0000084d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b76 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081d ), + .Q(\blk00000003/sig00000b40 ), + .Q15(\NLW_blk00000003/blk00000b76_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b75 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3f ), + .Q(\blk00000003/sig00000849 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b74 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000819 ), + .Q(\blk00000003/sig00000b3f ), + .Q15(\NLW_blk00000003/blk00000b74_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b73 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3e ), + .Q(\blk00000003/sig00000848 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b72 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000818 ), + .Q(\blk00000003/sig00000b3e ), + .Q15(\NLW_blk00000003/blk00000b72_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b71 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3d ), + .Q(\blk00000003/sig0000084a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b70 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081a ), + .Q(\blk00000003/sig00000b3d ), + .Q15(\NLW_blk00000003/blk00000b70_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3c ), + .Q(\blk00000003/sig00000847 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000817 ), + .Q(\blk00000003/sig00000b3c ), + .Q15(\NLW_blk00000003/blk00000b6e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3b ), + .Q(\blk00000003/sig00000846 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000816 ), + .Q(\blk00000003/sig00000b3b ), + .Q15(\NLW_blk00000003/blk00000b6c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3a ), + .Q(\blk00000003/sig00000845 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000815 ), + .Q(\blk00000003/sig00000b3a ), + .Q15(\NLW_blk00000003/blk00000b6a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b69 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b39 ), + .Q(\blk00000003/sig00000844 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b68 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000814 ), + .Q(\blk00000003/sig00000b39 ), + .Q15(\NLW_blk00000003/blk00000b68_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b67 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b38 ), + .Q(\blk00000003/sig00000842 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b66 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000812 ), + .Q(\blk00000003/sig00000b38 ), + .Q15(\NLW_blk00000003/blk00000b66_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b65 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b37 ), + .Q(\blk00000003/sig00000841 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b64 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000811 ), + .Q(\blk00000003/sig00000b37 ), + .Q15(\NLW_blk00000003/blk00000b64_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b63 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b36 ), + .Q(\blk00000003/sig00000843 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b62 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000813 ), + .Q(\blk00000003/sig00000b36 ), + .Q15(\NLW_blk00000003/blk00000b62_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b61 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b35 ), + .Q(\blk00000003/sig0000083f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b60 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080f ), + .Q(\blk00000003/sig00000b35 ), + .Q15(\NLW_blk00000003/blk00000b60_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b34 ), + .Q(\blk00000003/sig0000083e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080e ), + .Q(\blk00000003/sig00000b34 ), + .Q15(\NLW_blk00000003/blk00000b5e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b33 ), + .Q(\blk00000003/sig00000840 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000810 ), + .Q(\blk00000003/sig00000b33 ), + .Q15(\NLW_blk00000003/blk00000b5c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b32 ), + .Q(\blk00000003/sig0000083c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080c ), + .Q(\blk00000003/sig00000b32 ), + .Q15(\NLW_blk00000003/blk00000b5a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b59 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b31 ), + .Q(\blk00000003/sig0000083b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b58 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080b ), + .Q(\blk00000003/sig00000b31 ), + .Q15(\NLW_blk00000003/blk00000b58_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b57 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b30 ), + .Q(\blk00000003/sig0000083d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b56 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080d ), + .Q(\blk00000003/sig00000b30 ), + .Q15(\NLW_blk00000003/blk00000b56_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b55 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b2f ), + .Q(\blk00000003/sig0000083a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b54 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080a ), + .Q(\blk00000003/sig00000b2f ), + .Q15(\NLW_blk00000003/blk00000b54_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b53 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000b2e ), + .Q(\blk00000003/sig000009ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b52 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000761 ), + .Q(\blk00000003/sig00000b2e ), + .Q15(\NLW_blk00000003/blk00000b52_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b51 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b2d ), + .Q(\blk00000003/sig00000808 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b50 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d8 ), + .Q(\blk00000003/sig00000b2d ), + .Q15(\NLW_blk00000003/blk00000b50_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b2c ), + .Q(\blk00000003/sig00000807 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d7 ), + .Q(\blk00000003/sig00000b2c ), + .Q15(\NLW_blk00000003/blk00000b4e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b2b ), + .Q(\blk00000003/sig00000809 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d9 ), + .Q(\blk00000003/sig00000b2b ), + .Q15(\NLW_blk00000003/blk00000b4c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b2a ), + .Q(\blk00000003/sig00000806 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d6 ), + .Q(\blk00000003/sig00000b2a ), + .Q15(\NLW_blk00000003/blk00000b4a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b49 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b29 ), + .Q(\blk00000003/sig00000805 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b48 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d5 ), + .Q(\blk00000003/sig00000b29 ), + .Q15(\NLW_blk00000003/blk00000b48_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b47 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b28 ), + .Q(\blk00000003/sig00000804 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b46 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d4 ), + .Q(\blk00000003/sig00000b28 ), + .Q15(\NLW_blk00000003/blk00000b46_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b45 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b27 ), + .Q(\blk00000003/sig00000803 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b44 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d3 ), + .Q(\blk00000003/sig00000b27 ), + .Q15(\NLW_blk00000003/blk00000b44_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b43 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b26 ), + .Q(\blk00000003/sig00000801 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b42 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d1 ), + .Q(\blk00000003/sig00000b26 ), + .Q15(\NLW_blk00000003/blk00000b42_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b41 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b25 ), + .Q(\blk00000003/sig00000800 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b40 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d0 ), + .Q(\blk00000003/sig00000b25 ), + .Q15(\NLW_blk00000003/blk00000b40_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b24 ), + .Q(\blk00000003/sig00000802 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d2 ), + .Q(\blk00000003/sig00000b24 ), + .Q15(\NLW_blk00000003/blk00000b3e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b23 ), + .Q(\blk00000003/sig000007fe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ce ), + .Q(\blk00000003/sig00000b23 ), + .Q15(\NLW_blk00000003/blk00000b3c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b22 ), + .Q(\blk00000003/sig000007fd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007cd ), + .Q(\blk00000003/sig00000b22 ), + .Q15(\NLW_blk00000003/blk00000b3a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b39 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b21 ), + .Q(\blk00000003/sig000007ff ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b38 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007cf ), + .Q(\blk00000003/sig00000b21 ), + .Q15(\NLW_blk00000003/blk00000b38_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b37 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b20 ), + .Q(\blk00000003/sig000007fb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b36 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007cb ), + .Q(\blk00000003/sig00000b20 ), + .Q15(\NLW_blk00000003/blk00000b36_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b35 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1f ), + .Q(\blk00000003/sig000007fa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b34 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ca ), + .Q(\blk00000003/sig00000b1f ), + .Q15(\NLW_blk00000003/blk00000b34_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b33 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1e ), + .Q(\blk00000003/sig000007fc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b32 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007cc ), + .Q(\blk00000003/sig00000b1e ), + .Q15(\NLW_blk00000003/blk00000b32_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b31 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1d ), + .Q(\blk00000003/sig000007f9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b30 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c9 ), + .Q(\blk00000003/sig00000b1d ), + .Q15(\NLW_blk00000003/blk00000b30_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1c ), + .Q(\blk00000003/sig000007f8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c8 ), + .Q(\blk00000003/sig00000b1c ), + .Q15(\NLW_blk00000003/blk00000b2e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1b ), + .Q(\blk00000003/sig000007f7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c7 ), + .Q(\blk00000003/sig00000b1b ), + .Q15(\NLW_blk00000003/blk00000b2c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1a ), + .Q(\blk00000003/sig000007f6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c6 ), + .Q(\blk00000003/sig00000b1a ), + .Q15(\NLW_blk00000003/blk00000b2a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b29 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b19 ), + .Q(\blk00000003/sig000007f4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b28 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c4 ), + .Q(\blk00000003/sig00000b19 ), + .Q15(\NLW_blk00000003/blk00000b28_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b27 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b18 ), + .Q(\blk00000003/sig000007f3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b26 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c3 ), + .Q(\blk00000003/sig00000b18 ), + .Q15(\NLW_blk00000003/blk00000b26_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b25 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b17 ), + .Q(\blk00000003/sig000007f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b24 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c5 ), + .Q(\blk00000003/sig00000b17 ), + .Q15(\NLW_blk00000003/blk00000b24_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b23 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b16 ), + .Q(\blk00000003/sig000007f2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b22 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c2 ), + .Q(\blk00000003/sig00000b16 ), + .Q15(\NLW_blk00000003/blk00000b22_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b21 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b15 ), + .Q(\blk00000003/sig00000821 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b20 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007f1 ), + .Q(\blk00000003/sig00000b15 ), + .Q15(\NLW_blk00000003/blk00000b20_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b14 ), + .Q(\blk00000003/sig00000820 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007f0 ), + .Q(\blk00000003/sig00000b14 ), + .Q15(\NLW_blk00000003/blk00000b1e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b13 ), + .Q(\blk00000003/sig0000081f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ef ), + .Q(\blk00000003/sig00000b13 ), + .Q15(\NLW_blk00000003/blk00000b1c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b12 ), + .Q(\blk00000003/sig0000081d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ed ), + .Q(\blk00000003/sig00000b12 ), + .Q15(\NLW_blk00000003/blk00000b1a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b19 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b11 ), + .Q(\blk00000003/sig0000081c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b18 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ec ), + .Q(\blk00000003/sig00000b11 ), + .Q15(\NLW_blk00000003/blk00000b18_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b17 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b10 ), + .Q(\blk00000003/sig0000081e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b16 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ee ), + .Q(\blk00000003/sig00000b10 ), + .Q15(\NLW_blk00000003/blk00000b16_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b15 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0f ), + .Q(\blk00000003/sig0000081a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b14 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ea ), + .Q(\blk00000003/sig00000b0f ), + .Q15(\NLW_blk00000003/blk00000b14_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b13 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0e ), + .Q(\blk00000003/sig00000819 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b12 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e9 ), + .Q(\blk00000003/sig00000b0e ), + .Q15(\NLW_blk00000003/blk00000b12_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b11 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0d ), + .Q(\blk00000003/sig0000081b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b10 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007eb ), + .Q(\blk00000003/sig00000b0d ), + .Q15(\NLW_blk00000003/blk00000b10_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0c ), + .Q(\blk00000003/sig00000817 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e7 ), + .Q(\blk00000003/sig00000b0c ), + .Q15(\NLW_blk00000003/blk00000b0e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0b ), + .Q(\blk00000003/sig00000816 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e6 ), + .Q(\blk00000003/sig00000b0b ), + .Q15(\NLW_blk00000003/blk00000b0c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0a ), + .Q(\blk00000003/sig00000818 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e8 ), + .Q(\blk00000003/sig00000b0a ), + .Q15(\NLW_blk00000003/blk00000b0a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b09 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b09 ), + .Q(\blk00000003/sig00000815 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b08 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e5 ), + .Q(\blk00000003/sig00000b09 ), + .Q15(\NLW_blk00000003/blk00000b08_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b07 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b08 ), + .Q(\blk00000003/sig00000814 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b06 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e4 ), + .Q(\blk00000003/sig00000b08 ), + .Q15(\NLW_blk00000003/blk00000b06_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b05 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b07 ), + .Q(\blk00000003/sig00000813 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b04 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e3 ), + .Q(\blk00000003/sig00000b07 ), + .Q15(\NLW_blk00000003/blk00000b04_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b03 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b06 ), + .Q(\blk00000003/sig00000812 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b02 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e2 ), + .Q(\blk00000003/sig00000b06 ), + .Q15(\NLW_blk00000003/blk00000b02_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b01 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b05 ), + .Q(\blk00000003/sig00000810 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b00 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e0 ), + .Q(\blk00000003/sig00000b05 ), + .Q15(\NLW_blk00000003/blk00000b00_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aff ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b04 ), + .Q(\blk00000003/sig0000080f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007df ), + .Q(\blk00000003/sig00000b04 ), + .Q15(\NLW_blk00000003/blk00000afe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afd ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b03 ), + .Q(\blk00000003/sig00000811 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e1 ), + .Q(\blk00000003/sig00000b03 ), + .Q15(\NLW_blk00000003/blk00000afc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afb ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b02 ), + .Q(\blk00000003/sig0000080d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007dd ), + .Q(\blk00000003/sig00000b02 ), + .Q15(\NLW_blk00000003/blk00000afa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af9 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b01 ), + .Q(\blk00000003/sig0000080c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007dc ), + .Q(\blk00000003/sig00000b01 ), + .Q15(\NLW_blk00000003/blk00000af8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af7 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b00 ), + .Q(\blk00000003/sig0000080e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007de ), + .Q(\blk00000003/sig00000b00 ), + .Q15(\NLW_blk00000003/blk00000af6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af5 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000aff ), + .Q(\blk00000003/sig0000080a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007da ), + .Q(\blk00000003/sig00000aff ), + .Q15(\NLW_blk00000003/blk00000af4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af3 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000afe ), + .Q(\blk00000003/sig0000080b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007db ), + .Q(\blk00000003/sig00000afe ), + .Q15(\NLW_blk00000003/blk00000af2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000afd ), + .Q(\blk00000003/sig00000937 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000760 ), + .Q(\blk00000003/sig00000afd ), + .Q15(\NLW_blk00000003/blk00000af0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000afc ), + .Q(\blk00000003/sig000001c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aee ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a9a ), + .Q(\blk00000003/sig00000afc ), + .Q15(\NLW_blk00000003/blk00000aee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000afb ), + .Q(\blk00000003/sig000001c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aec ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a98 ), + .Q(\blk00000003/sig00000afb ), + .Q15(\NLW_blk00000003/blk00000aec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aeb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000afa ), + .Q(\blk00000003/sig000001c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aea ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a96 ), + .Q(\blk00000003/sig00000afa ), + .Q15(\NLW_blk00000003/blk00000aea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af9 ), + .Q(\blk00000003/sig000001c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a94 ), + .Q(\blk00000003/sig00000af9 ), + .Q15(\NLW_blk00000003/blk00000ae8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af8 ), + .Q(\blk00000003/sig000001c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a92 ), + .Q(\blk00000003/sig00000af8 ), + .Q15(\NLW_blk00000003/blk00000ae6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af7 ), + .Q(\blk00000003/sig000001c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a90 ), + .Q(\blk00000003/sig00000af7 ), + .Q15(\NLW_blk00000003/blk00000ae4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af6 ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a8e ), + .Q(\blk00000003/sig00000af6 ), + .Q15(\NLW_blk00000003/blk00000ae2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af5 ), + .Q(\blk00000003/sig000001c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a8c ), + .Q(\blk00000003/sig00000af5 ), + .Q15(\NLW_blk00000003/blk00000ae0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000adf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af4 ), + .Q(\blk00000003/sig000001c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ade ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a8a ), + .Q(\blk00000003/sig00000af4 ), + .Q15(\NLW_blk00000003/blk00000ade_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000add ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af3 ), + .Q(\blk00000003/sig000001bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000adc ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a86 ), + .Q(\blk00000003/sig00000af3 ), + .Q15(\NLW_blk00000003/blk00000adc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000adb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af2 ), + .Q(\blk00000003/sig000001be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ada ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a84 ), + .Q(\blk00000003/sig00000af2 ), + .Q15(\NLW_blk00000003/blk00000ada_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af1 ), + .Q(\blk00000003/sig000001c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a88 ), + .Q(\blk00000003/sig00000af1 ), + .Q15(\NLW_blk00000003/blk00000ad8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af0 ), + .Q(\blk00000003/sig000001bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a7c ), + .Q(\blk00000003/sig00000af0 ), + .Q15(\NLW_blk00000003/blk00000ad6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aef ), + .Q(\blk00000003/sig000001bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a80 ), + .Q(\blk00000003/sig00000aef ), + .Q15(\NLW_blk00000003/blk00000ad4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aee ), + .Q(\blk00000003/sig000001bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a82 ), + .Q(\blk00000003/sig00000aee ), + .Q15(\NLW_blk00000003/blk00000ad2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aed ), + .Q(\blk00000003/sig000001b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a76 ), + .Q(\blk00000003/sig00000aed ), + .Q15(\NLW_blk00000003/blk00000ad0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000acf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aec ), + .Q(\blk00000003/sig000001b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ace ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a7a ), + .Q(\blk00000003/sig00000aec ), + .Q15(\NLW_blk00000003/blk00000ace_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000acd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aeb ), + .Q(\blk00000003/sig000001ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000acc ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a7e ), + .Q(\blk00000003/sig00000aeb ), + .Q15(\NLW_blk00000003/blk00000acc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000acb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aea ), + .Q(\blk00000003/sig000001b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aca ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a78 ), + .Q(\blk00000003/sig00000aea ), + .Q15(\NLW_blk00000003/blk00000aca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae9 ), + .Q(\blk00000003/sig000001b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a70 ), + .Q(\blk00000003/sig00000ae9 ), + .Q15(\NLW_blk00000003/blk00000ac8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae8 ), + .Q(\blk00000003/sig000001b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a74 ), + .Q(\blk00000003/sig00000ae8 ), + .Q15(\NLW_blk00000003/blk00000ac6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae7 ), + .Q(\blk00000003/sig000001b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a72 ), + .Q(\blk00000003/sig00000ae7 ), + .Q15(\NLW_blk00000003/blk00000ac4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae6 ), + .Q(\blk00000003/sig000001b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a6c ), + .Q(\blk00000003/sig00000ae6 ), + .Q15(\NLW_blk00000003/blk00000ac2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae5 ), + .Q(\blk00000003/sig00000152 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a6a ), + .Q(\blk00000003/sig00000ae5 ), + .Q15(\NLW_blk00000003/blk00000ac0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae4 ), + .Q(\blk00000003/sig000001b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abe ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a6e ), + .Q(\blk00000003/sig00000ae4 ), + .Q15(\NLW_blk00000003/blk00000abe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae3 ), + .Q(\blk00000003/sig00000150 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abc ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a62 ), + .Q(\blk00000003/sig00000ae3 ), + .Q15(\NLW_blk00000003/blk00000abc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae2 ), + .Q(\blk00000003/sig0000014f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aba ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a66 ), + .Q(\blk00000003/sig00000ae2 ), + .Q15(\NLW_blk00000003/blk00000aba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae1 ), + .Q(\blk00000003/sig00000151 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a68 ), + .Q(\blk00000003/sig00000ae1 ), + .Q15(\NLW_blk00000003/blk00000ab8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae0 ), + .Q(\blk00000003/sig0000014d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a5c ), + .Q(\blk00000003/sig00000ae0 ), + .Q15(\NLW_blk00000003/blk00000ab6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000adf ), + .Q(\blk00000003/sig0000014c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a60 ), + .Q(\blk00000003/sig00000adf ), + .Q15(\NLW_blk00000003/blk00000ab4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ade ), + .Q(\blk00000003/sig0000014e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a64 ), + .Q(\blk00000003/sig00000ade ), + .Q15(\NLW_blk00000003/blk00000ab2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000add ), + .Q(\blk00000003/sig0000014b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a5e ), + .Q(\blk00000003/sig00000add ), + .Q15(\NLW_blk00000003/blk00000ab0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aaf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000adc ), + .Q(\blk00000003/sig0000014a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aae ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a56 ), + .Q(\blk00000003/sig00000adc ), + .Q15(\NLW_blk00000003/blk00000aae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000adb ), + .Q(\blk00000003/sig00000149 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aac ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a5a ), + .Q(\blk00000003/sig00000adb ), + .Q15(\NLW_blk00000003/blk00000aac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ada ), + .Q(\blk00000003/sig00000148 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aaa ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a58 ), + .Q(\blk00000003/sig00000ada ), + .Q15(\NLW_blk00000003/blk00000aaa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad9 ), + .Q(\blk00000003/sig00000146 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a52 ), + .Q(\blk00000003/sig00000ad9 ), + .Q15(\NLW_blk00000003/blk00000aa8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad8 ), + .Q(\blk00000003/sig00000145 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a50 ), + .Q(\blk00000003/sig00000ad8 ), + .Q15(\NLW_blk00000003/blk00000aa6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad7 ), + .Q(\blk00000003/sig00000147 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a54 ), + .Q(\blk00000003/sig00000ad7 ), + .Q15(\NLW_blk00000003/blk00000aa4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad6 ), + .Q(\blk00000003/sig00000143 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a48 ), + .Q(\blk00000003/sig00000ad6 ), + .Q15(\NLW_blk00000003/blk00000aa2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad5 ), + .Q(\blk00000003/sig00000142 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a4c ), + .Q(\blk00000003/sig00000ad5 ), + .Q15(\NLW_blk00000003/blk00000aa0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad4 ), + .Q(\blk00000003/sig00000144 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a4e ), + .Q(\blk00000003/sig00000ad4 ), + .Q15(\NLW_blk00000003/blk00000a9e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad3 ), + .Q(\blk00000003/sig00000140 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a42 ), + .Q(\blk00000003/sig00000ad3 ), + .Q15(\NLW_blk00000003/blk00000a9c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad2 ), + .Q(\blk00000003/sig0000013f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a46 ), + .Q(\blk00000003/sig00000ad2 ), + .Q15(\NLW_blk00000003/blk00000a9a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a99 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad1 ), + .Q(\blk00000003/sig00000141 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a98 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a4a ), + .Q(\blk00000003/sig00000ad1 ), + .Q15(\NLW_blk00000003/blk00000a98_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a97 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad0 ), + .Q(\blk00000003/sig0000013e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a96 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a44 ), + .Q(\blk00000003/sig00000ad0 ), + .Q15(\NLW_blk00000003/blk00000a96_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a95 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000acf ), + .Q(\blk00000003/sig0000013d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a94 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a3c ), + .Q(\blk00000003/sig00000acf ), + .Q15(\NLW_blk00000003/blk00000a94_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a93 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ace ), + .Q(\blk00000003/sig0000013c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a92 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a40 ), + .Q(\blk00000003/sig00000ace ), + .Q15(\NLW_blk00000003/blk00000a92_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a91 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000acd ), + .Q(\blk00000003/sig0000013b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a90 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a3e ), + .Q(\blk00000003/sig00000acd ), + .Q15(\NLW_blk00000003/blk00000a90_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000acc ), + .Q(\blk00000003/sig000007d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a9 ), + .Q(\blk00000003/sig00000acc ), + .Q15(\NLW_blk00000003/blk00000a8e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000acb ), + .Q(\blk00000003/sig000007d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a8 ), + .Q(\blk00000003/sig00000acb ), + .Q15(\NLW_blk00000003/blk00000a8c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aca ), + .Q(\blk00000003/sig000007d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a6 ), + .Q(\blk00000003/sig00000aca ), + .Q15(\NLW_blk00000003/blk00000a8a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a89 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac9 ), + .Q(\blk00000003/sig000007d5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a88 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a5 ), + .Q(\blk00000003/sig00000ac9 ), + .Q15(\NLW_blk00000003/blk00000a88_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a87 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac8 ), + .Q(\blk00000003/sig000007d7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a86 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a7 ), + .Q(\blk00000003/sig00000ac8 ), + .Q15(\NLW_blk00000003/blk00000a86_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a85 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac7 ), + .Q(\blk00000003/sig000007d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a84 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a4 ), + .Q(\blk00000003/sig00000ac7 ), + .Q15(\NLW_blk00000003/blk00000a84_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a83 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac6 ), + .Q(\blk00000003/sig000007d3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a82 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a3 ), + .Q(\blk00000003/sig00000ac6 ), + .Q15(\NLW_blk00000003/blk00000a82_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a81 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac5 ), + .Q(\blk00000003/sig000007d2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a80 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a2 ), + .Q(\blk00000003/sig00000ac5 ), + .Q15(\NLW_blk00000003/blk00000a80_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac4 ), + .Q(\blk00000003/sig000007d1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a1 ), + .Q(\blk00000003/sig00000ac4 ), + .Q15(\NLW_blk00000003/blk00000a7e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac3 ), + .Q(\blk00000003/sig000007cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079f ), + .Q(\blk00000003/sig00000ac3 ), + .Q15(\NLW_blk00000003/blk00000a7c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac2 ), + .Q(\blk00000003/sig000007ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079e ), + .Q(\blk00000003/sig00000ac2 ), + .Q15(\NLW_blk00000003/blk00000a7a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a79 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac1 ), + .Q(\blk00000003/sig000007d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a78 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a0 ), + .Q(\blk00000003/sig00000ac1 ), + .Q15(\NLW_blk00000003/blk00000a78_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a77 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac0 ), + .Q(\blk00000003/sig000007cc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a76 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079c ), + .Q(\blk00000003/sig00000ac0 ), + .Q15(\NLW_blk00000003/blk00000a76_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a75 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abf ), + .Q(\blk00000003/sig000007cb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a74 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079b ), + .Q(\blk00000003/sig00000abf ), + .Q15(\NLW_blk00000003/blk00000a74_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a73 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abe ), + .Q(\blk00000003/sig000007cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a72 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079d ), + .Q(\blk00000003/sig00000abe ), + .Q15(\NLW_blk00000003/blk00000a72_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a71 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abd ), + .Q(\blk00000003/sig000007c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a70 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000799 ), + .Q(\blk00000003/sig00000abd ), + .Q15(\NLW_blk00000003/blk00000a70_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abc ), + .Q(\blk00000003/sig000007c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000798 ), + .Q(\blk00000003/sig00000abc ), + .Q15(\NLW_blk00000003/blk00000a6e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abb ), + .Q(\blk00000003/sig000007ca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079a ), + .Q(\blk00000003/sig00000abb ), + .Q15(\NLW_blk00000003/blk00000a6c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aba ), + .Q(\blk00000003/sig000007c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000797 ), + .Q(\blk00000003/sig00000aba ), + .Q15(\NLW_blk00000003/blk00000a6a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a69 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab9 ), + .Q(\blk00000003/sig000007c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a68 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000796 ), + .Q(\blk00000003/sig00000ab9 ), + .Q15(\NLW_blk00000003/blk00000a68_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a67 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab8 ), + .Q(\blk00000003/sig000007c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a66 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000795 ), + .Q(\blk00000003/sig00000ab8 ), + .Q15(\NLW_blk00000003/blk00000a66_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a65 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab7 ), + .Q(\blk00000003/sig000007c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a64 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000794 ), + .Q(\blk00000003/sig00000ab7 ), + .Q15(\NLW_blk00000003/blk00000a64_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a63 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab6 ), + .Q(\blk00000003/sig000007c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a62 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000792 ), + .Q(\blk00000003/sig00000ab6 ), + .Q15(\NLW_blk00000003/blk00000a62_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a61 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab5 ), + .Q(\blk00000003/sig000007c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a60 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000793 ), + .Q(\blk00000003/sig00000ab5 ), + .Q15(\NLW_blk00000003/blk00000a60_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab4 ), + .Q(\blk00000003/sig000007f1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007c1 ), + .Q(\blk00000003/sig00000ab4 ), + .Q15(\NLW_blk00000003/blk00000a5e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab3 ), + .Q(\blk00000003/sig000007f0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007c0 ), + .Q(\blk00000003/sig00000ab3 ), + .Q15(\NLW_blk00000003/blk00000a5c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab2 ), + .Q(\blk00000003/sig000007ef ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007bf ), + .Q(\blk00000003/sig00000ab2 ), + .Q15(\NLW_blk00000003/blk00000a5a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a59 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab1 ), + .Q(\blk00000003/sig000007ee ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a58 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007be ), + .Q(\blk00000003/sig00000ab1 ), + .Q15(\NLW_blk00000003/blk00000a58_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a57 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab0 ), + .Q(\blk00000003/sig000007ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a56 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007bd ), + .Q(\blk00000003/sig00000ab0 ), + .Q15(\NLW_blk00000003/blk00000a56_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a55 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aaf ), + .Q(\blk00000003/sig000007eb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a54 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007bb ), + .Q(\blk00000003/sig00000aaf ), + .Q15(\NLW_blk00000003/blk00000a54_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a53 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aae ), + .Q(\blk00000003/sig000007ea ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a52 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ba ), + .Q(\blk00000003/sig00000aae ), + .Q15(\NLW_blk00000003/blk00000a52_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a51 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aad ), + .Q(\blk00000003/sig000007ec ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a50 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007bc ), + .Q(\blk00000003/sig00000aad ), + .Q15(\NLW_blk00000003/blk00000a50_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aac ), + .Q(\blk00000003/sig000007e8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b8 ), + .Q(\blk00000003/sig00000aac ), + .Q15(\NLW_blk00000003/blk00000a4e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aab ), + .Q(\blk00000003/sig000007e7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b7 ), + .Q(\blk00000003/sig00000aab ), + .Q15(\NLW_blk00000003/blk00000a4c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aaa ), + .Q(\blk00000003/sig000007e9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b9 ), + .Q(\blk00000003/sig00000aaa ), + .Q15(\NLW_blk00000003/blk00000a4a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a49 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa9 ), + .Q(\blk00000003/sig000007e5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a48 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b5 ), + .Q(\blk00000003/sig00000aa9 ), + .Q15(\NLW_blk00000003/blk00000a48_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a47 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa8 ), + .Q(\blk00000003/sig000007e4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a46 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b4 ), + .Q(\blk00000003/sig00000aa8 ), + .Q15(\NLW_blk00000003/blk00000a46_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a45 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa7 ), + .Q(\blk00000003/sig000007e6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a44 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b6 ), + .Q(\blk00000003/sig00000aa7 ), + .Q15(\NLW_blk00000003/blk00000a44_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a43 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa6 ), + .Q(\blk00000003/sig000007e3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a42 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b3 ), + .Q(\blk00000003/sig00000aa6 ), + .Q15(\NLW_blk00000003/blk00000a42_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a41 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa5 ), + .Q(\blk00000003/sig000007e2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a40 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b2 ), + .Q(\blk00000003/sig00000aa5 ), + .Q15(\NLW_blk00000003/blk00000a40_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa4 ), + .Q(\blk00000003/sig000007e1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b1 ), + .Q(\blk00000003/sig00000aa4 ), + .Q15(\NLW_blk00000003/blk00000a3e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa3 ), + .Q(\blk00000003/sig000007e0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b0 ), + .Q(\blk00000003/sig00000aa3 ), + .Q15(\NLW_blk00000003/blk00000a3c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa2 ), + .Q(\blk00000003/sig000007de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ae ), + .Q(\blk00000003/sig00000aa2 ), + .Q15(\NLW_blk00000003/blk00000a3a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a39 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa1 ), + .Q(\blk00000003/sig000007dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a38 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ad ), + .Q(\blk00000003/sig00000aa1 ), + .Q15(\NLW_blk00000003/blk00000a38_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a37 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa0 ), + .Q(\blk00000003/sig000007df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a36 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007af ), + .Q(\blk00000003/sig00000aa0 ), + .Q15(\NLW_blk00000003/blk00000a36_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a35 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000a9f ), + .Q(\blk00000003/sig000007db ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a34 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ab ), + .Q(\blk00000003/sig00000a9f ), + .Q15(\NLW_blk00000003/blk00000a34_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a33 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000a9e ), + .Q(\blk00000003/sig000007da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a32 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007aa ), + .Q(\blk00000003/sig00000a9e ), + .Q15(\NLW_blk00000003/blk00000a32_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a31 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000a9d ), + .Q(\blk00000003/sig000007dc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a30 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ac ), + .Q(\blk00000003/sig00000a9d ), + .Q15(\NLW_blk00000003/blk00000a30_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a9c ), + .Q(\blk00000003/sig00000761 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001de ), + .Q(\blk00000003/sig00000a9c ), + .Q15(\NLW_blk00000003/blk00000a2e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a9b ), + .Q(\blk00000003/sig000009ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(NlwRenamedSig_OI_rfd), + .A3(NlwRenamedSig_OI_rfd), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ca ), + .Q(\blk00000003/sig00000a9b ), + .Q15(\NLW_blk00000003/blk00000a2c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2b ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a99 ), + .Q(\blk00000003/sig00000a9a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2a ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000218 ), + .Q(\blk00000003/sig00000a99 ), + .Q15(\NLW_blk00000003/blk00000a2a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a29 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a97 ), + .Q(\blk00000003/sig00000a98 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a28 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig00000a97 ), + .Q15(\NLW_blk00000003/blk00000a28_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a27 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a95 ), + .Q(\blk00000003/sig00000a96 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a26 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000219 ), + .Q(\blk00000003/sig00000a95 ), + .Q15(\NLW_blk00000003/blk00000a26_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a25 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a93 ), + .Q(\blk00000003/sig00000a94 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a24 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig00000a93 ), + .Q15(\NLW_blk00000003/blk00000a24_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a23 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a91 ), + .Q(\blk00000003/sig00000a92 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a22 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig00000a91 ), + .Q15(\NLW_blk00000003/blk00000a22_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a21 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a8f ), + .Q(\blk00000003/sig00000a90 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a20 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig00000a8f ), + .Q15(\NLW_blk00000003/blk00000a20_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1f ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a8d ), + .Q(\blk00000003/sig00000a8e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1e ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig00000a8d ), + .Q15(\NLW_blk00000003/blk00000a1e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1d ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a8b ), + .Q(\blk00000003/sig00000a8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1c ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000a8b ), + .Q15(\NLW_blk00000003/blk00000a1c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1b ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a89 ), + .Q(\blk00000003/sig00000a8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1a ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig00000a89 ), + .Q15(\NLW_blk00000003/blk00000a1a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a19 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a87 ), + .Q(\blk00000003/sig00000a88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a18 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig00000a87 ), + .Q15(\NLW_blk00000003/blk00000a18_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a17 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a85 ), + .Q(\blk00000003/sig00000a86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a16 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig00000a85 ), + .Q15(\NLW_blk00000003/blk00000a16_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a15 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a83 ), + .Q(\blk00000003/sig00000a84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a14 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig00000a83 ), + .Q15(\NLW_blk00000003/blk00000a14_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a13 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a81 ), + .Q(\blk00000003/sig00000a82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a12 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig00000a81 ), + .Q15(\NLW_blk00000003/blk00000a12_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a11 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a7f ), + .Q(\blk00000003/sig00000a80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a10 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig00000a7f ), + .Q15(\NLW_blk00000003/blk00000a10_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0f ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a7d ), + .Q(\blk00000003/sig00000a7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0e ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig00000a7d ), + .Q15(\NLW_blk00000003/blk00000a0e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0d ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a7b ), + .Q(\blk00000003/sig00000a7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0c ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig00000a7b ), + .Q15(\NLW_blk00000003/blk00000a0c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0b ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a79 ), + .Q(\blk00000003/sig00000a7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0a ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig00000a79 ), + .Q15(\NLW_blk00000003/blk00000a0a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a09 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a77 ), + .Q(\blk00000003/sig00000a78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a08 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig00000a77 ), + .Q15(\NLW_blk00000003/blk00000a08_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a07 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a75 ), + .Q(\blk00000003/sig00000a76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a06 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig00000a75 ), + .Q15(\NLW_blk00000003/blk00000a06_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a05 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a73 ), + .Q(\blk00000003/sig00000a74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a04 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig00000a73 ), + .Q15(\NLW_blk00000003/blk00000a04_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a03 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a71 ), + .Q(\blk00000003/sig00000a72 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a02 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig00000a71 ), + .Q15(\NLW_blk00000003/blk00000a02_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a01 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a6f ), + .Q(\blk00000003/sig00000a70 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a00 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig00000a6f ), + .Q15(\NLW_blk00000003/blk00000a00_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ff ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a6d ), + .Q(\blk00000003/sig00000a6e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fe ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig00000a6d ), + .Q15(\NLW_blk00000003/blk000009fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fd ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a6b ), + .Q(\blk00000003/sig00000a6c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fc ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig00000a6b ), + .Q15(\NLW_blk00000003/blk000009fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fb ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a69 ), + .Q(\blk00000003/sig00000a6a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fa ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig00000a69 ), + .Q15(\NLW_blk00000003/blk000009fa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f9 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a67 ), + .Q(\blk00000003/sig00000a68 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f8 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig00000a67 ), + .Q15(\NLW_blk00000003/blk000009f8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f7 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a65 ), + .Q(\blk00000003/sig00000a66 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f6 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig00000a65 ), + .Q15(\NLW_blk00000003/blk000009f6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f5 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a63 ), + .Q(\blk00000003/sig00000a64 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f4 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig00000a63 ), + .Q15(\NLW_blk00000003/blk000009f4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f3 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a61 ), + .Q(\blk00000003/sig00000a62 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f2 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig00000a61 ), + .Q15(\NLW_blk00000003/blk000009f2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f1 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a5f ), + .Q(\blk00000003/sig00000a60 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f0 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig00000a5f ), + .Q15(\NLW_blk00000003/blk000009f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ef ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a5d ), + .Q(\blk00000003/sig00000a5e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ee ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig00000a5d ), + .Q15(\NLW_blk00000003/blk000009ee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ed ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a5b ), + .Q(\blk00000003/sig00000a5c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ec ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig00000a5b ), + .Q15(\NLW_blk00000003/blk000009ec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009eb ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a59 ), + .Q(\blk00000003/sig00000a5a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ea ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig00000a59 ), + .Q15(\NLW_blk00000003/blk000009ea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e9 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a57 ), + .Q(\blk00000003/sig00000a58 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig00000a57 ), + .Q15(\NLW_blk00000003/blk000009e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e7 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a55 ), + .Q(\blk00000003/sig00000a56 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e6 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig00000a55 ), + .Q15(\NLW_blk00000003/blk000009e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e5 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a53 ), + .Q(\blk00000003/sig00000a54 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e4 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig00000a53 ), + .Q15(\NLW_blk00000003/blk000009e4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e3 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a51 ), + .Q(\blk00000003/sig00000a52 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e2 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig00000a51 ), + .Q15(\NLW_blk00000003/blk000009e2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e1 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a4f ), + .Q(\blk00000003/sig00000a50 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e0 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig00000a4f ), + .Q15(\NLW_blk00000003/blk000009e0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009df ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a4d ), + .Q(\blk00000003/sig00000a4e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009de ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig00000a4d ), + .Q15(\NLW_blk00000003/blk000009de_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009dd ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a4b ), + .Q(\blk00000003/sig00000a4c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009dc ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig00000a4b ), + .Q15(\NLW_blk00000003/blk000009dc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009db ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a49 ), + .Q(\blk00000003/sig00000a4a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009da ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig00000a49 ), + .Q15(\NLW_blk00000003/blk000009da_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d9 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a47 ), + .Q(\blk00000003/sig00000a48 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d8 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig00000a47 ), + .Q15(\NLW_blk00000003/blk000009d8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d7 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a45 ), + .Q(\blk00000003/sig00000a46 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d6 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig00000a45 ), + .Q15(\NLW_blk00000003/blk000009d6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d5 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a43 ), + .Q(\blk00000003/sig00000a44 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d4 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig00000a43 ), + .Q15(\NLW_blk00000003/blk000009d4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d3 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a41 ), + .Q(\blk00000003/sig00000a42 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d2 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig00000a41 ), + .Q15(\NLW_blk00000003/blk000009d2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d1 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a3f ), + .Q(\blk00000003/sig00000a40 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d0 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig00000a3f ), + .Q15(\NLW_blk00000003/blk000009d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009cf ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a3d ), + .Q(\blk00000003/sig00000a3e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ce ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig00000a3d ), + .Q15(\NLW_blk00000003/blk000009ce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009cd ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a3b ), + .Q(\blk00000003/sig00000a3c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009cc ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig00000a3b ), + .Q15(\NLW_blk00000003/blk000009cc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009cb ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a3a ), + .Q(\blk00000003/sig000007a9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ca ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000779 ), + .Q(\blk00000003/sig00000a3a ), + .Q15(\NLW_blk00000003/blk000009ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c9 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a39 ), + .Q(\blk00000003/sig000007a7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000777 ), + .Q(\blk00000003/sig00000a39 ), + .Q15(\NLW_blk00000003/blk000009c8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c7 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a38 ), + .Q(\blk00000003/sig000007a6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000776 ), + .Q(\blk00000003/sig00000a38 ), + .Q15(\NLW_blk00000003/blk000009c6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c5 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a37 ), + .Q(\blk00000003/sig000007a8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000778 ), + .Q(\blk00000003/sig00000a37 ), + .Q15(\NLW_blk00000003/blk000009c4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c3 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a36 ), + .Q(\blk00000003/sig000007a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000774 ), + .Q(\blk00000003/sig00000a36 ), + .Q15(\NLW_blk00000003/blk000009c2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c1 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a35 ), + .Q(\blk00000003/sig000007a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000773 ), + .Q(\blk00000003/sig00000a35 ), + .Q15(\NLW_blk00000003/blk000009c0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bf ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a34 ), + .Q(\blk00000003/sig000007a5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009be ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000775 ), + .Q(\blk00000003/sig00000a34 ), + .Q15(\NLW_blk00000003/blk000009be_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bd ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a33 ), + .Q(\blk00000003/sig000007a2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000772 ), + .Q(\blk00000003/sig00000a33 ), + .Q15(\NLW_blk00000003/blk000009bc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a32 ), + .Q(\blk00000003/sig000007a1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ba ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000771 ), + .Q(\blk00000003/sig00000a32 ), + .Q15(\NLW_blk00000003/blk000009ba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b9 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a31 ), + .Q(\blk00000003/sig000007a0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000770 ), + .Q(\blk00000003/sig00000a31 ), + .Q15(\NLW_blk00000003/blk000009b8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b7 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a30 ), + .Q(\blk00000003/sig0000079f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076f ), + .Q(\blk00000003/sig00000a30 ), + .Q15(\NLW_blk00000003/blk000009b6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b5 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2f ), + .Q(\blk00000003/sig0000079d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076d ), + .Q(\blk00000003/sig00000a2f ), + .Q15(\NLW_blk00000003/blk000009b4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b3 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2e ), + .Q(\blk00000003/sig0000079c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076c ), + .Q(\blk00000003/sig00000a2e ), + .Q15(\NLW_blk00000003/blk000009b2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b1 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2d ), + .Q(\blk00000003/sig0000079e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076e ), + .Q(\blk00000003/sig00000a2d ), + .Q15(\NLW_blk00000003/blk000009b0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009af ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2c ), + .Q(\blk00000003/sig0000079a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ae ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076a ), + .Q(\blk00000003/sig00000a2c ), + .Q15(\NLW_blk00000003/blk000009ae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ad ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2b ), + .Q(\blk00000003/sig00000799 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ac ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000769 ), + .Q(\blk00000003/sig00000a2b ), + .Q15(\NLW_blk00000003/blk000009ac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ab ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2a ), + .Q(\blk00000003/sig0000079b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009aa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076b ), + .Q(\blk00000003/sig00000a2a ), + .Q15(\NLW_blk00000003/blk000009aa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a9 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a29 ), + .Q(\blk00000003/sig00000797 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000767 ), + .Q(\blk00000003/sig00000a29 ), + .Q15(\NLW_blk00000003/blk000009a8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a7 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a28 ), + .Q(\blk00000003/sig00000796 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000766 ), + .Q(\blk00000003/sig00000a28 ), + .Q15(\NLW_blk00000003/blk000009a6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a5 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a27 ), + .Q(\blk00000003/sig00000798 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000768 ), + .Q(\blk00000003/sig00000a27 ), + .Q15(\NLW_blk00000003/blk000009a4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a3 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a26 ), + .Q(\blk00000003/sig00000794 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000764 ), + .Q(\blk00000003/sig00000a26 ), + .Q15(\NLW_blk00000003/blk000009a2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a1 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a25 ), + .Q(\blk00000003/sig00000793 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000763 ), + .Q(\blk00000003/sig00000a25 ), + .Q15(\NLW_blk00000003/blk000009a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a24 ), + .Q(\blk00000003/sig00000795 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000765 ), + .Q(\blk00000003/sig00000a24 ), + .Q15(\NLW_blk00000003/blk0000099e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a23 ), + .Q(\blk00000003/sig00000792 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000762 ), + .Q(\blk00000003/sig00000a23 ), + .Q15(\NLW_blk00000003/blk0000099c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a22 ), + .Q(\blk00000003/sig000007c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000790 ), + .Q(\blk00000003/sig00000a22 ), + .Q15(\NLW_blk00000003/blk0000099a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000999 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a21 ), + .Q(\blk00000003/sig000007bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000998 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078f ), + .Q(\blk00000003/sig00000a21 ), + .Q15(\NLW_blk00000003/blk00000998_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000997 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a20 ), + .Q(\blk00000003/sig000007c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000996 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000791 ), + .Q(\blk00000003/sig00000a20 ), + .Q15(\NLW_blk00000003/blk00000996_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000995 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1f ), + .Q(\blk00000003/sig000007bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000994 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078d ), + .Q(\blk00000003/sig00000a1f ), + .Q15(\NLW_blk00000003/blk00000994_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000993 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1e ), + .Q(\blk00000003/sig000007bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000992 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078c ), + .Q(\blk00000003/sig00000a1e ), + .Q15(\NLW_blk00000003/blk00000992_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000991 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1d ), + .Q(\blk00000003/sig000007be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000990 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078e ), + .Q(\blk00000003/sig00000a1d ), + .Q15(\NLW_blk00000003/blk00000990_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1c ), + .Q(\blk00000003/sig000007ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078a ), + .Q(\blk00000003/sig00000a1c ), + .Q15(\NLW_blk00000003/blk0000098e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1b ), + .Q(\blk00000003/sig000007b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000789 ), + .Q(\blk00000003/sig00000a1b ), + .Q15(\NLW_blk00000003/blk0000098c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1a ), + .Q(\blk00000003/sig000007bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078b ), + .Q(\blk00000003/sig00000a1a ), + .Q15(\NLW_blk00000003/blk0000098a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000989 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a19 ), + .Q(\blk00000003/sig000007b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000988 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000787 ), + .Q(\blk00000003/sig00000a19 ), + .Q15(\NLW_blk00000003/blk00000988_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000987 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a18 ), + .Q(\blk00000003/sig000007b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000986 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000786 ), + .Q(\blk00000003/sig00000a18 ), + .Q15(\NLW_blk00000003/blk00000986_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000985 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a17 ), + .Q(\blk00000003/sig000007b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000984 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000788 ), + .Q(\blk00000003/sig00000a17 ), + .Q15(\NLW_blk00000003/blk00000984_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000983 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a16 ), + .Q(\blk00000003/sig000007b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000982 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000784 ), + .Q(\blk00000003/sig00000a16 ), + .Q15(\NLW_blk00000003/blk00000982_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000981 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a15 ), + .Q(\blk00000003/sig000007b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000980 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000783 ), + .Q(\blk00000003/sig00000a15 ), + .Q15(\NLW_blk00000003/blk00000980_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a14 ), + .Q(\blk00000003/sig000007b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000785 ), + .Q(\blk00000003/sig00000a14 ), + .Q15(\NLW_blk00000003/blk0000097e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a13 ), + .Q(\blk00000003/sig000007b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000782 ), + .Q(\blk00000003/sig00000a13 ), + .Q15(\NLW_blk00000003/blk0000097c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a12 ), + .Q(\blk00000003/sig000007b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000781 ), + .Q(\blk00000003/sig00000a12 ), + .Q15(\NLW_blk00000003/blk0000097a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000979 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a11 ), + .Q(\blk00000003/sig000007b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000978 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000780 ), + .Q(\blk00000003/sig00000a11 ), + .Q15(\NLW_blk00000003/blk00000978_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000977 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a10 ), + .Q(\blk00000003/sig000007af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000976 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077f ), + .Q(\blk00000003/sig00000a10 ), + .Q15(\NLW_blk00000003/blk00000976_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000975 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0f ), + .Q(\blk00000003/sig000007ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000974 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077d ), + .Q(\blk00000003/sig00000a0f ), + .Q15(\NLW_blk00000003/blk00000974_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000973 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0e ), + .Q(\blk00000003/sig000007ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000972 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077c ), + .Q(\blk00000003/sig00000a0e ), + .Q15(\NLW_blk00000003/blk00000972_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000971 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0d ), + .Q(\blk00000003/sig000007ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000970 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077e ), + .Q(\blk00000003/sig00000a0d ), + .Q15(\NLW_blk00000003/blk00000970_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0c ), + .Q(\blk00000003/sig000007aa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077a ), + .Q(\blk00000003/sig00000a0c ), + .Q15(\NLW_blk00000003/blk0000096e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0b ), + .Q(\blk00000003/sig00000869 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000219 ), + .Q(\blk00000003/sig00000a0b ), + .Q15(\NLW_blk00000003/blk0000096c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0a ), + .Q(\blk00000003/sig000007ab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077b ), + .Q(\blk00000003/sig00000a0a ), + .Q15(\NLW_blk00000003/blk0000096a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000969 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a09 ), + .Q(\blk00000003/sig00000867 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000968 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig00000a09 ), + .Q15(\NLW_blk00000003/blk00000968_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000967 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a08 ), + .Q(\blk00000003/sig00000866 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000966 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig00000a08 ), + .Q15(\NLW_blk00000003/blk00000966_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000965 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a07 ), + .Q(\blk00000003/sig00000868 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000964 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000218 ), + .Q(\blk00000003/sig00000a07 ), + .Q15(\NLW_blk00000003/blk00000964_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000963 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a06 ), + .Q(\blk00000003/sig00000865 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000962 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig00000a06 ), + .Q15(\NLW_blk00000003/blk00000962_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a05 ), + .Q(\blk00000003/sig00000864 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000960 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig00000a05 ), + .Q15(\NLW_blk00000003/blk00000960_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a04 ), + .Q(\blk00000003/sig00000863 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig00000a04 ), + .Q15(\NLW_blk00000003/blk0000095e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a03 ), + .Q(\blk00000003/sig00000862 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig00000a03 ), + .Q15(\NLW_blk00000003/blk0000095c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a02 ), + .Q(\blk00000003/sig00000860 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig00000a02 ), + .Q15(\NLW_blk00000003/blk0000095a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000959 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a01 ), + .Q(\blk00000003/sig0000085f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000958 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig00000a01 ), + .Q15(\NLW_blk00000003/blk00000958_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000957 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a00 ), + .Q(\blk00000003/sig00000861 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000956 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000a00 ), + .Q15(\NLW_blk00000003/blk00000956_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000955 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ff ), + .Q(\blk00000003/sig0000085d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000954 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig000009ff ), + .Q15(\NLW_blk00000003/blk00000954_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000953 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fe ), + .Q(\blk00000003/sig0000085c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000952 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig000009fe ), + .Q15(\NLW_blk00000003/blk00000952_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000951 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fd ), + .Q(\blk00000003/sig0000085e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000950 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig000009fd ), + .Q15(\NLW_blk00000003/blk00000950_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000094f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fc ), + .Q(\blk00000003/sig0000085a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig000009fc ), + .Q15(\NLW_blk00000003/blk0000094e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000094d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fb ), + .Q(\blk00000003/sig00000859 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig000009fb ), + .Q15(\NLW_blk00000003/blk0000094c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000094b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fa ), + .Q(\blk00000003/sig0000085b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig000009fa ), + .Q15(\NLW_blk00000003/blk0000094a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000949 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f9 ), + .Q(\blk00000003/sig00000858 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000948 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig000009f9 ), + .Q15(\NLW_blk00000003/blk00000948_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000947 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f8 ), + .Q(\blk00000003/sig00000857 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000946 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig000009f8 ), + .Q15(\NLW_blk00000003/blk00000946_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000945 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f7 ), + .Q(\blk00000003/sig00000856 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000944 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig000009f7 ), + .Q15(\NLW_blk00000003/blk00000944_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000943 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f6 ), + .Q(\blk00000003/sig00000855 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000942 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig000009f6 ), + .Q15(\NLW_blk00000003/blk00000942_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000941 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f5 ), + .Q(\blk00000003/sig00000853 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000940 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig000009f5 ), + .Q15(\NLW_blk00000003/blk00000940_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000093f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f4 ), + .Q(\blk00000003/sig00000852 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000093e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig000009f4 ), + .Q15(\NLW_blk00000003/blk0000093e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000093d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f3 ), + .Q(\blk00000003/sig00000854 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000093c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig000009f3 ), + .Q15(\NLW_blk00000003/blk0000093c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000093b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f2 ), + .Q(\blk00000003/sig00000898 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000093a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000009f2 ), + .Q15(\NLW_blk00000003/blk0000093a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000939 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f1 ), + .Q(\blk00000003/sig00000897 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000938 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000009f1 ), + .Q15(\NLW_blk00000003/blk00000938_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000937 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f0 ), + .Q(\blk00000003/sig00000899 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000936 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000009f0 ), + .Q15(\NLW_blk00000003/blk00000936_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000935 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ef ), + .Q(\blk00000003/sig00000895 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000934 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000009ef ), + .Q15(\NLW_blk00000003/blk00000934_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000933 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ee ), + .Q(\blk00000003/sig00000894 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000932 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000009ee ), + .Q15(\NLW_blk00000003/blk00000932_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000931 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ed ), + .Q(\blk00000003/sig00000896 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000930 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000009ed ), + .Q15(\NLW_blk00000003/blk00000930_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000092f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ec ), + .Q(\blk00000003/sig00000893 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000092e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000009ec ), + .Q15(\NLW_blk00000003/blk0000092e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000092d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009eb ), + .Q(\blk00000003/sig00000892 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000092c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000009eb ), + .Q15(\NLW_blk00000003/blk0000092c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000092b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ea ), + .Q(\blk00000003/sig00000891 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000092a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000009ea ), + .Q15(\NLW_blk00000003/blk0000092a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000929 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e9 ), + .Q(\blk00000003/sig00000890 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000928 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000009e9 ), + .Q15(\NLW_blk00000003/blk00000928_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000927 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e8 ), + .Q(\blk00000003/sig0000088e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000926 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000009e8 ), + .Q15(\NLW_blk00000003/blk00000926_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000925 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e7 ), + .Q(\blk00000003/sig0000088d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000924 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000009e7 ), + .Q15(\NLW_blk00000003/blk00000924_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000923 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e6 ), + .Q(\blk00000003/sig0000088f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000922 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000009e6 ), + .Q15(\NLW_blk00000003/blk00000922_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000921 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e5 ), + .Q(\blk00000003/sig0000088b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000920 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000009e5 ), + .Q15(\NLW_blk00000003/blk00000920_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e4 ), + .Q(\blk00000003/sig0000088a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000091e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000009e4 ), + .Q15(\NLW_blk00000003/blk0000091e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e3 ), + .Q(\blk00000003/sig0000088c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000091c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000009e3 ), + .Q15(\NLW_blk00000003/blk0000091c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e2 ), + .Q(\blk00000003/sig00000888 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000091a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000009e2 ), + .Q15(\NLW_blk00000003/blk0000091a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000919 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e1 ), + .Q(\blk00000003/sig00000887 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000918 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000009e1 ), + .Q15(\NLW_blk00000003/blk00000918_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000917 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e0 ), + .Q(\blk00000003/sig00000889 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000916 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000009e0 ), + .Q15(\NLW_blk00000003/blk00000916_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000915 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009df ), + .Q(\blk00000003/sig00000886 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000914 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000009df ), + .Q15(\NLW_blk00000003/blk00000914_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000913 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009de ), + .Q(\blk00000003/sig00000885 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000912 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000009de ), + .Q15(\NLW_blk00000003/blk00000912_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000911 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009dd ), + .Q(\blk00000003/sig00000884 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000910 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000009dd ), + .Q15(\NLW_blk00000003/blk00000910_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009dc ), + .Q(\blk00000003/sig00000883 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000090e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000009dc ), + .Q15(\NLW_blk00000003/blk0000090e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009db ), + .Q(\blk00000003/sig000002a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000090c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d5 ), + .Q(\blk00000003/sig000009db ), + .Q15(\NLW_blk00000003/blk0000090c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009da ), + .Q(\blk00000003/sig000002a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000090a ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000029e ), + .Q(\blk00000003/sig000009da ), + .Q15(\NLW_blk00000003/blk0000090a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000909 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d9 ), + .Q(\blk00000003/sig00000882 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000908 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig000009d9 ), + .Q15(\NLW_blk00000003/blk00000908_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000907 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d8 ), + .Q(\blk00000003/sig000008c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000906 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig000009d8 ), + .Q15(\NLW_blk00000003/blk00000906_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000905 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d7 ), + .Q(\blk00000003/sig000008c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000904 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig000009d7 ), + .Q15(\NLW_blk00000003/blk00000904_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000903 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d6 ), + .Q(\blk00000003/sig000009b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000902 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d1 ), + .Q(\blk00000003/sig000009d6 ), + .Q15(\NLW_blk00000003/blk00000902_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000901 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d5 ), + .Q(\blk00000003/sig000008c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000900 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig000009d5 ), + .Q15(\NLW_blk00000003/blk00000900_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d4 ), + .Q(\blk00000003/sig000008bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008fe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig000009d4 ), + .Q15(\NLW_blk00000003/blk000008fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d3 ), + .Q(\blk00000003/sig000008c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008fc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig000009d3 ), + .Q15(\NLW_blk00000003/blk000008fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d2 ), + .Q(\blk00000003/sig000008be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008fa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig000009d2 ), + .Q15(\NLW_blk00000003/blk000008fa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d1 ), + .Q(\blk00000003/sig000008bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig000009d1 ), + .Q15(\NLW_blk00000003/blk000008f8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d0 ), + .Q(\blk00000003/sig000008bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig000009d0 ), + .Q15(\NLW_blk00000003/blk000008f6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009cf ), + .Q(\blk00000003/sig000008bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig000009cf ), + .Q15(\NLW_blk00000003/blk000008f4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ce ), + .Q(\blk00000003/sig000008b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig000009ce ), + .Q15(\NLW_blk00000003/blk000008f2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009cd ), + .Q(\blk00000003/sig000008b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig000009cd ), + .Q15(\NLW_blk00000003/blk000008f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009cc ), + .Q(\blk00000003/sig000008ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008ee ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig000009cc ), + .Q15(\NLW_blk00000003/blk000008ee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009cb ), + .Q(\blk00000003/sig000008b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008ec ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig000009cb ), + .Q15(\NLW_blk00000003/blk000008ec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ca ), + .Q(\blk00000003/sig000008b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008ea ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig000009ca ), + .Q15(\NLW_blk00000003/blk000008ea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c9 ), + .Q(\blk00000003/sig000008b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig000009c9 ), + .Q15(\NLW_blk00000003/blk000008e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c8 ), + .Q(\blk00000003/sig000008b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig000009c8 ), + .Q15(\NLW_blk00000003/blk000008e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c7 ), + .Q(\blk00000003/sig000008b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig000009c7 ), + .Q15(\NLW_blk00000003/blk000008e4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c6 ), + .Q(\blk00000003/sig000008b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig000009c6 ), + .Q15(\NLW_blk00000003/blk000008e2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c5 ), + .Q(\blk00000003/sig000001de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e0 ), + .Q(\blk00000003/sig000009c5 ), + .Q15(\NLW_blk00000003/blk000008e0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c4 ), + .Q(\blk00000003/sig00000760 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008de ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d7 ), + .Q(\blk00000003/sig000009c4 ), + .Q15(\NLW_blk00000003/blk000008de_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c3 ), + .Q(\blk00000003/sig0000091f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008dc ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001cf ), + .Q(\blk00000003/sig000009c3 ), + .Q15(\NLW_blk00000003/blk000008dc_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk000008db ( + .I(\blk00000003/sig00000243 ), + .O(\blk00000003/sig00000275 ) + ); + INV \blk00000003/blk000008da ( + .I(\blk00000003/sig00000223 ), + .O(\blk00000003/sig00000232 ) + ); + INV \blk00000003/blk000008d9 ( + .I(\blk00000003/sig0000027e ), + .O(\blk00000003/sig0000026e ) + ); + INV \blk00000003/blk000008d8 ( + .I(\blk00000003/sig000001cf ), + .O(\blk00000003/sig00000283 ) + ); + INV \blk00000003/blk000008d7 ( + .I(\blk00000003/sig00000285 ), + .O(\blk00000003/sig00000274 ) + ); + INV \blk00000003/blk000008d6 ( + .I(\blk00000003/sig00000931 ), + .O(\blk00000003/sig000009ab ) + ); + INV \blk00000003/blk000008d5 ( + .I(\blk00000003/sig00000247 ), + .O(\blk00000003/sig00000286 ) + ); + INV \blk00000003/blk000008d4 ( + .I(\blk00000003/sig00000243 ), + .O(\blk00000003/sig0000026f ) + ); + INV \blk00000003/blk000008d3 ( + .I(\blk00000003/sig0000021d ), + .O(\blk00000003/sig00000248 ) + ); + INV \blk00000003/blk000008d2 ( + .I(\blk00000003/sig00000223 ), + .O(\blk00000003/sig00000231 ) + ); + INV \blk00000003/blk000008d1 ( + .I(\blk00000003/sig000001cd ), + .O(\blk00000003/sig000000c1 ) + ); + INV \blk00000003/blk000008d0 ( + .I(\blk00000003/sig000000b4 ), + .O(\blk00000003/sig000001cb ) + ); + INV \blk00000003/blk000008cf ( + .I(\blk00000003/sig000000be ), + .O(\blk00000003/sig000000bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000937 ), + .Q(\blk00000003/sig000009b0 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk000008cd ( + .I0(\blk00000003/sig00000239 ), + .I1(\blk00000003/sig00000250 ), + .I2(coef_ld), + .O(\blk00000003/sig0000024c ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk000008cc ( + .I0(\blk00000003/sig0000024d ), + .I1(\blk00000003/sig00000241 ), + .I2(\blk00000003/sig00000250 ), + .I3(coef_ld), + .I4(\blk00000003/sig00000239 ), + .O(\blk00000003/sig00000244 ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk000008cb ( + .I0(coef_ld), + .I1(\blk00000003/sig0000023b ), + .I2(coef_we), + .I3(\blk00000003/sig00000239 ), + .O(\blk00000003/sig0000024b ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk000008ca ( + .I0(\blk00000003/sig0000025b ), + .I1(\blk00000003/sig00000227 ), + .I2(coef_we), + .I3(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000255 ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk000008c9 ( + .I0(\blk00000003/sig00000239 ), + .I1(\blk00000003/sig0000023b ), + .I2(coef_we), + .I3(\blk00000003/sig00000250 ), + .I4(coef_ld), + .O(\blk00000003/sig0000024a ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk000008c8 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig000009b3 ), + .O(\blk00000003/sig000009ba ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000008c7 ( + .I0(\blk00000003/sig0000027e ), + .I1(ce), + .I2(\blk00000003/sig00000241 ), + .I3(\blk00000003/sig0000021b ), + .O(\blk00000003/sig000009c2 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000008c6 ( + .I0(\blk00000003/sig00000285 ), + .I1(ce), + .I2(\blk00000003/sig0000023f ), + .I3(\blk00000003/sig00000276 ), + .O(\blk00000003/sig000009c1 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000008c5 ( + .I0(\blk00000003/sig000009af ), + .I1(ce), + .I2(\blk00000003/sig000001d5 ), + .I3(\blk00000003/sig000001d7 ), + .O(\blk00000003/sig000009bc ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk000008c4 ( + .I0(ce), + .I1(\blk00000003/sig00000250 ), + .I2(\blk00000003/sig000009b1 ), + .O(\blk00000003/sig000009b9 ) + ); + LUT5 #( + .INIT ( 32'h6AAAAAAA )) + \blk00000003/blk000008c3 ( + .I0(\blk00000003/sig000001e7 ), + .I1(\blk00000003/sig000009ae ), + .I2(\blk00000003/sig000000ad ), + .I3(ce), + .I4(nd), + .O(\blk00000003/sig000009c0 ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \blk00000003/blk000008c2 ( + .I0(\blk00000003/sig000001e2 ), + .I1(\blk00000003/sig000001d7 ), + .I2(\blk00000003/sig000009be ), + .I3(ce), + .O(\blk00000003/sig000009bf ) + ); + LUT3 #( + .INIT ( 8'h6C )) + \blk00000003/blk000008c1 ( + .I0(\blk00000003/sig000001d7 ), + .I1(\blk00000003/sig000009be ), + .I2(ce), + .O(\blk00000003/sig000009bd ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \blk00000003/blk000008c0 ( + .I0(\blk00000003/sig000009ae ), + .I1(\blk00000003/sig000000ad ), + .I2(ce), + .I3(nd), + .O(\blk00000003/sig000009bb ) + ); + LUT4 #( + .INIT ( 16'hECCC )) + \blk00000003/blk000008bf ( + .I0(coef_we), + .I1(\blk00000003/sig0000025c ), + .I2(\blk00000003/sig00000227 ), + .I3(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000258 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000008be ( + .C(clk), + .D(\blk00000003/sig000009c2 ), + .Q(\blk00000003/sig0000027e ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000008bd ( + .C(clk), + .D(\blk00000003/sig000009c1 ), + .Q(\blk00000003/sig00000285 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008bc ( + .C(clk), + .D(\blk00000003/sig000009c0 ), + .R(sclr), + .Q(\blk00000003/sig000001e7 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008bb ( + .C(clk), + .D(\blk00000003/sig000009bf ), + .R(sclr), + .Q(\blk00000003/sig000001e2 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ba ( + .C(clk), + .D(\blk00000003/sig000009bd ), + .R(sclr), + .Q(\blk00000003/sig000009be ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008b9 ( + .C(clk), + .D(\blk00000003/sig000009bc ), + .R(sclr), + .Q(\blk00000003/sig000009af ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008b8 ( + .C(clk), + .D(\blk00000003/sig000009bb ), + .R(sclr), + .Q(\blk00000003/sig000009ae ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b7 ( + .I0(\blk00000003/sig00000935 ), + .O(\blk00000003/sig0000092f ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b6 ( + .I0(\blk00000003/sig00000934 ), + .O(\blk00000003/sig0000092c ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b5 ( + .I0(\blk00000003/sig00000933 ), + .O(\blk00000003/sig00000929 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b4 ( + .I0(\blk00000003/sig00000932 ), + .O(\blk00000003/sig00000926 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b3 ( + .I0(\blk00000003/sig00000931 ), + .O(\blk00000003/sig00000923 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b2 ( + .I0(\blk00000003/sig000002a0 ), + .O(\blk00000003/sig000002a1 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b1 ( + .I0(\blk00000003/sig00000294 ), + .O(\blk00000003/sig0000028e ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b0 ( + .I0(\blk00000003/sig0000025f ), + .O(\blk00000003/sig00000260 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008af ( + .I0(\blk00000003/sig000001cd ), + .O(\blk00000003/sig000000c2 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008ae ( + .I0(\blk00000003/sig000009ae ), + .O(\blk00000003/sig000000b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009a5 ), + .R(sclr), + .Q(\blk00000003/sig000009aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009a2 ), + .R(sclr), + .Q(\blk00000003/sig000009a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000099f ), + .R(sclr), + .Q(\blk00000003/sig000009a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000099c ), + .R(sclr), + .Q(\blk00000003/sig000009a7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000999 ), + .R(sclr), + .Q(\blk00000003/sig000009a6 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000921 ), + .S(sclr), + .Q(\blk00000003/sig00000936 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000930 ), + .S(sclr), + .Q(\blk00000003/sig00000935 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092d ), + .S(sclr), + .Q(\blk00000003/sig00000934 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092a ), + .S(sclr), + .Q(\blk00000003/sig00000933 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000927 ), + .R(sclr), + .Q(\blk00000003/sig00000932 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000924 ), + .S(sclr), + .Q(\blk00000003/sig00000931 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a2 ), + .R(\blk00000003/sig000002a5 ), + .Q(\blk00000003/sig000002a0 ) + ); + FDR \blk00000003/blk000008a1 ( + .C(clk), + .D(\blk00000003/sig000009ba ), + .R(ce), + .Q(\blk00000003/sig000009b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029c ), + .R(\blk00000003/sig000002a4 ), + .Q(\blk00000003/sig0000029a ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000089f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000297 ), + .S(\blk00000003/sig000002a4 ), + .Q(\blk00000003/sig00000295 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000089e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000028f ), + .S(sclr), + .Q(\blk00000003/sig00000294 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000089d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000292 ), + .R(sclr), + .Q(\blk00000003/sig00000293 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000089c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000289 ), + .R(sclr), + .Q(\blk00000003/sig000001e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000089b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000028c ), + .R(sclr), + .Q(\blk00000003/sig000001e8 ) + ); + FDR \blk00000003/blk0000089a ( + .C(clk), + .D(\blk00000003/sig000009b9 ), + .R(ce), + .Q(\blk00000003/sig000009b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000899 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000261 ), + .R(\blk00000003/sig00000264 ), + .Q(\blk00000003/sig0000025f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000898 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000253 ), + .R(coef_ld), + .Q(\blk00000003/sig0000025d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000897 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000259 ), + .R(coef_ld), + .Q(\blk00000003/sig0000025c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000896 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000256 ), + .R(coef_ld), + .Q(\blk00000003/sig0000025b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000895 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000225 ), + .R(coef_ld), + .Q(\blk00000003/sig00000223 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000894 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000b6 ), + .R(sclr), + .Q(\blk00000003/sig000000b4 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000893 ( + .I0(\blk00000003/sig000009a6 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig00000998 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000892 ( + .I0(\blk00000003/sig000009a7 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig0000099b ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000891 ( + .I0(\blk00000003/sig000009a8 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig0000099e ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000890 ( + .I0(\blk00000003/sig000009a9 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig000009a1 ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk0000088f ( + .I0(\blk00000003/sig000009aa ), + .I1(\blk00000003/sig00000931 ), + .I2(\blk00000003/sig000001dc ), + .O(\blk00000003/sig000009a4 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk0000088e ( + .I0(\blk00000003/sig000001dc ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig00000931 ), + .O(\blk00000003/sig00000996 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000088d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000010d ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig00000994 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000088c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000010c ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig00000995 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000088b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000010e ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig00000993 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000088a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000110 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig00000991 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000889 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000010f ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig00000992 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000888 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000111 ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig00000990 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000887 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000113 ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig0000098e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000886 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000112 ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig0000098f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000885 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000114 ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig0000098d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000884 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000116 ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig0000098b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000883 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000115 ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig0000098c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000882 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000117 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig0000098a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000881 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000119 ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig00000988 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000880 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000118 ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig00000989 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011a ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig00000987 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011c ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig00000985 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011b ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig00000986 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011d ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig00000984 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011f ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig00000982 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011e ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig00000983 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000879 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000120 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig00000981 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000878 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000122 ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig0000097f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000877 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000121 ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig00000980 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000876 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000123 ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig0000097e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000875 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000125 ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig0000097c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000874 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000124 ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig0000097d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000873 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000126 ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig0000097b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000872 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000128 ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig00000979 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000871 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000127 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig0000097a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000870 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000129 ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig00000978 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012b ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig00000976 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012a ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig00000977 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012c ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig00000975 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012e ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig00000973 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012d ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig00000974 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012f ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig00000972 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000869 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000131 ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig00000970 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000868 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000130 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig00000971 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000867 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000132 ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig0000096f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000866 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000134 ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig0000096d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000865 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000133 ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig0000096e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000864 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000135 ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig0000096c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000863 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000137 ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig0000096a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000862 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000136 ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig0000096b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000861 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000138 ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig00000969 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000860 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000139 ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig00000968 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000183 ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig00000966 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000013a ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig00000967 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000184 ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig00000965 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000186 ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig00000963 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000185 ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig00000964 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000187 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig00000962 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000859 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000189 ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig00000960 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000858 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000188 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig00000961 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000857 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018a ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig0000095f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000856 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018c ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig0000095d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000855 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018b ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig0000095e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000854 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018d ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig0000095c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000853 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018f ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig0000095a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000852 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018e ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig0000095b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000851 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000190 ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig00000959 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000850 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000192 ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig00000957 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000191 ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig00000958 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000193 ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig00000956 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000195 ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig00000954 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000194 ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig00000955 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000196 ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig00000953 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000198 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig00000951 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000849 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000197 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig00000952 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000848 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000199 ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig00000950 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000847 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019b ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig0000094e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000846 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019a ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig0000094f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000845 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019c ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig0000094d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000844 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019e ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig0000094b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000843 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019d ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig0000094c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000842 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019f ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig0000094a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000841 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a1 ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig00000948 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000840 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a0 ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig00000949 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a2 ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig00000947 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a4 ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig00000945 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a3 ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig00000946 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a5 ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig00000944 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a7 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig00000942 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a6 ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig00000943 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000839 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a8 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig00000941 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000838 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001aa ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig0000093f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000837 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a9 ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig00000940 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000836 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001ab ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig0000093e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000835 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001ad ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig0000093c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000834 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001ac ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig0000093d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000833 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001ae ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig0000093b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000832 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001b0 ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig00000939 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000831 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001af ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig0000093a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000830 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001b1 ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig00000938 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000082f ( + .I0(\blk00000003/sig00000936 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig00000920 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082e ( + .I0(ce), + .I1(\blk00000003/sig000001de ), + .O(\blk00000003/sig000009b8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082d ( + .I0(ce), + .I1(\blk00000003/sig0000075a ), + .O(\blk00000003/sig000009b7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082c ( + .I0(ce), + .I1(\blk00000003/sig00000754 ), + .O(\blk00000003/sig000009b6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082b ( + .I0(ce), + .I1(\blk00000003/sig0000074f ), + .O(\blk00000003/sig000009b5 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082a ( + .I0(ce), + .I1(\blk00000003/sig00000744 ), + .O(\blk00000003/sig000009b4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000829 ( + .I0(ce), + .I1(\blk00000003/sig00000745 ), + .O(\blk00000003/sig0000091e ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000828 ( + .I0(sclr), + .I1(\blk00000003/sig000009b3 ), + .O(\blk00000003/sig0000029d ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000827 ( + .I0(\blk00000003/sig000002a3 ), + .I1(\blk00000003/sig000009b2 ), + .O(\blk00000003/sig00000298 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000826 ( + .I0(\blk00000003/sig00000295 ), + .I1(\blk00000003/sig000002a3 ), + .O(\blk00000003/sig00000296 ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk00000825 ( + .I0(\blk00000003/sig000002a3 ), + .I1(\blk00000003/sig000009b2 ), + .I2(\blk00000003/sig0000029a ), + .O(\blk00000003/sig0000029b ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000824 ( + .I0(\blk00000003/sig00000293 ), + .I1(\blk00000003/sig000001d7 ), + .O(\blk00000003/sig00000291 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000823 ( + .I0(nd), + .I1(\blk00000003/sig000000b2 ), + .O(\blk00000003/sig0000028d ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk00000822 ( + .I0(\blk00000003/sig000001e8 ), + .I1(nd), + .I2(\blk00000003/sig000000b2 ), + .O(\blk00000003/sig0000028b ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk00000821 ( + .I0(nd), + .I1(\blk00000003/sig000000b2 ), + .I2(\blk00000003/sig000001e9 ), + .O(\blk00000003/sig00000288 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000820 ( + .I0(\blk00000003/sig00000240 ), + .I1(\blk00000003/sig00000247 ), + .O(\blk00000003/sig00000284 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000081f ( + .I0(\blk00000003/sig00000247 ), + .I1(\blk00000003/sig0000023f ), + .O(\blk00000003/sig00000281 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000081e ( + .I0(\blk00000003/sig00000247 ), + .I1(\blk00000003/sig00000243 ), + .O(\blk00000003/sig0000027f ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000081d ( + .I0(\blk00000003/sig00000245 ), + .I1(\blk00000003/sig0000024d ), + .I2(\blk00000003/sig00000247 ), + .O(\blk00000003/sig0000027a ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000081c ( + .I0(\blk00000003/sig00000245 ), + .I1(\blk00000003/sig00000243 ), + .I2(\blk00000003/sig00000247 ), + .O(\blk00000003/sig0000027c ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000081b ( + .I0(\blk00000003/sig00000240 ), + .I1(\blk00000003/sig00000243 ), + .O(\blk00000003/sig00000273 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000081a ( + .I0(\blk00000003/sig0000023f ), + .I1(\blk00000003/sig00000243 ), + .O(\blk00000003/sig00000271 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000819 ( + .I0(\blk00000003/sig0000023d ), + .I1(\blk00000003/sig00000247 ), + .I2(\blk00000003/sig00000243 ), + .O(\blk00000003/sig0000026c ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000818 ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig00000243 ), + .O(\blk00000003/sig00000268 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000817 ( + .I0(\blk00000003/sig00000241 ), + .I1(\blk00000003/sig00000243 ), + .I2(\blk00000003/sig0000024d ), + .O(\blk00000003/sig0000026a ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000816 ( + .I0(\blk00000003/sig00000250 ), + .I1(\blk00000003/sig000009b1 ), + .O(\blk00000003/sig00000263 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000815 ( + .I0(coef_we), + .I1(\blk00000003/sig00000227 ), + .I2(\blk00000003/sig0000022f ), + .O(\blk00000003/sig0000025a ) + ); + LUT4 #( + .INIT ( 16'hE6CC )) + \blk00000003/blk00000814 ( + .I0(coef_we), + .I1(\blk00000003/sig0000025d ), + .I2(\blk00000003/sig00000227 ), + .I3(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000252 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000813 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000250 ), + .O(\blk00000003/sig00000246 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000812 ( + .I0(coef_we), + .I1(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000228 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000811 ( + .I0(coef_we), + .I1(coef_ld), + .I2(\blk00000003/sig0000023b ), + .O(\blk00000003/sig0000024e ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000810 ( + .I0(\blk00000003/sig0000025b ), + .I1(\blk00000003/sig0000025c ), + .I2(\blk00000003/sig0000025d ), + .O(\blk00000003/sig0000022c ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk0000080f ( + .I0(\blk00000003/sig0000025c ), + .I1(\blk00000003/sig0000025b ), + .I2(\blk00000003/sig0000025d ), + .O(\blk00000003/sig0000022a ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk0000080e ( + .I0(coef_ld), + .I1(\blk00000003/sig00000250 ), + .I2(\blk00000003/sig00000239 ), + .O(\blk00000003/sig00000222 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk0000080d ( + .I0(coef_we), + .I1(\blk00000003/sig0000023b ), + .I2(\blk00000003/sig00000239 ), + .O(\blk00000003/sig0000021f ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000080c ( + .I0(\blk00000003/sig00000223 ), + .I1(coef_we), + .O(\blk00000003/sig00000224 ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk0000080b ( + .I0(\blk00000003/sig0000023b ), + .I1(coef_we), + .I2(\blk00000003/sig0000022f ), + .I3(\blk00000003/sig00000227 ), + .I4(coef_ld), + .O(\blk00000003/sig0000023a ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk0000080a ( + .I0(\blk00000003/sig00000239 ), + .I1(\blk00000003/sig0000023b ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig00000238 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000809 ( + .I0(\blk00000003/sig000000ad ), + .I1(nd), + .O(\blk00000003/sig000001e6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000808 ( + .I0(\blk00000003/sig000000c6 ), + .I1(\blk00000003/sig000001dc ), + .O(\blk00000003/sig000001e4 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk00000807 ( + .I0(\blk00000003/sig000000c6 ), + .I1(\blk00000003/sig00000931 ), + .I2(\blk00000003/sig000009b0 ), + .O(\blk00000003/sig000000c7 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk00000806 ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig00000931 ), + .O(\blk00000003/sig000001dd ) + ); + LUT5 #( + .INIT ( 32'h00002000 )) + \blk00000003/blk00000805 ( + .I0(\blk00000003/sig000009a6 ), + .I1(\blk00000003/sig000009a7 ), + .I2(\blk00000003/sig000009a8 ), + .I3(\blk00000003/sig000009a9 ), + .I4(\blk00000003/sig000009aa ), + .O(\blk00000003/sig000000c9 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000804 ( + .I0(\blk00000003/sig000001d7 ), + .I1(\blk00000003/sig000001ca ), + .I2(\blk00000003/sig000001e5 ), + .O(\blk00000003/sig000001d6 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000803 ( + .I0(\blk00000003/sig00000294 ), + .I1(\blk00000003/sig000001e1 ), + .O(\blk00000003/sig000001d8 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000802 ( + .I0(ce), + .I1(\blk00000003/sig000009ac ), + .I2(\blk00000003/sig000000bc ), + .O(\blk00000003/sig000000bb ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000801 ( + .I0(ce), + .I1(\blk00000003/sig000009ac ), + .I2(\blk00000003/sig000000ba ), + .O(\blk00000003/sig000000b9 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000800 ( + .I0(\blk00000003/sig000000b4 ), + .I1(\blk00000003/sig000001ca ), + .O(\blk00000003/sig000000b5 ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk000007ff ( + .I0(\blk00000003/sig000001ca ), + .I1(\blk00000003/sig000001e5 ), + .I2(\blk00000003/sig000001d5 ), + .I3(\blk00000003/sig000001d7 ), + .I4(\blk00000003/sig000001d3 ), + .O(\blk00000003/sig000001d4 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk000007fe ( + .I0(\blk00000003/sig000001d5 ), + .I1(\blk00000003/sig000009af ), + .I2(\blk00000003/sig000001d7 ), + .I3(\blk00000003/sig000001e5 ), + .O(\blk00000003/sig000001d0 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk000007fd ( + .I0(\blk00000003/sig000009ae ), + .I1(\blk00000003/sig000001e8 ), + .I2(\blk00000003/sig000001e9 ), + .O(\blk00000003/sig000000b0 ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk000007fc ( + .I0(\blk00000003/sig000001e5 ), + .I1(\blk00000003/sig000001d5 ), + .I2(\blk00000003/sig000001d7 ), + .I3(\blk00000003/sig000001d3 ), + .O(\blk00000003/sig000001d2 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk000007fb ( + .I0(\blk00000003/sig00000293 ), + .I1(\blk00000003/sig00000294 ), + .I2(\blk00000003/sig000001e1 ), + .O(\blk00000003/sig000001da ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk000007fa ( + .I0(ce), + .I1(\blk00000003/sig000009ac ), + .I2(\blk00000003/sig000009ad ), + .I3(\blk00000003/sig000000b8 ), + .O(\blk00000003/sig000000b7 ) + ); + MUXCY \blk00000003/blk000007f9 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig000009ab ), + .O(\blk00000003/sig000009a3 ) + ); + MUXCY_L \blk00000003/blk000007f8 ( + .CI(\blk00000003/sig000009a3 ), + .DI(\blk00000003/sig000009aa ), + .S(\blk00000003/sig000009a4 ), + .LO(\blk00000003/sig000009a0 ) + ); + MUXCY_L \blk00000003/blk000007f7 ( + .CI(\blk00000003/sig000009a0 ), + .DI(\blk00000003/sig000009a9 ), + .S(\blk00000003/sig000009a1 ), + .LO(\blk00000003/sig0000099d ) + ); + MUXCY_L \blk00000003/blk000007f6 ( + .CI(\blk00000003/sig0000099d ), + .DI(\blk00000003/sig000009a8 ), + .S(\blk00000003/sig0000099e ), + .LO(\blk00000003/sig0000099a ) + ); + MUXCY_L \blk00000003/blk000007f5 ( + .CI(\blk00000003/sig0000099a ), + .DI(\blk00000003/sig000009a7 ), + .S(\blk00000003/sig0000099b ), + .LO(\blk00000003/sig00000997 ) + ); + MUXCY_D \blk00000003/blk000007f4 ( + .CI(\blk00000003/sig00000997 ), + .DI(\blk00000003/sig000009a6 ), + .S(\blk00000003/sig00000998 ), + .O(\NLW_blk00000003/blk000007f4_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000007f4_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000007f3 ( + .CI(\blk00000003/sig000009a3 ), + .LI(\blk00000003/sig000009a4 ), + .O(\blk00000003/sig000009a5 ) + ); + XORCY \blk00000003/blk000007f2 ( + .CI(\blk00000003/sig000009a0 ), + .LI(\blk00000003/sig000009a1 ), + .O(\blk00000003/sig000009a2 ) + ); + XORCY \blk00000003/blk000007f1 ( + .CI(\blk00000003/sig0000099d ), + .LI(\blk00000003/sig0000099e ), + .O(\blk00000003/sig0000099f ) + ); + XORCY \blk00000003/blk000007f0 ( + .CI(\blk00000003/sig0000099a ), + .LI(\blk00000003/sig0000099b ), + .O(\blk00000003/sig0000099c ) + ); + XORCY \blk00000003/blk000007ef ( + .CI(\blk00000003/sig00000997 ), + .LI(\blk00000003/sig00000998 ), + .O(\blk00000003/sig00000999 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000996 ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000995 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000994 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000993 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000992 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000991 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000990 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000989 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000988 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000987 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000986 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000985 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000984 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007db ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000983 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000982 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000981 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000980 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000979 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000978 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000977 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000976 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000975 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000974 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000973 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000972 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000971 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000970 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000969 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000968 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000967 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000966 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000965 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000964 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000963 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000962 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000961 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000960 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000959 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000958 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000957 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000956 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000955 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000954 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000953 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000952 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000951 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000950 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000949 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000948 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000947 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000946 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000945 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000944 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000943 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000942 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000799 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000941 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000798 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000940 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000797 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000796 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000795 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000794 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000793 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000792 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000791 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000939 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000790 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000938 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000078f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000937 ), + .Q(\blk00000003/sig000001dc ) + ); + MUXCY_L \blk00000003/blk0000078e ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000936 ), + .S(\blk00000003/sig00000920 ), + .LO(\blk00000003/sig0000092e ) + ); + MUXCY_L \blk00000003/blk0000078d ( + .CI(\blk00000003/sig0000092e ), + .DI(\blk00000003/sig00000935 ), + .S(\blk00000003/sig0000092f ), + .LO(\blk00000003/sig0000092b ) + ); + MUXCY_L \blk00000003/blk0000078c ( + .CI(\blk00000003/sig0000092b ), + .DI(\blk00000003/sig00000934 ), + .S(\blk00000003/sig0000092c ), + .LO(\blk00000003/sig00000928 ) + ); + MUXCY_L \blk00000003/blk0000078b ( + .CI(\blk00000003/sig00000928 ), + .DI(\blk00000003/sig00000933 ), + .S(\blk00000003/sig00000929 ), + .LO(\blk00000003/sig00000925 ) + ); + MUXCY_L \blk00000003/blk0000078a ( + .CI(\blk00000003/sig00000925 ), + .DI(\blk00000003/sig00000932 ), + .S(\blk00000003/sig00000926 ), + .LO(\blk00000003/sig00000922 ) + ); + MUXCY_D \blk00000003/blk00000789 ( + .CI(\blk00000003/sig00000922 ), + .DI(\blk00000003/sig00000931 ), + .S(\blk00000003/sig00000923 ), + .O(\NLW_blk00000003/blk00000789_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000789_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000788 ( + .CI(\blk00000003/sig0000092e ), + .LI(\blk00000003/sig0000092f ), + .O(\blk00000003/sig00000930 ) + ); + XORCY \blk00000003/blk00000787 ( + .CI(\blk00000003/sig0000092b ), + .LI(\blk00000003/sig0000092c ), + .O(\blk00000003/sig0000092d ) + ); + XORCY \blk00000003/blk00000786 ( + .CI(\blk00000003/sig00000928 ), + .LI(\blk00000003/sig00000929 ), + .O(\blk00000003/sig0000092a ) + ); + XORCY \blk00000003/blk00000785 ( + .CI(\blk00000003/sig00000925 ), + .LI(\blk00000003/sig00000926 ), + .O(\blk00000003/sig00000927 ) + ); + XORCY \blk00000003/blk00000784 ( + .CI(\blk00000003/sig00000922 ), + .LI(\blk00000003/sig00000923 ), + .O(\blk00000003/sig00000924 ) + ); + XORCY \blk00000003/blk00000783 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000920 ), + .O(\blk00000003/sig00000921 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003d2 ), + .R(sclr), + .Q(\blk00000003/sig00000779 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075a ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003d1 ), + .R(sclr), + .Q(\blk00000003/sig00000778 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000759 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003d0 ), + .R(sclr), + .Q(\blk00000003/sig00000777 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003cf ), + .R(sclr), + .Q(\blk00000003/sig00000776 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000757 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003ce ), + .R(sclr), + .Q(\blk00000003/sig00000775 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000756 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003cd ), + .R(sclr), + .Q(\blk00000003/sig00000774 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000755 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003cc ), + .R(sclr), + .Q(\blk00000003/sig00000773 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000754 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003cb ), + .R(sclr), + .Q(\blk00000003/sig00000772 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000753 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003ca ), + .R(sclr), + .Q(\blk00000003/sig00000771 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000752 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c9 ), + .R(sclr), + .Q(\blk00000003/sig00000770 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000751 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c8 ), + .R(sclr), + .Q(\blk00000003/sig0000076f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000750 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c7 ), + .R(sclr), + .Q(\blk00000003/sig0000076e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c6 ), + .R(sclr), + .Q(\blk00000003/sig0000076d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074e ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c5 ), + .R(sclr), + .Q(\blk00000003/sig0000076c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c4 ), + .R(sclr), + .Q(\blk00000003/sig0000076b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074c ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c3 ), + .R(sclr), + .Q(\blk00000003/sig0000076a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c2 ), + .R(sclr), + .Q(\blk00000003/sig00000769 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074a ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c1 ), + .R(sclr), + .Q(\blk00000003/sig00000768 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000749 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c0 ), + .R(sclr), + .Q(\blk00000003/sig00000767 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000748 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003bf ), + .R(sclr), + .Q(\blk00000003/sig00000766 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000747 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003be ), + .R(sclr), + .Q(\blk00000003/sig00000765 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000746 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003bd ), + .R(sclr), + .Q(\blk00000003/sig00000764 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003bc ), + .R(sclr), + .Q(\blk00000003/sig00000763 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000744 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003bb ), + .R(sclr), + .Q(\blk00000003/sig00000762 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000743 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000432 ), + .R(sclr), + .Q(\blk00000003/sig00000791 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000742 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000431 ), + .R(sclr), + .Q(\blk00000003/sig00000790 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000741 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000430 ), + .R(sclr), + .Q(\blk00000003/sig0000078f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000740 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042f ), + .R(sclr), + .Q(\blk00000003/sig0000078e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042e ), + .R(sclr), + .Q(\blk00000003/sig0000078d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073e ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042d ), + .R(sclr), + .Q(\blk00000003/sig0000078c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042c ), + .R(sclr), + .Q(\blk00000003/sig0000078b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073c ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042b ), + .R(sclr), + .Q(\blk00000003/sig0000078a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042a ), + .R(sclr), + .Q(\blk00000003/sig00000789 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073a ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000429 ), + .R(sclr), + .Q(\blk00000003/sig00000788 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000739 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000428 ), + .R(sclr), + .Q(\blk00000003/sig00000787 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000427 ), + .R(sclr), + .Q(\blk00000003/sig00000786 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000737 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000426 ), + .R(sclr), + .Q(\blk00000003/sig00000785 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000736 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000425 ), + .R(sclr), + .Q(\blk00000003/sig00000784 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000735 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000424 ), + .R(sclr), + .Q(\blk00000003/sig00000783 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000734 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000423 ), + .R(sclr), + .Q(\blk00000003/sig00000782 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000733 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000422 ), + .R(sclr), + .Q(\blk00000003/sig00000781 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000421 ), + .R(sclr), + .Q(\blk00000003/sig00000780 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000731 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000420 ), + .R(sclr), + .Q(\blk00000003/sig0000077f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000730 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041f ), + .R(sclr), + .Q(\blk00000003/sig0000077e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041e ), + .R(sclr), + .Q(\blk00000003/sig0000077d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072e ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041d ), + .R(sclr), + .Q(\blk00000003/sig0000077c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041c ), + .R(sclr), + .Q(\blk00000003/sig0000077b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072c ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041b ), + .R(sclr), + .Q(\blk00000003/sig0000077a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000295 ), + .R(sclr), + .Q(\blk00000003/sig0000075f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a0 ), + .R(sclr), + .Q(\blk00000003/sig0000075c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a6 ), + .R(sclr), + .Q(\blk00000003/sig0000075b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000761 ), + .R(sclr), + .Q(\blk00000003/sig0000075d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000760 ), + .R(sclr), + .Q(\blk00000003/sig0000075a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029a ), + .R(sclr), + .Q(\blk00000003/sig0000075e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075f ), + .R(sclr), + .Q(\blk00000003/sig00000759 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000118 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075e ), + .R(sclr), + .Q(\blk00000003/sig00000758 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075d ), + .R(sclr), + .Q(\blk00000003/sig00000755 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075c ), + .R(sclr), + .Q(\blk00000003/sig00000757 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000115 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075b ), + .R(sclr), + .Q(\blk00000003/sig00000756 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000114 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075a ), + .R(sclr), + .Q(\blk00000003/sig00000754 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000113 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000759 ), + .R(sclr), + .Q(\blk00000003/sig00000750 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000112 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000758 ), + .R(sclr), + .Q(\blk00000003/sig00000751 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000111 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000757 ), + .R(sclr), + .Q(\blk00000003/sig00000753 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000110 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000756 ), + .R(sclr), + .Q(\blk00000003/sig00000752 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000755 ), + .R(sclr), + .Q(\blk00000003/sig0000074e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000754 ), + .R(sclr), + .Q(\blk00000003/sig0000074f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000753 ), + .R(sclr), + .Q(\blk00000003/sig0000074c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000752 ), + .R(sclr), + .Q(\blk00000003/sig0000074a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000751 ), + .R(sclr), + .Q(\blk00000003/sig00000748 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000750 ), + .R(sclr), + .Q(\blk00000003/sig00000746 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000109 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074f ), + .R(sclr), + .Q(\blk00000003/sig00000744 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000108 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074e ), + .R(sclr), + .Q(\blk00000003/sig00000742 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000107 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074c ), + .R(sclr), + .Q(\blk00000003/sig0000074d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000106 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074a ), + .R(sclr), + .Q(\blk00000003/sig0000074b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000105 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000748 ), + .R(sclr), + .Q(\blk00000003/sig00000749 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000104 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000746 ), + .R(sclr), + .Q(\blk00000003/sig00000747 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000103 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000744 ), + .R(sclr), + .Q(\blk00000003/sig00000745 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000102 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000742 ), + .R(sclr), + .Q(\blk00000003/sig00000743 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000101 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000740 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000741 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000100 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000740 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073d ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000237 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000739 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000738 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000737 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000739 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000736 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000738 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000735 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000737 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000734 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000736 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000733 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000735 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000262 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000734 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000733 ) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f2 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f2_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f2_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f2_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f2_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f2_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f2_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f2_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig000006d3 , \blk00000003/sig000006d4 , \blk00000003/sig000006d5 , \blk00000003/sig000006d6 , \blk00000003/sig000006d7 , +\blk00000003/sig000006d8 , \blk00000003/sig000006d9 , \blk00000003/sig000006da , \blk00000003/sig000006db , \blk00000003/sig000006dc , +\blk00000003/sig000006dd , \blk00000003/sig000006de , \blk00000003/sig000006df , \blk00000003/sig000006e0 , \blk00000003/sig000006e1 , +\blk00000003/sig000006e2 , \blk00000003/sig000006e3 , \blk00000003/sig000006e4 , \blk00000003/sig000006e5 , \blk00000003/sig000006e6 , +\blk00000003/sig000006e7 , \blk00000003/sig000006e8 , \blk00000003/sig000006e9 , \blk00000003/sig000006ea , \blk00000003/sig000006eb , +\blk00000003/sig000006ec , \blk00000003/sig000006ed , \blk00000003/sig000006ee , \blk00000003/sig000006ef , \blk00000003/sig000006f0 , +\blk00000003/sig000006f1 , \blk00000003/sig000006f2 , \blk00000003/sig000006f3 , \blk00000003/sig000006f4 , \blk00000003/sig000006f5 , +\blk00000003/sig000006f6 , \blk00000003/sig000006f7 , \blk00000003/sig000006f8 , \blk00000003/sig000006f9 , \blk00000003/sig000006fa , +\blk00000003/sig000006fb , \blk00000003/sig000006fc , \blk00000003/sig000006fd , \blk00000003/sig000006fe , \blk00000003/sig000006ff , +\blk00000003/sig00000700 , \blk00000003/sig00000701 , \blk00000003/sig00000702 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f2_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f2_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f2_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000005a1 , \blk00000003/sig000005a2 , \blk00000003/sig000005a3 , \blk00000003/sig000005a4 , \blk00000003/sig000005a5 , +\blk00000003/sig000005a6 , \blk00000003/sig000005a7 , \blk00000003/sig000005a8 , \blk00000003/sig000005a9 , \blk00000003/sig000005aa , +\blk00000003/sig000005ab , \blk00000003/sig000005ac , \blk00000003/sig000005ad , \blk00000003/sig000005ae , \blk00000003/sig000005af , +\blk00000003/sig000005b0 , \blk00000003/sig000005b1 , \blk00000003/sig000005b2 }), + .BCOUT({\NLW_blk00000003/blk000000f2_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000703 , \blk00000003/sig00000703 , \blk00000003/sig00000704 , \blk00000003/sig00000705 , \blk00000003/sig00000706 , +\blk00000003/sig00000707 , \blk00000003/sig00000708 , \blk00000003/sig00000709 , \blk00000003/sig0000070a , \blk00000003/sig0000070b , +\blk00000003/sig0000070c , \blk00000003/sig0000070d , \blk00000003/sig0000070e , \blk00000003/sig0000070f , \blk00000003/sig00000710 , +\blk00000003/sig00000711 , \blk00000003/sig00000712 , \blk00000003/sig00000713 , \blk00000003/sig00000714 , \blk00000003/sig00000715 , +\blk00000003/sig00000716 , \blk00000003/sig00000717 , \blk00000003/sig00000718 , \blk00000003/sig00000719 , \blk00000003/sig0000071a }), + .P({\NLW_blk00000003/blk000000f2_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000071b , \blk00000003/sig0000071b , \blk00000003/sig0000071b , \blk00000003/sig0000071b , \blk00000003/sig0000071b , +\blk00000003/sig0000071b , \blk00000003/sig0000071b , \blk00000003/sig0000071c , \blk00000003/sig0000071d , \blk00000003/sig0000071e , +\blk00000003/sig0000071f , \blk00000003/sig00000720 , \blk00000003/sig00000721 , \blk00000003/sig00000722 , \blk00000003/sig00000723 , +\blk00000003/sig00000724 , \blk00000003/sig00000725 , \blk00000003/sig00000726 , \blk00000003/sig00000727 , \blk00000003/sig00000728 , +\blk00000003/sig00000729 , \blk00000003/sig0000072a , \blk00000003/sig0000072b , \blk00000003/sig0000072c , \blk00000003/sig0000072d , +\blk00000003/sig0000072e , \blk00000003/sig0000072f , \blk00000003/sig00000730 , \blk00000003/sig00000731 , \blk00000003/sig00000732 }), + .PCOUT({\blk00000003/sig000003eb , \blk00000003/sig000003ec , \blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , +\blk00000003/sig000003f0 , \blk00000003/sig000003f1 , \blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , +\blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , +\blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 , +\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d , +\blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , \blk00000003/sig00000412 , +\blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , \blk00000003/sig00000417 , +\blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f1 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f1_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f1_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f1_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f1_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f1_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f1_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f1_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000673 , \blk00000003/sig00000674 , \blk00000003/sig00000675 , \blk00000003/sig00000676 , \blk00000003/sig00000677 , +\blk00000003/sig00000678 , \blk00000003/sig00000679 , \blk00000003/sig0000067a , \blk00000003/sig0000067b , \blk00000003/sig0000067c , +\blk00000003/sig0000067d , \blk00000003/sig0000067e , \blk00000003/sig0000067f , \blk00000003/sig00000680 , \blk00000003/sig00000681 , +\blk00000003/sig00000682 , \blk00000003/sig00000683 , \blk00000003/sig00000684 , \blk00000003/sig00000685 , \blk00000003/sig00000686 , +\blk00000003/sig00000687 , \blk00000003/sig00000688 , \blk00000003/sig00000689 , \blk00000003/sig0000068a , \blk00000003/sig0000068b , +\blk00000003/sig0000068c , \blk00000003/sig0000068d , \blk00000003/sig0000068e , \blk00000003/sig0000068f , \blk00000003/sig00000690 , +\blk00000003/sig00000691 , \blk00000003/sig00000692 , \blk00000003/sig00000693 , \blk00000003/sig00000694 , \blk00000003/sig00000695 , +\blk00000003/sig00000696 , \blk00000003/sig00000697 , \blk00000003/sig00000698 , \blk00000003/sig00000699 , \blk00000003/sig0000069a , +\blk00000003/sig0000069b , \blk00000003/sig0000069c , \blk00000003/sig0000069d , \blk00000003/sig0000069e , \blk00000003/sig0000069f , +\blk00000003/sig000006a0 , \blk00000003/sig000006a1 , \blk00000003/sig000006a2 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f1_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f1_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f1_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig0000052f , \blk00000003/sig00000530 , \blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , +\blk00000003/sig00000534 , \blk00000003/sig00000535 , \blk00000003/sig00000536 , \blk00000003/sig00000537 , \blk00000003/sig00000538 , +\blk00000003/sig00000539 , \blk00000003/sig0000053a , \blk00000003/sig0000053b , \blk00000003/sig0000053c , \blk00000003/sig0000053d , +\blk00000003/sig0000053e , \blk00000003/sig0000053f , \blk00000003/sig00000540 }), + .BCOUT({\NLW_blk00000003/blk000000f1_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000006a3 , \blk00000003/sig000006a3 , \blk00000003/sig000006a4 , \blk00000003/sig000006a5 , \blk00000003/sig000006a6 , +\blk00000003/sig000006a7 , \blk00000003/sig000006a8 , \blk00000003/sig000006a9 , \blk00000003/sig000006aa , \blk00000003/sig000006ab , +\blk00000003/sig000006ac , \blk00000003/sig000006ad , \blk00000003/sig000006ae , \blk00000003/sig000006af , \blk00000003/sig000006b0 , +\blk00000003/sig000006b1 , \blk00000003/sig000006b2 , \blk00000003/sig000006b3 , \blk00000003/sig000006b4 , \blk00000003/sig000006b5 , +\blk00000003/sig000006b6 , \blk00000003/sig000006b7 , \blk00000003/sig000006b8 , \blk00000003/sig000006b9 , \blk00000003/sig000006ba }), + .P({\NLW_blk00000003/blk000000f1_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000006bb , \blk00000003/sig000006bb , \blk00000003/sig000006bb , \blk00000003/sig000006bb , \blk00000003/sig000006bb , +\blk00000003/sig000006bb , \blk00000003/sig000006bb , \blk00000003/sig000006bc , \blk00000003/sig000006bd , \blk00000003/sig000006be , +\blk00000003/sig000006bf , \blk00000003/sig000006c0 , \blk00000003/sig000006c1 , \blk00000003/sig000006c2 , \blk00000003/sig000006c3 , +\blk00000003/sig000006c4 , \blk00000003/sig000006c5 , \blk00000003/sig000006c6 , \blk00000003/sig000006c7 , \blk00000003/sig000006c8 , +\blk00000003/sig000006c9 , \blk00000003/sig000006ca , \blk00000003/sig000006cb , \blk00000003/sig000006cc , \blk00000003/sig000006cd , +\blk00000003/sig000006ce , \blk00000003/sig000006cf , \blk00000003/sig000006d0 , \blk00000003/sig000006d1 , \blk00000003/sig000006d2 }), + .PCOUT({\blk00000003/sig000006d3 , \blk00000003/sig000006d4 , \blk00000003/sig000006d5 , \blk00000003/sig000006d6 , \blk00000003/sig000006d7 , +\blk00000003/sig000006d8 , \blk00000003/sig000006d9 , \blk00000003/sig000006da , \blk00000003/sig000006db , \blk00000003/sig000006dc , +\blk00000003/sig000006dd , \blk00000003/sig000006de , \blk00000003/sig000006df , \blk00000003/sig000006e0 , \blk00000003/sig000006e1 , +\blk00000003/sig000006e2 , \blk00000003/sig000006e3 , \blk00000003/sig000006e4 , \blk00000003/sig000006e5 , \blk00000003/sig000006e6 , +\blk00000003/sig000006e7 , \blk00000003/sig000006e8 , \blk00000003/sig000006e9 , \blk00000003/sig000006ea , \blk00000003/sig000006eb , +\blk00000003/sig000006ec , \blk00000003/sig000006ed , \blk00000003/sig000006ee , \blk00000003/sig000006ef , \blk00000003/sig000006f0 , +\blk00000003/sig000006f1 , \blk00000003/sig000006f2 , \blk00000003/sig000006f3 , \blk00000003/sig000006f4 , \blk00000003/sig000006f5 , +\blk00000003/sig000006f6 , \blk00000003/sig000006f7 , \blk00000003/sig000006f8 , \blk00000003/sig000006f9 , \blk00000003/sig000006fa , +\blk00000003/sig000006fb , \blk00000003/sig000006fc , \blk00000003/sig000006fd , \blk00000003/sig000006fe , \blk00000003/sig000006ff , +\blk00000003/sig00000700 , \blk00000003/sig00000701 , \blk00000003/sig00000702 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f0 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f0_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f0_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f0_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f0_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f0_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f0_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f0_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000613 , \blk00000003/sig00000614 , \blk00000003/sig00000615 , \blk00000003/sig00000616 , \blk00000003/sig00000617 , +\blk00000003/sig00000618 , \blk00000003/sig00000619 , \blk00000003/sig0000061a , \blk00000003/sig0000061b , \blk00000003/sig0000061c , +\blk00000003/sig0000061d , \blk00000003/sig0000061e , \blk00000003/sig0000061f , \blk00000003/sig00000620 , \blk00000003/sig00000621 , +\blk00000003/sig00000622 , \blk00000003/sig00000623 , \blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , +\blk00000003/sig00000627 , \blk00000003/sig00000628 , \blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , +\blk00000003/sig0000062c , \blk00000003/sig0000062d , \blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , +\blk00000003/sig00000631 , \blk00000003/sig00000632 , \blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 , +\blk00000003/sig00000636 , \blk00000003/sig00000637 , \blk00000003/sig00000638 , \blk00000003/sig00000639 , \blk00000003/sig0000063a , +\blk00000003/sig0000063b , \blk00000003/sig0000063c , \blk00000003/sig0000063d , \blk00000003/sig0000063e , \blk00000003/sig0000063f , +\blk00000003/sig00000640 , \blk00000003/sig00000641 , \blk00000003/sig00000642 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f0_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f0_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f0_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000004bd , \blk00000003/sig000004be , \blk00000003/sig000004bf , \blk00000003/sig000004c0 , \blk00000003/sig000004c1 , +\blk00000003/sig000004c2 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , \blk00000003/sig000004c5 , \blk00000003/sig000004c6 , +\blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , \blk00000003/sig000004ca , \blk00000003/sig000004cb , +\blk00000003/sig000004cc , \blk00000003/sig000004cd , \blk00000003/sig000004ce }), + .BCOUT({\NLW_blk00000003/blk000000f0_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000643 , \blk00000003/sig00000643 , \blk00000003/sig00000644 , \blk00000003/sig00000645 , \blk00000003/sig00000646 , +\blk00000003/sig00000647 , \blk00000003/sig00000648 , \blk00000003/sig00000649 , \blk00000003/sig0000064a , \blk00000003/sig0000064b , +\blk00000003/sig0000064c , \blk00000003/sig0000064d , \blk00000003/sig0000064e , \blk00000003/sig0000064f , \blk00000003/sig00000650 , +\blk00000003/sig00000651 , \blk00000003/sig00000652 , \blk00000003/sig00000653 , \blk00000003/sig00000654 , \blk00000003/sig00000655 , +\blk00000003/sig00000656 , \blk00000003/sig00000657 , \blk00000003/sig00000658 , \blk00000003/sig00000659 , \blk00000003/sig0000065a }), + .P({\NLW_blk00000003/blk000000f0_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000065b , \blk00000003/sig0000065b , \blk00000003/sig0000065b , \blk00000003/sig0000065b , \blk00000003/sig0000065b , +\blk00000003/sig0000065b , \blk00000003/sig0000065b , \blk00000003/sig0000065c , \blk00000003/sig0000065d , \blk00000003/sig0000065e , +\blk00000003/sig0000065f , \blk00000003/sig00000660 , \blk00000003/sig00000661 , \blk00000003/sig00000662 , \blk00000003/sig00000663 , +\blk00000003/sig00000664 , \blk00000003/sig00000665 , \blk00000003/sig00000666 , \blk00000003/sig00000667 , \blk00000003/sig00000668 , +\blk00000003/sig00000669 , \blk00000003/sig0000066a , \blk00000003/sig0000066b , \blk00000003/sig0000066c , \blk00000003/sig0000066d , +\blk00000003/sig0000066e , \blk00000003/sig0000066f , \blk00000003/sig00000670 , \blk00000003/sig00000671 , \blk00000003/sig00000672 }), + .PCOUT({\blk00000003/sig00000673 , \blk00000003/sig00000674 , \blk00000003/sig00000675 , \blk00000003/sig00000676 , \blk00000003/sig00000677 , +\blk00000003/sig00000678 , \blk00000003/sig00000679 , \blk00000003/sig0000067a , \blk00000003/sig0000067b , \blk00000003/sig0000067c , +\blk00000003/sig0000067d , \blk00000003/sig0000067e , \blk00000003/sig0000067f , \blk00000003/sig00000680 , \blk00000003/sig00000681 , +\blk00000003/sig00000682 , \blk00000003/sig00000683 , \blk00000003/sig00000684 , \blk00000003/sig00000685 , \blk00000003/sig00000686 , +\blk00000003/sig00000687 , \blk00000003/sig00000688 , \blk00000003/sig00000689 , \blk00000003/sig0000068a , \blk00000003/sig0000068b , +\blk00000003/sig0000068c , \blk00000003/sig0000068d , \blk00000003/sig0000068e , \blk00000003/sig0000068f , \blk00000003/sig00000690 , +\blk00000003/sig00000691 , \blk00000003/sig00000692 , \blk00000003/sig00000693 , \blk00000003/sig00000694 , \blk00000003/sig00000695 , +\blk00000003/sig00000696 , \blk00000003/sig00000697 , \blk00000003/sig00000698 , \blk00000003/sig00000699 , \blk00000003/sig0000069a , +\blk00000003/sig0000069b , \blk00000003/sig0000069c , \blk00000003/sig0000069d , \blk00000003/sig0000069e , \blk00000003/sig0000069f , +\blk00000003/sig000006a0 , \blk00000003/sig000006a1 , \blk00000003/sig000006a2 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ef ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ef_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ef_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ef_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ef_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ef_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ef_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ef_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000349 , \blk00000003/sig0000034a , \blk00000003/sig0000034b , \blk00000003/sig0000034c , \blk00000003/sig0000034d , +\blk00000003/sig0000034e , \blk00000003/sig0000034f , \blk00000003/sig00000350 , \blk00000003/sig00000351 , \blk00000003/sig00000352 , +\blk00000003/sig00000353 , \blk00000003/sig00000354 , \blk00000003/sig00000355 , \blk00000003/sig00000356 , \blk00000003/sig00000357 , +\blk00000003/sig00000358 , \blk00000003/sig00000359 , \blk00000003/sig0000035a , \blk00000003/sig0000035b , \blk00000003/sig0000035c , +\blk00000003/sig0000035d , \blk00000003/sig0000035e , \blk00000003/sig0000035f , \blk00000003/sig00000360 , \blk00000003/sig00000361 , +\blk00000003/sig00000362 , \blk00000003/sig00000363 , \blk00000003/sig00000364 , \blk00000003/sig00000365 , \blk00000003/sig00000366 , +\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b , +\blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , \blk00000003/sig00000370 , +\blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , \blk00000003/sig00000375 , +\blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ef_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ef_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ef_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig0000044b , \blk00000003/sig0000044c , \blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , +\blk00000003/sig00000450 , \blk00000003/sig00000451 , \blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , +\blk00000003/sig00000455 , \blk00000003/sig00000456 , \blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , +\blk00000003/sig0000045a , \blk00000003/sig0000045b , \blk00000003/sig0000045c }), + .BCOUT({\NLW_blk00000003/blk000000ef_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000005e3 , \blk00000003/sig000005e3 , \blk00000003/sig000005e4 , \blk00000003/sig000005e5 , \blk00000003/sig000005e6 , +\blk00000003/sig000005e7 , \blk00000003/sig000005e8 , \blk00000003/sig000005e9 , \blk00000003/sig000005ea , \blk00000003/sig000005eb , +\blk00000003/sig000005ec , \blk00000003/sig000005ed , \blk00000003/sig000005ee , \blk00000003/sig000005ef , \blk00000003/sig000005f0 , +\blk00000003/sig000005f1 , \blk00000003/sig000005f2 , \blk00000003/sig000005f3 , \blk00000003/sig000005f4 , \blk00000003/sig000005f5 , +\blk00000003/sig000005f6 , \blk00000003/sig000005f7 , \blk00000003/sig000005f8 , \blk00000003/sig000005f9 , \blk00000003/sig000005fa }), + .P({\NLW_blk00000003/blk000000ef_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000005fb , \blk00000003/sig000005fb , \blk00000003/sig000005fb , \blk00000003/sig000005fb , \blk00000003/sig000005fb , +\blk00000003/sig000005fb , \blk00000003/sig000005fb , \blk00000003/sig000005fc , \blk00000003/sig000005fd , \blk00000003/sig000005fe , +\blk00000003/sig000005ff , \blk00000003/sig00000600 , \blk00000003/sig00000601 , \blk00000003/sig00000602 , \blk00000003/sig00000603 , +\blk00000003/sig00000604 , \blk00000003/sig00000605 , \blk00000003/sig00000606 , \blk00000003/sig00000607 , \blk00000003/sig00000608 , +\blk00000003/sig00000609 , \blk00000003/sig0000060a , \blk00000003/sig0000060b , \blk00000003/sig0000060c , \blk00000003/sig0000060d , +\blk00000003/sig0000060e , \blk00000003/sig0000060f , \blk00000003/sig00000610 , \blk00000003/sig00000611 , \blk00000003/sig00000612 }), + .PCOUT({\blk00000003/sig00000613 , \blk00000003/sig00000614 , \blk00000003/sig00000615 , \blk00000003/sig00000616 , \blk00000003/sig00000617 , +\blk00000003/sig00000618 , \blk00000003/sig00000619 , \blk00000003/sig0000061a , \blk00000003/sig0000061b , \blk00000003/sig0000061c , +\blk00000003/sig0000061d , \blk00000003/sig0000061e , \blk00000003/sig0000061f , \blk00000003/sig00000620 , \blk00000003/sig00000621 , +\blk00000003/sig00000622 , \blk00000003/sig00000623 , \blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , +\blk00000003/sig00000627 , \blk00000003/sig00000628 , \blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , +\blk00000003/sig0000062c , \blk00000003/sig0000062d , \blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , +\blk00000003/sig00000631 , \blk00000003/sig00000632 , \blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 , +\blk00000003/sig00000636 , \blk00000003/sig00000637 , \blk00000003/sig00000638 , \blk00000003/sig00000639 , \blk00000003/sig0000063a , +\blk00000003/sig0000063b , \blk00000003/sig0000063c , \blk00000003/sig0000063d , \blk00000003/sig0000063e , \blk00000003/sig0000063f , +\blk00000003/sig00000640 , \blk00000003/sig00000641 , \blk00000003/sig00000642 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ee ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ee_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ee_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ee_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ee_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ee_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ee_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ee_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000571 , \blk00000003/sig00000572 , \blk00000003/sig00000573 , \blk00000003/sig00000574 , \blk00000003/sig00000575 , +\blk00000003/sig00000576 , \blk00000003/sig00000577 , \blk00000003/sig00000578 , \blk00000003/sig00000579 , \blk00000003/sig0000057a , +\blk00000003/sig0000057b , \blk00000003/sig0000057c , \blk00000003/sig0000057d , \blk00000003/sig0000057e , \blk00000003/sig0000057f , +\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 , \blk00000003/sig00000592 , \blk00000003/sig00000593 , +\blk00000003/sig00000594 , \blk00000003/sig00000595 , \blk00000003/sig00000596 , \blk00000003/sig00000597 , \blk00000003/sig00000598 , +\blk00000003/sig00000599 , \blk00000003/sig0000059a , \blk00000003/sig0000059b , \blk00000003/sig0000059c , \blk00000003/sig0000059d , +\blk00000003/sig0000059e , \blk00000003/sig0000059f , \blk00000003/sig000005a0 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ee_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ee_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ee_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000005a1 , \blk00000003/sig000005a2 , \blk00000003/sig000005a3 , \blk00000003/sig000005a4 , \blk00000003/sig000005a5 , +\blk00000003/sig000005a6 , \blk00000003/sig000005a7 , \blk00000003/sig000005a8 , \blk00000003/sig000005a9 , \blk00000003/sig000005aa , +\blk00000003/sig000005ab , \blk00000003/sig000005ac , \blk00000003/sig000005ad , \blk00000003/sig000005ae , \blk00000003/sig000005af , +\blk00000003/sig000005b0 , \blk00000003/sig000005b1 , \blk00000003/sig000005b2 }), + .BCOUT({\NLW_blk00000003/blk000000ee_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000005b3 , \blk00000003/sig000005b3 , \blk00000003/sig000005b4 , \blk00000003/sig000005b5 , \blk00000003/sig000005b6 , +\blk00000003/sig000005b7 , \blk00000003/sig000005b8 , \blk00000003/sig000005b9 , \blk00000003/sig000005ba , \blk00000003/sig000005bb , +\blk00000003/sig000005bc , \blk00000003/sig000005bd , \blk00000003/sig000005be , \blk00000003/sig000005bf , \blk00000003/sig000005c0 , +\blk00000003/sig000005c1 , \blk00000003/sig000005c2 , \blk00000003/sig000005c3 , \blk00000003/sig000005c4 , \blk00000003/sig000005c5 , +\blk00000003/sig000005c6 , \blk00000003/sig000005c7 , \blk00000003/sig000005c8 , \blk00000003/sig000005c9 , \blk00000003/sig000005ca }), + .P({\NLW_blk00000003/blk000000ee_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000005cb , \blk00000003/sig000005cb , \blk00000003/sig000005cb , \blk00000003/sig000005cb , \blk00000003/sig000005cb , +\blk00000003/sig000005cb , \blk00000003/sig000005cb , \blk00000003/sig000005cc , \blk00000003/sig000005cd , \blk00000003/sig000005ce , +\blk00000003/sig000005cf , \blk00000003/sig000005d0 , \blk00000003/sig000005d1 , \blk00000003/sig000005d2 , \blk00000003/sig000005d3 , +\blk00000003/sig000005d4 , \blk00000003/sig000005d5 , \blk00000003/sig000005d6 , \blk00000003/sig000005d7 , \blk00000003/sig000005d8 , +\blk00000003/sig000005d9 , \blk00000003/sig000005da , \blk00000003/sig000005db , \blk00000003/sig000005dc , \blk00000003/sig000005dd , +\blk00000003/sig000005de , \blk00000003/sig000005df , \blk00000003/sig000005e0 , \blk00000003/sig000005e1 , \blk00000003/sig000005e2 }), + .PCOUT({\blk00000003/sig00000379 , \blk00000003/sig0000037a , \blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , +\blk00000003/sig0000037e , \blk00000003/sig0000037f , \blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , +\blk00000003/sig00000383 , \blk00000003/sig00000384 , \blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , +\blk00000003/sig00000388 , \blk00000003/sig00000389 , \blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , +\blk00000003/sig0000038d , \blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , +\blk00000003/sig00000392 , \blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 , +\blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , +\blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , +\blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , +\blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ed ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ed_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ed_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ed_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ed_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ed_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ed_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ed_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig000004ff , \blk00000003/sig00000500 , \blk00000003/sig00000501 , \blk00000003/sig00000502 , \blk00000003/sig00000503 , +\blk00000003/sig00000504 , \blk00000003/sig00000505 , \blk00000003/sig00000506 , \blk00000003/sig00000507 , \blk00000003/sig00000508 , +\blk00000003/sig00000509 , \blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c , \blk00000003/sig0000050d , +\blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , \blk00000003/sig00000512 , +\blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , \blk00000003/sig00000517 , +\blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , \blk00000003/sig0000051c , +\blk00000003/sig0000051d , \blk00000003/sig0000051e , \blk00000003/sig0000051f , \blk00000003/sig00000520 , \blk00000003/sig00000521 , +\blk00000003/sig00000522 , \blk00000003/sig00000523 , \blk00000003/sig00000524 , \blk00000003/sig00000525 , \blk00000003/sig00000526 , +\blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , \blk00000003/sig0000052b , +\blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ed_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ed_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ed_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig0000052f , \blk00000003/sig00000530 , \blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , +\blk00000003/sig00000534 , \blk00000003/sig00000535 , \blk00000003/sig00000536 , \blk00000003/sig00000537 , \blk00000003/sig00000538 , +\blk00000003/sig00000539 , \blk00000003/sig0000053a , \blk00000003/sig0000053b , \blk00000003/sig0000053c , \blk00000003/sig0000053d , +\blk00000003/sig0000053e , \blk00000003/sig0000053f , \blk00000003/sig00000540 }), + .BCOUT({\NLW_blk00000003/blk000000ed_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000541 , \blk00000003/sig00000541 , \blk00000003/sig00000542 , \blk00000003/sig00000543 , \blk00000003/sig00000544 , +\blk00000003/sig00000545 , \blk00000003/sig00000546 , \blk00000003/sig00000547 , \blk00000003/sig00000548 , \blk00000003/sig00000549 , +\blk00000003/sig0000054a , \blk00000003/sig0000054b , \blk00000003/sig0000054c , \blk00000003/sig0000054d , \blk00000003/sig0000054e , +\blk00000003/sig0000054f , \blk00000003/sig00000550 , \blk00000003/sig00000551 , \blk00000003/sig00000552 , \blk00000003/sig00000553 , +\blk00000003/sig00000554 , \blk00000003/sig00000555 , \blk00000003/sig00000556 , \blk00000003/sig00000557 , \blk00000003/sig00000558 }), + .P({\NLW_blk00000003/blk000000ed_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000559 , \blk00000003/sig00000559 , \blk00000003/sig00000559 , \blk00000003/sig00000559 , \blk00000003/sig00000559 , +\blk00000003/sig00000559 , \blk00000003/sig00000559 , \blk00000003/sig0000055a , \blk00000003/sig0000055b , \blk00000003/sig0000055c , +\blk00000003/sig0000055d , \blk00000003/sig0000055e , \blk00000003/sig0000055f , \blk00000003/sig00000560 , \blk00000003/sig00000561 , +\blk00000003/sig00000562 , \blk00000003/sig00000563 , \blk00000003/sig00000564 , \blk00000003/sig00000565 , \blk00000003/sig00000566 , +\blk00000003/sig00000567 , \blk00000003/sig00000568 , \blk00000003/sig00000569 , \blk00000003/sig0000056a , \blk00000003/sig0000056b , +\blk00000003/sig0000056c , \blk00000003/sig0000056d , \blk00000003/sig0000056e , \blk00000003/sig0000056f , \blk00000003/sig00000570 }), + .PCOUT({\blk00000003/sig00000571 , \blk00000003/sig00000572 , \blk00000003/sig00000573 , \blk00000003/sig00000574 , \blk00000003/sig00000575 , +\blk00000003/sig00000576 , \blk00000003/sig00000577 , \blk00000003/sig00000578 , \blk00000003/sig00000579 , \blk00000003/sig0000057a , +\blk00000003/sig0000057b , \blk00000003/sig0000057c , \blk00000003/sig0000057d , \blk00000003/sig0000057e , \blk00000003/sig0000057f , +\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 , \blk00000003/sig00000592 , \blk00000003/sig00000593 , +\blk00000003/sig00000594 , \blk00000003/sig00000595 , \blk00000003/sig00000596 , \blk00000003/sig00000597 , \blk00000003/sig00000598 , +\blk00000003/sig00000599 , \blk00000003/sig0000059a , \blk00000003/sig0000059b , \blk00000003/sig0000059c , \blk00000003/sig0000059d , +\blk00000003/sig0000059e , \blk00000003/sig0000059f , \blk00000003/sig000005a0 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ec ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ec_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ec_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ec_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ec_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ec_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ec_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ec_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig0000048d , \blk00000003/sig0000048e , \blk00000003/sig0000048f , \blk00000003/sig00000490 , \blk00000003/sig00000491 , +\blk00000003/sig00000492 , \blk00000003/sig00000493 , \blk00000003/sig00000494 , \blk00000003/sig00000495 , \blk00000003/sig00000496 , +\blk00000003/sig00000497 , \blk00000003/sig00000498 , \blk00000003/sig00000499 , \blk00000003/sig0000049a , \blk00000003/sig0000049b , +\blk00000003/sig0000049c , \blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , +\blk00000003/sig000004a1 , \blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , +\blk00000003/sig000004a6 , \blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa , +\blk00000003/sig000004ab , \blk00000003/sig000004ac , \blk00000003/sig000004ad , \blk00000003/sig000004ae , \blk00000003/sig000004af , +\blk00000003/sig000004b0 , \blk00000003/sig000004b1 , \blk00000003/sig000004b2 , \blk00000003/sig000004b3 , \blk00000003/sig000004b4 , +\blk00000003/sig000004b5 , \blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , +\blk00000003/sig000004ba , \blk00000003/sig000004bb , \blk00000003/sig000004bc }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ec_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ec_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ec_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000004bd , \blk00000003/sig000004be , \blk00000003/sig000004bf , \blk00000003/sig000004c0 , \blk00000003/sig000004c1 , +\blk00000003/sig000004c2 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , \blk00000003/sig000004c5 , \blk00000003/sig000004c6 , +\blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , \blk00000003/sig000004ca , \blk00000003/sig000004cb , +\blk00000003/sig000004cc , \blk00000003/sig000004cd , \blk00000003/sig000004ce }), + .BCOUT({\NLW_blk00000003/blk000000ec_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000004cf , \blk00000003/sig000004cf , \blk00000003/sig000004d0 , \blk00000003/sig000004d1 , \blk00000003/sig000004d2 , +\blk00000003/sig000004d3 , \blk00000003/sig000004d4 , \blk00000003/sig000004d5 , \blk00000003/sig000004d6 , \blk00000003/sig000004d7 , +\blk00000003/sig000004d8 , \blk00000003/sig000004d9 , \blk00000003/sig000004da , \blk00000003/sig000004db , \blk00000003/sig000004dc , +\blk00000003/sig000004dd , \blk00000003/sig000004de , \blk00000003/sig000004df , \blk00000003/sig000004e0 , \blk00000003/sig000004e1 , +\blk00000003/sig000004e2 , \blk00000003/sig000004e3 , \blk00000003/sig000004e4 , \blk00000003/sig000004e5 , \blk00000003/sig000004e6 }), + .P({\NLW_blk00000003/blk000000ec_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000004e7 , \blk00000003/sig000004e7 , \blk00000003/sig000004e7 , \blk00000003/sig000004e7 , \blk00000003/sig000004e7 , +\blk00000003/sig000004e7 , \blk00000003/sig000004e7 , \blk00000003/sig000004e8 , \blk00000003/sig000004e9 , \blk00000003/sig000004ea , +\blk00000003/sig000004eb , \blk00000003/sig000004ec , \blk00000003/sig000004ed , \blk00000003/sig000004ee , \blk00000003/sig000004ef , +\blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , \blk00000003/sig000004f3 , \blk00000003/sig000004f4 , +\blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , \blk00000003/sig000004f8 , \blk00000003/sig000004f9 , +\blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , \blk00000003/sig000004fd , \blk00000003/sig000004fe }), + .PCOUT({\blk00000003/sig000004ff , \blk00000003/sig00000500 , \blk00000003/sig00000501 , \blk00000003/sig00000502 , \blk00000003/sig00000503 , +\blk00000003/sig00000504 , \blk00000003/sig00000505 , \blk00000003/sig00000506 , \blk00000003/sig00000507 , \blk00000003/sig00000508 , +\blk00000003/sig00000509 , \blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c , \blk00000003/sig0000050d , +\blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , \blk00000003/sig00000512 , +\blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , \blk00000003/sig00000517 , +\blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , \blk00000003/sig0000051c , +\blk00000003/sig0000051d , \blk00000003/sig0000051e , \blk00000003/sig0000051f , \blk00000003/sig00000520 , \blk00000003/sig00000521 , +\blk00000003/sig00000522 , \blk00000003/sig00000523 , \blk00000003/sig00000524 , \blk00000003/sig00000525 , \blk00000003/sig00000526 , +\blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , \blk00000003/sig0000052b , +\blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000eb ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000eb_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000eb_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000eb_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000eb_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000eb_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000eb_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000eb_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig000002e9 , \blk00000003/sig000002ea , \blk00000003/sig000002eb , \blk00000003/sig000002ec , \blk00000003/sig000002ed , +\blk00000003/sig000002ee , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , \blk00000003/sig000002f1 , \blk00000003/sig000002f2 , +\blk00000003/sig000002f3 , \blk00000003/sig000002f4 , \blk00000003/sig000002f5 , \blk00000003/sig000002f6 , \blk00000003/sig000002f7 , +\blk00000003/sig000002f8 , \blk00000003/sig000002f9 , \blk00000003/sig000002fa , \blk00000003/sig000002fb , \blk00000003/sig000002fc , +\blk00000003/sig000002fd , \blk00000003/sig000002fe , \blk00000003/sig000002ff , \blk00000003/sig00000300 , \blk00000003/sig00000301 , +\blk00000003/sig00000302 , \blk00000003/sig00000303 , \blk00000003/sig00000304 , \blk00000003/sig00000305 , \blk00000003/sig00000306 , +\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b , +\blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , \blk00000003/sig00000310 , +\blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , \blk00000003/sig00000315 , +\blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000eb_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000eb_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000eb_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig0000044b , \blk00000003/sig0000044c , \blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , +\blk00000003/sig00000450 , \blk00000003/sig00000451 , \blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , +\blk00000003/sig00000455 , \blk00000003/sig00000456 , \blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , +\blk00000003/sig0000045a , \blk00000003/sig0000045b , \blk00000003/sig0000045c }), + .BCOUT({\NLW_blk00000003/blk000000eb_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig0000045d , \blk00000003/sig0000045d , \blk00000003/sig0000045e , \blk00000003/sig0000045f , \blk00000003/sig00000460 , +\blk00000003/sig00000461 , \blk00000003/sig00000462 , \blk00000003/sig00000463 , \blk00000003/sig00000464 , \blk00000003/sig00000465 , +\blk00000003/sig00000466 , \blk00000003/sig00000467 , \blk00000003/sig00000468 , \blk00000003/sig00000469 , \blk00000003/sig0000046a , +\blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d , \blk00000003/sig0000046e , \blk00000003/sig0000046f , +\blk00000003/sig00000470 , \blk00000003/sig00000471 , \blk00000003/sig00000472 , \blk00000003/sig00000473 , \blk00000003/sig00000474 }), + .P({\NLW_blk00000003/blk000000eb_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000475 , \blk00000003/sig00000475 , \blk00000003/sig00000475 , \blk00000003/sig00000475 , \blk00000003/sig00000475 , +\blk00000003/sig00000475 , \blk00000003/sig00000475 , \blk00000003/sig00000476 , \blk00000003/sig00000477 , \blk00000003/sig00000478 , +\blk00000003/sig00000479 , \blk00000003/sig0000047a , \blk00000003/sig0000047b , \blk00000003/sig0000047c , \blk00000003/sig0000047d , +\blk00000003/sig0000047e , \blk00000003/sig0000047f , \blk00000003/sig00000480 , \blk00000003/sig00000481 , \blk00000003/sig00000482 , +\blk00000003/sig00000483 , \blk00000003/sig00000484 , \blk00000003/sig00000485 , \blk00000003/sig00000486 , \blk00000003/sig00000487 , +\blk00000003/sig00000488 , \blk00000003/sig00000489 , \blk00000003/sig0000048a , \blk00000003/sig0000048b , \blk00000003/sig0000048c }), + .PCOUT({\blk00000003/sig0000048d , \blk00000003/sig0000048e , \blk00000003/sig0000048f , \blk00000003/sig00000490 , \blk00000003/sig00000491 , +\blk00000003/sig00000492 , \blk00000003/sig00000493 , \blk00000003/sig00000494 , \blk00000003/sig00000495 , \blk00000003/sig00000496 , +\blk00000003/sig00000497 , \blk00000003/sig00000498 , \blk00000003/sig00000499 , \blk00000003/sig0000049a , \blk00000003/sig0000049b , +\blk00000003/sig0000049c , \blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , +\blk00000003/sig000004a1 , \blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , +\blk00000003/sig000004a6 , \blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa , +\blk00000003/sig000004ab , \blk00000003/sig000004ac , \blk00000003/sig000004ad , \blk00000003/sig000004ae , \blk00000003/sig000004af , +\blk00000003/sig000004b0 , \blk00000003/sig000004b1 , \blk00000003/sig000004b2 , \blk00000003/sig000004b3 , \blk00000003/sig000004b4 , +\blk00000003/sig000004b5 , \blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , +\blk00000003/sig000004ba , \blk00000003/sig000004bb , \blk00000003/sig000004bc }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ea ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ea_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ea_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ea_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ea_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ea_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ea_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ea_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig000003eb , \blk00000003/sig000003ec , \blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , +\blk00000003/sig000003f0 , \blk00000003/sig000003f1 , \blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , +\blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , +\blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 , +\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d , +\blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , \blk00000003/sig00000412 , +\blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , \blk00000003/sig00000417 , +\blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ea_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ea_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ea_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003a9 , \blk00000003/sig000003aa , \blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , +\blk00000003/sig000003ae , \blk00000003/sig000003af , \blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , +\blk00000003/sig000003b3 , \blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , +\blk00000003/sig000003b8 , \blk00000003/sig000003b9 , \blk00000003/sig000003ba }), + .BCOUT({\NLW_blk00000003/blk000000ea_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig0000041b , \blk00000003/sig0000041b , \blk00000003/sig0000041c , \blk00000003/sig0000041d , \blk00000003/sig0000041e , +\blk00000003/sig0000041f , \blk00000003/sig00000420 , \blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , +\blk00000003/sig00000424 , \blk00000003/sig00000425 , \blk00000003/sig00000426 , \blk00000003/sig00000427 , \blk00000003/sig00000428 , +\blk00000003/sig00000429 , \blk00000003/sig0000042a , \blk00000003/sig0000042b , \blk00000003/sig0000042c , \blk00000003/sig0000042d , +\blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , \blk00000003/sig00000431 , \blk00000003/sig00000432 }), + .P({\NLW_blk00000003/blk000000ea_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000433 , \blk00000003/sig00000433 , \blk00000003/sig00000433 , \blk00000003/sig00000433 , \blk00000003/sig00000433 , +\blk00000003/sig00000433 , \blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , \blk00000003/sig00000436 , +\blk00000003/sig00000437 , \blk00000003/sig00000438 , \blk00000003/sig00000439 , \blk00000003/sig0000043a , \blk00000003/sig0000043b , +\blk00000003/sig0000043c , \blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , \blk00000003/sig00000440 , +\blk00000003/sig00000441 , \blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , \blk00000003/sig00000445 , +\blk00000003/sig00000446 , \blk00000003/sig00000447 , \blk00000003/sig00000448 , \blk00000003/sig00000449 , \blk00000003/sig0000044a }), + .PCOUT({\blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , +\blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , +\blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , +\blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , \blk00000003/sig000000dc , \blk00000003/sig000000dd , +\blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , +\blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , +\blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , +\blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 , +\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , +\blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000e9 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000e9_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000e9_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000e9_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000e9_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000e9_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000e9_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000e9_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000379 , \blk00000003/sig0000037a , \blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , +\blk00000003/sig0000037e , \blk00000003/sig0000037f , \blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , +\blk00000003/sig00000383 , \blk00000003/sig00000384 , \blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , +\blk00000003/sig00000388 , \blk00000003/sig00000389 , \blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , +\blk00000003/sig0000038d , \blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , +\blk00000003/sig00000392 , \blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 , +\blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , +\blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , +\blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , +\blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000e9_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e9_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e9_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003a9 , \blk00000003/sig000003aa , \blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , +\blk00000003/sig000003ae , \blk00000003/sig000003af , \blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , +\blk00000003/sig000003b3 , \blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , +\blk00000003/sig000003b8 , \blk00000003/sig000003b9 , \blk00000003/sig000003ba }), + .BCOUT({\NLW_blk00000003/blk000000e9_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000003bb , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , +\blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd , +\blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 }), + .P({\NLW_blk00000003/blk000000e9_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000003d3 , \blk00000003/sig000003d3 , \blk00000003/sig000003d3 , \blk00000003/sig000003d3 , \blk00000003/sig000003d3 , +\blk00000003/sig000003d3 , \blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , \blk00000003/sig000003d6 , +\blk00000003/sig000003d7 , \blk00000003/sig000003d8 , \blk00000003/sig000003d9 , \blk00000003/sig000003da , \blk00000003/sig000003db , +\blk00000003/sig000003dc , \blk00000003/sig000003dd , \blk00000003/sig000003de , \blk00000003/sig000003df , \blk00000003/sig000003e0 , +\blk00000003/sig000003e1 , \blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , \blk00000003/sig000003e5 , +\blk00000003/sig000003e6 , \blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , \blk00000003/sig000003ea }), + .PCOUT({\blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , \blk00000003/sig00000156 , \blk00000003/sig00000157 , +\blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , \blk00000003/sig0000015b , \blk00000003/sig0000015c , +\blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , \blk00000003/sig00000160 , \blk00000003/sig00000161 , +\blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , \blk00000003/sig00000165 , \blk00000003/sig00000166 , +\blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , \blk00000003/sig0000016a , \blk00000003/sig0000016b , +\blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , \blk00000003/sig0000016f , \blk00000003/sig00000170 , +\blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , \blk00000003/sig00000174 , \blk00000003/sig00000175 , +\blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , +\blk00000003/sig0000017b , \blk00000003/sig0000017c , \blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , +\blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000e8 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000e8_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000e8_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000e8_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000e8_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000e8_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000e8_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000e8_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000e8_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e8_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e8_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002a7 , \blk00000003/sig000002a8 , \blk00000003/sig000002a9 , \blk00000003/sig000002aa , \blk00000003/sig000002ab , +\blk00000003/sig000002ac , \blk00000003/sig000002ad , \blk00000003/sig000002ae , \blk00000003/sig000002af , \blk00000003/sig000002b0 , +\blk00000003/sig000002b1 , \blk00000003/sig000002b2 , \blk00000003/sig000002b3 , \blk00000003/sig000002b4 , \blk00000003/sig000002b5 , +\blk00000003/sig000002b6 , \blk00000003/sig000002b7 , \blk00000003/sig000002b8 }), + .BCOUT({\NLW_blk00000003/blk000000e8_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000319 , \blk00000003/sig00000319 , \blk00000003/sig0000031a , \blk00000003/sig0000031b , \blk00000003/sig0000031c , +\blk00000003/sig0000031d , \blk00000003/sig0000031e , \blk00000003/sig0000031f , \blk00000003/sig00000320 , \blk00000003/sig00000321 , +\blk00000003/sig00000322 , \blk00000003/sig00000323 , \blk00000003/sig00000324 , \blk00000003/sig00000325 , \blk00000003/sig00000326 , +\blk00000003/sig00000327 , \blk00000003/sig00000328 , \blk00000003/sig00000329 , \blk00000003/sig0000032a , \blk00000003/sig0000032b , +\blk00000003/sig0000032c , \blk00000003/sig0000032d , \blk00000003/sig0000032e , \blk00000003/sig0000032f , \blk00000003/sig00000330 }), + .P({\NLW_blk00000003/blk000000e8_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000331 , \blk00000003/sig00000331 , \blk00000003/sig00000331 , \blk00000003/sig00000331 , \blk00000003/sig00000331 , +\blk00000003/sig00000331 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , \blk00000003/sig00000333 , \blk00000003/sig00000334 , +\blk00000003/sig00000335 , \blk00000003/sig00000336 , \blk00000003/sig00000337 , \blk00000003/sig00000338 , \blk00000003/sig00000339 , +\blk00000003/sig0000033a , \blk00000003/sig0000033b , \blk00000003/sig0000033c , \blk00000003/sig0000033d , \blk00000003/sig0000033e , +\blk00000003/sig0000033f , \blk00000003/sig00000340 , \blk00000003/sig00000341 , \blk00000003/sig00000342 , \blk00000003/sig00000343 , +\blk00000003/sig00000344 , \blk00000003/sig00000345 , \blk00000003/sig00000346 , \blk00000003/sig00000347 , \blk00000003/sig00000348 }), + .PCOUT({\blk00000003/sig00000349 , \blk00000003/sig0000034a , \blk00000003/sig0000034b , \blk00000003/sig0000034c , \blk00000003/sig0000034d , +\blk00000003/sig0000034e , \blk00000003/sig0000034f , \blk00000003/sig00000350 , \blk00000003/sig00000351 , \blk00000003/sig00000352 , +\blk00000003/sig00000353 , \blk00000003/sig00000354 , \blk00000003/sig00000355 , \blk00000003/sig00000356 , \blk00000003/sig00000357 , +\blk00000003/sig00000358 , \blk00000003/sig00000359 , \blk00000003/sig0000035a , \blk00000003/sig0000035b , \blk00000003/sig0000035c , +\blk00000003/sig0000035d , \blk00000003/sig0000035e , \blk00000003/sig0000035f , \blk00000003/sig00000360 , \blk00000003/sig00000361 , +\blk00000003/sig00000362 , \blk00000003/sig00000363 , \blk00000003/sig00000364 , \blk00000003/sig00000365 , \blk00000003/sig00000366 , +\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b , +\blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , \blk00000003/sig00000370 , +\blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , \blk00000003/sig00000375 , +\blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000e7 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000e7_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000e7_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000e7_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000e7_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000e7_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000e7_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000e7_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000e7_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e7_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e7_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002a7 , \blk00000003/sig000002a8 , \blk00000003/sig000002a9 , \blk00000003/sig000002aa , \blk00000003/sig000002ab , +\blk00000003/sig000002ac , \blk00000003/sig000002ad , \blk00000003/sig000002ae , \blk00000003/sig000002af , \blk00000003/sig000002b0 , +\blk00000003/sig000002b1 , \blk00000003/sig000002b2 , \blk00000003/sig000002b3 , \blk00000003/sig000002b4 , \blk00000003/sig000002b5 , +\blk00000003/sig000002b6 , \blk00000003/sig000002b7 , \blk00000003/sig000002b8 }), + .BCOUT({\NLW_blk00000003/blk000000e7_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000002b9 , \blk00000003/sig000002b9 , \blk00000003/sig000002ba , \blk00000003/sig000002bb , \blk00000003/sig000002bc , +\blk00000003/sig000002bd , \blk00000003/sig000002be , \blk00000003/sig000002bf , \blk00000003/sig000002c0 , \blk00000003/sig000002c1 , +\blk00000003/sig000002c2 , \blk00000003/sig000002c3 , \blk00000003/sig000002c4 , \blk00000003/sig000002c5 , \blk00000003/sig000002c6 , +\blk00000003/sig000002c7 , \blk00000003/sig000002c8 , \blk00000003/sig000002c9 , \blk00000003/sig000002ca , \blk00000003/sig000002cb , +\blk00000003/sig000002cc , \blk00000003/sig000002cd , \blk00000003/sig000002ce , \blk00000003/sig000002cf , \blk00000003/sig000002d0 }), + .P({\NLW_blk00000003/blk000000e7_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000002d1 , \blk00000003/sig000002d1 , \blk00000003/sig000002d1 , \blk00000003/sig000002d1 , \blk00000003/sig000002d1 , +\blk00000003/sig000002d1 , \blk00000003/sig000002d1 , \blk00000003/sig000002d2 , \blk00000003/sig000002d3 , \blk00000003/sig000002d4 , +\blk00000003/sig000002d5 , \blk00000003/sig000002d6 , \blk00000003/sig000002d7 , \blk00000003/sig000002d8 , \blk00000003/sig000002d9 , +\blk00000003/sig000002da , \blk00000003/sig000002db , \blk00000003/sig000002dc , \blk00000003/sig000002dd , \blk00000003/sig000002de , +\blk00000003/sig000002df , \blk00000003/sig000002e0 , \blk00000003/sig000002e1 , \blk00000003/sig000002e2 , \blk00000003/sig000002e3 , +\blk00000003/sig000002e4 , \blk00000003/sig000002e5 , \blk00000003/sig000002e6 , \blk00000003/sig000002e7 , \blk00000003/sig000002e8 }), + .PCOUT({\blk00000003/sig000002e9 , \blk00000003/sig000002ea , \blk00000003/sig000002eb , \blk00000003/sig000002ec , \blk00000003/sig000002ed , +\blk00000003/sig000002ee , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , \blk00000003/sig000002f1 , \blk00000003/sig000002f2 , +\blk00000003/sig000002f3 , \blk00000003/sig000002f4 , \blk00000003/sig000002f5 , \blk00000003/sig000002f6 , \blk00000003/sig000002f7 , +\blk00000003/sig000002f8 , \blk00000003/sig000002f9 , \blk00000003/sig000002fa , \blk00000003/sig000002fb , \blk00000003/sig000002fc , +\blk00000003/sig000002fd , \blk00000003/sig000002fe , \blk00000003/sig000002ff , \blk00000003/sig00000300 , \blk00000003/sig00000301 , +\blk00000003/sig00000302 , \blk00000003/sig00000303 , \blk00000003/sig00000304 , \blk00000003/sig00000305 , \blk00000003/sig00000306 , +\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b , +\blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , \blk00000003/sig00000310 , +\blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , \blk00000003/sig00000315 , +\blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ce ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a4 ), + .Q(\blk00000003/sig000002a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a3 ), + .Q(\blk00000003/sig0000029f ) + ); + XORCY \blk00000003/blk000000e3 ( + .CI(\blk00000003/sig0000029f ), + .LI(\blk00000003/sig000002a1 ), + .O(\blk00000003/sig000002a2 ) + ); + MUXCY_D \blk00000003/blk000000e2 ( + .CI(\blk00000003/sig0000029f ), + .DI(\blk00000003/sig000002a0 ), + .S(\blk00000003/sig000002a1 ), + .O(\NLW_blk00000003/blk000000e2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e2_LO_UNCONNECTED ) + ); + FDE \blk00000003/blk000000e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029d ), + .Q(\blk00000003/sig0000029e ) + ); + XORCY \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig00000299 ), + .LI(\blk00000003/sig0000029b ), + .O(\blk00000003/sig0000029c ) + ); + MUXCY_D \blk00000003/blk000000df ( + .CI(\blk00000003/sig00000299 ), + .DI(\blk00000003/sig0000029a ), + .S(\blk00000003/sig0000029b ), + .O(\NLW_blk00000003/blk000000df_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000df_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000de ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig00000298 ), + .O(\blk00000003/sig00000299 ) + ); + XORCY \blk00000003/blk000000dd ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000296 ), + .O(\blk00000003/sig00000297 ) + ); + MUXCY_D \blk00000003/blk000000dc ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000295 ), + .S(\blk00000003/sig00000296 ), + .O(\NLW_blk00000003/blk000000dc_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000dc_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000db ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000294 ), + .S(\blk00000003/sig0000028e ), + .LO(\blk00000003/sig00000290 ) + ); + MUXCY_D \blk00000003/blk000000da ( + .CI(\blk00000003/sig00000290 ), + .DI(\blk00000003/sig00000293 ), + .S(\blk00000003/sig00000291 ), + .O(\NLW_blk00000003/blk000000da_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000da_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000d9 ( + .CI(\blk00000003/sig00000290 ), + .LI(\blk00000003/sig00000291 ), + .O(\blk00000003/sig00000292 ) + ); + XORCY \blk00000003/blk000000d8 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig0000028e ), + .O(\blk00000003/sig0000028f ) + ); + MUXCY_L \blk00000003/blk000000d7 ( + .CI(\blk00000003/sig00000287 ), + .DI(\blk00000003/sig000001e9 ), + .S(\blk00000003/sig00000288 ), + .LO(\blk00000003/sig0000028a ) + ); + MUXCY_D \blk00000003/blk000000d6 ( + .CI(\blk00000003/sig0000028a ), + .DI(\blk00000003/sig000001e8 ), + .S(\blk00000003/sig0000028b ), + .O(\NLW_blk00000003/blk000000d6_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000d6_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000d5 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig0000028d ), + .O(\blk00000003/sig00000287 ) + ); + XORCY \blk00000003/blk000000d4 ( + .CI(\blk00000003/sig0000028a ), + .LI(\blk00000003/sig0000028b ), + .O(\blk00000003/sig0000028c ) + ); + XORCY \blk00000003/blk000000d3 ( + .CI(\blk00000003/sig00000287 ), + .LI(\blk00000003/sig00000288 ), + .O(\blk00000003/sig00000289 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000278 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000221 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000277 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021e ) + ); + MUXCY_D \blk00000003/blk000000d0 ( + .CI(\blk00000003/sig0000021e ), + .DI(\blk00000003/sig00000285 ), + .S(\blk00000003/sig00000286 ), + .O(\blk00000003/sig00000282 ), + .LO(\NLW_blk00000003/blk000000d0_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cf ( + .CI(\blk00000003/sig00000282 ), + .DI(\blk00000003/sig00000283 ), + .S(\blk00000003/sig00000284 ), + .O(\blk00000003/sig00000280 ), + .LO(\NLW_blk00000003/blk000000cf_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000ce ( + .CI(\blk00000003/sig00000280 ), + .DI(\blk00000003/sig00000276 ), + .S(\blk00000003/sig00000281 ), + .O(\blk00000003/sig0000027d ), + .LO(\NLW_blk00000003/blk000000ce_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cd ( + .CI(\blk00000003/sig0000027d ), + .DI(\blk00000003/sig0000027e ), + .S(\blk00000003/sig0000027f ), + .O(\blk00000003/sig0000027b ), + .LO(\NLW_blk00000003/blk000000cd_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cc ( + .CI(\blk00000003/sig0000027b ), + .DI(\blk00000003/sig00000249 ), + .S(\blk00000003/sig0000027c ), + .O(\blk00000003/sig00000279 ), + .LO(\NLW_blk00000003/blk000000cc_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cb ( + .CI(\blk00000003/sig00000279 ), + .DI(\blk00000003/sig0000021b ), + .S(\blk00000003/sig0000027a ), + .O(\NLW_blk00000003/blk000000cb_O_UNCONNECTED ), + .LO(\blk00000003/sig00000277 ) + ); + XORCY \blk00000003/blk000000ca ( + .CI(\blk00000003/sig00000277 ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000278 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000266 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000276 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000265 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000001ce ) + ); + MUXCY_D \blk00000003/blk000000c7 ( + .CI(\blk00000003/sig000001ce ), + .DI(\blk00000003/sig00000274 ), + .S(\blk00000003/sig00000275 ), + .O(\blk00000003/sig00000272 ), + .LO(\NLW_blk00000003/blk000000c7_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c6 ( + .CI(\blk00000003/sig00000272 ), + .DI(\blk00000003/sig000001cf ), + .S(\blk00000003/sig00000273 ), + .O(\blk00000003/sig00000270 ), + .LO(\NLW_blk00000003/blk000000c6_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c5 ( + .CI(\blk00000003/sig00000270 ), + .DI(\blk00000003/sig000001ce ), + .S(\blk00000003/sig00000271 ), + .O(\blk00000003/sig0000026d ), + .LO(\NLW_blk00000003/blk000000c5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c4 ( + .CI(\blk00000003/sig0000026d ), + .DI(\blk00000003/sig0000026e ), + .S(\blk00000003/sig0000026f ), + .O(\blk00000003/sig0000026b ), + .LO(\NLW_blk00000003/blk000000c4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c3 ( + .CI(\blk00000003/sig0000026b ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig0000026c ), + .O(\blk00000003/sig00000267 ), + .LO(\NLW_blk00000003/blk000000c3_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c2 ( + .CI(\blk00000003/sig00000269 ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig0000026a ), + .O(\NLW_blk00000003/blk000000c2_O_UNCONNECTED ), + .LO(\blk00000003/sig00000265 ) + ); + MUXCY_D \blk00000003/blk000000c1 ( + .CI(\blk00000003/sig00000267 ), + .DI(\blk00000003/sig0000023e ), + .S(\blk00000003/sig00000268 ), + .O(\blk00000003/sig00000269 ), + .LO(\NLW_blk00000003/blk000000c1_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c0 ( + .CI(\blk00000003/sig00000265 ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000266 ) + ); + FDE \blk00000003/blk000000bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000263 ), + .Q(\blk00000003/sig00000264 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000262 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000025e ) + ); + XORCY \blk00000003/blk000000bc ( + .CI(\blk00000003/sig0000025e ), + .LI(\blk00000003/sig00000260 ), + .O(\blk00000003/sig00000261 ) + ); + MUXCY_D \blk00000003/blk000000bb ( + .CI(\blk00000003/sig0000025e ), + .DI(\blk00000003/sig0000025f ), + .S(\blk00000003/sig00000260 ), + .O(\NLW_blk00000003/blk000000bb_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000bb_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000ba ( + .CI(\blk00000003/sig00000251 ), + .DI(\blk00000003/sig0000025d ), + .S(\blk00000003/sig00000252 ), + .LO(\blk00000003/sig00000257 ) + ); + MUXCY_L \blk00000003/blk000000b9 ( + .CI(\blk00000003/sig00000257 ), + .DI(\blk00000003/sig0000025c ), + .S(\blk00000003/sig00000258 ), + .LO(\blk00000003/sig00000254 ) + ); + MUXCY_D \blk00000003/blk000000b8 ( + .CI(\blk00000003/sig00000254 ), + .DI(\blk00000003/sig0000025b ), + .S(\blk00000003/sig00000255 ), + .O(\NLW_blk00000003/blk000000b8_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b8_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000b7 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig0000025a ), + .O(\blk00000003/sig00000251 ) + ); + XORCY \blk00000003/blk000000b6 ( + .CI(\blk00000003/sig00000257 ), + .LI(\blk00000003/sig00000258 ), + .O(\blk00000003/sig00000259 ) + ); + XORCY \blk00000003/blk000000b5 ( + .CI(\blk00000003/sig00000254 ), + .LI(\blk00000003/sig00000255 ), + .O(\blk00000003/sig00000256 ) + ); + XORCY \blk00000003/blk000000b4 ( + .CI(\blk00000003/sig00000251 ), + .LI(\blk00000003/sig00000252 ), + .O(\blk00000003/sig00000253 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b3 ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig00000250 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b2 ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig0000024f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001df ), + .Q(\blk00000003/sig00000243 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024e ), + .Q(\blk00000003/sig00000236 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024c ), + .Q(\blk00000003/sig0000024d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024b ), + .Q(\blk00000003/sig00000234 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024a ), + .Q(\blk00000003/sig00000241 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000248 ), + .Q(\blk00000003/sig00000249 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000246 ), + .Q(\blk00000003/sig00000247 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000244 ), + .Q(\blk00000003/sig00000245 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000243 ), + .Q(\blk00000003/sig0000023f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000241 ), + .Q(\blk00000003/sig00000242 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023f ), + .Q(\blk00000003/sig00000240 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021d ), + .Q(\blk00000003/sig0000023e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000239 ), + .Q(\blk00000003/sig0000023d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000233 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a4_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000230 ), + .R(coef_ld), + .Q(\blk00000003/sig0000022f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022d ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a2_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000229 ), + .R(coef_ld), + .Q(\blk00000003/sig00000227 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000023c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000023b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000238 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000239 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000236 ), + .Q(\blk00000003/sig00000237 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000234 ), + .Q(\blk00000003/sig00000235 ) + ); + MUXCY_D \blk00000003/blk0000009b ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000232 ), + .O(\blk00000003/sig0000022b ), + .LO(\blk00000003/sig00000233 ) + ); + MUXCY_D \blk00000003/blk0000009a ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000231 ), + .O(\blk00000003/sig0000022e ), + .LO(\NLW_blk00000003/blk0000009a_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000099 ( + .CI(\blk00000003/sig0000022e ), + .DI(\blk00000003/sig0000022f ), + .S(coef_we), + .O(\NLW_blk00000003/blk00000099_O_UNCONNECTED ), + .LO(\blk00000003/sig00000230 ) + ); + MUXCY_D \blk00000003/blk00000098 ( + .CI(\blk00000003/sig0000022b ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022c ), + .O(\NLW_blk00000003/blk00000098_O_UNCONNECTED ), + .LO(\blk00000003/sig0000022d ) + ); + MUXCY_D \blk00000003/blk00000097 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022a ), + .O(\blk00000003/sig00000226 ), + .LO(\NLW_blk00000003/blk00000097_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000096 ( + .CI(\blk00000003/sig00000226 ), + .DI(\blk00000003/sig00000227 ), + .S(\blk00000003/sig00000228 ), + .O(\NLW_blk00000003/blk00000096_O_UNCONNECTED ), + .LO(\blk00000003/sig00000229 ) + ); + XORCY \blk00000003/blk00000095 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000224 ), + .O(\blk00000003/sig00000225 ) + ); + MUXCY_D \blk00000003/blk00000094 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000223 ), + .S(\blk00000003/sig00000224 ), + .O(\NLW_blk00000003/blk00000094_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000094_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000093 ( + .CI(\blk00000003/sig0000021c ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000021a ) + ); + MUXCY_D \blk00000003/blk00000092 ( + .CI(\blk00000003/sig00000220 ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig00000222 ), + .O(\NLW_blk00000003/blk00000092_O_UNCONNECTED ), + .LO(\blk00000003/sig0000021c ) + ); + MUXCY_D \blk00000003/blk00000091 ( + .CI(\blk00000003/sig0000021d ), + .DI(\blk00000003/sig0000021e ), + .S(\blk00000003/sig0000021f ), + .O(\blk00000003/sig00000220 ), + .LO(\NLW_blk00000003/blk00000091_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000090 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021d ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000008f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021a ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021b ) + ); + FDR #( + .INIT ( 1'b1 )) + \blk00000003/blk0000002b ( + .C(clk), + .D(\blk00000003/sig000000be ), + .R(sclr), + .Q(\blk00000003/sig000000be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e6 ), + .R(sclr), + .Q(\blk00000003/sig000001e5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000029 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e5 ), + .R(sclr), + .Q(\blk00000003/sig000001e0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000028 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e4 ), + .R(\blk00000003/sig000001dd ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e2 ), + .R(sclr), + .Q(\blk00000003/sig000001e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e0 ), + .R(sclr), + .Q(\blk00000003/sig000001e1 ) + ); + FDRE \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001de ), + .R(sclr), + .Q(\blk00000003/sig000001df ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001dc ), + .R(\blk00000003/sig000001dd ), + .Q(rdy) + ); + FDRE \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001da ), + .R(sclr), + .Q(\blk00000003/sig000001db ) + ); + FDSE \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d8 ), + .S(sclr), + .Q(\blk00000003/sig000001d9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000021 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cc ), + .R(sclr), + .Q(\blk00000003/sig000001d7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000020 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d6 ), + .R(sclr), + .Q(\blk00000003/sig000001ca ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d4 ), + .R(sclr), + .Q(\blk00000003/sig000001d5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d2 ), + .R(sclr), + .Q(\blk00000003/sig000001d3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d0 ), + .R(sclr), + .Q(\NLW_blk00000003/blk0000001d_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d0 ), + .R(sclr), + .Q(\blk00000003/sig000001d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ce ), + .Q(\blk00000003/sig000001cf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c8 ), + .R(sclr), + .Q(\blk00000003/sig000000c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000019 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c3 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000019_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000018 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c4 ), + .S(sclr), + .Q(\blk00000003/sig000001cd ) + ); + MUXCY_D \blk00000003/blk00000017 ( + .CI(\blk00000003/sig000001ca ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001cb ), + .O(\NLW_blk00000003/blk00000017_O_UNCONNECTED ), + .LO(\blk00000003/sig000001cc ) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000016 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000016_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk00000016_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000016_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000016_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000016_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000016_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000016_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b8 , \blk00000003/sig00000049 , \blk00000003/sig000000bc , +\blk00000003/sig000000ba , \blk00000003/sig000000bc }), + .PCIN({\blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , \blk00000003/sig00000156 , \blk00000003/sig00000157 , +\blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , \blk00000003/sig0000015b , \blk00000003/sig0000015c , +\blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , \blk00000003/sig00000160 , \blk00000003/sig00000161 , +\blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , \blk00000003/sig00000165 , \blk00000003/sig00000166 , +\blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , \blk00000003/sig0000016a , \blk00000003/sig0000016b , +\blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , \blk00000003/sig0000016f , \blk00000003/sig00000170 , +\blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , \blk00000003/sig00000174 , \blk00000003/sig00000175 , +\blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , +\blk00000003/sig0000017b , \blk00000003/sig0000017c , \blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , +\blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000016_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000fa , \blk00000003/sig000000fb , \blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , +\blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , \blk00000003/sig00000102 , \blk00000003/sig00000103 , +\blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , \blk00000003/sig00000107 , \blk00000003/sig00000108 , +\blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b }), + .BCOUT({\NLW_blk00000003/blk00000016_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000016_P<47>_UNCONNECTED , \blk00000003/sig00000183 , \blk00000003/sig00000184 , \blk00000003/sig00000185 , +\blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , \blk00000003/sig0000018a , +\blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , \blk00000003/sig0000018f , +\blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , \blk00000003/sig00000194 , +\blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , \blk00000003/sig00000199 , +\blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , \blk00000003/sig0000019e , +\blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , \blk00000003/sig000001a3 , +\blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 , \blk00000003/sig000001a8 , +\blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , \blk00000003/sig000001ad , +\blk00000003/sig000001ae , \blk00000003/sig000001af , \blk00000003/sig000001b0 , \blk00000003/sig000001b1 }), + .A({\blk00000003/sig000001b2 , \blk00000003/sig000001b2 , \blk00000003/sig000001b2 , \blk00000003/sig000001b2 , \blk00000003/sig000001b2 , +\blk00000003/sig000001b2 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , \blk00000003/sig000001b5 , +\blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , \blk00000003/sig000001ba , +\blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , \blk00000003/sig000001bf , +\blk00000003/sig000001c0 , \blk00000003/sig000001c1 , \blk00000003/sig000001c2 , \blk00000003/sig000001c3 , \blk00000003/sig000001c4 , +\blk00000003/sig000001c5 , \blk00000003/sig000001c6 , \blk00000003/sig000001c7 , \blk00000003/sig000001c8 , \blk00000003/sig000001c9 }), + .PCOUT({\NLW_blk00000003/blk00000016_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000015 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000015_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk00000015_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000015_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000015_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000015_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000015_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000015_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b8 , \blk00000003/sig00000049 , \blk00000003/sig000000bc , +\blk00000003/sig000000ba , \blk00000003/sig000000bc }), + .PCIN({\blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , +\blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , +\blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , +\blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , \blk00000003/sig000000dc , \blk00000003/sig000000dd , +\blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , +\blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , +\blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , +\blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 , +\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , +\blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000015_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000fa , \blk00000003/sig000000fb , \blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , +\blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , \blk00000003/sig00000102 , \blk00000003/sig00000103 , +\blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , \blk00000003/sig00000107 , \blk00000003/sig00000108 , +\blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b }), + .BCOUT({\NLW_blk00000003/blk00000015_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000015_P<47>_UNCONNECTED , \blk00000003/sig0000010c , \blk00000003/sig0000010d , \blk00000003/sig0000010e , +\blk00000003/sig0000010f , \blk00000003/sig00000110 , \blk00000003/sig00000111 , \blk00000003/sig00000112 , \blk00000003/sig00000113 , +\blk00000003/sig00000114 , \blk00000003/sig00000115 , \blk00000003/sig00000116 , \blk00000003/sig00000117 , \blk00000003/sig00000118 , +\blk00000003/sig00000119 , \blk00000003/sig0000011a , \blk00000003/sig0000011b , \blk00000003/sig0000011c , \blk00000003/sig0000011d , +\blk00000003/sig0000011e , \blk00000003/sig0000011f , \blk00000003/sig00000120 , \blk00000003/sig00000121 , \blk00000003/sig00000122 , +\blk00000003/sig00000123 , \blk00000003/sig00000124 , \blk00000003/sig00000125 , \blk00000003/sig00000126 , \blk00000003/sig00000127 , +\blk00000003/sig00000128 , \blk00000003/sig00000129 , \blk00000003/sig0000012a , \blk00000003/sig0000012b , \blk00000003/sig0000012c , +\blk00000003/sig0000012d , \blk00000003/sig0000012e , \blk00000003/sig0000012f , \blk00000003/sig00000130 , \blk00000003/sig00000131 , +\blk00000003/sig00000132 , \blk00000003/sig00000133 , \blk00000003/sig00000134 , \blk00000003/sig00000135 , \blk00000003/sig00000136 , +\blk00000003/sig00000137 , \blk00000003/sig00000138 , \blk00000003/sig00000139 , \blk00000003/sig0000013a }), + .A({\blk00000003/sig0000013b , \blk00000003/sig0000013b , \blk00000003/sig0000013b , \blk00000003/sig0000013b , \blk00000003/sig0000013b , +\blk00000003/sig0000013b , \blk00000003/sig0000013b , \blk00000003/sig0000013c , \blk00000003/sig0000013d , \blk00000003/sig0000013e , +\blk00000003/sig0000013f , \blk00000003/sig00000140 , \blk00000003/sig00000141 , \blk00000003/sig00000142 , \blk00000003/sig00000143 , +\blk00000003/sig00000144 , \blk00000003/sig00000145 , \blk00000003/sig00000146 , \blk00000003/sig00000147 , \blk00000003/sig00000148 , +\blk00000003/sig00000149 , \blk00000003/sig0000014a , \blk00000003/sig0000014b , \blk00000003/sig0000014c , \blk00000003/sig0000014d , +\blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , \blk00000003/sig00000151 , \blk00000003/sig00000152 }), + .PCOUT({\NLW_blk00000003/blk00000015_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + MUXCY_D \blk00000003/blk00000014 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000c9 ), + .O(\blk00000003/sig000000c5 ), + .LO(\NLW_blk00000003/blk00000014_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000013 ( + .CI(\blk00000003/sig000000c5 ), + .DI(\blk00000003/sig000000c6 ), + .S(\blk00000003/sig000000c7 ), + .O(\blk00000003/sig000000bd ), + .LO(\blk00000003/sig000000c8 ) + ); + XORCY \blk00000003/blk00000012 ( + .CI(\blk00000003/sig000000c3 ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000000c4 ) + ); + MUXCY_D \blk00000003/blk00000011 ( + .CI(\blk00000003/sig000000c0 ), + .DI(\blk00000003/sig000000c1 ), + .S(\blk00000003/sig000000c2 ), + .O(\NLW_blk00000003/blk00000011_O_UNCONNECTED ), + .LO(\blk00000003/sig000000c3 ) + ); + MUXCY_D \blk00000003/blk00000010 ( + .CI(\blk00000003/sig000000bd ), + .DI(\blk00000003/sig000000be ), + .S(\blk00000003/sig000000bf ), + .O(\blk00000003/sig000000c0 ), + .LO(\NLW_blk00000003/blk00000010_LO_UNCONNECTED ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000f ( + .C(clk), + .D(\blk00000003/sig000000bb ), + .Q(\blk00000003/sig000000bc ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000e ( + .C(clk), + .D(\blk00000003/sig000000b9 ), + .Q(\blk00000003/sig000000ba ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000d ( + .C(clk), + .D(\blk00000003/sig000000b7 ), + .Q(\blk00000003/sig000000b8 ) + ); + XORCY \blk00000003/blk0000000c ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000000b5 ), + .O(\blk00000003/sig000000b6 ) + ); + MUXCY_D \blk00000003/blk0000000b ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000b4 ), + .S(\blk00000003/sig000000b5 ), + .O(\NLW_blk00000003/blk0000000b_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000000b_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000000a ( + .CI(\blk00000003/sig000000af ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000b3 ), + .O(\NLW_blk00000003/blk0000000a_O_UNCONNECTED ), + .LO(\blk00000003/sig000000b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000009 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000b1 ), + .R(sclr), + .Q(\blk00000003/sig000000b2 ) + ); + MUXCY_D \blk00000003/blk00000008 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000b0 ), + .O(\blk00000003/sig000000ae ), + .LO(\NLW_blk00000003/blk00000008_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000007 ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig000000ad ), + .S(nd), + .O(\blk00000003/sig000000af ), + .LO(\blk00000003/sig000000ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000006 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000ac ), + .R(sclr), + .Q(\blk00000003/sig000000ad ) + ); + VCC \blk00000003/blk00000005 ( + .P(NlwRenamedSig_OI_rfd) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000002c/blk0000008e ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk0000002c/sig00000c29 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000008d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000008d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c27 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000008c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000008c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c26 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000008b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c28 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000008a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c24 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000089 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c23 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000088 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c25 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000087 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c21 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000086 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c20 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000085 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c22 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000084 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1e ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000083 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000082 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1f ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000081 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1b ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000080 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1a ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1c ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c18 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c17 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c19 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c15 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c14 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000079 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c16 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000078 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c12 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000077 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c11 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000076 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c13 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000075 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0f ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000074 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0e ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000073 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c10 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000072 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0c ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000071 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0b ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000070 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c09 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c08 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0a ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c06 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c05 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c07 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000069 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c03 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000068 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c02 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000067 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c04 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000066 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000066_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c00 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000065 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000065_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bff ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000064 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000064_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c01 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000063 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000063_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000062 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000062_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000061 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000061_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfe ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000060 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000060_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfa ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000005f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000005f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bf9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000005e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000005e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000005d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c28 ), + .Q(\blk00000003/sig000001ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000005c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c27 ), + .Q(\blk00000003/sig000001eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c26 ), + .Q(\blk00000003/sig000001ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c25 ), + .Q(\blk00000003/sig000001ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c24 ), + .Q(\blk00000003/sig000001ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c23 ), + .Q(\blk00000003/sig000001ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c22 ), + .Q(\blk00000003/sig000001f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c21 ), + .Q(\blk00000003/sig000001f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c20 ), + .Q(\blk00000003/sig000001f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1f ), + .Q(\blk00000003/sig000001f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1e ), + .Q(\blk00000003/sig000001f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1d ), + .Q(\blk00000003/sig000001f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1c ), + .Q(\blk00000003/sig000001f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1b ), + .Q(\blk00000003/sig000001f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1a ), + .Q(\blk00000003/sig000001f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c19 ), + .Q(\blk00000003/sig000001f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c18 ), + .Q(\blk00000003/sig000001fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c17 ), + .Q(\blk00000003/sig000001fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c16 ), + .Q(\blk00000003/sig000001fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c15 ), + .Q(\blk00000003/sig000001fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c14 ), + .Q(\blk00000003/sig000001fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c13 ), + .Q(\blk00000003/sig000001ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c12 ), + .Q(\blk00000003/sig00000200 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c11 ), + .Q(\blk00000003/sig00000201 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c10 ), + .Q(\blk00000003/sig00000202 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0f ), + .Q(\blk00000003/sig00000203 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0e ), + .Q(\blk00000003/sig00000204 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0d ), + .Q(\blk00000003/sig00000205 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0c ), + .Q(\blk00000003/sig00000206 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0b ), + .Q(\blk00000003/sig00000207 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0a ), + .Q(\blk00000003/sig00000208 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c09 ), + .Q(\blk00000003/sig00000209 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c08 ), + .Q(\blk00000003/sig0000020a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c07 ), + .Q(\blk00000003/sig0000020b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c06 ), + .Q(\blk00000003/sig0000020c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c05 ), + .Q(\blk00000003/sig0000020d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c04 ), + .Q(\blk00000003/sig0000020e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c03 ), + .Q(\blk00000003/sig0000020f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c02 ), + .Q(\blk00000003/sig00000210 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000036 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c01 ), + .Q(\blk00000003/sig00000211 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000035 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c00 ), + .Q(\blk00000003/sig00000212 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000034 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bff ), + .Q(\blk00000003/sig00000213 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfe ), + .Q(\blk00000003/sig00000214 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfd ), + .Q(\blk00000003/sig00000215 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfc ), + .Q(\blk00000003/sig00000216 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfb ), + .Q(\blk00000003/sig00000217 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfa ), + .Q(\blk00000003/sig00000218 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bf9 ), + .Q(\blk00000003/sig00000219 ) + ); + GND \blk00000003/blk0000002c/blk0000002d ( + .G(\blk00000003/blk0000002c/sig00000bf8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000120/blk00000152 ( + .I0(ce), + .I1(\blk00000003/sig00000743 ), + .O(\blk00000003/blk00000120/sig00000c77 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000151 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b4 ), + .Q(\blk00000003/blk00000120/sig00000c75 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000151_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000150 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b5 ), + .Q(\blk00000003/blk00000120/sig00000c74 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000150_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014f ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b3 ), + .Q(\blk00000003/blk00000120/sig00000c76 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014e ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b7 ), + .Q(\blk00000003/blk00000120/sig00000c72 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014d ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b8 ), + .Q(\blk00000003/blk00000120/sig00000c71 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014c ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b6 ), + .Q(\blk00000003/blk00000120/sig00000c73 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014b ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005ba ), + .Q(\blk00000003/blk00000120/sig00000c6f ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014a ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005bb ), + .Q(\blk00000003/blk00000120/sig00000c6e ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000149 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b9 ), + .Q(\blk00000003/blk00000120/sig00000c70 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000149_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000148 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005bd ), + .Q(\blk00000003/blk00000120/sig00000c6c ), + .Q15(\NLW_blk00000003/blk00000120/blk00000148_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000147 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005be ), + .Q(\blk00000003/blk00000120/sig00000c6b ), + .Q15(\NLW_blk00000003/blk00000120/blk00000147_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000146 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005bc ), + .Q(\blk00000003/blk00000120/sig00000c6d ), + .Q15(\NLW_blk00000003/blk00000120/blk00000146_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000145 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c0 ), + .Q(\blk00000003/blk00000120/sig00000c69 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000145_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000144 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c1 ), + .Q(\blk00000003/blk00000120/sig00000c68 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000144_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000143 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005bf ), + .Q(\blk00000003/blk00000120/sig00000c6a ), + .Q15(\NLW_blk00000003/blk00000120/blk00000143_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000142 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c3 ), + .Q(\blk00000003/blk00000120/sig00000c66 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000142_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000141 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c4 ), + .Q(\blk00000003/blk00000120/sig00000c65 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000141_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000140 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c2 ), + .Q(\blk00000003/blk00000120/sig00000c67 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000140_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013f ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c6 ), + .Q(\blk00000003/blk00000120/sig00000c63 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013e ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c7 ), + .Q(\blk00000003/blk00000120/sig00000c62 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013d ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c5 ), + .Q(\blk00000003/blk00000120/sig00000c64 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013c ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c9 ), + .Q(\blk00000003/blk00000120/sig00000c60 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013b ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005ca ), + .Q(\blk00000003/blk00000120/sig00000c5f ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013a ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c8 ), + .Q(\blk00000003/blk00000120/sig00000c61 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000139 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c76 ), + .Q(\blk00000003/sig000003bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000138 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c75 ), + .Q(\blk00000003/sig000003bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000137 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c74 ), + .Q(\blk00000003/sig000003bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000136 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c73 ), + .Q(\blk00000003/sig000003be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000135 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c72 ), + .Q(\blk00000003/sig000003bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000134 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c71 ), + .Q(\blk00000003/sig000003c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000133 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c70 ), + .Q(\blk00000003/sig000003c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000132 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6f ), + .Q(\blk00000003/sig000003c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000131 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6e ), + .Q(\blk00000003/sig000003c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000130 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6d ), + .Q(\blk00000003/sig000003c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6c ), + .Q(\blk00000003/sig000003c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6b ), + .Q(\blk00000003/sig000003c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6a ), + .Q(\blk00000003/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c69 ), + .Q(\blk00000003/sig000003c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c68 ), + .Q(\blk00000003/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c67 ), + .Q(\blk00000003/sig000003ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c66 ), + .Q(\blk00000003/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c65 ), + .Q(\blk00000003/sig000003cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c64 ), + .Q(\blk00000003/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c63 ), + .Q(\blk00000003/sig000003ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c62 ), + .Q(\blk00000003/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c61 ), + .Q(\blk00000003/sig000003d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c60 ), + .Q(\blk00000003/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c5f ), + .Q(\blk00000003/sig000003d2 ) + ); + GND \blk00000003/blk00000120/blk00000121 ( + .G(\blk00000003/blk00000120/sig00000c5e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000153/blk00000185 ( + .I0(ce), + .I1(\blk00000003/sig00000745 ), + .O(\blk00000003/blk00000153/sig00000cc5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000184 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000763 ), + .Q(\blk00000003/blk00000153/sig00000cc3 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000184_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000183 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000764 ), + .Q(\blk00000003/blk00000153/sig00000cc2 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000183_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000182 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000762 ), + .Q(\blk00000003/blk00000153/sig00000cc4 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000182_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000181 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000766 ), + .Q(\blk00000003/blk00000153/sig00000cc0 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000181_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000180 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000767 ), + .Q(\blk00000003/blk00000153/sig00000cbf ), + .Q15(\NLW_blk00000003/blk00000153/blk00000180_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017f ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000765 ), + .Q(\blk00000003/blk00000153/sig00000cc1 ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017e ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000769 ), + .Q(\blk00000003/blk00000153/sig00000cbd ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017d ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076a ), + .Q(\blk00000003/blk00000153/sig00000cbc ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017c ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000768 ), + .Q(\blk00000003/blk00000153/sig00000cbe ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017b ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076c ), + .Q(\blk00000003/blk00000153/sig00000cba ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017a ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076d ), + .Q(\blk00000003/blk00000153/sig00000cb9 ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000179 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076b ), + .Q(\blk00000003/blk00000153/sig00000cbb ), + .Q15(\NLW_blk00000003/blk00000153/blk00000179_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000178 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076f ), + .Q(\blk00000003/blk00000153/sig00000cb7 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000178_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000177 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000770 ), + .Q(\blk00000003/blk00000153/sig00000cb6 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000177_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000176 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076e ), + .Q(\blk00000003/blk00000153/sig00000cb8 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000176_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000175 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000772 ), + .Q(\blk00000003/blk00000153/sig00000cb4 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000175_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000174 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000773 ), + .Q(\blk00000003/blk00000153/sig00000cb3 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000173 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000771 ), + .Q(\blk00000003/blk00000153/sig00000cb5 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000172 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000775 ), + .Q(\blk00000003/blk00000153/sig00000cb1 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000172_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000171 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000776 ), + .Q(\blk00000003/blk00000153/sig00000cb0 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000171_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000170 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000774 ), + .Q(\blk00000003/blk00000153/sig00000cb2 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000170_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016f ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000778 ), + .Q(\blk00000003/blk00000153/sig00000cae ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016e ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000779 ), + .Q(\blk00000003/blk00000153/sig00000cad ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016d ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000777 ), + .Q(\blk00000003/blk00000153/sig00000caf ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000016c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc4 ), + .Q(\blk00000003/sig000003d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000016b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc3 ), + .Q(\blk00000003/sig000003d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000016a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc2 ), + .Q(\blk00000003/sig000003d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000169 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc1 ), + .Q(\blk00000003/sig000003d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000168 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc0 ), + .Q(\blk00000003/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000167 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbf ), + .Q(\blk00000003/sig000003d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000166 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbe ), + .Q(\blk00000003/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000165 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbd ), + .Q(\blk00000003/sig000003da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000164 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbc ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbb ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cba ), + .Q(\blk00000003/sig000003dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000161 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb9 ), + .Q(\blk00000003/sig000003de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000160 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb8 ), + .Q(\blk00000003/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb7 ), + .Q(\blk00000003/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb6 ), + .Q(\blk00000003/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb5 ), + .Q(\blk00000003/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb4 ), + .Q(\blk00000003/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb3 ), + .Q(\blk00000003/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb2 ), + .Q(\blk00000003/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000159 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb1 ), + .Q(\blk00000003/sig000003e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000158 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb0 ), + .Q(\blk00000003/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000157 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000caf ), + .Q(\blk00000003/sig000003e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000156 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cae ), + .Q(\blk00000003/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000155 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cad ), + .Q(\blk00000003/sig000003ea ) + ); + GND \blk00000003/blk00000153/blk00000154 ( + .G(\blk00000003/blk00000153/sig00000cac ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000186/blk000001b8 ( + .I0(ce), + .I1(\blk00000003/sig00000743 ), + .O(\blk00000003/blk00000186/sig00000d13 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b7 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000704 ), + .Q(\blk00000003/blk00000186/sig00000d11 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b6 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000705 ), + .Q(\blk00000003/blk00000186/sig00000d10 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b5 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000703 ), + .Q(\blk00000003/blk00000186/sig00000d12 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b4 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000707 ), + .Q(\blk00000003/blk00000186/sig00000d0e ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b3 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000708 ), + .Q(\blk00000003/blk00000186/sig00000d0d ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b2 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000706 ), + .Q(\blk00000003/blk00000186/sig00000d0f ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b1 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070a ), + .Q(\blk00000003/blk00000186/sig00000d0b ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b0 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070b ), + .Q(\blk00000003/blk00000186/sig00000d0a ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001af ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000709 ), + .Q(\blk00000003/blk00000186/sig00000d0c ), + .Q15(\NLW_blk00000003/blk00000186/blk000001af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001ae ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070d ), + .Q(\blk00000003/blk00000186/sig00000d08 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001ad ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070e ), + .Q(\blk00000003/blk00000186/sig00000d07 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001ac ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070c ), + .Q(\blk00000003/blk00000186/sig00000d09 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001ab ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000710 ), + .Q(\blk00000003/blk00000186/sig00000d05 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001aa ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000711 ), + .Q(\blk00000003/blk00000186/sig00000d04 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a9 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070f ), + .Q(\blk00000003/blk00000186/sig00000d06 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a8 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000713 ), + .Q(\blk00000003/blk00000186/sig00000d02 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a7 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000714 ), + .Q(\blk00000003/blk00000186/sig00000d01 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a6 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000712 ), + .Q(\blk00000003/blk00000186/sig00000d03 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a5 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000716 ), + .Q(\blk00000003/blk00000186/sig00000cff ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a4 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000717 ), + .Q(\blk00000003/blk00000186/sig00000cfe ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a3 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000715 ), + .Q(\blk00000003/blk00000186/sig00000d00 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a2 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000719 ), + .Q(\blk00000003/blk00000186/sig00000cfc ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a1 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000071a ), + .Q(\blk00000003/blk00000186/sig00000cfb ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a0 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000718 ), + .Q(\blk00000003/blk00000186/sig00000cfd ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d12 ), + .Q(\blk00000003/sig0000041b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d11 ), + .Q(\blk00000003/sig0000041c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d10 ), + .Q(\blk00000003/sig0000041d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0f ), + .Q(\blk00000003/sig0000041e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0e ), + .Q(\blk00000003/sig0000041f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0d ), + .Q(\blk00000003/sig00000420 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000199 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0c ), + .Q(\blk00000003/sig00000421 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000198 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0b ), + .Q(\blk00000003/sig00000422 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000197 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0a ), + .Q(\blk00000003/sig00000423 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000196 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d09 ), + .Q(\blk00000003/sig00000424 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000195 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d08 ), + .Q(\blk00000003/sig00000425 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000194 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d07 ), + .Q(\blk00000003/sig00000426 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000193 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d06 ), + .Q(\blk00000003/sig00000427 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000192 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d05 ), + .Q(\blk00000003/sig00000428 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000191 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d04 ), + .Q(\blk00000003/sig00000429 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000190 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d03 ), + .Q(\blk00000003/sig0000042a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d02 ), + .Q(\blk00000003/sig0000042b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d01 ), + .Q(\blk00000003/sig0000042c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d00 ), + .Q(\blk00000003/sig0000042d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cff ), + .Q(\blk00000003/sig0000042e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cfe ), + .Q(\blk00000003/sig0000042f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cfd ), + .Q(\blk00000003/sig00000430 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000189 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cfc ), + .Q(\blk00000003/sig00000431 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000188 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cfb ), + .Q(\blk00000003/sig00000432 ) + ); + GND \blk00000003/blk00000186/blk00000187 ( + .G(\blk00000003/blk00000186/sig00000cfa ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001b9/blk000001eb ( + .I0(ce), + .I1(\blk00000003/sig00000745 ), + .O(\blk00000003/blk000001b9/sig00000d61 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001ea ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077b ), + .Q(\blk00000003/blk000001b9/sig00000d5f ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001ea_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e9 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077c ), + .Q(\blk00000003/blk000001b9/sig00000d5e ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e8 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077a ), + .Q(\blk00000003/blk000001b9/sig00000d60 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e7 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077e ), + .Q(\blk00000003/blk000001b9/sig00000d5c ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e6 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077f ), + .Q(\blk00000003/blk000001b9/sig00000d5b ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e5 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077d ), + .Q(\blk00000003/blk000001b9/sig00000d5d ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e4 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000781 ), + .Q(\blk00000003/blk000001b9/sig00000d59 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e3 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000782 ), + .Q(\blk00000003/blk000001b9/sig00000d58 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e2 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000780 ), + .Q(\blk00000003/blk000001b9/sig00000d5a ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e1 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000784 ), + .Q(\blk00000003/blk000001b9/sig00000d56 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e0 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000785 ), + .Q(\blk00000003/blk000001b9/sig00000d55 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001df ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000783 ), + .Q(\blk00000003/blk000001b9/sig00000d57 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001de ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000787 ), + .Q(\blk00000003/blk000001b9/sig00000d53 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001dd ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000788 ), + .Q(\blk00000003/blk000001b9/sig00000d52 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001dc ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000786 ), + .Q(\blk00000003/blk000001b9/sig00000d54 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001db ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078a ), + .Q(\blk00000003/blk000001b9/sig00000d50 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001da ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078b ), + .Q(\blk00000003/blk000001b9/sig00000d4f ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d9 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000789 ), + .Q(\blk00000003/blk000001b9/sig00000d51 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d8 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078d ), + .Q(\blk00000003/blk000001b9/sig00000d4d ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d7 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078e ), + .Q(\blk00000003/blk000001b9/sig00000d4c ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d6 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078c ), + .Q(\blk00000003/blk000001b9/sig00000d4e ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d5 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000790 ), + .Q(\blk00000003/blk000001b9/sig00000d4a ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d4 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000791 ), + .Q(\blk00000003/blk000001b9/sig00000d49 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d3 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078f ), + .Q(\blk00000003/blk000001b9/sig00000d4b ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d60 ), + .Q(\blk00000003/sig00000433 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5f ), + .Q(\blk00000003/sig00000434 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5e ), + .Q(\blk00000003/sig00000435 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5d ), + .Q(\blk00000003/sig00000436 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5c ), + .Q(\blk00000003/sig00000437 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5b ), + .Q(\blk00000003/sig00000438 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5a ), + .Q(\blk00000003/sig00000439 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d59 ), + .Q(\blk00000003/sig0000043a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d58 ), + .Q(\blk00000003/sig0000043b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d57 ), + .Q(\blk00000003/sig0000043c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d56 ), + .Q(\blk00000003/sig0000043d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d55 ), + .Q(\blk00000003/sig0000043e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d54 ), + .Q(\blk00000003/sig0000043f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d53 ), + .Q(\blk00000003/sig00000440 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d52 ), + .Q(\blk00000003/sig00000441 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d51 ), + .Q(\blk00000003/sig00000442 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d50 ), + .Q(\blk00000003/sig00000443 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4f ), + .Q(\blk00000003/sig00000444 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4e ), + .Q(\blk00000003/sig00000445 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4d ), + .Q(\blk00000003/sig00000446 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4c ), + .Q(\blk00000003/sig00000447 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4b ), + .Q(\blk00000003/sig00000448 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4a ), + .Q(\blk00000003/sig00000449 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d49 ), + .Q(\blk00000003/sig0000044a ) + ); + GND \blk00000003/blk000001b9/blk000001ba ( + .G(\blk00000003/blk000001b9/sig00000d48 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001ec/blk0000021e ( + .I0(ce), + .I1(\blk00000003/sig00000742 ), + .O(\blk00000003/blk000001ec/sig00000daf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000021d ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000542 ), + .Q(\blk00000003/blk000001ec/sig00000dad ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000021d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000021c ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000543 ), + .Q(\blk00000003/blk000001ec/sig00000dac ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000021c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000021b ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000541 ), + .Q(\blk00000003/blk000001ec/sig00000dae ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000021b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000021a ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000545 ), + .Q(\blk00000003/blk000001ec/sig00000daa ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000021a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000219 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000546 ), + .Q(\blk00000003/blk000001ec/sig00000da9 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000219_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000218 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000544 ), + .Q(\blk00000003/blk000001ec/sig00000dab ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000218_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000217 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000548 ), + .Q(\blk00000003/blk000001ec/sig00000da7 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000217_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000216 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000549 ), + .Q(\blk00000003/blk000001ec/sig00000da6 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000216_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000215 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000547 ), + .Q(\blk00000003/blk000001ec/sig00000da8 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000215_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000214 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054b ), + .Q(\blk00000003/blk000001ec/sig00000da4 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000214_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000213 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054c ), + .Q(\blk00000003/blk000001ec/sig00000da3 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000213_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000212 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054a ), + .Q(\blk00000003/blk000001ec/sig00000da5 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000212_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000211 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054e ), + .Q(\blk00000003/blk000001ec/sig00000da1 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000211_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000210 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054f ), + .Q(\blk00000003/blk000001ec/sig00000da0 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000210_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020f ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054d ), + .Q(\blk00000003/blk000001ec/sig00000da2 ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020e ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000551 ), + .Q(\blk00000003/blk000001ec/sig00000d9e ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020d ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000552 ), + .Q(\blk00000003/blk000001ec/sig00000d9d ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020c ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000550 ), + .Q(\blk00000003/blk000001ec/sig00000d9f ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020b ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000554 ), + .Q(\blk00000003/blk000001ec/sig00000d9b ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020a ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000555 ), + .Q(\blk00000003/blk000001ec/sig00000d9a ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000209 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000553 ), + .Q(\blk00000003/blk000001ec/sig00000d9c ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000209_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000208 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000557 ), + .Q(\blk00000003/blk000001ec/sig00000d98 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000208_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000207 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000558 ), + .Q(\blk00000003/blk000001ec/sig00000d97 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000207_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000206 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000556 ), + .Q(\blk00000003/blk000001ec/sig00000d99 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000206_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000205 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000dae ), + .Q(\blk00000003/sig000005b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000204 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000dad ), + .Q(\blk00000003/sig000005b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000203 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000dac ), + .Q(\blk00000003/sig000005b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000202 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000dab ), + .Q(\blk00000003/sig000005b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000201 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000daa ), + .Q(\blk00000003/sig000005b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000200 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da9 ), + .Q(\blk00000003/sig000005b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da8 ), + .Q(\blk00000003/sig000005b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da7 ), + .Q(\blk00000003/sig000005ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da6 ), + .Q(\blk00000003/sig000005bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da5 ), + .Q(\blk00000003/sig000005bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da4 ), + .Q(\blk00000003/sig000005bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da3 ), + .Q(\blk00000003/sig000005be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da2 ), + .Q(\blk00000003/sig000005bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da1 ), + .Q(\blk00000003/sig000005c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da0 ), + .Q(\blk00000003/sig000005c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9f ), + .Q(\blk00000003/sig000005c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9e ), + .Q(\blk00000003/sig000005c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9d ), + .Q(\blk00000003/sig000005c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9c ), + .Q(\blk00000003/sig000005c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9b ), + .Q(\blk00000003/sig000005c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9a ), + .Q(\blk00000003/sig000005c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d99 ), + .Q(\blk00000003/sig000005c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d98 ), + .Q(\blk00000003/sig000005c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d97 ), + .Q(\blk00000003/sig000005ca ) + ); + GND \blk00000003/blk000001ec/blk000001ed ( + .G(\blk00000003/blk000001ec/sig00000d96 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000021f/blk00000251 ( + .I0(ce), + .I1(\blk00000003/sig00000744 ), + .O(\blk00000003/blk0000021f/sig00000dfd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000250 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000793 ), + .Q(\blk00000003/blk0000021f/sig00000dfb ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000250_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024f ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000794 ), + .Q(\blk00000003/blk0000021f/sig00000dfa ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024e ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000792 ), + .Q(\blk00000003/blk0000021f/sig00000dfc ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024d ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000796 ), + .Q(\blk00000003/blk0000021f/sig00000df8 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024c ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000797 ), + .Q(\blk00000003/blk0000021f/sig00000df7 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024b ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000795 ), + .Q(\blk00000003/blk0000021f/sig00000df9 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024a ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000799 ), + .Q(\blk00000003/blk0000021f/sig00000df5 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000249 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079a ), + .Q(\blk00000003/blk0000021f/sig00000df4 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000249_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000248 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000798 ), + .Q(\blk00000003/blk0000021f/sig00000df6 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000248_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000247 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079c ), + .Q(\blk00000003/blk0000021f/sig00000df2 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000247_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000246 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079d ), + .Q(\blk00000003/blk0000021f/sig00000df1 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000245 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079b ), + .Q(\blk00000003/blk0000021f/sig00000df3 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000244 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079f ), + .Q(\blk00000003/blk0000021f/sig00000def ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000244_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000243 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a0 ), + .Q(\blk00000003/blk0000021f/sig00000dee ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000243_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000242 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079e ), + .Q(\blk00000003/blk0000021f/sig00000df0 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000242_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000241 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a2 ), + .Q(\blk00000003/blk0000021f/sig00000dec ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000241_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000240 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a3 ), + .Q(\blk00000003/blk0000021f/sig00000deb ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000240_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023f ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a1 ), + .Q(\blk00000003/blk0000021f/sig00000ded ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023e ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a5 ), + .Q(\blk00000003/blk0000021f/sig00000de9 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023d ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a6 ), + .Q(\blk00000003/blk0000021f/sig00000de8 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023c ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a4 ), + .Q(\blk00000003/blk0000021f/sig00000dea ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023b ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a8 ), + .Q(\blk00000003/blk0000021f/sig00000de6 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023a ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a9 ), + .Q(\blk00000003/blk0000021f/sig00000de5 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000239 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a7 ), + .Q(\blk00000003/blk0000021f/sig00000de7 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000239_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000238 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dfc ), + .Q(\blk00000003/sig000005cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000237 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dfb ), + .Q(\blk00000003/sig000005cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000236 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dfa ), + .Q(\blk00000003/sig000005cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000235 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df9 ), + .Q(\blk00000003/sig000005ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000234 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df8 ), + .Q(\blk00000003/sig000005cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000233 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df7 ), + .Q(\blk00000003/sig000005d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000232 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df6 ), + .Q(\blk00000003/sig000005d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000231 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df5 ), + .Q(\blk00000003/sig000005d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000230 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df4 ), + .Q(\blk00000003/sig000005d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df3 ), + .Q(\blk00000003/sig000005d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df2 ), + .Q(\blk00000003/sig000005d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df1 ), + .Q(\blk00000003/sig000005d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df0 ), + .Q(\blk00000003/sig000005d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000def ), + .Q(\blk00000003/sig000005d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dee ), + .Q(\blk00000003/sig000005d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000229 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000ded ), + .Q(\blk00000003/sig000005da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000228 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dec ), + .Q(\blk00000003/sig000005db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000227 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000deb ), + .Q(\blk00000003/sig000005dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000226 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dea ), + .Q(\blk00000003/sig000005dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000225 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de9 ), + .Q(\blk00000003/sig000005de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000224 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de8 ), + .Q(\blk00000003/sig000005df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000223 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de7 ), + .Q(\blk00000003/sig000005e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000222 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de6 ), + .Q(\blk00000003/sig000005e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000221 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de5 ), + .Q(\blk00000003/sig000005e2 ) + ); + GND \blk00000003/blk0000021f/blk00000220 ( + .G(\blk00000003/blk0000021f/sig00000de4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000252/blk00000284 ( + .I0(ce), + .I1(\blk00000003/sig00000742 ), + .O(\blk00000003/blk00000252/sig00000e4b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000283 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a4 ), + .Q(\blk00000003/blk00000252/sig00000e49 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000283_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000282 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a5 ), + .Q(\blk00000003/blk00000252/sig00000e48 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000282_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000281 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a3 ), + .Q(\blk00000003/blk00000252/sig00000e4a ), + .Q15(\NLW_blk00000003/blk00000252/blk00000281_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000280 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a7 ), + .Q(\blk00000003/blk00000252/sig00000e46 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000280_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027f ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a8 ), + .Q(\blk00000003/blk00000252/sig00000e45 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027e ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a6 ), + .Q(\blk00000003/blk00000252/sig00000e47 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027d ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006aa ), + .Q(\blk00000003/blk00000252/sig00000e43 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027c ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ab ), + .Q(\blk00000003/blk00000252/sig00000e42 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027b ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a9 ), + .Q(\blk00000003/blk00000252/sig00000e44 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027a ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ad ), + .Q(\blk00000003/blk00000252/sig00000e40 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000279 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ae ), + .Q(\blk00000003/blk00000252/sig00000e3f ), + .Q15(\NLW_blk00000003/blk00000252/blk00000279_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000278 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ac ), + .Q(\blk00000003/blk00000252/sig00000e41 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000278_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000277 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b0 ), + .Q(\blk00000003/blk00000252/sig00000e3d ), + .Q15(\NLW_blk00000003/blk00000252/blk00000277_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000276 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b1 ), + .Q(\blk00000003/blk00000252/sig00000e3c ), + .Q15(\NLW_blk00000003/blk00000252/blk00000276_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000275 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006af ), + .Q(\blk00000003/blk00000252/sig00000e3e ), + .Q15(\NLW_blk00000003/blk00000252/blk00000275_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000274 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b3 ), + .Q(\blk00000003/blk00000252/sig00000e3a ), + .Q15(\NLW_blk00000003/blk00000252/blk00000274_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000273 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b4 ), + .Q(\blk00000003/blk00000252/sig00000e39 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000273_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000272 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b2 ), + .Q(\blk00000003/blk00000252/sig00000e3b ), + .Q15(\NLW_blk00000003/blk00000252/blk00000272_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000271 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b6 ), + .Q(\blk00000003/blk00000252/sig00000e37 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000271_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000270 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b7 ), + .Q(\blk00000003/blk00000252/sig00000e36 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000270_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000026f ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b5 ), + .Q(\blk00000003/blk00000252/sig00000e38 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000026f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000026e ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b9 ), + .Q(\blk00000003/blk00000252/sig00000e34 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000026e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000026d ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ba ), + .Q(\blk00000003/blk00000252/sig00000e33 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000026d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000026c ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b8 ), + .Q(\blk00000003/blk00000252/sig00000e35 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000026c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000026b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e4a ), + .Q(\blk00000003/sig00000703 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000026a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e49 ), + .Q(\blk00000003/sig00000704 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000269 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e48 ), + .Q(\blk00000003/sig00000705 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000268 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e47 ), + .Q(\blk00000003/sig00000706 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000267 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e46 ), + .Q(\blk00000003/sig00000707 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000266 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e45 ), + .Q(\blk00000003/sig00000708 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000265 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e44 ), + .Q(\blk00000003/sig00000709 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000264 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e43 ), + .Q(\blk00000003/sig0000070a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000263 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e42 ), + .Q(\blk00000003/sig0000070b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000262 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e41 ), + .Q(\blk00000003/sig0000070c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000261 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e40 ), + .Q(\blk00000003/sig0000070d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000260 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3f ), + .Q(\blk00000003/sig0000070e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3e ), + .Q(\blk00000003/sig0000070f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3d ), + .Q(\blk00000003/sig00000710 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3c ), + .Q(\blk00000003/sig00000711 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3b ), + .Q(\blk00000003/sig00000712 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3a ), + .Q(\blk00000003/sig00000713 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e39 ), + .Q(\blk00000003/sig00000714 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e38 ), + .Q(\blk00000003/sig00000715 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e37 ), + .Q(\blk00000003/sig00000716 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e36 ), + .Q(\blk00000003/sig00000717 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000256 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e35 ), + .Q(\blk00000003/sig00000718 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000255 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e34 ), + .Q(\blk00000003/sig00000719 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000254 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e33 ), + .Q(\blk00000003/sig0000071a ) + ); + GND \blk00000003/blk00000252/blk00000253 ( + .G(\blk00000003/blk00000252/sig00000e32 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000285/blk000002b7 ( + .I0(ce), + .I1(\blk00000003/sig00000744 ), + .O(\blk00000003/blk00000285/sig00000e99 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b6 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ab ), + .Q(\blk00000003/blk00000285/sig00000e97 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b5 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ac ), + .Q(\blk00000003/blk00000285/sig00000e96 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b4 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007aa ), + .Q(\blk00000003/blk00000285/sig00000e98 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b3 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ae ), + .Q(\blk00000003/blk00000285/sig00000e94 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b2 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007af ), + .Q(\blk00000003/blk00000285/sig00000e93 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b1 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ad ), + .Q(\blk00000003/blk00000285/sig00000e95 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b0 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b1 ), + .Q(\blk00000003/blk00000285/sig00000e91 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002af ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b2 ), + .Q(\blk00000003/blk00000285/sig00000e90 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002ae ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b0 ), + .Q(\blk00000003/blk00000285/sig00000e92 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002ad ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b4 ), + .Q(\blk00000003/blk00000285/sig00000e8e ), + .Q15(\NLW_blk00000003/blk00000285/blk000002ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002ac ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b5 ), + .Q(\blk00000003/blk00000285/sig00000e8d ), + .Q15(\NLW_blk00000003/blk00000285/blk000002ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002ab ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b3 ), + .Q(\blk00000003/blk00000285/sig00000e8f ), + .Q15(\NLW_blk00000003/blk00000285/blk000002ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002aa ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b7 ), + .Q(\blk00000003/blk00000285/sig00000e8b ), + .Q15(\NLW_blk00000003/blk00000285/blk000002aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a9 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b8 ), + .Q(\blk00000003/blk00000285/sig00000e8a ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a8 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b6 ), + .Q(\blk00000003/blk00000285/sig00000e8c ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a7 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ba ), + .Q(\blk00000003/blk00000285/sig00000e88 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a6 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007bb ), + .Q(\blk00000003/blk00000285/sig00000e87 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a5 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b9 ), + .Q(\blk00000003/blk00000285/sig00000e89 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a4 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007bd ), + .Q(\blk00000003/blk00000285/sig00000e85 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a3 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007be ), + .Q(\blk00000003/blk00000285/sig00000e84 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a2 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007bc ), + .Q(\blk00000003/blk00000285/sig00000e86 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a1 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007c0 ), + .Q(\blk00000003/blk00000285/sig00000e82 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a0 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007c1 ), + .Q(\blk00000003/blk00000285/sig00000e81 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk0000029f ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007bf ), + .Q(\blk00000003/blk00000285/sig00000e83 ), + .Q15(\NLW_blk00000003/blk00000285/blk0000029f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e98 ), + .Q(\blk00000003/sig0000071b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e97 ), + .Q(\blk00000003/sig0000071c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e96 ), + .Q(\blk00000003/sig0000071d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e95 ), + .Q(\blk00000003/sig0000071e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e94 ), + .Q(\blk00000003/sig0000071f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000299 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e93 ), + .Q(\blk00000003/sig00000720 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000298 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e92 ), + .Q(\blk00000003/sig00000721 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000297 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e91 ), + .Q(\blk00000003/sig00000722 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000296 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e90 ), + .Q(\blk00000003/sig00000723 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000295 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8f ), + .Q(\blk00000003/sig00000724 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000294 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8e ), + .Q(\blk00000003/sig00000725 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000293 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8d ), + .Q(\blk00000003/sig00000726 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000292 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8c ), + .Q(\blk00000003/sig00000727 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000291 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8b ), + .Q(\blk00000003/sig00000728 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000290 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8a ), + .Q(\blk00000003/sig00000729 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e89 ), + .Q(\blk00000003/sig0000072a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e88 ), + .Q(\blk00000003/sig0000072b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e87 ), + .Q(\blk00000003/sig0000072c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e86 ), + .Q(\blk00000003/sig0000072d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e85 ), + .Q(\blk00000003/sig0000072e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e84 ), + .Q(\blk00000003/sig0000072f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000289 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e83 ), + .Q(\blk00000003/sig00000730 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000288 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e82 ), + .Q(\blk00000003/sig00000731 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000287 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e81 ), + .Q(\blk00000003/sig00000732 ) + ); + GND \blk00000003/blk00000285/blk00000286 ( + .G(\blk00000003/blk00000285/sig00000e80 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002b8/blk000002ea ( + .I0(ce), + .I1(\blk00000003/sig0000074e ), + .O(\blk00000003/blk000002b8/sig00000ee7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e9 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d0 ), + .Q(\blk00000003/blk000002b8/sig00000ee5 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e8 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d1 ), + .Q(\blk00000003/blk000002b8/sig00000ee4 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e7 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004cf ), + .Q(\blk00000003/blk000002b8/sig00000ee6 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e6 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d3 ), + .Q(\blk00000003/blk000002b8/sig00000ee2 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e5 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d4 ), + .Q(\blk00000003/blk000002b8/sig00000ee1 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e4 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d2 ), + .Q(\blk00000003/blk000002b8/sig00000ee3 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e3 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d6 ), + .Q(\blk00000003/blk000002b8/sig00000edf ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e2 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d7 ), + .Q(\blk00000003/blk000002b8/sig00000ede ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e1 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d5 ), + .Q(\blk00000003/blk000002b8/sig00000ee0 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e0 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d9 ), + .Q(\blk00000003/blk000002b8/sig00000edc ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002df ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004da ), + .Q(\blk00000003/blk000002b8/sig00000edb ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002de ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d8 ), + .Q(\blk00000003/blk000002b8/sig00000edd ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002dd ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004dc ), + .Q(\blk00000003/blk000002b8/sig00000ed9 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002dc ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004dd ), + .Q(\blk00000003/blk000002b8/sig00000ed8 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002db ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004db ), + .Q(\blk00000003/blk000002b8/sig00000eda ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002da ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004df ), + .Q(\blk00000003/blk000002b8/sig00000ed6 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d9 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e0 ), + .Q(\blk00000003/blk000002b8/sig00000ed5 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d8 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004de ), + .Q(\blk00000003/blk000002b8/sig00000ed7 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d7 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e2 ), + .Q(\blk00000003/blk000002b8/sig00000ed3 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d6 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e3 ), + .Q(\blk00000003/blk000002b8/sig00000ed2 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d5 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e1 ), + .Q(\blk00000003/blk000002b8/sig00000ed4 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d4 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e5 ), + .Q(\blk00000003/blk000002b8/sig00000ed0 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d3 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e6 ), + .Q(\blk00000003/blk000002b8/sig00000ecf ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d2 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e4 ), + .Q(\blk00000003/blk000002b8/sig00000ed1 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee6 ), + .Q(\blk00000003/sig00000541 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee5 ), + .Q(\blk00000003/sig00000542 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee4 ), + .Q(\blk00000003/sig00000543 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee3 ), + .Q(\blk00000003/sig00000544 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee2 ), + .Q(\blk00000003/sig00000545 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee1 ), + .Q(\blk00000003/sig00000546 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee0 ), + .Q(\blk00000003/sig00000547 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000edf ), + .Q(\blk00000003/sig00000548 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ede ), + .Q(\blk00000003/sig00000549 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000edd ), + .Q(\blk00000003/sig0000054a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000edc ), + .Q(\blk00000003/sig0000054b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000edb ), + .Q(\blk00000003/sig0000054c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000eda ), + .Q(\blk00000003/sig0000054d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed9 ), + .Q(\blk00000003/sig0000054e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed8 ), + .Q(\blk00000003/sig0000054f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed7 ), + .Q(\blk00000003/sig00000550 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed6 ), + .Q(\blk00000003/sig00000551 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed5 ), + .Q(\blk00000003/sig00000552 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed4 ), + .Q(\blk00000003/sig00000553 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed3 ), + .Q(\blk00000003/sig00000554 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed2 ), + .Q(\blk00000003/sig00000555 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed1 ), + .Q(\blk00000003/sig00000556 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed0 ), + .Q(\blk00000003/sig00000557 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ecf ), + .Q(\blk00000003/sig00000558 ) + ); + GND \blk00000003/blk000002b8/blk000002b9 ( + .G(\blk00000003/blk000002b8/sig00000ece ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002eb/blk0000031d ( + .I0(ce), + .I1(\blk00000003/sig0000074f ), + .O(\blk00000003/blk000002eb/sig00000f35 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000031c ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c3 ), + .Q(\blk00000003/blk000002eb/sig00000f33 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000031c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000031b ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c4 ), + .Q(\blk00000003/blk000002eb/sig00000f32 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000031b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000031a ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c2 ), + .Q(\blk00000003/blk000002eb/sig00000f34 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000031a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000319 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c6 ), + .Q(\blk00000003/blk000002eb/sig00000f30 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000319_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000318 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c7 ), + .Q(\blk00000003/blk000002eb/sig00000f2f ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000318_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000317 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c5 ), + .Q(\blk00000003/blk000002eb/sig00000f31 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000317_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000316 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c9 ), + .Q(\blk00000003/blk000002eb/sig00000f2d ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000316_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000315 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007ca ), + .Q(\blk00000003/blk000002eb/sig00000f2c ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000315_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000314 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c8 ), + .Q(\blk00000003/blk000002eb/sig00000f2e ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000314_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000313 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007cc ), + .Q(\blk00000003/blk000002eb/sig00000f2a ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000313_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000312 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007cd ), + .Q(\blk00000003/blk000002eb/sig00000f29 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000312_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000311 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007cb ), + .Q(\blk00000003/blk000002eb/sig00000f2b ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000311_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000310 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007cf ), + .Q(\blk00000003/blk000002eb/sig00000f27 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000310_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030f ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d0 ), + .Q(\blk00000003/blk000002eb/sig00000f26 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030e ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007ce ), + .Q(\blk00000003/blk000002eb/sig00000f28 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030d ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d2 ), + .Q(\blk00000003/blk000002eb/sig00000f24 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030c ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d3 ), + .Q(\blk00000003/blk000002eb/sig00000f23 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030b ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d1 ), + .Q(\blk00000003/blk000002eb/sig00000f25 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030a ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d5 ), + .Q(\blk00000003/blk000002eb/sig00000f21 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000309 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d6 ), + .Q(\blk00000003/blk000002eb/sig00000f20 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000309_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000308 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d4 ), + .Q(\blk00000003/blk000002eb/sig00000f22 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000308_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000307 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d8 ), + .Q(\blk00000003/blk000002eb/sig00000f1e ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000307_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000306 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d9 ), + .Q(\blk00000003/blk000002eb/sig00000f1d ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000306_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000305 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d7 ), + .Q(\blk00000003/blk000002eb/sig00000f1f ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000305_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000304 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f34 ), + .Q(\blk00000003/sig00000559 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000303 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f33 ), + .Q(\blk00000003/sig0000055a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000302 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f32 ), + .Q(\blk00000003/sig0000055b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000301 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f31 ), + .Q(\blk00000003/sig0000055c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000300 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f30 ), + .Q(\blk00000003/sig0000055d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2f ), + .Q(\blk00000003/sig0000055e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2e ), + .Q(\blk00000003/sig0000055f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2d ), + .Q(\blk00000003/sig00000560 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2c ), + .Q(\blk00000003/sig00000561 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2b ), + .Q(\blk00000003/sig00000562 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2a ), + .Q(\blk00000003/sig00000563 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f29 ), + .Q(\blk00000003/sig00000564 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f28 ), + .Q(\blk00000003/sig00000565 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f27 ), + .Q(\blk00000003/sig00000566 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f26 ), + .Q(\blk00000003/sig00000567 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f25 ), + .Q(\blk00000003/sig00000568 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f24 ), + .Q(\blk00000003/sig00000569 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f23 ), + .Q(\blk00000003/sig0000056a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f22 ), + .Q(\blk00000003/sig0000056b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f21 ), + .Q(\blk00000003/sig0000056c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f20 ), + .Q(\blk00000003/sig0000056d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f1f ), + .Q(\blk00000003/sig0000056e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f1e ), + .Q(\blk00000003/sig0000056f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f1d ), + .Q(\blk00000003/sig00000570 ) + ); + GND \blk00000003/blk000002eb/blk000002ec ( + .G(\blk00000003/blk000002eb/sig00000f1c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000031e/blk00000350 ( + .I0(ce), + .I1(\blk00000003/sig0000074e ), + .O(\blk00000003/blk0000031e/sig00000f83 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034f ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000644 ), + .Q(\blk00000003/blk0000031e/sig00000f81 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034e ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000645 ), + .Q(\blk00000003/blk0000031e/sig00000f80 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034d ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000643 ), + .Q(\blk00000003/blk0000031e/sig00000f82 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034c ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000647 ), + .Q(\blk00000003/blk0000031e/sig00000f7e ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034b ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000648 ), + .Q(\blk00000003/blk0000031e/sig00000f7d ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034a ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000646 ), + .Q(\blk00000003/blk0000031e/sig00000f7f ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000349 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064a ), + .Q(\blk00000003/blk0000031e/sig00000f7b ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000349_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000348 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064b ), + .Q(\blk00000003/blk0000031e/sig00000f7a ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000348_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000347 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000649 ), + .Q(\blk00000003/blk0000031e/sig00000f7c ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000347_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000346 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064d ), + .Q(\blk00000003/blk0000031e/sig00000f78 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000346_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000345 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064e ), + .Q(\blk00000003/blk0000031e/sig00000f77 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000345_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000344 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064c ), + .Q(\blk00000003/blk0000031e/sig00000f79 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000344_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000343 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000650 ), + .Q(\blk00000003/blk0000031e/sig00000f75 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000343_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000342 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000651 ), + .Q(\blk00000003/blk0000031e/sig00000f74 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000342_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000341 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064f ), + .Q(\blk00000003/blk0000031e/sig00000f76 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000341_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000340 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000653 ), + .Q(\blk00000003/blk0000031e/sig00000f72 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000340_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033f ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000654 ), + .Q(\blk00000003/blk0000031e/sig00000f71 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033e ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000652 ), + .Q(\blk00000003/blk0000031e/sig00000f73 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033d ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000656 ), + .Q(\blk00000003/blk0000031e/sig00000f6f ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033c ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000657 ), + .Q(\blk00000003/blk0000031e/sig00000f6e ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033b ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000655 ), + .Q(\blk00000003/blk0000031e/sig00000f70 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033a ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000659 ), + .Q(\blk00000003/blk0000031e/sig00000f6c ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000339 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000065a ), + .Q(\blk00000003/blk0000031e/sig00000f6b ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000339_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000338 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000658 ), + .Q(\blk00000003/blk0000031e/sig00000f6d ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000338_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000337 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f82 ), + .Q(\blk00000003/sig000006a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000336 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f81 ), + .Q(\blk00000003/sig000006a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000335 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f80 ), + .Q(\blk00000003/sig000006a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000334 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7f ), + .Q(\blk00000003/sig000006a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000333 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7e ), + .Q(\blk00000003/sig000006a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000332 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7d ), + .Q(\blk00000003/sig000006a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000331 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7c ), + .Q(\blk00000003/sig000006a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000330 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7b ), + .Q(\blk00000003/sig000006aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7a ), + .Q(\blk00000003/sig000006ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f79 ), + .Q(\blk00000003/sig000006ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f78 ), + .Q(\blk00000003/sig000006ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f77 ), + .Q(\blk00000003/sig000006ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f76 ), + .Q(\blk00000003/sig000006af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f75 ), + .Q(\blk00000003/sig000006b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000329 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f74 ), + .Q(\blk00000003/sig000006b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000328 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f73 ), + .Q(\blk00000003/sig000006b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000327 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f72 ), + .Q(\blk00000003/sig000006b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000326 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f71 ), + .Q(\blk00000003/sig000006b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000325 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f70 ), + .Q(\blk00000003/sig000006b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000324 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6f ), + .Q(\blk00000003/sig000006b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000323 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6e ), + .Q(\blk00000003/sig000006b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000322 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6d ), + .Q(\blk00000003/sig000006b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000321 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6c ), + .Q(\blk00000003/sig000006b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000320 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6b ), + .Q(\blk00000003/sig000006ba ) + ); + GND \blk00000003/blk0000031e/blk0000031f ( + .G(\blk00000003/blk0000031e/sig00000f6a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000351/blk00000383 ( + .I0(ce), + .I1(\blk00000003/sig0000074f ), + .O(\blk00000003/blk00000351/sig00000fd1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000382 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007db ), + .Q(\blk00000003/blk00000351/sig00000fcf ), + .Q15(\NLW_blk00000003/blk00000351/blk00000382_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000381 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007dc ), + .Q(\blk00000003/blk00000351/sig00000fce ), + .Q15(\NLW_blk00000003/blk00000351/blk00000381_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000380 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007da ), + .Q(\blk00000003/blk00000351/sig00000fd0 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000380_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037f ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007de ), + .Q(\blk00000003/blk00000351/sig00000fcc ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037e ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007df ), + .Q(\blk00000003/blk00000351/sig00000fcb ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037d ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007dd ), + .Q(\blk00000003/blk00000351/sig00000fcd ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037c ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e1 ), + .Q(\blk00000003/blk00000351/sig00000fc9 ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037b ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e2 ), + .Q(\blk00000003/blk00000351/sig00000fc8 ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037a ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e0 ), + .Q(\blk00000003/blk00000351/sig00000fca ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000379 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e4 ), + .Q(\blk00000003/blk00000351/sig00000fc6 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000379_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000378 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e5 ), + .Q(\blk00000003/blk00000351/sig00000fc5 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000378_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000377 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e3 ), + .Q(\blk00000003/blk00000351/sig00000fc7 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000377_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000376 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e7 ), + .Q(\blk00000003/blk00000351/sig00000fc3 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000376_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000375 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e8 ), + .Q(\blk00000003/blk00000351/sig00000fc2 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000375_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000374 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e6 ), + .Q(\blk00000003/blk00000351/sig00000fc4 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000374_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000373 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ea ), + .Q(\blk00000003/blk00000351/sig00000fc0 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000373_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000372 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007eb ), + .Q(\blk00000003/blk00000351/sig00000fbf ), + .Q15(\NLW_blk00000003/blk00000351/blk00000372_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000371 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e9 ), + .Q(\blk00000003/blk00000351/sig00000fc1 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000371_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000370 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ed ), + .Q(\blk00000003/blk00000351/sig00000fbd ), + .Q15(\NLW_blk00000003/blk00000351/blk00000370_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036f ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ee ), + .Q(\blk00000003/blk00000351/sig00000fbc ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036e ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ec ), + .Q(\blk00000003/blk00000351/sig00000fbe ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036d ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007f0 ), + .Q(\blk00000003/blk00000351/sig00000fba ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036c ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007f1 ), + .Q(\blk00000003/blk00000351/sig00000fb9 ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036b ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ef ), + .Q(\blk00000003/blk00000351/sig00000fbb ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000036a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fd0 ), + .Q(\blk00000003/sig000006bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000369 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fcf ), + .Q(\blk00000003/sig000006bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000368 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fce ), + .Q(\blk00000003/sig000006bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000367 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fcd ), + .Q(\blk00000003/sig000006be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000366 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fcc ), + .Q(\blk00000003/sig000006bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000365 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fcb ), + .Q(\blk00000003/sig000006c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000364 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fca ), + .Q(\blk00000003/sig000006c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000363 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc9 ), + .Q(\blk00000003/sig000006c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000362 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc8 ), + .Q(\blk00000003/sig000006c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000361 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc7 ), + .Q(\blk00000003/sig000006c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000360 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc6 ), + .Q(\blk00000003/sig000006c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc5 ), + .Q(\blk00000003/sig000006c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc4 ), + .Q(\blk00000003/sig000006c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc3 ), + .Q(\blk00000003/sig000006c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc2 ), + .Q(\blk00000003/sig000006c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc1 ), + .Q(\blk00000003/sig000006ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc0 ), + .Q(\blk00000003/sig000006cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000359 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbf ), + .Q(\blk00000003/sig000006cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000358 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbe ), + .Q(\blk00000003/sig000006cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000357 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbd ), + .Q(\blk00000003/sig000006ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000356 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbc ), + .Q(\blk00000003/sig000006cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000355 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbb ), + .Q(\blk00000003/sig000006d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000354 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fba ), + .Q(\blk00000003/sig000006d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000353 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fb9 ), + .Q(\blk00000003/sig000006d2 ) + ); + GND \blk00000003/blk00000351/blk00000352 ( + .G(\blk00000003/blk00000351/sig00000fb8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000384/blk000003b6 ( + .I0(ce), + .I1(\blk00000003/sig00000755 ), + .O(\blk00000003/blk00000384/sig0000101f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b5 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000045e ), + .Q(\blk00000003/blk00000384/sig0000101d ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b4 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000045f ), + .Q(\blk00000003/blk00000384/sig0000101c ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b3 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000045d ), + .Q(\blk00000003/blk00000384/sig0000101e ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b2 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000461 ), + .Q(\blk00000003/blk00000384/sig0000101a ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b1 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000462 ), + .Q(\blk00000003/blk00000384/sig00001019 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b0 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000460 ), + .Q(\blk00000003/blk00000384/sig0000101b ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003af ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000464 ), + .Q(\blk00000003/blk00000384/sig00001017 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003ae ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000465 ), + .Q(\blk00000003/blk00000384/sig00001016 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003ad ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000463 ), + .Q(\blk00000003/blk00000384/sig00001018 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003ac ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000467 ), + .Q(\blk00000003/blk00000384/sig00001014 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003ab ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000468 ), + .Q(\blk00000003/blk00000384/sig00001013 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003aa ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000466 ), + .Q(\blk00000003/blk00000384/sig00001015 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a9 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046a ), + .Q(\blk00000003/blk00000384/sig00001011 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a8 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046b ), + .Q(\blk00000003/blk00000384/sig00001010 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a7 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000469 ), + .Q(\blk00000003/blk00000384/sig00001012 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a6 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046d ), + .Q(\blk00000003/blk00000384/sig0000100e ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a5 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046e ), + .Q(\blk00000003/blk00000384/sig0000100d ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a4 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046c ), + .Q(\blk00000003/blk00000384/sig0000100f ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a3 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000470 ), + .Q(\blk00000003/blk00000384/sig0000100b ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a2 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000471 ), + .Q(\blk00000003/blk00000384/sig0000100a ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a1 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046f ), + .Q(\blk00000003/blk00000384/sig0000100c ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a0 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000473 ), + .Q(\blk00000003/blk00000384/sig00001008 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk0000039f ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000474 ), + .Q(\blk00000003/blk00000384/sig00001007 ), + .Q15(\NLW_blk00000003/blk00000384/blk0000039f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk0000039e ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000472 ), + .Q(\blk00000003/blk00000384/sig00001009 ), + .Q15(\NLW_blk00000003/blk00000384/blk0000039e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000039d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101e ), + .Q(\blk00000003/sig000004cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000039c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101d ), + .Q(\blk00000003/sig000004d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000039b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101c ), + .Q(\blk00000003/sig000004d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000039a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101b ), + .Q(\blk00000003/sig000004d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000399 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101a ), + .Q(\blk00000003/sig000004d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000398 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001019 ), + .Q(\blk00000003/sig000004d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000397 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001018 ), + .Q(\blk00000003/sig000004d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000396 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001017 ), + .Q(\blk00000003/sig000004d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000395 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001016 ), + .Q(\blk00000003/sig000004d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000394 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001015 ), + .Q(\blk00000003/sig000004d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000393 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001014 ), + .Q(\blk00000003/sig000004d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000392 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001013 ), + .Q(\blk00000003/sig000004da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000391 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001012 ), + .Q(\blk00000003/sig000004db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000390 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001011 ), + .Q(\blk00000003/sig000004dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001010 ), + .Q(\blk00000003/sig000004dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100f ), + .Q(\blk00000003/sig000004de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100e ), + .Q(\blk00000003/sig000004df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100d ), + .Q(\blk00000003/sig000004e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100c ), + .Q(\blk00000003/sig000004e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100b ), + .Q(\blk00000003/sig000004e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000389 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100a ), + .Q(\blk00000003/sig000004e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000388 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001009 ), + .Q(\blk00000003/sig000004e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000387 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001008 ), + .Q(\blk00000003/sig000004e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000386 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001007 ), + .Q(\blk00000003/sig000004e6 ) + ); + GND \blk00000003/blk00000384/blk00000385 ( + .G(\blk00000003/blk00000384/sig00001006 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003b7/blk000003e9 ( + .I0(ce), + .I1(\blk00000003/sig00000754 ), + .O(\blk00000003/blk000003b7/sig0000106d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e8 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f3 ), + .Q(\blk00000003/blk000003b7/sig0000106b ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e7 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f4 ), + .Q(\blk00000003/blk000003b7/sig0000106a ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e6 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f2 ), + .Q(\blk00000003/blk000003b7/sig0000106c ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e5 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f6 ), + .Q(\blk00000003/blk000003b7/sig00001068 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e4 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f7 ), + .Q(\blk00000003/blk000003b7/sig00001067 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e3 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f5 ), + .Q(\blk00000003/blk000003b7/sig00001069 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e2 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f9 ), + .Q(\blk00000003/blk000003b7/sig00001065 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e1 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fa ), + .Q(\blk00000003/blk000003b7/sig00001064 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e0 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f8 ), + .Q(\blk00000003/blk000003b7/sig00001066 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003df ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fc ), + .Q(\blk00000003/blk000003b7/sig00001062 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003de ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fd ), + .Q(\blk00000003/blk000003b7/sig00001061 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003dd ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fb ), + .Q(\blk00000003/blk000003b7/sig00001063 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003dc ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007ff ), + .Q(\blk00000003/blk000003b7/sig0000105f ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003db ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000800 ), + .Q(\blk00000003/blk000003b7/sig0000105e ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003da ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fe ), + .Q(\blk00000003/blk000003b7/sig00001060 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d9 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000802 ), + .Q(\blk00000003/blk000003b7/sig0000105c ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d8 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000803 ), + .Q(\blk00000003/blk000003b7/sig0000105b ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d7 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000801 ), + .Q(\blk00000003/blk000003b7/sig0000105d ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d6 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000805 ), + .Q(\blk00000003/blk000003b7/sig00001059 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d5 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000806 ), + .Q(\blk00000003/blk000003b7/sig00001058 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d4 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000804 ), + .Q(\blk00000003/blk000003b7/sig0000105a ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d3 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000808 ), + .Q(\blk00000003/blk000003b7/sig00001056 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d2 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000809 ), + .Q(\blk00000003/blk000003b7/sig00001055 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d1 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000807 ), + .Q(\blk00000003/blk000003b7/sig00001057 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000106c ), + .Q(\blk00000003/sig000004e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000106b ), + .Q(\blk00000003/sig000004e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000106a ), + .Q(\blk00000003/sig000004e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001069 ), + .Q(\blk00000003/sig000004ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001068 ), + .Q(\blk00000003/sig000004eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001067 ), + .Q(\blk00000003/sig000004ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001066 ), + .Q(\blk00000003/sig000004ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001065 ), + .Q(\blk00000003/sig000004ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001064 ), + .Q(\blk00000003/sig000004ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001063 ), + .Q(\blk00000003/sig000004f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001062 ), + .Q(\blk00000003/sig000004f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001061 ), + .Q(\blk00000003/sig000004f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001060 ), + .Q(\blk00000003/sig000004f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105f ), + .Q(\blk00000003/sig000004f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105e ), + .Q(\blk00000003/sig000004f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105d ), + .Q(\blk00000003/sig000004f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105c ), + .Q(\blk00000003/sig000004f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105b ), + .Q(\blk00000003/sig000004f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105a ), + .Q(\blk00000003/sig000004f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001059 ), + .Q(\blk00000003/sig000004fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001058 ), + .Q(\blk00000003/sig000004fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001057 ), + .Q(\blk00000003/sig000004fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001056 ), + .Q(\blk00000003/sig000004fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001055 ), + .Q(\blk00000003/sig000004fe ) + ); + GND \blk00000003/blk000003b7/blk000003b8 ( + .G(\blk00000003/blk000003b7/sig00001054 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003ea/blk0000041c ( + .I0(ce), + .I1(\blk00000003/sig00000755 ), + .O(\blk00000003/blk000003ea/sig000010bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000041b ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e4 ), + .Q(\blk00000003/blk000003ea/sig000010b9 ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000041b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000041a ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e5 ), + .Q(\blk00000003/blk000003ea/sig000010b8 ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000041a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000419 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e3 ), + .Q(\blk00000003/blk000003ea/sig000010ba ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000419_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000418 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e7 ), + .Q(\blk00000003/blk000003ea/sig000010b6 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000418_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000417 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e8 ), + .Q(\blk00000003/blk000003ea/sig000010b5 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000417_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000416 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e6 ), + .Q(\blk00000003/blk000003ea/sig000010b7 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000416_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000415 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ea ), + .Q(\blk00000003/blk000003ea/sig000010b3 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000415_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000414 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005eb ), + .Q(\blk00000003/blk000003ea/sig000010b2 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000414_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000413 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e9 ), + .Q(\blk00000003/blk000003ea/sig000010b4 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000413_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000412 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ed ), + .Q(\blk00000003/blk000003ea/sig000010b0 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000412_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000411 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ee ), + .Q(\blk00000003/blk000003ea/sig000010af ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000411_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000410 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ec ), + .Q(\blk00000003/blk000003ea/sig000010b1 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000410_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040f ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f0 ), + .Q(\blk00000003/blk000003ea/sig000010ad ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040e ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f1 ), + .Q(\blk00000003/blk000003ea/sig000010ac ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040d ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ef ), + .Q(\blk00000003/blk000003ea/sig000010ae ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040c ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f3 ), + .Q(\blk00000003/blk000003ea/sig000010aa ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040b ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f4 ), + .Q(\blk00000003/blk000003ea/sig000010a9 ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040a ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f2 ), + .Q(\blk00000003/blk000003ea/sig000010ab ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000409 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f6 ), + .Q(\blk00000003/blk000003ea/sig000010a7 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000409_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000408 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f7 ), + .Q(\blk00000003/blk000003ea/sig000010a6 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000408_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000407 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f5 ), + .Q(\blk00000003/blk000003ea/sig000010a8 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000407_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000406 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f9 ), + .Q(\blk00000003/blk000003ea/sig000010a4 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000406_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000405 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005fa ), + .Q(\blk00000003/blk000003ea/sig000010a3 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000405_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000404 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f8 ), + .Q(\blk00000003/blk000003ea/sig000010a5 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000404_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk00000403 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ba ), + .Q(\blk00000003/sig00000643 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk00000402 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b9 ), + .Q(\blk00000003/sig00000644 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk00000401 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b8 ), + .Q(\blk00000003/sig00000645 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk00000400 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b7 ), + .Q(\blk00000003/sig00000646 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b6 ), + .Q(\blk00000003/sig00000647 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b5 ), + .Q(\blk00000003/sig00000648 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b4 ), + .Q(\blk00000003/sig00000649 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b3 ), + .Q(\blk00000003/sig0000064a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b2 ), + .Q(\blk00000003/sig0000064b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b1 ), + .Q(\blk00000003/sig0000064c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b0 ), + .Q(\blk00000003/sig0000064d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010af ), + .Q(\blk00000003/sig0000064e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ae ), + .Q(\blk00000003/sig0000064f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ad ), + .Q(\blk00000003/sig00000650 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ac ), + .Q(\blk00000003/sig00000651 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ab ), + .Q(\blk00000003/sig00000652 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010aa ), + .Q(\blk00000003/sig00000653 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a9 ), + .Q(\blk00000003/sig00000654 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a8 ), + .Q(\blk00000003/sig00000655 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a7 ), + .Q(\blk00000003/sig00000656 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a6 ), + .Q(\blk00000003/sig00000657 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a5 ), + .Q(\blk00000003/sig00000658 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a4 ), + .Q(\blk00000003/sig00000659 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a3 ), + .Q(\blk00000003/sig0000065a ) + ); + GND \blk00000003/blk000003ea/blk000003eb ( + .G(\blk00000003/blk000003ea/sig000010a2 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000041d/blk0000044f ( + .I0(ce), + .I1(\blk00000003/sig00000754 ), + .O(\blk00000003/blk0000041d/sig00001109 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044e ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080b ), + .Q(\blk00000003/blk0000041d/sig00001107 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044d ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080c ), + .Q(\blk00000003/blk0000041d/sig00001106 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044c ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080a ), + .Q(\blk00000003/blk0000041d/sig00001108 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044b ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080e ), + .Q(\blk00000003/blk0000041d/sig00001104 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044a ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080f ), + .Q(\blk00000003/blk0000041d/sig00001103 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000449 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080d ), + .Q(\blk00000003/blk0000041d/sig00001105 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000449_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000448 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000811 ), + .Q(\blk00000003/blk0000041d/sig00001101 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000448_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000447 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000812 ), + .Q(\blk00000003/blk0000041d/sig00001100 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000447_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000446 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000810 ), + .Q(\blk00000003/blk0000041d/sig00001102 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000446_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000445 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000814 ), + .Q(\blk00000003/blk0000041d/sig000010fe ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000445_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000444 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000815 ), + .Q(\blk00000003/blk0000041d/sig000010fd ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000444_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000443 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000813 ), + .Q(\blk00000003/blk0000041d/sig000010ff ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000443_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000442 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000817 ), + .Q(\blk00000003/blk0000041d/sig000010fb ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000442_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000441 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000818 ), + .Q(\blk00000003/blk0000041d/sig000010fa ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000441_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000440 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000816 ), + .Q(\blk00000003/blk0000041d/sig000010fc ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000440_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043f ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081a ), + .Q(\blk00000003/blk0000041d/sig000010f8 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043e ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081b ), + .Q(\blk00000003/blk0000041d/sig000010f7 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043d ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000819 ), + .Q(\blk00000003/blk0000041d/sig000010f9 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043c ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081d ), + .Q(\blk00000003/blk0000041d/sig000010f5 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043b ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081e ), + .Q(\blk00000003/blk0000041d/sig000010f4 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043a ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081c ), + .Q(\blk00000003/blk0000041d/sig000010f6 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000439 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000820 ), + .Q(\blk00000003/blk0000041d/sig000010f2 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000439_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000438 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000821 ), + .Q(\blk00000003/blk0000041d/sig000010f1 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000438_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000437 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081f ), + .Q(\blk00000003/blk0000041d/sig000010f3 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000437_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000436 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001108 ), + .Q(\blk00000003/sig0000065b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000435 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001107 ), + .Q(\blk00000003/sig0000065c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000434 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001106 ), + .Q(\blk00000003/sig0000065d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000433 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001105 ), + .Q(\blk00000003/sig0000065e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000432 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001104 ), + .Q(\blk00000003/sig0000065f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000431 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001103 ), + .Q(\blk00000003/sig00000660 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000430 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001102 ), + .Q(\blk00000003/sig00000661 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001101 ), + .Q(\blk00000003/sig00000662 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001100 ), + .Q(\blk00000003/sig00000663 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010ff ), + .Q(\blk00000003/sig00000664 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fe ), + .Q(\blk00000003/sig00000665 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fd ), + .Q(\blk00000003/sig00000666 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fc ), + .Q(\blk00000003/sig00000667 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000429 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fb ), + .Q(\blk00000003/sig00000668 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000428 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fa ), + .Q(\blk00000003/sig00000669 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000427 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f9 ), + .Q(\blk00000003/sig0000066a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000426 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f8 ), + .Q(\blk00000003/sig0000066b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000425 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f7 ), + .Q(\blk00000003/sig0000066c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000424 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f6 ), + .Q(\blk00000003/sig0000066d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000423 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f5 ), + .Q(\blk00000003/sig0000066e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000422 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f4 ), + .Q(\blk00000003/sig0000066f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000421 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f3 ), + .Q(\blk00000003/sig00000670 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000420 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f2 ), + .Q(\blk00000003/sig00000671 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000041f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f1 ), + .Q(\blk00000003/sig00000672 ) + ); + GND \blk00000003/blk0000041d/blk0000041e ( + .G(\blk00000003/blk0000041d/sig000010f0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000450/blk00000482 ( + .I0(ce), + .I1(\blk00000003/sig0000075d ), + .O(\blk00000003/blk00000450/sig00001157 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000481 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002ba ), + .Q(\blk00000003/blk00000450/sig00001155 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000481_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000480 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/blk00000450/sig00001154 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000480_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047f ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002b9 ), + .Q(\blk00000003/blk00000450/sig00001156 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047e ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/blk00000450/sig00001152 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047d ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/blk00000450/sig00001151 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047c ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/blk00000450/sig00001153 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047b ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/blk00000450/sig0000114f ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047a ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/blk00000450/sig0000114e ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000479 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/blk00000450/sig00001150 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000479_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000478 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/blk00000450/sig0000114c ), + .Q15(\NLW_blk00000003/blk00000450/blk00000478_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000477 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/blk00000450/sig0000114b ), + .Q15(\NLW_blk00000003/blk00000450/blk00000477_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000476 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/blk00000450/sig0000114d ), + .Q15(\NLW_blk00000003/blk00000450/blk00000476_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000475 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/blk00000450/sig00001149 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000475_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000474 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/blk00000450/sig00001148 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000474_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000473 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/blk00000450/sig0000114a ), + .Q15(\NLW_blk00000003/blk00000450/blk00000473_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000472 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/blk00000450/sig00001146 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000472_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000471 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/blk00000450/sig00001145 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000471_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000470 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/blk00000450/sig00001147 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000470_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046f ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/blk00000450/sig00001143 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046e ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/blk00000450/sig00001142 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046d ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/blk00000450/sig00001144 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046c ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/blk00000450/sig00001140 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046b ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/blk00000450/sig0000113f ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046a ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/blk00000450/sig00001141 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000469 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001156 ), + .Q(\blk00000003/sig0000045d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000468 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001155 ), + .Q(\blk00000003/sig0000045e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000467 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001154 ), + .Q(\blk00000003/sig0000045f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000466 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001153 ), + .Q(\blk00000003/sig00000460 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000465 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001152 ), + .Q(\blk00000003/sig00000461 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000464 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001151 ), + .Q(\blk00000003/sig00000462 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000463 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001150 ), + .Q(\blk00000003/sig00000463 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000462 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114f ), + .Q(\blk00000003/sig00000464 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000461 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114e ), + .Q(\blk00000003/sig00000465 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000460 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114d ), + .Q(\blk00000003/sig00000466 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114c ), + .Q(\blk00000003/sig00000467 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114b ), + .Q(\blk00000003/sig00000468 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114a ), + .Q(\blk00000003/sig00000469 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001149 ), + .Q(\blk00000003/sig0000046a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001148 ), + .Q(\blk00000003/sig0000046b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001147 ), + .Q(\blk00000003/sig0000046c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000459 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001146 ), + .Q(\blk00000003/sig0000046d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000458 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001145 ), + .Q(\blk00000003/sig0000046e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000457 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001144 ), + .Q(\blk00000003/sig0000046f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000456 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001143 ), + .Q(\blk00000003/sig00000470 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000455 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001142 ), + .Q(\blk00000003/sig00000471 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000454 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001141 ), + .Q(\blk00000003/sig00000472 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000453 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001140 ), + .Q(\blk00000003/sig00000473 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000452 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000113f ), + .Q(\blk00000003/sig00000474 ) + ); + GND \blk00000003/blk00000450/blk00000451 ( + .G(\blk00000003/blk00000450/sig0000113e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000483/blk000004b5 ( + .I0(ce), + .I1(\blk00000003/sig0000075a ), + .O(\blk00000003/blk00000483/sig000011a5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b4 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000823 ), + .Q(\blk00000003/blk00000483/sig000011a3 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b3 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000824 ), + .Q(\blk00000003/blk00000483/sig000011a2 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b2 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000822 ), + .Q(\blk00000003/blk00000483/sig000011a4 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b1 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000826 ), + .Q(\blk00000003/blk00000483/sig000011a0 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b0 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000827 ), + .Q(\blk00000003/blk00000483/sig0000119f ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004af ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000825 ), + .Q(\blk00000003/blk00000483/sig000011a1 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004ae ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000829 ), + .Q(\blk00000003/blk00000483/sig0000119d ), + .Q15(\NLW_blk00000003/blk00000483/blk000004ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004ad ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082a ), + .Q(\blk00000003/blk00000483/sig0000119c ), + .Q15(\NLW_blk00000003/blk00000483/blk000004ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004ac ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000828 ), + .Q(\blk00000003/blk00000483/sig0000119e ), + .Q15(\NLW_blk00000003/blk00000483/blk000004ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004ab ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082c ), + .Q(\blk00000003/blk00000483/sig0000119a ), + .Q15(\NLW_blk00000003/blk00000483/blk000004ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004aa ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082d ), + .Q(\blk00000003/blk00000483/sig00001199 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a9 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082b ), + .Q(\blk00000003/blk00000483/sig0000119b ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a8 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082f ), + .Q(\blk00000003/blk00000483/sig00001197 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a7 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000830 ), + .Q(\blk00000003/blk00000483/sig00001196 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a6 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082e ), + .Q(\blk00000003/blk00000483/sig00001198 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a5 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000832 ), + .Q(\blk00000003/blk00000483/sig00001194 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a4 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000833 ), + .Q(\blk00000003/blk00000483/sig00001193 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a3 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000831 ), + .Q(\blk00000003/blk00000483/sig00001195 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a2 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000835 ), + .Q(\blk00000003/blk00000483/sig00001191 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a1 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000836 ), + .Q(\blk00000003/blk00000483/sig00001190 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a0 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000834 ), + .Q(\blk00000003/blk00000483/sig00001192 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk0000049f ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000838 ), + .Q(\blk00000003/blk00000483/sig0000118e ), + .Q15(\NLW_blk00000003/blk00000483/blk0000049f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk0000049e ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000839 ), + .Q(\blk00000003/blk00000483/sig0000118d ), + .Q15(\NLW_blk00000003/blk00000483/blk0000049e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk0000049d ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000837 ), + .Q(\blk00000003/blk00000483/sig0000118f ), + .Q15(\NLW_blk00000003/blk00000483/blk0000049d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000049c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a4 ), + .Q(\blk00000003/sig00000475 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000049b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a3 ), + .Q(\blk00000003/sig00000476 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000049a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a2 ), + .Q(\blk00000003/sig00000477 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000499 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a1 ), + .Q(\blk00000003/sig00000478 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000498 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a0 ), + .Q(\blk00000003/sig00000479 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000497 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119f ), + .Q(\blk00000003/sig0000047a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000496 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119e ), + .Q(\blk00000003/sig0000047b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000495 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119d ), + .Q(\blk00000003/sig0000047c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000494 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119c ), + .Q(\blk00000003/sig0000047d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000493 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119b ), + .Q(\blk00000003/sig0000047e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000492 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119a ), + .Q(\blk00000003/sig0000047f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000491 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001199 ), + .Q(\blk00000003/sig00000480 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000490 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001198 ), + .Q(\blk00000003/sig00000481 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001197 ), + .Q(\blk00000003/sig00000482 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001196 ), + .Q(\blk00000003/sig00000483 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001195 ), + .Q(\blk00000003/sig00000484 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001194 ), + .Q(\blk00000003/sig00000485 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001193 ), + .Q(\blk00000003/sig00000486 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001192 ), + .Q(\blk00000003/sig00000487 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000489 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001191 ), + .Q(\blk00000003/sig00000488 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000488 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001190 ), + .Q(\blk00000003/sig00000489 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000487 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000118f ), + .Q(\blk00000003/sig0000048a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000486 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000118e ), + .Q(\blk00000003/sig0000048b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000485 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000118d ), + .Q(\blk00000003/sig0000048c ) + ); + GND \blk00000003/blk00000483/blk00000484 ( + .G(\blk00000003/blk00000483/sig0000118c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004b6/blk000004e8 ( + .I0(ce), + .I1(\blk00000003/sig0000075d ), + .O(\blk00000003/blk000004b6/sig000011f3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e7 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031a ), + .Q(\blk00000003/blk000004b6/sig000011f1 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e6 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031b ), + .Q(\blk00000003/blk000004b6/sig000011f0 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e5 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000319 ), + .Q(\blk00000003/blk000004b6/sig000011f2 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e4 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031d ), + .Q(\blk00000003/blk000004b6/sig000011ee ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e3 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031e ), + .Q(\blk00000003/blk000004b6/sig000011ed ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e2 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031c ), + .Q(\blk00000003/blk000004b6/sig000011ef ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e1 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000320 ), + .Q(\blk00000003/blk000004b6/sig000011eb ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e0 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000321 ), + .Q(\blk00000003/blk000004b6/sig000011ea ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004df ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031f ), + .Q(\blk00000003/blk000004b6/sig000011ec ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004de ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000323 ), + .Q(\blk00000003/blk000004b6/sig000011e8 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004dd ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000324 ), + .Q(\blk00000003/blk000004b6/sig000011e7 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004dc ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000322 ), + .Q(\blk00000003/blk000004b6/sig000011e9 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004db ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000326 ), + .Q(\blk00000003/blk000004b6/sig000011e5 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004da ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000327 ), + .Q(\blk00000003/blk000004b6/sig000011e4 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d9 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000325 ), + .Q(\blk00000003/blk000004b6/sig000011e6 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d8 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000329 ), + .Q(\blk00000003/blk000004b6/sig000011e2 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d7 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032a ), + .Q(\blk00000003/blk000004b6/sig000011e1 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d6 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000328 ), + .Q(\blk00000003/blk000004b6/sig000011e3 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d5 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032c ), + .Q(\blk00000003/blk000004b6/sig000011df ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d4 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032d ), + .Q(\blk00000003/blk000004b6/sig000011de ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d3 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032b ), + .Q(\blk00000003/blk000004b6/sig000011e0 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d2 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032f ), + .Q(\blk00000003/blk000004b6/sig000011dc ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d1 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000330 ), + .Q(\blk00000003/blk000004b6/sig000011db ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d0 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032e ), + .Q(\blk00000003/blk000004b6/sig000011dd ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011f2 ), + .Q(\blk00000003/sig000005e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011f1 ), + .Q(\blk00000003/sig000005e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011f0 ), + .Q(\blk00000003/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ef ), + .Q(\blk00000003/sig000005e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ee ), + .Q(\blk00000003/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ed ), + .Q(\blk00000003/sig000005e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ec ), + .Q(\blk00000003/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011eb ), + .Q(\blk00000003/sig000005ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ea ), + .Q(\blk00000003/sig000005eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e9 ), + .Q(\blk00000003/sig000005ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e8 ), + .Q(\blk00000003/sig000005ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e7 ), + .Q(\blk00000003/sig000005ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e6 ), + .Q(\blk00000003/sig000005ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e5 ), + .Q(\blk00000003/sig000005f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e4 ), + .Q(\blk00000003/sig000005f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e3 ), + .Q(\blk00000003/sig000005f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e2 ), + .Q(\blk00000003/sig000005f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e1 ), + .Q(\blk00000003/sig000005f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e0 ), + .Q(\blk00000003/sig000005f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011df ), + .Q(\blk00000003/sig000005f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011de ), + .Q(\blk00000003/sig000005f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011dd ), + .Q(\blk00000003/sig000005f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011dc ), + .Q(\blk00000003/sig000005f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011db ), + .Q(\blk00000003/sig000005fa ) + ); + GND \blk00000003/blk000004b6/blk000004b7 ( + .G(\blk00000003/blk000004b6/sig000011da ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004e9/blk0000051b ( + .I0(ce), + .I1(\blk00000003/sig0000075a ), + .O(\blk00000003/blk000004e9/sig00001241 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000051a ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083b ), + .Q(\blk00000003/blk000004e9/sig0000123f ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000051a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000519 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083c ), + .Q(\blk00000003/blk000004e9/sig0000123e ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000519_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000518 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083a ), + .Q(\blk00000003/blk000004e9/sig00001240 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000518_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000517 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083e ), + .Q(\blk00000003/blk000004e9/sig0000123c ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000517_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000516 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083f ), + .Q(\blk00000003/blk000004e9/sig0000123b ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000516_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000515 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083d ), + .Q(\blk00000003/blk000004e9/sig0000123d ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000515_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000514 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000841 ), + .Q(\blk00000003/blk000004e9/sig00001239 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000514_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000513 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000842 ), + .Q(\blk00000003/blk000004e9/sig00001238 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000513_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000512 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000840 ), + .Q(\blk00000003/blk000004e9/sig0000123a ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000512_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000511 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000844 ), + .Q(\blk00000003/blk000004e9/sig00001236 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000511_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000510 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000845 ), + .Q(\blk00000003/blk000004e9/sig00001235 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000510_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050f ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000843 ), + .Q(\blk00000003/blk000004e9/sig00001237 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050e ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000847 ), + .Q(\blk00000003/blk000004e9/sig00001233 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050d ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000848 ), + .Q(\blk00000003/blk000004e9/sig00001232 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050c ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000846 ), + .Q(\blk00000003/blk000004e9/sig00001234 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050b ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084a ), + .Q(\blk00000003/blk000004e9/sig00001230 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050a ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084b ), + .Q(\blk00000003/blk000004e9/sig0000122f ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000509 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000849 ), + .Q(\blk00000003/blk000004e9/sig00001231 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000509_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000508 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084d ), + .Q(\blk00000003/blk000004e9/sig0000122d ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000508_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000507 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084e ), + .Q(\blk00000003/blk000004e9/sig0000122c ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000507_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000506 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084c ), + .Q(\blk00000003/blk000004e9/sig0000122e ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000506_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000505 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000850 ), + .Q(\blk00000003/blk000004e9/sig0000122a ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000505_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000504 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000851 ), + .Q(\blk00000003/blk000004e9/sig00001229 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000504_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000503 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084f ), + .Q(\blk00000003/blk000004e9/sig0000122b ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000503_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk00000502 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001240 ), + .Q(\blk00000003/sig000005fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk00000501 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123f ), + .Q(\blk00000003/sig000005fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk00000500 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123e ), + .Q(\blk00000003/sig000005fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123d ), + .Q(\blk00000003/sig000005fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123c ), + .Q(\blk00000003/sig000005ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123b ), + .Q(\blk00000003/sig00000600 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123a ), + .Q(\blk00000003/sig00000601 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001239 ), + .Q(\blk00000003/sig00000602 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001238 ), + .Q(\blk00000003/sig00000603 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001237 ), + .Q(\blk00000003/sig00000604 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001236 ), + .Q(\blk00000003/sig00000605 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001235 ), + .Q(\blk00000003/sig00000606 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001234 ), + .Q(\blk00000003/sig00000607 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001233 ), + .Q(\blk00000003/sig00000608 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001232 ), + .Q(\blk00000003/sig00000609 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001231 ), + .Q(\blk00000003/sig0000060a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001230 ), + .Q(\blk00000003/sig0000060b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122f ), + .Q(\blk00000003/sig0000060c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122e ), + .Q(\blk00000003/sig0000060d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122d ), + .Q(\blk00000003/sig0000060e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122c ), + .Q(\blk00000003/sig0000060f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122b ), + .Q(\blk00000003/sig00000610 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122a ), + .Q(\blk00000003/sig00000611 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001229 ), + .Q(\blk00000003/sig00000612 ) + ); + GND \blk00000003/blk000004e9/blk000004ea ( + .G(\blk00000003/blk000004e9/sig00001228 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000051c/blk0000054e ( + .I0(ce), + .I1(\blk00000003/sig00000761 ), + .O(\blk00000003/blk0000051c/sig0000128f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000054d ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000853 ), + .Q(\blk00000003/blk0000051c/sig0000128d ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000054d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000054c ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000854 ), + .Q(\blk00000003/blk0000051c/sig0000128c ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000054c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000054b ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000852 ), + .Q(\blk00000003/blk0000051c/sig0000128e ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000054b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000054a ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000856 ), + .Q(\blk00000003/blk0000051c/sig0000128a ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000054a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000549 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000857 ), + .Q(\blk00000003/blk0000051c/sig00001289 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000549_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000548 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000855 ), + .Q(\blk00000003/blk0000051c/sig0000128b ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000548_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000547 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000859 ), + .Q(\blk00000003/blk0000051c/sig00001287 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000547_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000546 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085a ), + .Q(\blk00000003/blk0000051c/sig00001286 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000546_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000545 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000858 ), + .Q(\blk00000003/blk0000051c/sig00001288 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000545_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000544 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085c ), + .Q(\blk00000003/blk0000051c/sig00001284 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000544_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000543 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085d ), + .Q(\blk00000003/blk0000051c/sig00001283 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000543_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000542 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085b ), + .Q(\blk00000003/blk0000051c/sig00001285 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000542_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000541 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085f ), + .Q(\blk00000003/blk0000051c/sig00001281 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000541_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000540 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000860 ), + .Q(\blk00000003/blk0000051c/sig00001280 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000540_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053f ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085e ), + .Q(\blk00000003/blk0000051c/sig00001282 ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053e ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000862 ), + .Q(\blk00000003/blk0000051c/sig0000127e ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053d ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000863 ), + .Q(\blk00000003/blk0000051c/sig0000127d ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053c ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000861 ), + .Q(\blk00000003/blk0000051c/sig0000127f ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053b ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000865 ), + .Q(\blk00000003/blk0000051c/sig0000127b ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053a ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000866 ), + .Q(\blk00000003/blk0000051c/sig0000127a ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000539 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000864 ), + .Q(\blk00000003/blk0000051c/sig0000127c ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000539_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000538 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000868 ), + .Q(\blk00000003/blk0000051c/sig00001278 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000538_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000537 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000869 ), + .Q(\blk00000003/blk0000051c/sig00001277 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000537_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000536 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000867 ), + .Q(\blk00000003/blk0000051c/sig00001279 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000536_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000535 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128e ), + .Q(\blk00000003/sig000002b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000534 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128d ), + .Q(\blk00000003/sig000002ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128c ), + .Q(\blk00000003/sig000002bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000532 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128b ), + .Q(\blk00000003/sig000002bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000531 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128a ), + .Q(\blk00000003/sig000002bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000530 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001289 ), + .Q(\blk00000003/sig000002be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001288 ), + .Q(\blk00000003/sig000002bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001287 ), + .Q(\blk00000003/sig000002c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001286 ), + .Q(\blk00000003/sig000002c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001285 ), + .Q(\blk00000003/sig000002c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001284 ), + .Q(\blk00000003/sig000002c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001283 ), + .Q(\blk00000003/sig000002c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000529 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001282 ), + .Q(\blk00000003/sig000002c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000528 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001281 ), + .Q(\blk00000003/sig000002c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000527 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001280 ), + .Q(\blk00000003/sig000002c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000526 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127f ), + .Q(\blk00000003/sig000002c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000525 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127e ), + .Q(\blk00000003/sig000002c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000524 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127d ), + .Q(\blk00000003/sig000002ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000523 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127c ), + .Q(\blk00000003/sig000002cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000522 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127b ), + .Q(\blk00000003/sig000002cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000521 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127a ), + .Q(\blk00000003/sig000002cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000520 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001279 ), + .Q(\blk00000003/sig000002ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000051f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001278 ), + .Q(\blk00000003/sig000002cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000051e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001277 ), + .Q(\blk00000003/sig000002d0 ) + ); + GND \blk00000003/blk0000051c/blk0000051d ( + .G(\blk00000003/blk0000051c/sig00001276 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000054f/blk00000581 ( + .I0(ce), + .I1(\blk00000003/sig00000760 ), + .O(\blk00000003/blk0000054f/sig000012dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000580 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086b ), + .Q(\blk00000003/blk0000054f/sig000012db ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000580_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057f ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086c ), + .Q(\blk00000003/blk0000054f/sig000012da ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057e ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086a ), + .Q(\blk00000003/blk0000054f/sig000012dc ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057d ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086e ), + .Q(\blk00000003/blk0000054f/sig000012d8 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057c ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086f ), + .Q(\blk00000003/blk0000054f/sig000012d7 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057b ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086d ), + .Q(\blk00000003/blk0000054f/sig000012d9 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057a ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000871 ), + .Q(\blk00000003/blk0000054f/sig000012d5 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000579 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000872 ), + .Q(\blk00000003/blk0000054f/sig000012d4 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000579_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000578 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000870 ), + .Q(\blk00000003/blk0000054f/sig000012d6 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000578_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000577 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000874 ), + .Q(\blk00000003/blk0000054f/sig000012d2 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000577_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000576 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000875 ), + .Q(\blk00000003/blk0000054f/sig000012d1 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000576_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000575 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000873 ), + .Q(\blk00000003/blk0000054f/sig000012d3 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000575_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000574 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000877 ), + .Q(\blk00000003/blk0000054f/sig000012cf ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000574_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000573 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000878 ), + .Q(\blk00000003/blk0000054f/sig000012ce ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000573_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000572 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000876 ), + .Q(\blk00000003/blk0000054f/sig000012d0 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000572_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000571 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087a ), + .Q(\blk00000003/blk0000054f/sig000012cc ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000571_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000570 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087b ), + .Q(\blk00000003/blk0000054f/sig000012cb ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000570_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056f ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000879 ), + .Q(\blk00000003/blk0000054f/sig000012cd ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056e ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087d ), + .Q(\blk00000003/blk0000054f/sig000012c9 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056d ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087e ), + .Q(\blk00000003/blk0000054f/sig000012c8 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056c ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087c ), + .Q(\blk00000003/blk0000054f/sig000012ca ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056b ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000880 ), + .Q(\blk00000003/blk0000054f/sig000012c6 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056a ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000881 ), + .Q(\blk00000003/blk0000054f/sig000012c5 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000569 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087f ), + .Q(\blk00000003/blk0000054f/sig000012c7 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000569_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000568 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012dc ), + .Q(\blk00000003/sig000002d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000567 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012db ), + .Q(\blk00000003/sig000002d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000566 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012da ), + .Q(\blk00000003/sig000002d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000565 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d9 ), + .Q(\blk00000003/sig000002d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000564 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d8 ), + .Q(\blk00000003/sig000002d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000563 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d7 ), + .Q(\blk00000003/sig000002d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000562 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d6 ), + .Q(\blk00000003/sig000002d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000561 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d5 ), + .Q(\blk00000003/sig000002d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000560 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d4 ), + .Q(\blk00000003/sig000002d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d3 ), + .Q(\blk00000003/sig000002da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d2 ), + .Q(\blk00000003/sig000002db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d1 ), + .Q(\blk00000003/sig000002dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d0 ), + .Q(\blk00000003/sig000002dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012cf ), + .Q(\blk00000003/sig000002de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012ce ), + .Q(\blk00000003/sig000002df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000559 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012cd ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000558 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012cc ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000557 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012cb ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000556 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012ca ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000555 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c9 ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000554 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c8 ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000553 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c7 ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000552 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c6 ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000551 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c5 ), + .Q(\blk00000003/sig000002e8 ) + ); + GND \blk00000003/blk0000054f/blk00000550 ( + .G(\blk00000003/blk0000054f/sig000012c4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000582/blk000005b4 ( + .I0(ce), + .I1(\blk00000003/sig00000761 ), + .O(\blk00000003/blk00000582/sig0000132b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005b3 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000883 ), + .Q(\blk00000003/blk00000582/sig00001329 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005b2 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000884 ), + .Q(\blk00000003/blk00000582/sig00001328 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005b1 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000882 ), + .Q(\blk00000003/blk00000582/sig0000132a ), + .Q15(\NLW_blk00000003/blk00000582/blk000005b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005b0 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000886 ), + .Q(\blk00000003/blk00000582/sig00001326 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005af ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000887 ), + .Q(\blk00000003/blk00000582/sig00001325 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005ae ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000885 ), + .Q(\blk00000003/blk00000582/sig00001327 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005ad ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000889 ), + .Q(\blk00000003/blk00000582/sig00001323 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005ac ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088a ), + .Q(\blk00000003/blk00000582/sig00001322 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005ab ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000888 ), + .Q(\blk00000003/blk00000582/sig00001324 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005aa ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088c ), + .Q(\blk00000003/blk00000582/sig00001320 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a9 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088d ), + .Q(\blk00000003/blk00000582/sig0000131f ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a8 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088b ), + .Q(\blk00000003/blk00000582/sig00001321 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a7 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088f ), + .Q(\blk00000003/blk00000582/sig0000131d ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a6 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000890 ), + .Q(\blk00000003/blk00000582/sig0000131c ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a5 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088e ), + .Q(\blk00000003/blk00000582/sig0000131e ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a4 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000892 ), + .Q(\blk00000003/blk00000582/sig0000131a ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a3 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000893 ), + .Q(\blk00000003/blk00000582/sig00001319 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a2 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000891 ), + .Q(\blk00000003/blk00000582/sig0000131b ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a1 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000895 ), + .Q(\blk00000003/blk00000582/sig00001317 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a0 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000896 ), + .Q(\blk00000003/blk00000582/sig00001316 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk0000059f ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000894 ), + .Q(\blk00000003/blk00000582/sig00001318 ), + .Q15(\NLW_blk00000003/blk00000582/blk0000059f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk0000059e ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000898 ), + .Q(\blk00000003/blk00000582/sig00001314 ), + .Q15(\NLW_blk00000003/blk00000582/blk0000059e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk0000059d ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000899 ), + .Q(\blk00000003/blk00000582/sig00001313 ), + .Q15(\NLW_blk00000003/blk00000582/blk0000059d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk0000059c ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000897 ), + .Q(\blk00000003/blk00000582/sig00001315 ), + .Q15(\NLW_blk00000003/blk00000582/blk0000059c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000059b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000132a ), + .Q(\blk00000003/sig00000319 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000059a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001329 ), + .Q(\blk00000003/sig0000031a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000599 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001328 ), + .Q(\blk00000003/sig0000031b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000598 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001327 ), + .Q(\blk00000003/sig0000031c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000597 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001326 ), + .Q(\blk00000003/sig0000031d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000596 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001325 ), + .Q(\blk00000003/sig0000031e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000595 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001324 ), + .Q(\blk00000003/sig0000031f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000594 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001323 ), + .Q(\blk00000003/sig00000320 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000593 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001322 ), + .Q(\blk00000003/sig00000321 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000592 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001321 ), + .Q(\blk00000003/sig00000322 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000591 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001320 ), + .Q(\blk00000003/sig00000323 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000590 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131f ), + .Q(\blk00000003/sig00000324 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131e ), + .Q(\blk00000003/sig00000325 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131d ), + .Q(\blk00000003/sig00000326 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131c ), + .Q(\blk00000003/sig00000327 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131b ), + .Q(\blk00000003/sig00000328 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131a ), + .Q(\blk00000003/sig00000329 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001319 ), + .Q(\blk00000003/sig0000032a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000589 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001318 ), + .Q(\blk00000003/sig0000032b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000588 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001317 ), + .Q(\blk00000003/sig0000032c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000587 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001316 ), + .Q(\blk00000003/sig0000032d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000586 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001315 ), + .Q(\blk00000003/sig0000032e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000585 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001314 ), + .Q(\blk00000003/sig0000032f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000584 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001313 ), + .Q(\blk00000003/sig00000330 ) + ); + GND \blk00000003/blk00000582/blk00000583 ( + .G(\blk00000003/blk00000582/sig00001312 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b5/blk000005e7 ( + .I0(ce), + .I1(\blk00000003/sig00000760 ), + .O(\blk00000003/blk000005b5/sig00001379 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e6 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089b ), + .Q(\blk00000003/blk000005b5/sig00001377 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e5 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089c ), + .Q(\blk00000003/blk000005b5/sig00001376 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e4 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089a ), + .Q(\blk00000003/blk000005b5/sig00001378 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e3 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089e ), + .Q(\blk00000003/blk000005b5/sig00001374 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e2 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089f ), + .Q(\blk00000003/blk000005b5/sig00001373 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e1 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089d ), + .Q(\blk00000003/blk000005b5/sig00001375 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e0 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a1 ), + .Q(\blk00000003/blk000005b5/sig00001371 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005df ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a2 ), + .Q(\blk00000003/blk000005b5/sig00001370 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005de ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a0 ), + .Q(\blk00000003/blk000005b5/sig00001372 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005dd ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a4 ), + .Q(\blk00000003/blk000005b5/sig0000136e ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005dc ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a5 ), + .Q(\blk00000003/blk000005b5/sig0000136d ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005db ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a3 ), + .Q(\blk00000003/blk000005b5/sig0000136f ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005da ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a7 ), + .Q(\blk00000003/blk000005b5/sig0000136b ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d9 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a8 ), + .Q(\blk00000003/blk000005b5/sig0000136a ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d8 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a6 ), + .Q(\blk00000003/blk000005b5/sig0000136c ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d7 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008aa ), + .Q(\blk00000003/blk000005b5/sig00001368 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d6 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008ab ), + .Q(\blk00000003/blk000005b5/sig00001367 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d5 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a9 ), + .Q(\blk00000003/blk000005b5/sig00001369 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d4 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008ad ), + .Q(\blk00000003/blk000005b5/sig00001365 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d3 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008ae ), + .Q(\blk00000003/blk000005b5/sig00001364 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d2 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008ac ), + .Q(\blk00000003/blk000005b5/sig00001366 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d1 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008b0 ), + .Q(\blk00000003/blk000005b5/sig00001362 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d0 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008b1 ), + .Q(\blk00000003/blk000005b5/sig00001361 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005cf ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008af ), + .Q(\blk00000003/blk000005b5/sig00001363 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005cf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001378 ), + .Q(\blk00000003/sig00000331 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001377 ), + .Q(\blk00000003/sig00000332 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001376 ), + .Q(\blk00000003/sig00000333 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001375 ), + .Q(\blk00000003/sig00000334 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001374 ), + .Q(\blk00000003/sig00000335 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001373 ), + .Q(\blk00000003/sig00000336 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001372 ), + .Q(\blk00000003/sig00000337 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001371 ), + .Q(\blk00000003/sig00000338 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001370 ), + .Q(\blk00000003/sig00000339 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136f ), + .Q(\blk00000003/sig0000033a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136e ), + .Q(\blk00000003/sig0000033b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136d ), + .Q(\blk00000003/sig0000033c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136c ), + .Q(\blk00000003/sig0000033d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136b ), + .Q(\blk00000003/sig0000033e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136a ), + .Q(\blk00000003/sig0000033f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001369 ), + .Q(\blk00000003/sig00000340 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001368 ), + .Q(\blk00000003/sig00000341 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001367 ), + .Q(\blk00000003/sig00000342 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001366 ), + .Q(\blk00000003/sig00000343 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001365 ), + .Q(\blk00000003/sig00000344 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001364 ), + .Q(\blk00000003/sig00000345 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001363 ), + .Q(\blk00000003/sig00000346 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001362 ), + .Q(\blk00000003/sig00000347 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001361 ), + .Q(\blk00000003/sig00000348 ) + ); + GND \blk00000003/blk000005b5/blk000005b6 ( + .G(\blk00000003/blk000005b5/sig00001360 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005e8/blk00000620 ( + .I0(ce), + .I1(\blk00000003/sig00000237 ), + .O(\blk00000003/blk000005e8/sig000013dc ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061f ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b2 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c9 ), + .DPO(\blk00000003/blk000005e8/sig000013db ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061e ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b3 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c8 ), + .DPO(\blk00000003/blk000005e8/sig000013da ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061d ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b4 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c7 ), + .DPO(\blk00000003/blk000005e8/sig000013d9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061c ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b5 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c6 ), + .DPO(\blk00000003/blk000005e8/sig000013d8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061b ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b6 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c5 ), + .DPO(\blk00000003/blk000005e8/sig000013d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061a ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b7 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c4 ), + .DPO(\blk00000003/blk000005e8/sig000013d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk00000619 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b9 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c2 ), + .DPO(\blk00000003/blk000005e8/sig000013d4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk00000618 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008ba ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c1 ), + .DPO(\blk00000003/blk000005e8/sig000013d3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk00000617 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b8 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c3 ), + .DPO(\blk00000003/blk000005e8/sig000013d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk00000616 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008bb ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c0 ), + .DPO(\blk00000003/blk000005e8/sig000013d2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000005e8/blk00000615 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008bc ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013bf ), + .DPO(\blk00000003/blk000005e8/sig000013d1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000005e8/blk00000614 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008bd ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013be ), + .DPO(\blk00000003/blk000005e8/sig000013d0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk00000613 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008be ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013bd ), + .DPO(\blk00000003/blk000005e8/sig000013cf ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk00000612 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008bf ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013bc ), + .DPO(\blk00000003/blk000005e8/sig000013ce ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk00000611 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008c0 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013bb ), + .DPO(\blk00000003/blk000005e8/sig000013cd ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000005e8/blk00000610 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008c2 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013b9 ), + .DPO(\blk00000003/blk000005e8/sig000013cb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk0000060f ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008c3 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013b8 ), + .DPO(\blk00000003/blk000005e8/sig000013ca ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk0000060e ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008c1 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013ba ), + .DPO(\blk00000003/blk000005e8/sig000013cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk0000060d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013db ), + .Q(\blk00000003/sig000002a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk0000060c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013da ), + .Q(\blk00000003/sig000002a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk0000060b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d9 ), + .Q(\blk00000003/sig000002a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk0000060a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d8 ), + .Q(\blk00000003/sig000002aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000609 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d7 ), + .Q(\blk00000003/sig000002ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000608 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d6 ), + .Q(\blk00000003/sig000002ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000607 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d5 ), + .Q(\blk00000003/sig000002ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000606 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d4 ), + .Q(\blk00000003/sig000002ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000605 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d3 ), + .Q(\blk00000003/sig000002af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000604 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d2 ), + .Q(\blk00000003/sig000002b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000603 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d1 ), + .Q(\blk00000003/sig000002b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000602 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d0 ), + .Q(\blk00000003/sig000002b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000601 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013cf ), + .Q(\blk00000003/sig000002b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000600 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013ce ), + .Q(\blk00000003/sig000002b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013cd ), + .Q(\blk00000003/sig000002b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013cc ), + .Q(\blk00000003/sig000002b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013cb ), + .Q(\blk00000003/sig000002b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013ca ), + .Q(\blk00000003/sig000002b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c9 ), + .Q(\blk00000003/sig000008c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c8 ), + .Q(\blk00000003/sig000008c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c7 ), + .Q(\blk00000003/sig000008c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c6 ), + .Q(\blk00000003/sig000008c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c5 ), + .Q(\blk00000003/sig000008c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c4 ), + .Q(\blk00000003/sig000008c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c3 ), + .Q(\blk00000003/sig000008ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c2 ), + .Q(\blk00000003/sig000008cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c1 ), + .Q(\blk00000003/sig000008cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c0 ), + .Q(\blk00000003/sig000008cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013bf ), + .Q(\blk00000003/sig000008ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013be ), + .Q(\blk00000003/sig000008cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013bd ), + .Q(\blk00000003/sig000008d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013bc ), + .Q(\blk00000003/sig000008d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013bb ), + .Q(\blk00000003/sig000008d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013ba ), + .Q(\blk00000003/sig000008d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013b9 ), + .Q(\blk00000003/sig000008d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013b8 ), + .Q(\blk00000003/sig000008d5 ) + ); + GND \blk00000003/blk000005e8/blk000005e9 ( + .G(\blk00000003/blk000005e8/sig000013b7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000621/blk00000659 ( + .I0(ce), + .I1(\blk00000003/sig0000073d ), + .O(\blk00000003/blk00000621/sig0000143f ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000658 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c4 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000142c ), + .DPO(\blk00000003/blk00000621/sig0000143e ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000657 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c5 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000142b ), + .DPO(\blk00000003/blk00000621/sig0000143d ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000656 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c6 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000142a ), + .DPO(\blk00000003/blk00000621/sig0000143c ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000655 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c7 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001429 ), + .DPO(\blk00000003/blk00000621/sig0000143b ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000654 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c8 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001428 ), + .DPO(\blk00000003/blk00000621/sig0000143a ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000653 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c9 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001427 ), + .DPO(\blk00000003/blk00000621/sig00001439 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000652 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008cb ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001425 ), + .DPO(\blk00000003/blk00000621/sig00001437 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000621/blk00000651 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008cc ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001424 ), + .DPO(\blk00000003/blk00000621/sig00001436 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000650 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008ca ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001426 ), + .DPO(\blk00000003/blk00000621/sig00001438 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk0000064f ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008cd ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001423 ), + .DPO(\blk00000003/blk00000621/sig00001435 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000621/blk0000064e ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008ce ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001422 ), + .DPO(\blk00000003/blk00000621/sig00001434 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000621/blk0000064d ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008cf ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001421 ), + .DPO(\blk00000003/blk00000621/sig00001433 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000621/blk0000064c ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d0 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001420 ), + .DPO(\blk00000003/blk00000621/sig00001432 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk0000064b ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d1 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141f ), + .DPO(\blk00000003/blk00000621/sig00001431 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk0000064a ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d2 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141e ), + .DPO(\blk00000003/blk00000621/sig00001430 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk00000649 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d4 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141c ), + .DPO(\blk00000003/blk00000621/sig0000142e ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk00000648 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d5 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141b ), + .DPO(\blk00000003/blk00000621/sig0000142d ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk00000647 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d3 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141d ), + .DPO(\blk00000003/blk00000621/sig0000142f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000646 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143e ), + .Q(\blk00000003/sig0000044b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000645 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143d ), + .Q(\blk00000003/sig0000044c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000644 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143c ), + .Q(\blk00000003/sig0000044d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000643 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143b ), + .Q(\blk00000003/sig0000044e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000642 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143a ), + .Q(\blk00000003/sig0000044f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000641 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001439 ), + .Q(\blk00000003/sig00000450 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000640 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001438 ), + .Q(\blk00000003/sig00000451 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001437 ), + .Q(\blk00000003/sig00000452 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001436 ), + .Q(\blk00000003/sig00000453 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001435 ), + .Q(\blk00000003/sig00000454 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001434 ), + .Q(\blk00000003/sig00000455 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001433 ), + .Q(\blk00000003/sig00000456 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001432 ), + .Q(\blk00000003/sig00000457 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000639 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001431 ), + .Q(\blk00000003/sig00000458 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000638 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001430 ), + .Q(\blk00000003/sig00000459 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000637 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142f ), + .Q(\blk00000003/sig0000045a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000636 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142e ), + .Q(\blk00000003/sig0000045b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000635 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142d ), + .Q(\blk00000003/sig0000045c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000634 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142c ), + .Q(\blk00000003/sig000008d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000633 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142b ), + .Q(\blk00000003/sig000008d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000632 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142a ), + .Q(\blk00000003/sig000008d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001429 ), + .Q(\blk00000003/sig000008d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000630 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001428 ), + .Q(\blk00000003/sig000008da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001427 ), + .Q(\blk00000003/sig000008db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001426 ), + .Q(\blk00000003/sig000008dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001425 ), + .Q(\blk00000003/sig000008dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001424 ), + .Q(\blk00000003/sig000008de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001423 ), + .Q(\blk00000003/sig000008df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001422 ), + .Q(\blk00000003/sig000008e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000629 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001421 ), + .Q(\blk00000003/sig000008e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000628 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001420 ), + .Q(\blk00000003/sig000008e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000627 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141f ), + .Q(\blk00000003/sig000008e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000626 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141e ), + .Q(\blk00000003/sig000008e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000625 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141d ), + .Q(\blk00000003/sig000008e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000624 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141c ), + .Q(\blk00000003/sig000008e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000623 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141b ), + .Q(\blk00000003/sig000008e7 ) + ); + GND \blk00000003/blk00000621/blk00000622 ( + .G(\blk00000003/blk00000621/sig0000141a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000065a/blk00000692 ( + .I0(ce), + .I1(\blk00000003/sig0000073e ), + .O(\blk00000003/blk0000065a/sig000014a2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk00000691 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008d6 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148f ), + .DPO(\blk00000003/blk0000065a/sig000014a1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk00000690 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008d7 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148e ), + .DPO(\blk00000003/blk0000065a/sig000014a0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068f ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008d8 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148d ), + .DPO(\blk00000003/blk0000065a/sig0000149f ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068e ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008d9 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148c ), + .DPO(\blk00000003/blk0000065a/sig0000149e ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068d ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008da ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148b ), + .DPO(\blk00000003/blk0000065a/sig0000149d ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068c ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008db ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148a ), + .DPO(\blk00000003/blk0000065a/sig0000149c ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000065a/blk0000068b ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008dd ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001488 ), + .DPO(\blk00000003/blk0000065a/sig0000149a ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068a ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008de ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001487 ), + .DPO(\blk00000003/blk0000065a/sig00001499 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000065a/blk00000689 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008dc ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001489 ), + .DPO(\blk00000003/blk0000065a/sig0000149b ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000065a/blk00000688 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008df ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001486 ), + .DPO(\blk00000003/blk0000065a/sig00001498 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000065a/blk00000687 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e0 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001485 ), + .DPO(\blk00000003/blk0000065a/sig00001497 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000065a/blk00000686 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e1 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001484 ), + .DPO(\blk00000003/blk0000065a/sig00001496 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000065a/blk00000685 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e2 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001483 ), + .DPO(\blk00000003/blk0000065a/sig00001495 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk00000684 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e3 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001482 ), + .DPO(\blk00000003/blk0000065a/sig00001494 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000065a/blk00000683 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e4 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001481 ), + .DPO(\blk00000003/blk0000065a/sig00001493 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000065a/blk00000682 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e6 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000147f ), + .DPO(\blk00000003/blk0000065a/sig00001491 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk00000681 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e7 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000147e ), + .DPO(\blk00000003/blk0000065a/sig00001490 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000065a/blk00000680 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e5 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001480 ), + .DPO(\blk00000003/blk0000065a/sig00001492 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig000014a1 ), + .Q(\blk00000003/sig000004bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig000014a0 ), + .Q(\blk00000003/sig000004be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149f ), + .Q(\blk00000003/sig000004bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149e ), + .Q(\blk00000003/sig000004c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149d ), + .Q(\blk00000003/sig000004c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149c ), + .Q(\blk00000003/sig000004c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000679 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149b ), + .Q(\blk00000003/sig000004c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000678 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149a ), + .Q(\blk00000003/sig000004c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000677 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001499 ), + .Q(\blk00000003/sig000004c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000676 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001498 ), + .Q(\blk00000003/sig000004c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000675 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001497 ), + .Q(\blk00000003/sig000004c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000674 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001496 ), + .Q(\blk00000003/sig000004c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000673 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001495 ), + .Q(\blk00000003/sig000004c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000672 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001494 ), + .Q(\blk00000003/sig000004ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000671 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001493 ), + .Q(\blk00000003/sig000004cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000670 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001492 ), + .Q(\blk00000003/sig000004cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001491 ), + .Q(\blk00000003/sig000004cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001490 ), + .Q(\blk00000003/sig000004ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148f ), + .Q(\blk00000003/sig000008e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148e ), + .Q(\blk00000003/sig000008e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148d ), + .Q(\blk00000003/sig000008ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148c ), + .Q(\blk00000003/sig000008eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000669 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148b ), + .Q(\blk00000003/sig000008ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000668 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148a ), + .Q(\blk00000003/sig000008ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000667 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001489 ), + .Q(\blk00000003/sig000008ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000666 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001488 ), + .Q(\blk00000003/sig000008ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000665 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001487 ), + .Q(\blk00000003/sig000008f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000664 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001486 ), + .Q(\blk00000003/sig000008f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000663 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001485 ), + .Q(\blk00000003/sig000008f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000662 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001484 ), + .Q(\blk00000003/sig000008f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000661 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001483 ), + .Q(\blk00000003/sig000008f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000660 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001482 ), + .Q(\blk00000003/sig000008f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000065f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001481 ), + .Q(\blk00000003/sig000008f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000065e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001480 ), + .Q(\blk00000003/sig000008f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000065d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000147f ), + .Q(\blk00000003/sig000008f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000065c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000147e ), + .Q(\blk00000003/sig000008f9 ) + ); + GND \blk00000003/blk0000065a/blk0000065b ( + .G(\blk00000003/blk0000065a/sig0000147d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000693/blk000006cb ( + .I0(ce), + .I1(\blk00000003/sig0000073f ), + .O(\blk00000003/blk00000693/sig00001505 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006ca ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008e8 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014f2 ), + .DPO(\blk00000003/blk00000693/sig00001504 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c9 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008e9 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014f1 ), + .DPO(\blk00000003/blk00000693/sig00001503 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c8 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ea ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014f0 ), + .DPO(\blk00000003/blk00000693/sig00001502 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c7 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008eb ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ef ), + .DPO(\blk00000003/blk00000693/sig00001501 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c6 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ec ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ee ), + .DPO(\blk00000003/blk00000693/sig00001500 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000693/blk000006c5 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ed ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ed ), + .DPO(\blk00000003/blk00000693/sig000014ff ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006c4 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ef ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014eb ), + .DPO(\blk00000003/blk00000693/sig000014fd ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006c3 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f0 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ea ), + .DPO(\blk00000003/blk00000693/sig000014fc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000693/blk000006c2 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ee ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ec ), + .DPO(\blk00000003/blk00000693/sig000014fe ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006c1 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f1 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e9 ), + .DPO(\blk00000003/blk00000693/sig000014fb ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c0 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f2 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e8 ), + .DPO(\blk00000003/blk00000693/sig000014fa ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000693/blk000006bf ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f3 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e7 ), + .DPO(\blk00000003/blk00000693/sig000014f9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006be ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f4 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e6 ), + .DPO(\blk00000003/blk00000693/sig000014f8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000693/blk000006bd ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f5 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e5 ), + .DPO(\blk00000003/blk00000693/sig000014f7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000693/blk000006bc ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f6 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e4 ), + .DPO(\blk00000003/blk00000693/sig000014f6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006bb ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f8 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e2 ), + .DPO(\blk00000003/blk00000693/sig000014f4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000693/blk000006ba ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f9 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e1 ), + .DPO(\blk00000003/blk00000693/sig000014f3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000693/blk000006b9 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f7 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e3 ), + .DPO(\blk00000003/blk00000693/sig000014f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001504 ), + .Q(\blk00000003/sig0000052f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001503 ), + .Q(\blk00000003/sig00000530 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001502 ), + .Q(\blk00000003/sig00000531 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001501 ), + .Q(\blk00000003/sig00000532 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001500 ), + .Q(\blk00000003/sig00000533 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ff ), + .Q(\blk00000003/sig00000534 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fe ), + .Q(\blk00000003/sig00000535 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fd ), + .Q(\blk00000003/sig00000536 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fc ), + .Q(\blk00000003/sig00000537 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fb ), + .Q(\blk00000003/sig00000538 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fa ), + .Q(\blk00000003/sig00000539 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f9 ), + .Q(\blk00000003/sig0000053a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f8 ), + .Q(\blk00000003/sig0000053b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f7 ), + .Q(\blk00000003/sig0000053c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f6 ), + .Q(\blk00000003/sig0000053d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f5 ), + .Q(\blk00000003/sig0000053e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f4 ), + .Q(\blk00000003/sig0000053f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f3 ), + .Q(\blk00000003/sig00000540 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f2 ), + .Q(\blk00000003/sig000008fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f1 ), + .Q(\blk00000003/sig000008fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f0 ), + .Q(\blk00000003/sig000008fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ef ), + .Q(\blk00000003/sig000008fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ee ), + .Q(\blk00000003/sig000008fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ed ), + .Q(\blk00000003/sig000008ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ec ), + .Q(\blk00000003/sig00000900 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014eb ), + .Q(\blk00000003/sig00000901 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ea ), + .Q(\blk00000003/sig00000902 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e9 ), + .Q(\blk00000003/sig00000903 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e8 ), + .Q(\blk00000003/sig00000904 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e7 ), + .Q(\blk00000003/sig00000905 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e6 ), + .Q(\blk00000003/sig00000906 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000699 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e5 ), + .Q(\blk00000003/sig00000907 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000698 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e4 ), + .Q(\blk00000003/sig00000908 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000697 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e3 ), + .Q(\blk00000003/sig00000909 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000696 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e2 ), + .Q(\blk00000003/sig0000090a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000695 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e1 ), + .Q(\blk00000003/sig0000090b ) + ); + GND \blk00000003/blk00000693/blk00000694 ( + .G(\blk00000003/blk00000693/sig000014e0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006cc/blk00000704 ( + .I0(ce), + .I1(\blk00000003/sig00000740 ), + .O(\blk00000003/blk000006cc/sig00001568 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk00000703 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fa ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001555 ), + .DPO(\blk00000003/blk000006cc/sig00001567 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk00000702 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fb ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001554 ), + .DPO(\blk00000003/blk000006cc/sig00001566 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk00000701 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fc ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001553 ), + .DPO(\blk00000003/blk000006cc/sig00001565 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk00000700 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fd ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001552 ), + .DPO(\blk00000003/blk000006cc/sig00001564 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk000006cc/blk000006ff ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fe ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001551 ), + .DPO(\blk00000003/blk000006cc/sig00001563 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000006cc/blk000006fe ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008ff ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001550 ), + .DPO(\blk00000003/blk000006cc/sig00001562 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk000006fd ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000901 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154e ), + .DPO(\blk00000003/blk000006cc/sig00001560 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000006cc/blk000006fc ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000902 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154d ), + .DPO(\blk00000003/blk000006cc/sig0000155f ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000006cc/blk000006fb ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000900 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154f ), + .DPO(\blk00000003/blk000006cc/sig00001561 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk000006cc/blk000006fa ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000903 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154c ), + .DPO(\blk00000003/blk000006cc/sig0000155e ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000006cc/blk000006f9 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000904 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154b ), + .DPO(\blk00000003/blk000006cc/sig0000155d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000006cc/blk000006f8 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000905 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154a ), + .DPO(\blk00000003/blk000006cc/sig0000155c ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk000006cc/blk000006f7 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000906 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001549 ), + .DPO(\blk00000003/blk000006cc/sig0000155b ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk000006f6 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000907 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001548 ), + .DPO(\blk00000003/blk000006cc/sig0000155a ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000006cc/blk000006f5 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000908 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001547 ), + .DPO(\blk00000003/blk000006cc/sig00001559 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000006cc/blk000006f4 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig0000090a ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001545 ), + .DPO(\blk00000003/blk000006cc/sig00001557 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk000006f3 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig0000090b ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001544 ), + .DPO(\blk00000003/blk000006cc/sig00001556 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk000006f2 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000909 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001546 ), + .DPO(\blk00000003/blk000006cc/sig00001558 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001567 ), + .Q(\blk00000003/sig000005a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001566 ), + .Q(\blk00000003/sig000005a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001565 ), + .Q(\blk00000003/sig000005a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001564 ), + .Q(\blk00000003/sig000005a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001563 ), + .Q(\blk00000003/sig000005a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001562 ), + .Q(\blk00000003/sig000005a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001561 ), + .Q(\blk00000003/sig000005a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001560 ), + .Q(\blk00000003/sig000005a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155f ), + .Q(\blk00000003/sig000005a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155e ), + .Q(\blk00000003/sig000005aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155d ), + .Q(\blk00000003/sig000005ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155c ), + .Q(\blk00000003/sig000005ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155b ), + .Q(\blk00000003/sig000005ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155a ), + .Q(\blk00000003/sig000005ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001559 ), + .Q(\blk00000003/sig000005af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001558 ), + .Q(\blk00000003/sig000005b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001557 ), + .Q(\blk00000003/sig000005b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001556 ), + .Q(\blk00000003/sig000005b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001555 ), + .Q(\blk00000003/sig0000090c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001554 ), + .Q(\blk00000003/sig0000090d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001553 ), + .Q(\blk00000003/sig0000090e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001552 ), + .Q(\blk00000003/sig0000090f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001551 ), + .Q(\blk00000003/sig00000910 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001550 ), + .Q(\blk00000003/sig00000911 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154f ), + .Q(\blk00000003/sig00000912 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154e ), + .Q(\blk00000003/sig00000913 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154d ), + .Q(\blk00000003/sig00000914 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154c ), + .Q(\blk00000003/sig00000915 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154b ), + .Q(\blk00000003/sig00000916 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154a ), + .Q(\blk00000003/sig00000917 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001549 ), + .Q(\blk00000003/sig00000918 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001548 ), + .Q(\blk00000003/sig00000919 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001547 ), + .Q(\blk00000003/sig0000091a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001546 ), + .Q(\blk00000003/sig0000091b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001545 ), + .Q(\blk00000003/sig0000091c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001544 ), + .Q(\blk00000003/sig0000091d ) + ); + GND \blk00000003/blk000006cc/blk000006cd ( + .G(\blk00000003/blk000006cc/sig00001543 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000705/blk0000072b ( + .I0(ce), + .I1(\blk00000003/sig00000741 ), + .O(\blk00000003/blk00000705/sig000015a7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk0000072a ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000090c ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000072a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000705/blk00000729 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000090d ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000729_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk00000728 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000090e ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000728_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000705/blk00000727 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000090f ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000727_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000726 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000910 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000726_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk00000725 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000911 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000725_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000705/blk00000724 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000913 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000724_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159f ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000723 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000914 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000723_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159e ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk00000722 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000912 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000722_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000721 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000915 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000721_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000720 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000916 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000720_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159c ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000705/blk0000071f ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000917 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159b ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk0000071e ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000918 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159a ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk0000071d ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000919 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001599 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk0000071c ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000091a ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001598 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk0000071b ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000091c ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001596 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000705/blk0000071a ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000091d ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001595 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000719 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000091b ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000719_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001597 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000718 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a6 ), + .Q(\blk00000003/sig000003a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000717 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a5 ), + .Q(\blk00000003/sig000003aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000716 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a4 ), + .Q(\blk00000003/sig000003ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000715 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a3 ), + .Q(\blk00000003/sig000003ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000714 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a2 ), + .Q(\blk00000003/sig000003ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000713 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a1 ), + .Q(\blk00000003/sig000003ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000712 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a0 ), + .Q(\blk00000003/sig000003af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000711 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159f ), + .Q(\blk00000003/sig000003b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000710 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159e ), + .Q(\blk00000003/sig000003b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159d ), + .Q(\blk00000003/sig000003b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159c ), + .Q(\blk00000003/sig000003b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159b ), + .Q(\blk00000003/sig000003b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159a ), + .Q(\blk00000003/sig000003b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001599 ), + .Q(\blk00000003/sig000003b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001598 ), + .Q(\blk00000003/sig000003b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000709 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001597 ), + .Q(\blk00000003/sig000003b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000708 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001596 ), + .Q(\blk00000003/sig000003b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000707 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001595 ), + .Q(\blk00000003/sig000003ba ) + ); + GND \blk00000003/blk00000705/blk00000706 ( + .G(\blk00000003/blk00000705/sig00001594 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000075c/blk00000782 ( + .I0(ce), + .I1(\blk00000003/sig00000235 ), + .O(\blk00000003/blk0000075c/sig000015e4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000075c/blk00000781 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b2 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000781_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015e3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000780 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b3 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000780_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015e2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077f ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b4 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015e1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077e ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b5 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015e0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077d ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b6 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015df ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077c ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b7 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015de ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077b ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b9 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015dc ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077a ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008ba ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015db ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000779 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b8 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000779_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015dd ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000778 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008bb ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000778_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015da ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000777 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008bc ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000777_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000776 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008bd ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000776_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000775 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008be ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000775_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000774 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008bf ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000774_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000773 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008c0 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000773_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000772 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008c2 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000772_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000771 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008c3 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000771_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000770 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008c1 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000770_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015e3 ), + .Q(\blk00000003/sig000000fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015e2 ), + .Q(\blk00000003/sig000000fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015e1 ), + .Q(\blk00000003/sig000000fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015e0 ), + .Q(\blk00000003/sig000000fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015df ), + .Q(\blk00000003/sig000000fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015de ), + .Q(\blk00000003/sig000000ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000769 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015dd ), + .Q(\blk00000003/sig00000100 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000768 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015dc ), + .Q(\blk00000003/sig00000101 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000767 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015db ), + .Q(\blk00000003/sig00000102 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000766 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015da ), + .Q(\blk00000003/sig00000103 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000765 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d9 ), + .Q(\blk00000003/sig00000104 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000764 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d8 ), + .Q(\blk00000003/sig00000105 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000763 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d7 ), + .Q(\blk00000003/sig00000106 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000762 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d6 ), + .Q(\blk00000003/sig00000107 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000761 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d5 ), + .Q(\blk00000003/sig00000108 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000760 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d4 ), + .Q(\blk00000003/sig00000109 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000075f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d3 ), + .Q(\blk00000003/sig0000010a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000075e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d2 ), + .Q(\blk00000003/sig0000010b ) + ); + GND \blk00000003/blk0000075c/blk0000075d ( + .G(\blk00000003/blk0000075c/sig000015d1 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.ngc b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.ngc new file mode 100644 index 000000000..e01cbfd43 --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$3155~753-Xnzd}foo8#5+421).97 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17a2;2;7c:>e;d8?j41n3:1(9?i:3:3?k26m3;;76a=6d83>!26n383<6`;1d825>=h:?i1<7*;1g81<5=i<8o1=?54o34a>5<#<8l1>5>4n53f>45<3f8=m7>5$53e>7>73g>:i7?;;:m12<<72->:j7<70:l75`<6=21d>;650;&75c<5091e8e;3;?>i5><0;6):>f;0;4>h39l0:565`27694?"39o094=5a40g95d=d:9l60`=83.?=k4=819m04c=9l10c?;k:18'04`=:1:0b9?j:0d8?j42k3:1(9?i:3:3?k26m38;76a=5c83>!26n383<6`;1d815>=h:?54o37:>5<#<8l1>5>4n53f>75<3f8>47>5$53e>7>73g>:i7<;;:m112<72->:j7<70:l75`<5=21d>5950;&75c<5091e81290/8e;0;?>i50=0;6):>f;0;4>h39l09565`29194?"39o094=5a40g96d=50z&77d<5i?1C8974H51g?j4f=3:17pl;8983>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3000;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;8`83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd30k0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;8b83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd30m0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;8d83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd30o0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9183>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3180;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9383>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31:0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9583>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31<0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9783>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31>0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9983>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3100;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9`83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31k0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9b83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31m0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9d83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31o0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a183>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i80;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a383>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i:0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a583>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i<0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a783>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i>0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a983>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i00;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a`83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3ik0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;ab83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3im0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;ad83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3io0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b183>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3j80;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b383>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3j:0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b583>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3j<0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b783>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3j>0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b983>c<729q/8>o54378L12>3A>8h6*=ae87?l?32900e4;50;9j=3<722c2;7>5;h;;>5<5<5<5<?6=44i566>5<5<i57>5f;294~"3;h0?>85G45;8L15c3-8jh7:4i8694?=n1<0;66g66;29?l?02900e4650;9j5d2=831b>5k50;9j6=`=831b>4>50;9j6<7=831b>4<50;9j012=831b89;50;9l061=831d>5j50;9~f1df290m6=4?{%60e?25=2B?845G42f8 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17a28o37c:>e;33?>i6ml0;6):>f;3f<>h39l0:=65`1df94?"39o0:i55a40g957=5:9l5`2=83.?=k4>e99m04c=9?10c50z&77d<5i?1C8974H51g?j4f=3:17pl83g83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0<90;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84083>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0<;0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84283>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0<=0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84483>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84683>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0<10;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84883>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84c83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84e83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84g83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0=90;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl85083>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0=;0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl85283>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0==0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl85483>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0=?0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl85683><<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<954?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0=00;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`41d<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<9n4?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0=m0;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`41`<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<:=4?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0>80;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`427<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<:94?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0><0;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`423<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<:54?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0>00;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`42d<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<:n4?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0>m0;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`42`<7200;6=u+42c906><@=>27E:6<729q/8>o52c`8L12>3A>8h6*=ae8;b>o5i10;66g=a883>>i4?>0;66s|200:>5<61rTm5638568:1>;0=1029638588:1>;0=h0296385c8:1>;0=j0296385e8:1>;0=l0296385g8:1>;0>9029638608:1>;0>;029638628:1>;0>=029638648:1>;0>?029638668:1>;0>1029638688:1>;0>h0296386c8:1>;0>j0296386e8:1>;0>l0296s|200b>5<61rTm;638568:0>;0=1028638588:0>;0=h0286385c8:0>;0=j0286385e8:0>;0=l0286385g8:0>;0>9028638608:0>;0>;028638628:0>;0>=028638648:0>;0>?028638668:0>;0>1028638688:0>;0>h0286386c8:0>;0>j0286386e8:0>;0>l0286s|200a>5<5sW;o<6386b82e1=z{;;9o7>52z\2g`=:??o1=l:4}r026a<72;qU=nj4=64g>4g33ty9=?k50;0xZ4ed34==57?n4:p644a2909wS?la:?42g<6i=1v??<0;296~X6k016;;o51`68yv46;80;6?uQ1b:8920128k?7p}=12094?4|V8i<70998;3b0>{t:8986=4={_3`2>;0>>0:m95rs3300?6=:rT:o85277195d2<>6<=8:181[7d:27<:=4>a59~w77403:1>vP>c09>334=9h>0q~<>3883>7}Y9m201:8>:0c7?xu59:k1<75<5sW;o:6385g82e1=z{;;8o7>52z\2`0=:?4g33ty9=>k50;0xZ4b434=>o7?n4:p645a2909wS?k2:?41g<6i=1v??;0;296~X6l816;8951`68yv46<80;6?uQ1b`8923>28k?7p}=15094?4|V8i;709:8;3b0>{t:8>86=4={_671>;0>o09m45rs3370?6=9hqU=5k4=61e>4>b34=?<7?7e:?404<60l16;9<519g89224282n709;4;3;a>;0<<0:4h5275495=c<5>><6<6j;<578d9>31g=91o01::m:0:f?813k3;3i6384e82<`=:?=o1=5k4=66e>4>b34=><7?7e:?414<60l16;8<519g89234282n709:4;3;a>;0=<0:4h5274495=c<5>515g8922628>n709;2;37a>;0<:0:8h52756951c<5>>>6<:j;<57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15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=31<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<81<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<91<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<21<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<31<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?81<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?91<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0??1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?21<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?31<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>81<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>91<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>?1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0><1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>21<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>31<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0181<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0191<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01?1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0121<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0131<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0081<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0091<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00?1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0021<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0031<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h81<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h91<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h?1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h21<7:?:34904}O<:n0(9=n:0466>\6w8;51e862?472;;1qdhi:18'04`=nl1e8:j7hj;o62a?7<3`li6=4+40d9b`=i<8o1>65f1g`94?"39o0:jl5a40g94>=n9o31<7*;1g82bd=i<8o1=65f1g:94?"39o0:jl5a40g96>=n9o=1<7*;1g82bd=i<8o1?65f1g494?"39o0:jl5a40g90>=n9o?1<7*;1g82bd=i<8o1965f1g694?"39o0:jl5a40g92>=n9o91<7*;1g82bd=i<8o1;65f23194?"39o0:jl5a40g9<>=n:;81<7*;1g82bd=i<8o1565f23394?"39o0:jl5a40g9e>=n:;:1<7*;1g82bd=i<8o1n65f20d94?"39o0:jl5a40g9g>=n:8o1<7*;1g82bd=i<8o1h65f20694?"39o0:jl5a40g9a>=n:931<7*;1g82bd=i<8o1j65f1gg94?"39o0:jl5a40g955=;;o62a?6<3`;;?7>5$53e>4633g>:i7?4;h335?6=,=;m6<>;;o62a?4<3`>?:7>5;h3;a?6=3`>8=7>5;h3:b?6=3f89h7>5$53e>74d3g>:i7>4;n01f?6=,=;m6?5$53e>74d3g>:i7<4;n01=?6=,=;m6?5$53e>74d3g>:i7:4;n013?6=,=;m6?5$53e>74d3g>:i784;n011?6=,=;m6?97>5$53e>74d3g>:i764;n060?6=,=;m6??7>5$53e>74d3g>:i7o4;n066?6=,=;m6?=7>5$53e>74d3g>:i7m4;n064?6=,=;m6?5$53e>74d3g>:i7k4;n00f?6=,=;m6?5$53e>74d3g>:i7??;:m161<72->:j7<=c:l75`<6921d>8h50;&75c<5=l1e88m50;&75c<5=l1e88o50;&75c<5=l1e88650;&75c<5=l1e85950;&75c<5=l1e85;50;&75c<5=l1e85=50;&75c<5=l1e8:650;&75c<5=l1e8;<50;&75c<5=l1e8"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7ac83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?ij0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7ae83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?il0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7ag83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j90;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b083>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j;0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b283>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j=0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b483>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j?0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b683>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j10;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b883>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?jh0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7bc83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?jj0;6k4?:1y'06g=<;?0D9:6;I60`>"5im0=7d7;:188m<3=831b5;4?::k:3?6=3`336=44i0c7>5<5<5<5<>6=44o514>5<1<75f9483>>o>>3:17d78:188m<>=831b=l:50;9j6=c=831b>5h50;9j6<6=831b>4?50;9j6<4=831b89:50;9j013=831d8>950;9l6=b=831vn5lj:18e>5<7s->8m7:=5:J70<=O<:n0(?ok:59j=1<722c297>5;h;5>5<>o6i=0;66g=8d83>>o50o0;66g=9183>>o5180;66g=9383>>o3<=0;66g;4483>>i3;>0;66a=8e83>>{e0kl1<7h50;2x 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7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc37>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk;>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg71290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno?8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno?n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg7e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc3`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk;o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg7b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno?i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno<=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg4429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc07>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk8>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg41290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno<8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg4e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc0`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk8o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg4b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno==:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg5429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc17>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk9>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg51290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno=8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno=n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg5e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc1`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk9o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg5b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno=i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<;6=4;:183!24i382i6F;489K06b<,;ko6?5f15g94?=n91o1<75f1`694?=h<;81<75rbc62>5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno:=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg2429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc67>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk>>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg21290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno:8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<36=4;:183!24i382i6F;489K06b<,;ko6?5f15g94?=n91o1<75f1`694?=h<;81<75rbc6:>5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno:n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg2e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc6`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk>o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg2b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno:i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno;=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg3429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc77>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk?>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg31290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno;8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno;n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg3e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc7`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk?o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg3b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno;i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno8=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg0429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc47>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk<>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg01290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno88:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno8n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg0e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc4`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg0b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno8i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno9=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg1429026=4?{%60e?2402B?845G42f8 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\ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.v b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.v new file mode 100644 index 000000000..e5423434c --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.v @@ -0,0 +1,24109 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: P.49d +// \ \ Application: netgen +// / / Filename: hbdec2.v +// /___/ /\ Timestamp: Wed Dec 4 13:33:47 2013 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/hbdec2.ngc ./tmp/_cg/hbdec2.v +// Device : 7k325tffg900-2 +// Input file : ./tmp/_cg/hbdec2.ngc +// Output file : ./tmp/_cg/hbdec2.v +// # of Modules : 1 +// Design Name : hbdec2 +// Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module hbdec2 ( + sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk, coef_ld, dout_1, dout_2, din_1, din_2, coef_din +)/* synthesis syn_black_box syn_noprune=1 */; + input sclr; + input ce; + output rfd; + output rdy; + output data_valid; + input coef_we; + input nd; + input clk; + input coef_ld; + output [46 : 0] dout_1; + output [46 : 0] dout_2; + input [23 : 0] din_1; + input [23 : 0] din_2; + input [17 : 0] coef_din; + + // synthesis translate_off + + wire NlwRenamedSig_OI_rfd; + wire \blk00000003/sig00000767 ; + wire \blk00000003/sig00000766 ; + wire \blk00000003/sig00000765 ; + wire \blk00000003/sig00000764 ; + wire \blk00000003/sig00000763 ; + wire \blk00000003/sig00000762 ; + wire \blk00000003/sig00000761 ; + wire \blk00000003/sig00000760 ; + wire \blk00000003/sig0000075f ; + wire \blk00000003/sig0000075e ; + wire \blk00000003/sig0000075d ; + wire \blk00000003/sig0000075c ; + wire \blk00000003/sig0000075b ; + wire \blk00000003/sig0000075a ; + wire \blk00000003/sig00000759 ; + wire \blk00000003/sig00000758 ; + wire \blk00000003/sig00000757 ; + wire \blk00000003/sig00000756 ; + wire \blk00000003/sig00000755 ; + wire \blk00000003/sig00000754 ; + wire \blk00000003/sig00000753 ; + wire \blk00000003/sig00000752 ; + wire \blk00000003/sig00000751 ; + wire \blk00000003/sig00000750 ; + wire \blk00000003/sig0000074f ; + wire \blk00000003/sig0000074e ; + wire \blk00000003/sig0000074d ; + wire \blk00000003/sig0000074c ; + wire \blk00000003/sig0000074b ; + wire \blk00000003/sig0000074a ; + wire \blk00000003/sig00000749 ; + wire \blk00000003/sig00000748 ; + wire \blk00000003/sig00000747 ; + wire \blk00000003/sig00000746 ; + wire \blk00000003/sig00000745 ; + wire \blk00000003/sig00000744 ; + wire \blk00000003/sig00000743 ; + wire \blk00000003/sig00000742 ; + wire \blk00000003/sig00000741 ; + wire \blk00000003/sig00000740 ; + wire \blk00000003/sig0000073f ; + wire \blk00000003/sig0000073e ; + wire \blk00000003/sig0000073d ; + wire \blk00000003/sig0000073c ; + wire \blk00000003/sig0000073b ; + wire \blk00000003/sig0000073a ; + wire \blk00000003/sig00000739 ; + wire \blk00000003/sig00000738 ; + wire \blk00000003/sig00000737 ; + wire \blk00000003/sig00000736 ; + wire \blk00000003/sig00000735 ; + wire \blk00000003/sig00000734 ; + wire \blk00000003/sig00000733 ; + wire \blk00000003/sig00000732 ; + wire \blk00000003/sig00000731 ; + wire \blk00000003/sig00000730 ; + wire \blk00000003/sig0000072f ; + wire \blk00000003/sig0000072e ; + wire \blk00000003/sig0000072d ; + wire \blk00000003/sig0000072c ; + wire \blk00000003/sig0000072b ; + wire \blk00000003/sig0000072a ; + wire \blk00000003/sig00000729 ; + wire \blk00000003/sig00000728 ; + wire \blk00000003/sig00000727 ; + wire \blk00000003/sig00000726 ; + wire \blk00000003/sig00000725 ; + wire \blk00000003/sig00000724 ; + wire \blk00000003/sig00000723 ; + wire \blk00000003/sig00000722 ; + wire \blk00000003/sig00000721 ; + wire \blk00000003/sig00000720 ; + wire \blk00000003/sig0000071f ; + wire \blk00000003/sig0000071e ; + wire \blk00000003/sig0000071d ; + wire \blk00000003/sig0000071c ; + wire \blk00000003/sig0000071b ; + wire \blk00000003/sig0000071a ; + wire \blk00000003/sig00000719 ; + wire \blk00000003/sig00000718 ; + wire \blk00000003/sig00000717 ; + wire \blk00000003/sig00000716 ; + wire \blk00000003/sig00000715 ; + wire \blk00000003/sig00000714 ; + wire \blk00000003/sig00000713 ; + wire \blk00000003/sig00000712 ; + wire \blk00000003/sig00000711 ; + wire \blk00000003/sig00000710 ; + wire \blk00000003/sig0000070f ; + wire \blk00000003/sig0000070e ; + wire \blk00000003/sig0000070d ; + wire \blk00000003/sig0000070c ; + wire \blk00000003/sig0000070b ; + wire \blk00000003/sig0000070a ; + wire \blk00000003/sig00000709 ; + wire \blk00000003/sig00000708 ; + wire \blk00000003/sig00000707 ; + wire \blk00000003/sig00000706 ; + wire \blk00000003/sig00000705 ; + wire \blk00000003/sig00000704 ; + wire \blk00000003/sig00000703 ; + wire \blk00000003/sig00000702 ; + wire \blk00000003/sig00000701 ; + wire \blk00000003/sig00000700 ; + wire \blk00000003/sig000006ff ; + wire \blk00000003/sig000006fe ; + wire \blk00000003/sig000006fd ; + wire \blk00000003/sig000006fc ; + wire \blk00000003/sig000006fb ; + wire \blk00000003/sig000006fa ; + wire \blk00000003/sig000006f9 ; + wire \blk00000003/sig000006f8 ; + wire \blk00000003/sig000006f7 ; + wire \blk00000003/sig000006f6 ; + wire \blk00000003/sig000006f5 ; + wire \blk00000003/sig000006f4 ; + wire \blk00000003/sig000006f3 ; + wire \blk00000003/sig000006f2 ; + wire \blk00000003/sig000006f1 ; + wire \blk00000003/sig000006f0 ; + wire \blk00000003/sig000006ef ; + wire \blk00000003/sig000006ee ; + wire \blk00000003/sig000006ed ; + wire \blk00000003/sig000006ec ; + wire \blk00000003/sig000006eb ; + wire \blk00000003/sig000006ea ; + wire \blk00000003/sig000006e9 ; + wire \blk00000003/sig000006e8 ; + wire \blk00000003/sig000006e7 ; + wire \blk00000003/sig000006e6 ; + wire \blk00000003/sig000006e5 ; + wire \blk00000003/sig000006e4 ; + wire \blk00000003/sig000006e3 ; + wire \blk00000003/sig000006e2 ; + wire \blk00000003/sig000006e1 ; + wire \blk00000003/sig000006e0 ; + wire \blk00000003/sig000006df ; + wire \blk00000003/sig000006de ; + wire \blk00000003/sig000006dd ; + wire \blk00000003/sig000006dc ; + wire \blk00000003/sig000006db ; + wire \blk00000003/sig000006da ; + wire \blk00000003/sig000006d9 ; + wire \blk00000003/sig000006d8 ; + wire \blk00000003/sig000006d7 ; + wire \blk00000003/sig000006d6 ; + wire \blk00000003/sig000006d5 ; + wire \blk00000003/sig000006d4 ; + wire \blk00000003/sig000006d3 ; + wire \blk00000003/sig000006d2 ; + wire \blk00000003/sig000006d1 ; + wire \blk00000003/sig000006d0 ; + wire \blk00000003/sig000006cf ; + wire \blk00000003/sig000006ce ; + wire \blk00000003/sig000006cd ; + wire \blk00000003/sig000006cc ; + wire \blk00000003/sig000006cb ; + wire \blk00000003/sig000006ca ; + wire \blk00000003/sig000006c9 ; + wire \blk00000003/sig000006c8 ; + wire \blk00000003/sig000006c7 ; + wire \blk00000003/sig000006c6 ; + wire \blk00000003/sig000006c5 ; + wire \blk00000003/sig000006c4 ; + wire \blk00000003/sig000006c3 ; + wire \blk00000003/sig000006c2 ; + wire \blk00000003/sig000006c1 ; + wire \blk00000003/sig000006c0 ; + wire \blk00000003/sig000006bf ; + wire \blk00000003/sig000006be ; + wire \blk00000003/sig000006bd ; + wire \blk00000003/sig000006bc ; + wire \blk00000003/sig000006bb ; + wire \blk00000003/sig000006ba ; + wire \blk00000003/sig000006b9 ; + wire \blk00000003/sig000006b8 ; + wire \blk00000003/sig000006b7 ; + wire \blk00000003/sig000006b6 ; + wire \blk00000003/sig000006b5 ; + wire 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\NLW_blk00000003/blk000006b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000698_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000696_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000694_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000692_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000690_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000068e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000068c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000068a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000688_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000686_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000684_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000682_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000680_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000067e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000067c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000067a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000678_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000676_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000672_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000670_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000066e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000066c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000066a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000668_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000666_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000664_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000662_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000660_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000065e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000065c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000065a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000658_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000656_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000654_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000652_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000650_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000648_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000646_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000644_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000642_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000640_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000638_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000636_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000634_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000632_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000630_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053a_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004d0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000004d0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e4_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000db_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000da_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ca_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c9_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bc_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b6_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a1_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a0_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000098_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000096_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000095_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000094_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000093_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000091_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000090_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001a_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000012_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000c_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000b_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000008c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000066_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000065_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000064_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000063_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000062_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000061_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000060_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000005f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000005e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000005d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000148_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000147_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000146_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000145_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000144_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000143_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000142_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000141_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000140_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000139_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000138_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000137_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000136_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000135_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000134_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000133_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000132_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000131_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000017b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000017a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000179_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000178_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000177_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000176_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000175_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000171_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000170_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000169_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000168_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000167_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000166_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000165_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000164_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk00000199_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk00000198_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk00000197_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000214_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000213_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000212_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000211_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000210_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000209_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000208_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000207_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000206_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000205_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000204_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000203_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000202_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000201_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000200_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk000001ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk000001fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk000001fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000247_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000243_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000242_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000241_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000240_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000239_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000238_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000237_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000236_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000235_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000234_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000233_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000232_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000231_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000230_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000027a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000279_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000278_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000277_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000276_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000275_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000274_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000273_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000272_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000271_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000270_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000269_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000268_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000267_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000266_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000265_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000264_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000263_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk00000299_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk00000298_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk00000297_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk00000296_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002c9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000313_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000312_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000311_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000310_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000309_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000308_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000307_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000306_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000305_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000304_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000303_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000302_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000301_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000300_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk000002ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk000002fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk000002fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk000002fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000346_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000345_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000344_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000343_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000342_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000341_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000340_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000339_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000338_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000337_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000336_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000335_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000334_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000333_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000332_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000331_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000330_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000032f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000379_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000378_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000377_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000376_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000375_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000374_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000373_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000372_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000371_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000370_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000369_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000368_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000367_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000366_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000365_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000364_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000363_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000362_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000472_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000471_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000470_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000469_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000468_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000467_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000466_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000465_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000464_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000463_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000462_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000461_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c5_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c4_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c3_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c2_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c1_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c0_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004bf_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004be_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004bd_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004bc_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004bb_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004ba_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004b9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004b8_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [46 : 0] NlwRenamedSig_OI_dout_1; + wire [46 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000783 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000767 ), + .Q(\blk00000003/sig00000679 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000782 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000004f6 ), + .Q(\blk00000003/sig00000767 ), + .Q15(\NLW_blk00000003/blk00000782_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000781 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000766 ), + .Q(\blk00000003/sig00000604 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000780 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000004f5 ), + .Q(\blk00000003/sig00000766 ), + .Q15(\NLW_blk00000003/blk00000780_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000765 ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000072f ), + .Q(\blk00000003/sig00000765 ), + .Q15(\NLW_blk00000003/blk0000077e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000764 ), + .Q(\blk00000003/sig000001c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000733 ), + .Q(\blk00000003/sig00000764 ), + .Q15(\NLW_blk00000003/blk0000077c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000763 ), + .Q(\blk00000003/sig000001c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000731 ), + .Q(\blk00000003/sig00000763 ), + .Q15(\NLW_blk00000003/blk0000077a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000779 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000762 ), + .Q(\blk00000003/sig000001bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000778 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000072d ), + .Q(\blk00000003/sig00000762 ), + .Q15(\NLW_blk00000003/blk00000778_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000777 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000761 ), + .Q(\blk00000003/sig000001bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000776 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000725 ), + .Q(\blk00000003/sig00000761 ), + .Q15(\NLW_blk00000003/blk00000776_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000775 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000760 ), + .Q(\blk00000003/sig000001bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000774 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000729 ), + .Q(\blk00000003/sig00000760 ), + .Q15(\NLW_blk00000003/blk00000774_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000773 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075f ), + .Q(\blk00000003/sig000001be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000772 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000072b ), + .Q(\blk00000003/sig0000075f ), + .Q15(\NLW_blk00000003/blk00000772_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000771 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075e ), + .Q(\blk00000003/sig000001bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000770 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000727 ), + .Q(\blk00000003/sig0000075e ), + .Q15(\NLW_blk00000003/blk00000770_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075d ), + .Q(\blk00000003/sig000001ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000071f ), + .Q(\blk00000003/sig0000075d ), + .Q15(\NLW_blk00000003/blk0000076e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075c ), + .Q(\blk00000003/sig000001b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000721 ), + .Q(\blk00000003/sig0000075c ), + .Q15(\NLW_blk00000003/blk0000076c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075b ), + .Q(\blk00000003/sig000001b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000719 ), + .Q(\blk00000003/sig0000075b ), + .Q15(\NLW_blk00000003/blk0000076a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000769 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075a ), + .Q(\blk00000003/sig000001b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000768 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000723 ), + .Q(\blk00000003/sig0000075a ), + .Q15(\NLW_blk00000003/blk00000768_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000767 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000759 ), + .Q(\blk00000003/sig000001b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000766 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000071b ), + .Q(\blk00000003/sig00000759 ), + .Q15(\NLW_blk00000003/blk00000766_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000765 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000758 ), + .Q(\blk00000003/sig000001b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000764 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000717 ), + .Q(\blk00000003/sig00000758 ), + .Q15(\NLW_blk00000003/blk00000764_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000763 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000757 ), + .Q(\blk00000003/sig000001b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000762 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000071d ), + .Q(\blk00000003/sig00000757 ), + .Q15(\NLW_blk00000003/blk00000762_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000761 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000756 ), + .Q(\blk00000003/sig000001b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000760 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000070f ), + .Q(\blk00000003/sig00000756 ), + .Q15(\NLW_blk00000003/blk00000760_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000755 ), + .Q(\blk00000003/sig000001b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000713 ), + .Q(\blk00000003/sig00000755 ), + .Q15(\NLW_blk00000003/blk0000075e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000754 ), + .Q(\blk00000003/sig000001b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000715 ), + .Q(\blk00000003/sig00000754 ), + .Q15(\NLW_blk00000003/blk0000075c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000753 ), + .Q(\blk00000003/sig000001b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000711 ), + .Q(\blk00000003/sig00000753 ), + .Q15(\NLW_blk00000003/blk0000075a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000759 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000752 ), + .Q(\blk00000003/sig000001af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000709 ), + .Q(\blk00000003/sig00000752 ), + .Q15(\NLW_blk00000003/blk00000758_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000757 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000751 ), + .Q(\blk00000003/sig000001ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000756 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000070b ), + .Q(\blk00000003/sig00000751 ), + .Q15(\NLW_blk00000003/blk00000756_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000755 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000750 ), + .Q(\blk00000003/sig000001ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000754 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000703 ), + .Q(\blk00000003/sig00000750 ), + .Q15(\NLW_blk00000003/blk00000754_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000753 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074f ), + .Q(\blk00000003/sig000001ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000752 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000070d ), + .Q(\blk00000003/sig0000074f ), + .Q15(\NLW_blk00000003/blk00000752_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000751 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074e ), + .Q(\blk00000003/sig0000014b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000750 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000705 ), + .Q(\blk00000003/sig0000074e ), + .Q15(\NLW_blk00000003/blk00000750_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074d ), + .Q(\blk00000003/sig0000014a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000701 ), + .Q(\blk00000003/sig0000074d ), + .Q15(\NLW_blk00000003/blk0000074e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074c ), + .Q(\blk00000003/sig000001ab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000707 ), + .Q(\blk00000003/sig0000074c ), + .Q15(\NLW_blk00000003/blk0000074c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074b ), + .Q(\blk00000003/sig00000148 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f9 ), + .Q(\blk00000003/sig0000074b ), + .Q15(\NLW_blk00000003/blk0000074a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000749 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074a ), + .Q(\blk00000003/sig00000147 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000748 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006fd ), + .Q(\blk00000003/sig0000074a ), + .Q15(\NLW_blk00000003/blk00000748_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000747 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000749 ), + .Q(\blk00000003/sig00000149 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000746 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006ff ), + .Q(\blk00000003/sig00000749 ), + .Q15(\NLW_blk00000003/blk00000746_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000748 ), + .Q(\blk00000003/sig00000146 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000744 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006fb ), + .Q(\blk00000003/sig00000748 ), + .Q15(\NLW_blk00000003/blk00000744_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000743 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000747 ), + .Q(\blk00000003/sig00000145 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000742 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f3 ), + .Q(\blk00000003/sig00000747 ), + .Q15(\NLW_blk00000003/blk00000742_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000741 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000746 ), + .Q(\blk00000003/sig00000143 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000740 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f5 ), + .Q(\blk00000003/sig00000746 ), + .Q15(\NLW_blk00000003/blk00000740_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000745 ), + .Q(\blk00000003/sig00000142 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006ed ), + .Q(\blk00000003/sig00000745 ), + .Q15(\NLW_blk00000003/blk0000073e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000744 ), + .Q(\blk00000003/sig00000144 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f7 ), + .Q(\blk00000003/sig00000744 ), + .Q15(\NLW_blk00000003/blk0000073c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000743 ), + .Q(\blk00000003/sig00000140 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006ef ), + .Q(\blk00000003/sig00000743 ), + .Q15(\NLW_blk00000003/blk0000073a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000739 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000742 ), + .Q(\blk00000003/sig0000013f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006eb ), + .Q(\blk00000003/sig00000742 ), + .Q15(\NLW_blk00000003/blk00000738_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000737 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000741 ), + .Q(\blk00000003/sig00000141 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000736 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f1 ), + .Q(\blk00000003/sig00000741 ), + .Q15(\NLW_blk00000003/blk00000736_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000735 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000740 ), + .Q(\blk00000003/sig0000013d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000734 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e3 ), + .Q(\blk00000003/sig00000740 ), + .Q15(\NLW_blk00000003/blk00000734_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000733 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073f ), + .Q(\blk00000003/sig0000013c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e7 ), + .Q(\blk00000003/sig0000073f ), + .Q15(\NLW_blk00000003/blk00000732_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000731 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073e ), + .Q(\blk00000003/sig0000013e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000730 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e9 ), + .Q(\blk00000003/sig0000073e ), + .Q15(\NLW_blk00000003/blk00000730_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073d ), + .Q(\blk00000003/sig0000013b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e5 ), + .Q(\blk00000003/sig0000073d ), + .Q15(\NLW_blk00000003/blk0000072e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073c ), + .Q(\blk00000003/sig0000013a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e1 ), + .Q(\blk00000003/sig0000073c ), + .Q15(\NLW_blk00000003/blk0000072c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073b ), + .Q(\blk00000003/sig00000138 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006d9 ), + .Q(\blk00000003/sig0000073b ), + .Q15(\NLW_blk00000003/blk0000072a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000729 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073a ), + .Q(\blk00000003/sig00000137 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000728 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006dd ), + .Q(\blk00000003/sig0000073a ), + .Q15(\NLW_blk00000003/blk00000728_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000727 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000739 ), + .Q(\blk00000003/sig00000139 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000726 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006df ), + .Q(\blk00000003/sig00000739 ), + .Q15(\NLW_blk00000003/blk00000726_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000725 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000738 ), + .Q(\blk00000003/sig00000135 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000724 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006d7 ), + .Q(\blk00000003/sig00000738 ), + .Q15(\NLW_blk00000003/blk00000724_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000723 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000737 ), + .Q(\blk00000003/sig00000134 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000722 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006d5 ), + .Q(\blk00000003/sig00000737 ), + .Q15(\NLW_blk00000003/blk00000722_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000721 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000736 ), + .Q(\blk00000003/sig00000136 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000720 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006db ), + .Q(\blk00000003/sig00000736 ), + .Q15(\NLW_blk00000003/blk00000720_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000735 ), + .Q(\blk00000003/sig000004f6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001df ), + .Q(\blk00000003/sig00000735 ), + .Q15(\NLW_blk00000003/blk0000071e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000734 ), + .Q(\blk00000003/sig0000067a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001c3 ), + .Q(\blk00000003/sig00000734 ), + .Q15(\NLW_blk00000003/blk0000071c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071b ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000732 ), + .Q(\blk00000003/sig00000733 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig00000732 ), + .Q15(\NLW_blk00000003/blk0000071a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000719 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000730 ), + .Q(\blk00000003/sig00000731 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000718 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig00000730 ), + .Q15(\NLW_blk00000003/blk00000718_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000717 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000072e ), + .Q(\blk00000003/sig0000072f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000716 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig0000072e ), + .Q15(\NLW_blk00000003/blk00000716_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000715 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000072c ), + .Q(\blk00000003/sig0000072d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000714 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig0000072c ), + .Q15(\NLW_blk00000003/blk00000714_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000713 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000072a ), + .Q(\blk00000003/sig0000072b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000712 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig0000072a ), + .Q15(\NLW_blk00000003/blk00000712_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000711 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000728 ), + .Q(\blk00000003/sig00000729 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000710 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000728 ), + .Q15(\NLW_blk00000003/blk00000710_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000726 ), + .Q(\blk00000003/sig00000727 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig00000726 ), + .Q15(\NLW_blk00000003/blk0000070e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070d ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000724 ), + .Q(\blk00000003/sig00000725 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig00000724 ), + .Q15(\NLW_blk00000003/blk0000070c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070b ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000722 ), + .Q(\blk00000003/sig00000723 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig00000722 ), + .Q15(\NLW_blk00000003/blk0000070a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000709 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000720 ), + .Q(\blk00000003/sig00000721 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000708 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig00000720 ), + .Q15(\NLW_blk00000003/blk00000708_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000707 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000071e ), + .Q(\blk00000003/sig0000071f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000706 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig0000071e ), + .Q15(\NLW_blk00000003/blk00000706_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000071c ), + .Q(\blk00000003/sig0000071d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000704 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig0000071c ), + .Q15(\NLW_blk00000003/blk00000704_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000703 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000071a ), + .Q(\blk00000003/sig0000071b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000702 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig0000071a ), + .Q15(\NLW_blk00000003/blk00000702_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000701 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000718 ), + .Q(\blk00000003/sig00000719 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000700 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig00000718 ), + .Q15(\NLW_blk00000003/blk00000700_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ff ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000716 ), + .Q(\blk00000003/sig00000717 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig00000716 ), + .Q15(\NLW_blk00000003/blk000006fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fd ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000714 ), + .Q(\blk00000003/sig00000715 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig00000714 ), + .Q15(\NLW_blk00000003/blk000006fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fb ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000712 ), + .Q(\blk00000003/sig00000713 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig00000712 ), + .Q15(\NLW_blk00000003/blk000006fa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000710 ), + .Q(\blk00000003/sig00000711 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig00000710 ), + .Q15(\NLW_blk00000003/blk000006f8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f7 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000070e ), + .Q(\blk00000003/sig0000070f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig0000070e ), + .Q15(\NLW_blk00000003/blk000006f6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f5 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000070c ), + .Q(\blk00000003/sig0000070d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig0000070c ), + .Q15(\NLW_blk00000003/blk000006f4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f3 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000070a ), + .Q(\blk00000003/sig0000070b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig0000070a ), + .Q15(\NLW_blk00000003/blk000006f2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f1 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000708 ), + .Q(\blk00000003/sig00000709 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig00000708 ), + .Q15(\NLW_blk00000003/blk000006f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ef ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000706 ), + .Q(\blk00000003/sig00000707 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ee ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig00000706 ), + .Q15(\NLW_blk00000003/blk000006ee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ed ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000704 ), + .Q(\blk00000003/sig00000705 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ec ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig00000704 ), + .Q15(\NLW_blk00000003/blk000006ec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006eb ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000702 ), + .Q(\blk00000003/sig00000703 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ea ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig00000702 ), + .Q15(\NLW_blk00000003/blk000006ea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e9 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000700 ), + .Q(\blk00000003/sig00000701 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig00000700 ), + .Q15(\NLW_blk00000003/blk000006e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e7 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006fe ), + .Q(\blk00000003/sig000006ff ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000006fe ), + .Q15(\NLW_blk00000003/blk000006e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e5 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006fc ), + .Q(\blk00000003/sig000006fd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000006fc ), + .Q15(\NLW_blk00000003/blk000006e4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e3 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006fa ), + .Q(\blk00000003/sig000006fb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000006fa ), + .Q15(\NLW_blk00000003/blk000006e2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e1 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f8 ), + .Q(\blk00000003/sig000006f9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000006f8 ), + .Q15(\NLW_blk00000003/blk000006e0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006df ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f6 ), + .Q(\blk00000003/sig000006f7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006de ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000006f6 ), + .Q15(\NLW_blk00000003/blk000006de_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006dd ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f4 ), + .Q(\blk00000003/sig000006f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006dc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000006f4 ), + .Q15(\NLW_blk00000003/blk000006dc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006db ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f2 ), + .Q(\blk00000003/sig000006f3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006da ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000006f2 ), + .Q15(\NLW_blk00000003/blk000006da_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d9 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f0 ), + .Q(\blk00000003/sig000006f1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000006f0 ), + .Q15(\NLW_blk00000003/blk000006d8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d7 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006ee ), + .Q(\blk00000003/sig000006ef ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000006ee ), + .Q15(\NLW_blk00000003/blk000006d6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d5 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006ec ), + .Q(\blk00000003/sig000006ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000006ec ), + .Q15(\NLW_blk00000003/blk000006d4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006ea ), + .Q(\blk00000003/sig000006eb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000006ea ), + .Q15(\NLW_blk00000003/blk000006d2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d1 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e8 ), + .Q(\blk00000003/sig000006e9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000006e8 ), + .Q15(\NLW_blk00000003/blk000006d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cf ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e6 ), + .Q(\blk00000003/sig000006e7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ce ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000006e6 ), + .Q15(\NLW_blk00000003/blk000006ce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cd ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e4 ), + .Q(\blk00000003/sig000006e5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006cc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000006e4 ), + .Q15(\NLW_blk00000003/blk000006cc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cb ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e2 ), + .Q(\blk00000003/sig000006e3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ca ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000006e2 ), + .Q15(\NLW_blk00000003/blk000006ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c9 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e0 ), + .Q(\blk00000003/sig000006e1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000006e0 ), + .Q15(\NLW_blk00000003/blk000006c8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c7 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006de ), + .Q(\blk00000003/sig000006df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000006de ), + .Q15(\NLW_blk00000003/blk000006c6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c5 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006dc ), + .Q(\blk00000003/sig000006dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000006dc ), + .Q15(\NLW_blk00000003/blk000006c4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c3 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006da ), + .Q(\blk00000003/sig000006db ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig000006da ), + .Q15(\NLW_blk00000003/blk000006c2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c1 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006d8 ), + .Q(\blk00000003/sig000006d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000006d8 ), + .Q15(\NLW_blk00000003/blk000006c0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bf ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006d6 ), + .Q(\blk00000003/sig000006d7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006be ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001e9 ), + .Q(\blk00000003/sig000006d6 ), + .Q15(\NLW_blk00000003/blk000006be_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bd ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006d4 ), + .Q(\blk00000003/sig000006d5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006bc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001e8 ), + .Q(\blk00000003/sig000006d4 ), + .Q15(\NLW_blk00000003/blk000006bc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006d3 ), + .Q(\blk00000003/sig00000682 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ba ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000004e5 ), + .Q(\blk00000003/sig000006d3 ), + .Q15(\NLW_blk00000003/blk000006ba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006d2 ), + .Q(\blk00000003/sig0000056e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b8 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig000006d2 ), + .Q15(\NLW_blk00000003/blk000006b8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006d1 ), + .Q(\blk00000003/sig00000681 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000004e6 ), + .Q(\blk00000003/sig000006d1 ), + .Q15(\NLW_blk00000003/blk000006b6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006d0 ), + .Q(\blk00000003/sig0000056c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b4 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig000006d0 ), + .Q15(\NLW_blk00000003/blk000006b4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006cf ), + .Q(\blk00000003/sig0000056b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b2 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig000006cf ), + .Q15(\NLW_blk00000003/blk000006b2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ce ), + .Q(\blk00000003/sig0000056d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b0 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig000006ce ), + .Q15(\NLW_blk00000003/blk000006b0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006cd ), + .Q(\blk00000003/sig00000569 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ae ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig000006cd ), + .Q15(\NLW_blk00000003/blk000006ae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006cc ), + .Q(\blk00000003/sig00000568 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ac ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig000006cc ), + .Q15(\NLW_blk00000003/blk000006ac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006cb ), + .Q(\blk00000003/sig0000056a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006aa ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig000006cb ), + .Q15(\NLW_blk00000003/blk000006aa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ca ), + .Q(\blk00000003/sig00000567 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a8 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig000006ca ), + .Q15(\NLW_blk00000003/blk000006a8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c9 ), + .Q(\blk00000003/sig00000566 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a6 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig000006c9 ), + .Q15(\NLW_blk00000003/blk000006a6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c8 ), + .Q(\blk00000003/sig00000564 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a4 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig000006c8 ), + .Q15(\NLW_blk00000003/blk000006a4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c7 ), + .Q(\blk00000003/sig00000563 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a2 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig000006c7 ), + .Q15(\NLW_blk00000003/blk000006a2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c6 ), + .Q(\blk00000003/sig00000565 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a0 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig000006c6 ), + .Q15(\NLW_blk00000003/blk000006a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c5 ), + .Q(\blk00000003/sig00000561 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig000006c5 ), + .Q15(\NLW_blk00000003/blk0000069e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c4 ), + .Q(\blk00000003/sig00000560 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig000006c4 ), + .Q15(\NLW_blk00000003/blk0000069c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c3 ), + .Q(\blk00000003/sig00000562 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig000006c3 ), + .Q15(\NLW_blk00000003/blk0000069a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000699 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c2 ), + .Q(\blk00000003/sig0000055e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000698 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig000006c2 ), + .Q15(\NLW_blk00000003/blk00000698_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000697 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c1 ), + .Q(\blk00000003/sig0000055d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000696 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig000006c1 ), + .Q15(\NLW_blk00000003/blk00000696_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000695 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c0 ), + .Q(\blk00000003/sig0000055f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000694 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig000006c0 ), + .Q15(\NLW_blk00000003/blk00000694_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006bf ), + .Q(\blk00000003/sig0000055c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000692 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig000006bf ), + .Q15(\NLW_blk00000003/blk00000692_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000691 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006be ), + .Q(\blk00000003/sig0000055b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000690 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig000006be ), + .Q15(\NLW_blk00000003/blk00000690_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006bd ), + .Q(\blk00000003/sig00000559 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig000006bd ), + .Q15(\NLW_blk00000003/blk0000068e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006bc ), + .Q(\blk00000003/sig00000558 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000006bc ), + .Q15(\NLW_blk00000003/blk0000068c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006bb ), + .Q(\blk00000003/sig0000055a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig000006bb ), + .Q15(\NLW_blk00000003/blk0000068a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000689 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ba ), + .Q(\blk00000003/sig0000059e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000688 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000006ba ), + .Q15(\NLW_blk00000003/blk00000688_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b9 ), + .Q(\blk00000003/sig0000059d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000686 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000006b9 ), + .Q15(\NLW_blk00000003/blk00000686_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000685 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b8 ), + .Q(\blk00000003/sig00000557 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000684 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000006b8 ), + .Q15(\NLW_blk00000003/blk00000684_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000683 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b7 ), + .Q(\blk00000003/sig0000059b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000682 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000006b7 ), + .Q15(\NLW_blk00000003/blk00000682_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000681 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b6 ), + .Q(\blk00000003/sig0000059a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000680 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000006b6 ), + .Q15(\NLW_blk00000003/blk00000680_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b5 ), + .Q(\blk00000003/sig0000059c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000006b5 ), + .Q15(\NLW_blk00000003/blk0000067e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b4 ), + .Q(\blk00000003/sig00000599 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000006b4 ), + .Q15(\NLW_blk00000003/blk0000067c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b3 ), + .Q(\blk00000003/sig00000598 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000006b3 ), + .Q15(\NLW_blk00000003/blk0000067a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000679 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b2 ), + .Q(\blk00000003/sig00000596 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000678 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000006b2 ), + .Q15(\NLW_blk00000003/blk00000678_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000677 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b1 ), + .Q(\blk00000003/sig00000595 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000676 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000006b1 ), + .Q15(\NLW_blk00000003/blk00000676_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000675 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b0 ), + .Q(\blk00000003/sig00000597 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000006b0 ), + .Q15(\NLW_blk00000003/blk00000674_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000673 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006af ), + .Q(\blk00000003/sig00000593 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000672 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000006af ), + .Q15(\NLW_blk00000003/blk00000672_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000671 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ae ), + .Q(\blk00000003/sig00000592 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000670 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000006ae ), + .Q15(\NLW_blk00000003/blk00000670_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ad ), + .Q(\blk00000003/sig00000594 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000006ad ), + .Q15(\NLW_blk00000003/blk0000066e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ac ), + .Q(\blk00000003/sig00000590 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000006ac ), + .Q15(\NLW_blk00000003/blk0000066c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ab ), + .Q(\blk00000003/sig0000058f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000006ab ), + .Q15(\NLW_blk00000003/blk0000066a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000669 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006aa ), + .Q(\blk00000003/sig00000591 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000668 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000006aa ), + .Q15(\NLW_blk00000003/blk00000668_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000667 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a9 ), + .Q(\blk00000003/sig0000058e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000666 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000006a9 ), + .Q15(\NLW_blk00000003/blk00000666_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000665 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a8 ), + .Q(\blk00000003/sig0000058d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000664 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000006a8 ), + .Q15(\NLW_blk00000003/blk00000664_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000663 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a7 ), + .Q(\blk00000003/sig0000058b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000662 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000006a7 ), + .Q15(\NLW_blk00000003/blk00000662_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a6 ), + .Q(\blk00000003/sig0000058a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000660 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000006a6 ), + .Q15(\NLW_blk00000003/blk00000660_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a5 ), + .Q(\blk00000003/sig0000058c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000065e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000006a5 ), + .Q15(\NLW_blk00000003/blk0000065e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a4 ), + .Q(\blk00000003/sig00000588 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000065c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e9 ), + .Q(\blk00000003/sig000006a4 ), + .Q15(\NLW_blk00000003/blk0000065c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a3 ), + .Q(\blk00000003/sig00000587 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000065a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e8 ), + .Q(\blk00000003/sig000006a3 ), + .Q15(\NLW_blk00000003/blk0000065a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000659 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a2 ), + .Q(\blk00000003/sig00000589 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000658 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig000006a2 ), + .Q15(\NLW_blk00000003/blk00000658_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000657 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a1 ), + .Q(\blk00000003/sig000002c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000656 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a8 ), + .Q(\blk00000003/sig000006a1 ), + .Q15(\NLW_blk00000003/blk00000656_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000655 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a0 ), + .Q(\blk00000003/sig00000680 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000654 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d0 ), + .Q(\blk00000003/sig000006a0 ), + .Q15(\NLW_blk00000003/blk00000654_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000653 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069f ), + .Q(\blk00000003/sig000002c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000652 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d4 ), + .Q(\blk00000003/sig0000069f ), + .Q15(\NLW_blk00000003/blk00000652_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000651 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069e ), + .Q(\blk00000003/sig000005c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000650 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig0000069e ), + .Q15(\NLW_blk00000003/blk00000650_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069d ), + .Q(\blk00000003/sig000005c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig0000069d ), + .Q15(\NLW_blk00000003/blk0000064e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069c ), + .Q(\blk00000003/sig000005c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig0000069c ), + .Q15(\NLW_blk00000003/blk0000064c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069b ), + .Q(\blk00000003/sig000005c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig0000069b ), + .Q15(\NLW_blk00000003/blk0000064a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000649 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069a ), + .Q(\blk00000003/sig000005c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000648 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig0000069a ), + .Q15(\NLW_blk00000003/blk00000648_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000647 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000699 ), + .Q(\blk00000003/sig000005c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000646 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig00000699 ), + .Q15(\NLW_blk00000003/blk00000646_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000645 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000698 ), + .Q(\blk00000003/sig000005c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000644 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig00000698 ), + .Q15(\NLW_blk00000003/blk00000644_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000643 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000697 ), + .Q(\blk00000003/sig000005c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000642 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig00000697 ), + .Q15(\NLW_blk00000003/blk00000642_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000641 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000696 ), + .Q(\blk00000003/sig000005bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000640 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig00000696 ), + .Q15(\NLW_blk00000003/blk00000640_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000695 ), + .Q(\blk00000003/sig000005be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig00000695 ), + .Q15(\NLW_blk00000003/blk0000063e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000694 ), + .Q(\blk00000003/sig000005c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig00000694 ), + .Q15(\NLW_blk00000003/blk0000063c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000693 ), + .Q(\blk00000003/sig000005bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig00000693 ), + .Q15(\NLW_blk00000003/blk0000063a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000639 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000692 ), + .Q(\blk00000003/sig000005bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000638 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig00000692 ), + .Q15(\NLW_blk00000003/blk00000638_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000637 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000691 ), + .Q(\blk00000003/sig000005ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000636 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig00000691 ), + .Q15(\NLW_blk00000003/blk00000636_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000635 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000690 ), + .Q(\blk00000003/sig000005b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000634 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig00000690 ), + .Q15(\NLW_blk00000003/blk00000634_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000633 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068f ), + .Q(\blk00000003/sig000005bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000632 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig0000068f ), + .Q15(\NLW_blk00000003/blk00000632_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068e ), + .Q(\blk00000003/sig000005b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000630 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig0000068e ), + .Q15(\NLW_blk00000003/blk00000630_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068d ), + .Q(\blk00000003/sig000005b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig0000068d ), + .Q15(\NLW_blk00000003/blk0000062e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068c ), + .Q(\blk00000003/sig000004f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d6 ), + .Q(\blk00000003/sig0000068c ), + .Q15(\NLW_blk00000003/blk0000062c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068b ), + .Q(\blk00000003/sig000005f0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ce ), + .Q(\blk00000003/sig0000068b ), + .Q15(\NLW_blk00000003/blk0000062a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000629 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068a ), + .Q(\blk00000003/sig000001df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e1 ), + .Q(\blk00000003/sig0000068a ), + .Q15(\NLW_blk00000003/blk00000628_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk00000627 ( + .I(\blk00000003/sig0000023e ), + .O(\blk00000003/sig0000027e ) + ); + INV \blk00000003/blk00000626 ( + .I(\blk00000003/sig00000287 ), + .O(\blk00000003/sig00000277 ) + ); + INV \blk00000003/blk00000625 ( + .I(\blk00000003/sig000001ce ), + .O(\blk00000003/sig0000028c ) + ); + INV \blk00000003/blk00000624 ( + .I(\blk00000003/sig0000028e ), + .O(\blk00000003/sig0000027d ) + ); + INV \blk00000003/blk00000623 ( + .I(\blk00000003/sig000005ff ), + .O(\blk00000003/sig00000678 ) + ); + INV \blk00000003/blk00000622 ( + .I(\blk00000003/sig00000242 ), + .O(\blk00000003/sig0000028f ) + ); + INV \blk00000003/blk00000621 ( + .I(\blk00000003/sig0000023e ), + .O(\blk00000003/sig00000278 ) + ); + INV \blk00000003/blk00000620 ( + .I(\blk00000003/sig0000021b ), + .O(\blk00000003/sig00000243 ) + ); + INV \blk00000003/blk0000061f ( + .I(\blk00000003/sig000001cc ), + .O(\blk00000003/sig000000ba ) + ); + INV \blk00000003/blk0000061e ( + .I(\blk00000003/sig000000ad ), + .O(\blk00000003/sig000001c7 ) + ); + INV \blk00000003/blk0000061d ( + .I(\blk00000003/sig000000b7 ), + .O(\blk00000003/sig000000b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000604 ), + .Q(\blk00000003/sig0000067c ) + ); + LUT3 #( + .INIT ( 8'h40 )) + \blk00000003/blk0000061b ( + .I0(\blk00000003/sig0000024b ), + .I1(\blk00000003/sig00000234 ), + .I2(coef_ld), + .O(\blk00000003/sig00000247 ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk0000061a ( + .I0(\blk00000003/sig00000248 ), + .I1(\blk00000003/sig0000023c ), + .I2(\blk00000003/sig0000024b ), + .I3(coef_ld), + .I4(\blk00000003/sig00000234 ), + .O(\blk00000003/sig0000023f ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk00000619 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000236 ), + .I2(coef_we), + .I3(\blk00000003/sig00000234 ), + .O(\blk00000003/sig00000246 ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk00000618 ( + .I0(\blk00000003/sig00000234 ), + .I1(\blk00000003/sig00000236 ), + .I2(coef_we), + .I3(\blk00000003/sig0000024b ), + .I4(coef_ld), + .O(\blk00000003/sig00000245 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000617 ( + .I0(\blk00000003/sig00000287 ), + .I1(ce), + .I2(\blk00000003/sig0000023c ), + .I3(\blk00000003/sig00000219 ), + .O(\blk00000003/sig00000689 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000616 ( + .I0(\blk00000003/sig0000028e ), + .I1(ce), + .I2(\blk00000003/sig0000023a ), + .I3(\blk00000003/sig0000027f ), + .O(\blk00000003/sig00000688 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000615 ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .I2(\blk00000003/sig000001d4 ), + .I3(\blk00000003/sig000001d6 ), + .O(\blk00000003/sig00000686 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000614 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig0000067f ), + .O(\blk00000003/sig00000685 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000613 ( + .I0(ce), + .I1(\blk00000003/sig0000024b ), + .I2(\blk00000003/sig0000067d ), + .O(\blk00000003/sig00000684 ) + ); + LUT5 #( + .INIT ( 32'h6AAAAAAA )) + \blk00000003/blk00000612 ( + .I0(\blk00000003/sig0000067e ), + .I1(\blk00000003/sig00000291 ), + .I2(ce), + .I3(nd), + .I4(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000687 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk00000611 ( + .C(clk), + .D(\blk00000003/sig00000689 ), + .Q(\blk00000003/sig00000287 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk00000610 ( + .C(clk), + .D(\blk00000003/sig00000688 ), + .Q(\blk00000003/sig0000028e ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060f ( + .C(clk), + .D(\blk00000003/sig00000687 ), + .R(sclr), + .Q(\blk00000003/sig0000067e ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060e ( + .C(clk), + .D(\blk00000003/sig00000686 ), + .R(sclr), + .Q(\blk00000003/sig0000067b ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000060d ( + .I0(\blk00000003/sig00000602 ), + .O(\blk00000003/sig000005fd ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000060c ( + .I0(\blk00000003/sig00000601 ), + .O(\blk00000003/sig000005fa ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000060b ( + .I0(\blk00000003/sig00000600 ), + .O(\blk00000003/sig000005f7 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000060a ( + .I0(\blk00000003/sig000005ff ), + .O(\blk00000003/sig000005f4 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000609 ( + .I0(\blk00000003/sig000002be ), + .O(\blk00000003/sig000002bf ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000608 ( + .I0(\blk00000003/sig000002ba ), + .O(\blk00000003/sig000002bb ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000607 ( + .I0(\blk00000003/sig000002a6 ), + .O(\blk00000003/sig000002a0 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000606 ( + .I0(\blk00000003/sig0000067e ), + .O(\blk00000003/sig00000296 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000605 ( + .I0(\blk00000003/sig00000268 ), + .O(\blk00000003/sig00000269 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000604 ( + .I0(\blk00000003/sig00000264 ), + .O(\blk00000003/sig00000265 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000603 ( + .I0(\blk00000003/sig00000256 ), + .O(\blk00000003/sig00000254 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000602 ( + .I0(\blk00000003/sig0000024f ), + .O(\blk00000003/sig0000024d ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000601 ( + .I0(\blk00000003/sig0000024f ), + .I1(\blk00000003/sig00000252 ), + .O(\blk00000003/sig0000022a ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000600 ( + .I0(\blk00000003/sig000001cc ), + .O(\blk00000003/sig000000bb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000672 ), + .R(sclr), + .Q(\blk00000003/sig00000677 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000066f ), + .R(sclr), + .Q(\blk00000003/sig00000676 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000066c ), + .R(sclr), + .Q(\blk00000003/sig00000675 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000669 ), + .R(sclr), + .Q(\blk00000003/sig00000674 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000666 ), + .R(sclr), + .Q(\blk00000003/sig00000673 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005f2 ), + .R(sclr), + .Q(\blk00000003/sig00000603 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005fe ), + .S(sclr), + .Q(\blk00000003/sig00000602 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005fb ), + .R(sclr), + .Q(\blk00000003/sig00000601 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005f8 ), + .R(sclr), + .Q(\blk00000003/sig00000600 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005f5 ), + .S(sclr), + .Q(\blk00000003/sig000005ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c0 ), + .R(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig000002be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002bd ), + .R(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig000002ba ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b3 ), + .S(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002b8 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b6 ), + .S(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ab ), + .R(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ae ), + .R(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002b0 ) + ); + FDR \blk00000003/blk000005ef ( + .C(clk), + .D(\blk00000003/sig00000685 ), + .R(ce), + .Q(\blk00000003/sig0000067f ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a1 ), + .S(sclr), + .Q(\blk00000003/sig000002a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a4 ), + .R(sclr), + .Q(\blk00000003/sig000002a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029b ), + .R(sclr), + .Q(\blk00000003/sig000001e7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029e ), + .R(sclr), + .Q(\blk00000003/sig000001e6 ) + ); + FDR \blk00000003/blk000005ea ( + .C(clk), + .D(\blk00000003/sig00000684 ), + .R(ce), + .Q(\blk00000003/sig0000067d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026a ), + .R(\blk00000003/sig0000026d ), + .Q(\blk00000003/sig00000268 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000267 ), + .R(\blk00000003/sig0000026d ), + .Q(\blk00000003/sig00000264 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025c ), + .R(coef_ld), + .Q(\blk00000003/sig00000262 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025f ), + .R(coef_ld), + .Q(\blk00000003/sig00000261 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000258 ), + .R(sclr), + .Q(\blk00000003/sig00000259 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000255 ), + .R(sclr), + .Q(\blk00000003/sig00000256 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000251 ), + .R(coef_ld), + .Q(\blk00000003/sig00000252 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024e ), + .R(coef_ld), + .Q(\blk00000003/sig0000024f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000af ), + .R(sclr), + .Q(\blk00000003/sig000000ad ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005e0 ( + .I0(\blk00000003/sig00000673 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig00000665 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005df ( + .I0(\blk00000003/sig00000674 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig00000668 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005de ( + .I0(\blk00000003/sig00000675 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig0000066b ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005dd ( + .I0(\blk00000003/sig00000676 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig0000066e ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk000005dc ( + .I0(\blk00000003/sig00000677 ), + .I1(\blk00000003/sig000005ff ), + .I2(\blk00000003/sig000001dd ), + .O(\blk00000003/sig00000671 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk000005db ( + .I0(\blk00000003/sig000001dd ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig000005ff ), + .O(\blk00000003/sig00000663 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005da ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000106 ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig00000661 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d9 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000105 ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig00000662 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d8 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000107 ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig00000660 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d7 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000109 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig0000065e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d6 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000108 ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig0000065f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d5 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010a ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig0000065d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d4 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010c ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig0000065b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d3 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010b ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig0000065c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d2 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010d ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig0000065a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d1 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010f ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig00000658 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d0 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010e ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig00000659 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cf ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000110 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig00000657 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ce ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000112 ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig00000655 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cd ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000111 ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig00000656 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cc ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000113 ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig00000654 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cb ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000115 ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig00000652 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ca ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000114 ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig00000653 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c9 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000116 ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig00000651 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c8 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000118 ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig0000064f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c7 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000117 ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig00000650 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c6 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000119 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig0000064e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c5 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011b ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig0000064c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c4 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011a ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig0000064d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c3 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011c ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig0000064b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c2 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011e ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig00000649 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c1 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011d ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig0000064a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c0 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011f ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig00000648 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bf ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000121 ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig00000646 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005be ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000120 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig00000647 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bd ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000122 ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig00000645 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bc ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000124 ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig00000643 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bb ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000123 ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig00000644 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ba ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000125 ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig00000642 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b9 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000127 ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig00000640 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b8 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000126 ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig00000641 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b7 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000128 ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig0000063f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b6 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012a ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig0000063d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b5 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000129 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig0000063e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b4 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012b ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig0000063c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b3 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012d ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig0000063a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b2 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012c ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig0000063b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b1 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012e ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig00000639 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b0 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000130 ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig00000637 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005af ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012f ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig00000638 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ae ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000131 ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig00000636 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ad ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000132 ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig00000635 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ac ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000017c ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig00000633 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ab ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000133 ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig00000634 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005aa ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000017d ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig00000632 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a9 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000017f ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig00000630 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a8 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000017e ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig00000631 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a7 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000180 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig0000062f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a6 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000182 ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig0000062d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a5 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000181 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig0000062e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a4 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000183 ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig0000062c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a3 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000185 ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig0000062a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a2 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000184 ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig0000062b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a1 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000186 ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig00000629 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a0 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000188 ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig00000627 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059f ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000187 ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig00000628 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059e ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000189 ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig00000626 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059d ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018b ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig00000624 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059c ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018a ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig00000625 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059b ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018c ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig00000623 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059a ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018e ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig00000621 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000599 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018d ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig00000622 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000598 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018f ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig00000620 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000597 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000191 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig0000061e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000596 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000190 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig0000061f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000595 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000192 ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig0000061d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000594 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000194 ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig0000061b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000593 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000193 ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig0000061c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000592 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000195 ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig0000061a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000591 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000197 ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig00000618 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000590 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000196 ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig00000619 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058f ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000198 ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig00000617 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058e ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019a ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig00000615 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058d ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000199 ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig00000616 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058c ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019b ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig00000614 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058b ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019d ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig00000612 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058a ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019c ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig00000613 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000589 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019e ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig00000611 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000588 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a0 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig0000060f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000587 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019f ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig00000610 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000586 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a1 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig0000060e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000585 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a3 ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig0000060c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000584 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a2 ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig0000060d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000583 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a4 ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig0000060b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000582 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a6 ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig00000609 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000581 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a5 ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig0000060a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000580 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a7 ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig00000608 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000057f ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a9 ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig00000606 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000057e ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a8 ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig00000607 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000057d ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001aa ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig00000605 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000057c ( + .I0(\blk00000003/sig00000603 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig000005f1 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000057b ( + .I0(ce), + .I1(\blk00000003/sig000001df ), + .O(\blk00000003/sig00000683 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000057a ( + .I0(ce), + .I1(\blk00000003/sig000004e4 ), + .O(\blk00000003/sig000005ef ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000579 ( + .I0(ce), + .I1(\blk00000003/sig00000682 ), + .O(\blk00000003/sig000005ee ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000578 ( + .I0(ce), + .I1(\blk00000003/sig00000681 ), + .O(\blk00000003/sig000005ed ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000577 ( + .I0(\blk00000003/sig000002b7 ), + .I1(\blk00000003/sig000002c1 ), + .O(\blk00000003/sig000002b5 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000576 ( + .I0(\blk00000003/sig000002c1 ), + .I1(\blk00000003/sig000002b8 ), + .O(\blk00000003/sig000002b2 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000575 ( + .I0(\blk00000003/sig000002c1 ), + .I1(\blk00000003/sig00000680 ), + .O(\blk00000003/sig000002af ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk00000574 ( + .I0(\blk00000003/sig000002b0 ), + .I1(\blk00000003/sig000002c1 ), + .I2(\blk00000003/sig00000680 ), + .O(\blk00000003/sig000002ad ) + ); + LUT3 #( + .INIT ( 8'hBC )) + \blk00000003/blk00000573 ( + .I0(\blk00000003/sig00000680 ), + .I1(\blk00000003/sig000002c1 ), + .I2(\blk00000003/sig000002b1 ), + .O(\blk00000003/sig000002aa ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000572 ( + .I0(sclr), + .I1(\blk00000003/sig0000067f ), + .O(\blk00000003/sig000002a7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000571 ( + .I0(\blk00000003/sig000002a5 ), + .I1(\blk00000003/sig000001d6 ), + .O(\blk00000003/sig000002a3 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000570 ( + .I0(nd), + .I1(\blk00000003/sig00000298 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000029f ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk0000056f ( + .I0(\blk00000003/sig000001e6 ), + .I1(nd), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig00000298 ), + .O(\blk00000003/sig0000029d ) + ); + LUT4 #( + .INIT ( 16'hDFA0 )) + \blk00000003/blk0000056e ( + .I0(nd), + .I1(\blk00000003/sig00000298 ), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000001e7 ), + .O(\blk00000003/sig0000029a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000056d ( + .I0(nd), + .I1(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000293 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk0000056c ( + .I0(\blk00000003/sig0000067e ), + .I1(\blk00000003/sig000001e6 ), + .I2(\blk00000003/sig000001e7 ), + .O(\blk00000003/sig00000295 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000056b ( + .I0(\blk00000003/sig0000023b ), + .I1(\blk00000003/sig00000242 ), + .O(\blk00000003/sig0000028d ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000056a ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig0000023a ), + .O(\blk00000003/sig0000028a ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000569 ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig0000023e ), + .O(\blk00000003/sig00000288 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000568 ( + .I0(\blk00000003/sig00000240 ), + .I1(\blk00000003/sig00000248 ), + .I2(\blk00000003/sig00000242 ), + .O(\blk00000003/sig00000283 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000567 ( + .I0(\blk00000003/sig00000240 ), + .I1(\blk00000003/sig0000023e ), + .I2(\blk00000003/sig00000242 ), + .O(\blk00000003/sig00000285 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000566 ( + .I0(\blk00000003/sig0000023b ), + .I1(\blk00000003/sig0000023e ), + .O(\blk00000003/sig0000027c ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000565 ( + .I0(\blk00000003/sig0000023a ), + .I1(\blk00000003/sig0000023e ), + .O(\blk00000003/sig0000027a ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000564 ( + .I0(\blk00000003/sig00000238 ), + .I1(\blk00000003/sig00000242 ), + .I2(\blk00000003/sig0000023e ), + .O(\blk00000003/sig00000275 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000563 ( + .I0(\blk00000003/sig0000023d ), + .I1(\blk00000003/sig0000023e ), + .O(\blk00000003/sig00000271 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000562 ( + .I0(\blk00000003/sig0000023c ), + .I1(\blk00000003/sig0000023e ), + .I2(\blk00000003/sig00000248 ), + .O(\blk00000003/sig00000273 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000561 ( + .I0(\blk00000003/sig0000024b ), + .I1(\blk00000003/sig0000067d ), + .O(\blk00000003/sig0000026c ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000560 ( + .I0(coef_we), + .I1(\blk00000003/sig00000222 ), + .I2(\blk00000003/sig00000227 ), + .O(\blk00000003/sig00000260 ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk0000055f ( + .I0(\blk00000003/sig00000261 ), + .I1(coef_we), + .I2(\blk00000003/sig00000227 ), + .I3(\blk00000003/sig00000222 ), + .O(\blk00000003/sig0000025e ) + ); + LUT4 #( + .INIT ( 16'hE6CC )) + \blk00000003/blk0000055e ( + .I0(coef_we), + .I1(\blk00000003/sig00000262 ), + .I2(\blk00000003/sig00000222 ), + .I3(\blk00000003/sig00000227 ), + .O(\blk00000003/sig0000025b ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000055d ( + .I0(\blk00000003/sig00000259 ), + .I1(\blk00000003/sig000001c3 ), + .O(\blk00000003/sig00000257 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000055c ( + .I0(\blk00000003/sig00000252 ), + .I1(coef_we), + .O(\blk00000003/sig00000250 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000055b ( + .I0(coef_ld), + .I1(\blk00000003/sig0000024b ), + .O(\blk00000003/sig00000241 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000055a ( + .I0(coef_we), + .I1(\blk00000003/sig00000227 ), + .O(\blk00000003/sig00000223 ) + ); + LUT3 #( + .INIT ( 8'h40 )) + \blk00000003/blk00000559 ( + .I0(coef_ld), + .I1(coef_we), + .I2(\blk00000003/sig00000236 ), + .O(\blk00000003/sig00000249 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000558 ( + .I0(\blk00000003/sig00000261 ), + .I1(\blk00000003/sig00000262 ), + .O(\blk00000003/sig0000022d ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000557 ( + .I0(\blk00000003/sig0000024f ), + .I1(\blk00000003/sig00000252 ), + .O(\blk00000003/sig00000229 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000556 ( + .I0(\blk00000003/sig00000262 ), + .I1(\blk00000003/sig00000261 ), + .O(\blk00000003/sig00000225 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000555 ( + .I0(coef_ld), + .I1(\blk00000003/sig0000024b ), + .I2(\blk00000003/sig00000234 ), + .O(\blk00000003/sig00000220 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000554 ( + .I0(coef_we), + .I1(\blk00000003/sig00000236 ), + .I2(\blk00000003/sig00000234 ), + .O(\blk00000003/sig0000021d ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk00000553 ( + .I0(\blk00000003/sig00000236 ), + .I1(coef_we), + .I2(\blk00000003/sig00000227 ), + .I3(\blk00000003/sig00000222 ), + .I4(coef_ld), + .O(\blk00000003/sig00000235 ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk00000552 ( + .I0(\blk00000003/sig00000234 ), + .I1(\blk00000003/sig00000236 ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig00000233 ) + ); + LUT3 #( + .INIT ( 8'h80 )) + \blk00000003/blk00000551 ( + .I0(nd), + .I1(\blk00000003/sig00000291 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000001e5 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000550 ( + .I0(\blk00000003/sig000000bf ), + .I1(\blk00000003/sig000001dd ), + .O(\blk00000003/sig000001e3 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk0000054f ( + .I0(\blk00000003/sig000000bf ), + .I1(\blk00000003/sig000005ff ), + .I2(\blk00000003/sig0000067c ), + .O(\blk00000003/sig000000c0 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk0000054e ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig000005ff ), + .O(\blk00000003/sig000001de ) + ); + LUT2 #( + .INIT ( 4'hD )) + \blk00000003/blk0000054d ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .O(\blk00000003/sig000001ca ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000054c ( + .I0(\blk00000003/sig00000256 ), + .I1(\blk00000003/sig00000259 ), + .O(\blk00000003/sig000001c4 ) + ); + LUT5 #( + .INIT ( 32'h00002000 )) + \blk00000003/blk0000054b ( + .I0(\blk00000003/sig00000673 ), + .I1(\blk00000003/sig00000674 ), + .I2(\blk00000003/sig00000675 ), + .I3(\blk00000003/sig00000676 ), + .I4(\blk00000003/sig00000677 ), + .O(\blk00000003/sig000000c2 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk0000054a ( + .I0(\blk00000003/sig000001d6 ), + .I1(\blk00000003/sig000001c3 ), + .I2(\blk00000003/sig000001e4 ), + .O(\blk00000003/sig000001d5 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000549 ( + .I0(\blk00000003/sig000002a6 ), + .I1(\blk00000003/sig000001e2 ), + .O(\blk00000003/sig000001db ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000548 ( + .I0(ce), + .I1(\blk00000003/sig00000679 ), + .I2(\blk00000003/sig000000b5 ), + .O(\blk00000003/sig000000b4 ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000547 ( + .I0(ce), + .I1(\blk00000003/sig00000679 ), + .I2(\blk00000003/sig000000b3 ), + .O(\blk00000003/sig000000b2 ) + ); + LUT4 #( + .INIT ( 16'h8F88 )) + \blk00000003/blk00000546 ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .I2(\blk00000003/sig000001d8 ), + .I3(\blk00000003/sig000001c6 ), + .O(\blk00000003/sig000001d7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000545 ( + .I0(\blk00000003/sig000000ad ), + .I1(\blk00000003/sig000001c6 ), + .O(\blk00000003/sig000000ae ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk00000544 ( + .I0(\blk00000003/sig000001c3 ), + .I1(\blk00000003/sig000001e4 ), + .I2(\blk00000003/sig000001d4 ), + .I3(\blk00000003/sig000001d6 ), + .I4(\blk00000003/sig000001d2 ), + .O(\blk00000003/sig000001d3 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk00000543 ( + .I0(\blk00000003/sig000001d4 ), + .I1(\blk00000003/sig0000067b ), + .I2(\blk00000003/sig000001d6 ), + .I3(\blk00000003/sig000001e4 ), + .O(\blk00000003/sig000001cf ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk00000542 ( + .I0(\blk00000003/sig000001e4 ), + .I1(\blk00000003/sig000001d4 ), + .I2(\blk00000003/sig000001d6 ), + .I3(\blk00000003/sig000001d2 ), + .O(\blk00000003/sig000001d1 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk00000541 ( + .I0(\blk00000003/sig000002a5 ), + .I1(\blk00000003/sig000002a6 ), + .I2(\blk00000003/sig000001e2 ), + .O(\blk00000003/sig000001d9 ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk00000540 ( + .I0(ce), + .I1(\blk00000003/sig00000679 ), + .I2(\blk00000003/sig0000067a ), + .I3(\blk00000003/sig000000b1 ), + .O(\blk00000003/sig000000b0 ) + ); + MUXCY \blk00000003/blk0000053f ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000678 ), + .O(\blk00000003/sig00000670 ) + ); + MUXCY_L \blk00000003/blk0000053e ( + .CI(\blk00000003/sig00000670 ), + .DI(\blk00000003/sig00000677 ), + .S(\blk00000003/sig00000671 ), + .LO(\blk00000003/sig0000066d ) + ); + MUXCY_L \blk00000003/blk0000053d ( + .CI(\blk00000003/sig0000066d ), + .DI(\blk00000003/sig00000676 ), + .S(\blk00000003/sig0000066e ), + .LO(\blk00000003/sig0000066a ) + ); + MUXCY_L \blk00000003/blk0000053c ( + .CI(\blk00000003/sig0000066a ), + .DI(\blk00000003/sig00000675 ), + .S(\blk00000003/sig0000066b ), + .LO(\blk00000003/sig00000667 ) + ); + MUXCY_L \blk00000003/blk0000053b ( + .CI(\blk00000003/sig00000667 ), + .DI(\blk00000003/sig00000674 ), + .S(\blk00000003/sig00000668 ), + .LO(\blk00000003/sig00000664 ) + ); + MUXCY_D \blk00000003/blk0000053a ( + .CI(\blk00000003/sig00000664 ), + .DI(\blk00000003/sig00000673 ), + .S(\blk00000003/sig00000665 ), + .O(\NLW_blk00000003/blk0000053a_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000053a_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000539 ( + .CI(\blk00000003/sig00000670 ), + .LI(\blk00000003/sig00000671 ), + .O(\blk00000003/sig00000672 ) + ); + XORCY \blk00000003/blk00000538 ( + .CI(\blk00000003/sig0000066d ), + .LI(\blk00000003/sig0000066e ), + .O(\blk00000003/sig0000066f ) + ); + XORCY \blk00000003/blk00000537 ( + .CI(\blk00000003/sig0000066a ), + .LI(\blk00000003/sig0000066b ), + .O(\blk00000003/sig0000066c ) + ); + XORCY \blk00000003/blk00000536 ( + .CI(\blk00000003/sig00000667 ), + .LI(\blk00000003/sig00000668 ), + .O(\blk00000003/sig00000669 ) + ); + XORCY \blk00000003/blk00000535 ( + .CI(\blk00000003/sig00000664 ), + .LI(\blk00000003/sig00000665 ), + .O(\blk00000003/sig00000666 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000534 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000663 ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000662 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000532 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000661 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000531 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000660 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000659 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000529 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000658 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000528 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000657 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000527 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000656 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000526 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000655 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000525 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000654 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000524 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000653 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000523 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000652 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000522 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000651 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000521 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000650 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000520 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000649 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000519 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000648 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000518 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000647 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000517 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000646 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000516 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000645 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000515 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000644 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000514 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000643 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000513 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000642 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000512 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000641 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000511 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000640 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000510 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000639 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000509 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000638 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000637 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000507 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000636 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000506 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000635 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000505 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000634 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000504 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000633 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000503 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000632 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000502 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000631 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000501 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000630 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000500 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000629 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000628 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000627 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000626 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000625 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000624 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000623 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000622 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000621 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000620 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000619 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000618 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000617 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000616 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000615 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000614 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000613 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000612 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000611 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000610 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004db ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000609 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000608 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000607 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000606 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000605 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000604 ), + .Q(\blk00000003/sig000001dd ) + ); + MUXCY_L \blk00000003/blk000004d4 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000603 ), + .S(\blk00000003/sig000005f1 ), + .LO(\blk00000003/sig000005fc ) + ); + MUXCY_L \blk00000003/blk000004d3 ( + .CI(\blk00000003/sig000005fc ), + .DI(\blk00000003/sig00000602 ), + .S(\blk00000003/sig000005fd ), + .LO(\blk00000003/sig000005f9 ) + ); + MUXCY_L \blk00000003/blk000004d2 ( + .CI(\blk00000003/sig000005f9 ), + .DI(\blk00000003/sig00000601 ), + .S(\blk00000003/sig000005fa ), + .LO(\blk00000003/sig000005f6 ) + ); + MUXCY_L \blk00000003/blk000004d1 ( + .CI(\blk00000003/sig000005f6 ), + .DI(\blk00000003/sig00000600 ), + .S(\blk00000003/sig000005f7 ), + .LO(\blk00000003/sig000005f3 ) + ); + MUXCY_D \blk00000003/blk000004d0 ( + .CI(\blk00000003/sig000005f3 ), + .DI(\blk00000003/sig000005ff ), + .S(\blk00000003/sig000005f4 ), + .O(\NLW_blk00000003/blk000004d0_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000004d0_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000004cf ( + .CI(\blk00000003/sig000005fc ), + .LI(\blk00000003/sig000005fd ), + .O(\blk00000003/sig000005fe ) + ); + XORCY \blk00000003/blk000004ce ( + .CI(\blk00000003/sig000005f9 ), + .LI(\blk00000003/sig000005fa ), + .O(\blk00000003/sig000005fb ) + ); + XORCY \blk00000003/blk000004cd ( + .CI(\blk00000003/sig000005f6 ), + .LI(\blk00000003/sig000005f7 ), + .O(\blk00000003/sig000005f8 ) + ); + XORCY \blk00000003/blk000004cc ( + .CI(\blk00000003/sig000005f3 ), + .LI(\blk00000003/sig000005f4 ), + .O(\blk00000003/sig000005f5 ) + ); + XORCY \blk00000003/blk000004cb ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000005f1 ), + .O(\blk00000003/sig000005f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a3 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003f0 ), + .R(sclr), + .Q(\blk00000003/sig0000050e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a2 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ef ), + .R(sclr), + .Q(\blk00000003/sig0000050d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a1 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ee ), + .R(sclr), + .Q(\blk00000003/sig0000050c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a0 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ed ), + .R(sclr), + .Q(\blk00000003/sig0000050b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049f ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ec ), + .R(sclr), + .Q(\blk00000003/sig0000050a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049e ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003eb ), + .R(sclr), + .Q(\blk00000003/sig00000509 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049d ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ea ), + .R(sclr), + .Q(\blk00000003/sig00000508 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049c ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e9 ), + .R(sclr), + .Q(\blk00000003/sig00000507 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049b ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e8 ), + .R(sclr), + .Q(\blk00000003/sig00000506 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049a ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e7 ), + .R(sclr), + .Q(\blk00000003/sig00000505 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000499 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e6 ), + .R(sclr), + .Q(\blk00000003/sig00000504 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000498 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e5 ), + .R(sclr), + .Q(\blk00000003/sig00000503 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000497 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e4 ), + .R(sclr), + .Q(\blk00000003/sig00000502 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000496 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e3 ), + .R(sclr), + .Q(\blk00000003/sig00000501 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000495 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e2 ), + .R(sclr), + .Q(\blk00000003/sig00000500 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000494 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e1 ), + .R(sclr), + .Q(\blk00000003/sig000004ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e0 ), + .R(sclr), + .Q(\blk00000003/sig000004fe ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000492 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003df ), + .R(sclr), + .Q(\blk00000003/sig000004fd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000491 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003de ), + .R(sclr), + .Q(\blk00000003/sig000004fc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000490 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003dd ), + .R(sclr), + .Q(\blk00000003/sig000004fb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048f ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003dc ), + .R(sclr), + .Q(\blk00000003/sig000004fa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048e ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003db ), + .R(sclr), + .Q(\blk00000003/sig000004f9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048d ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003da ), + .R(sclr), + .Q(\blk00000003/sig000004f8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048c ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003d9 ), + .R(sclr), + .Q(\blk00000003/sig000004f7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048b ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000450 ), + .R(sclr), + .Q(\blk00000003/sig00000526 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048a ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044f ), + .R(sclr), + .Q(\blk00000003/sig00000525 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000489 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044e ), + .R(sclr), + .Q(\blk00000003/sig00000524 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000488 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044d ), + .R(sclr), + .Q(\blk00000003/sig00000523 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000487 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044c ), + .R(sclr), + .Q(\blk00000003/sig00000522 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000486 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044b ), + .R(sclr), + .Q(\blk00000003/sig00000521 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044a ), + .R(sclr), + .Q(\blk00000003/sig00000520 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000484 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000449 ), + .R(sclr), + .Q(\blk00000003/sig0000051f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000448 ), + .R(sclr), + .Q(\blk00000003/sig0000051e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000482 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000447 ), + .R(sclr), + .Q(\blk00000003/sig0000051d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000481 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000446 ), + .R(sclr), + .Q(\blk00000003/sig0000051c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000480 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000445 ), + .R(sclr), + .Q(\blk00000003/sig0000051b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047f ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000444 ), + .R(sclr), + .Q(\blk00000003/sig0000051a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000443 ), + .R(sclr), + .Q(\blk00000003/sig00000519 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047d ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000442 ), + .R(sclr), + .Q(\blk00000003/sig00000518 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047c ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000441 ), + .R(sclr), + .Q(\blk00000003/sig00000517 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047b ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000440 ), + .R(sclr), + .Q(\blk00000003/sig00000516 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047a ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043f ), + .R(sclr), + .Q(\blk00000003/sig00000515 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000479 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043e ), + .R(sclr), + .Q(\blk00000003/sig00000514 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000478 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043d ), + .R(sclr), + .Q(\blk00000003/sig00000513 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000477 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043c ), + .R(sclr), + .Q(\blk00000003/sig00000512 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000476 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043b ), + .R(sclr), + .Q(\blk00000003/sig00000511 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000475 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043a ), + .R(sclr), + .Q(\blk00000003/sig00000510 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000474 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000439 ), + .R(sclr), + .Q(\blk00000003/sig0000050f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044c ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004aa ), + .R(sclr), + .Q(\blk00000003/sig00000586 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044b ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a9 ), + .R(sclr), + .Q(\blk00000003/sig00000585 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044a ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a8 ), + .R(sclr), + .Q(\blk00000003/sig00000584 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000449 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a7 ), + .R(sclr), + .Q(\blk00000003/sig00000583 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000448 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a6 ), + .R(sclr), + .Q(\blk00000003/sig00000582 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000447 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a5 ), + .R(sclr), + .Q(\blk00000003/sig00000581 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000446 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a4 ), + .R(sclr), + .Q(\blk00000003/sig00000580 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a3 ), + .R(sclr), + .Q(\blk00000003/sig0000057f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000444 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a2 ), + .R(sclr), + .Q(\blk00000003/sig0000057e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000443 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a1 ), + .R(sclr), + .Q(\blk00000003/sig0000057d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000442 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a0 ), + .R(sclr), + .Q(\blk00000003/sig0000057c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000441 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049f ), + .R(sclr), + .Q(\blk00000003/sig0000057b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000440 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049e ), + .R(sclr), + .Q(\blk00000003/sig0000057a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049d ), + .R(sclr), + .Q(\blk00000003/sig00000579 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043e ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049c ), + .R(sclr), + .Q(\blk00000003/sig00000578 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043d ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049b ), + .R(sclr), + .Q(\blk00000003/sig00000577 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043c ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049a ), + .R(sclr), + .Q(\blk00000003/sig00000576 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043b ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000499 ), + .R(sclr), + .Q(\blk00000003/sig00000575 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043a ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000498 ), + .R(sclr), + .Q(\blk00000003/sig00000574 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000439 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000497 ), + .R(sclr), + .Q(\blk00000003/sig00000573 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000438 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000496 ), + .R(sclr), + .Q(\blk00000003/sig00000572 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000437 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000495 ), + .R(sclr), + .Q(\blk00000003/sig00000571 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000436 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000494 ), + .R(sclr), + .Q(\blk00000003/sig00000570 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000435 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000493 ), + .R(sclr), + .Q(\blk00000003/sig0000056f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000434 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000408 ), + .R(sclr), + .Q(\blk00000003/sig0000053e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000433 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000407 ), + .R(sclr), + .Q(\blk00000003/sig0000053d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000406 ), + .R(sclr), + .Q(\blk00000003/sig0000053c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000431 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000405 ), + .R(sclr), + .Q(\blk00000003/sig0000053b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000430 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000404 ), + .R(sclr), + .Q(\blk00000003/sig0000053a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042f ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000403 ), + .R(sclr), + .Q(\blk00000003/sig00000539 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042e ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000402 ), + .R(sclr), + .Q(\blk00000003/sig00000538 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042d ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000401 ), + .R(sclr), + .Q(\blk00000003/sig00000537 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042c ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000400 ), + .R(sclr), + .Q(\blk00000003/sig00000536 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042b ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003ff ), + .R(sclr), + .Q(\blk00000003/sig00000535 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042a ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fe ), + .R(sclr), + .Q(\blk00000003/sig00000534 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000429 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fd ), + .R(sclr), + .Q(\blk00000003/sig00000533 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000428 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fc ), + .R(sclr), + .Q(\blk00000003/sig00000532 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000427 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fb ), + .R(sclr), + .Q(\blk00000003/sig00000531 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000426 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fa ), + .R(sclr), + .Q(\blk00000003/sig00000530 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000425 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f9 ), + .R(sclr), + .Q(\blk00000003/sig0000052f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000424 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f8 ), + .R(sclr), + .Q(\blk00000003/sig0000052e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000423 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f7 ), + .R(sclr), + .Q(\blk00000003/sig0000052d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000422 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f6 ), + .R(sclr), + .Q(\blk00000003/sig0000052c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000421 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f5 ), + .R(sclr), + .Q(\blk00000003/sig0000052b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000420 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f4 ), + .R(sclr), + .Q(\blk00000003/sig0000052a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f3 ), + .R(sclr), + .Q(\blk00000003/sig00000529 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041e ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f2 ), + .R(sclr), + .Q(\blk00000003/sig00000528 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f1 ), + .R(sclr), + .Q(\blk00000003/sig00000527 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004da ), + .R(sclr), + .Q(\blk00000003/sig000005b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041b ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d9 ), + .R(sclr), + .Q(\blk00000003/sig000005b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041a ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d8 ), + .R(sclr), + .Q(\blk00000003/sig000005b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000419 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d7 ), + .R(sclr), + .Q(\blk00000003/sig000005b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000418 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d6 ), + .R(sclr), + .Q(\blk00000003/sig000005b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000417 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d5 ), + .R(sclr), + .Q(\blk00000003/sig000005b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000416 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d4 ), + .R(sclr), + .Q(\blk00000003/sig000005b0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000415 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d3 ), + .R(sclr), + .Q(\blk00000003/sig000005af ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000414 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d2 ), + .R(sclr), + .Q(\blk00000003/sig000005ae ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000413 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d1 ), + .R(sclr), + .Q(\blk00000003/sig000005ad ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000412 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d0 ), + .R(sclr), + .Q(\blk00000003/sig000005ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000411 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004cf ), + .R(sclr), + .Q(\blk00000003/sig000005ab ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000410 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004ce ), + .R(sclr), + .Q(\blk00000003/sig000005aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040f ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004cd ), + .R(sclr), + .Q(\blk00000003/sig000005a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040e ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004cc ), + .R(sclr), + .Q(\blk00000003/sig000005a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040d ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004cb ), + .R(sclr), + .Q(\blk00000003/sig000005a7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004ca ), + .R(sclr), + .Q(\blk00000003/sig000005a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040b ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c9 ), + .R(sclr), + .Q(\blk00000003/sig000005a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040a ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c8 ), + .R(sclr), + .Q(\blk00000003/sig000005a4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000409 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c7 ), + .R(sclr), + .Q(\blk00000003/sig000005a3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000408 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c6 ), + .R(sclr), + .Q(\blk00000003/sig000005a2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000407 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c5 ), + .R(sclr), + .Q(\blk00000003/sig000005a1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000406 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c4 ), + .R(sclr), + .Q(\blk00000003/sig000005a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000405 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c3 ), + .R(sclr), + .Q(\blk00000003/sig0000059f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000404 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000468 ), + .R(sclr), + .Q(\blk00000003/sig00000556 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000403 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000467 ), + .R(sclr), + .Q(\blk00000003/sig00000555 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000402 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000466 ), + .R(sclr), + .Q(\blk00000003/sig00000554 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000401 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000465 ), + .R(sclr), + .Q(\blk00000003/sig00000553 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000400 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000464 ), + .R(sclr), + .Q(\blk00000003/sig00000552 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ff ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000463 ), + .R(sclr), + .Q(\blk00000003/sig00000551 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fe ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000462 ), + .R(sclr), + .Q(\blk00000003/sig00000550 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fd ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000461 ), + .R(sclr), + .Q(\blk00000003/sig0000054f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fc ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000460 ), + .R(sclr), + .Q(\blk00000003/sig0000054e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fb ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045f ), + .R(sclr), + .Q(\blk00000003/sig0000054d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fa ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045e ), + .R(sclr), + .Q(\blk00000003/sig0000054c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045d ), + .R(sclr), + .Q(\blk00000003/sig0000054b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f8 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045c ), + .R(sclr), + .Q(\blk00000003/sig0000054a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f7 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045b ), + .R(sclr), + .Q(\blk00000003/sig00000549 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f6 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045a ), + .R(sclr), + .Q(\blk00000003/sig00000548 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f5 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000459 ), + .R(sclr), + .Q(\blk00000003/sig00000547 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f4 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000458 ), + .R(sclr), + .Q(\blk00000003/sig00000546 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f3 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000457 ), + .R(sclr), + .Q(\blk00000003/sig00000545 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f2 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000456 ), + .R(sclr), + .Q(\blk00000003/sig00000544 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f1 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000455 ), + .R(sclr), + .Q(\blk00000003/sig00000543 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f0 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000454 ), + .R(sclr), + .Q(\blk00000003/sig00000542 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ef ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000453 ), + .R(sclr), + .Q(\blk00000003/sig00000541 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ee ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000452 ), + .R(sclr), + .Q(\blk00000003/sig00000540 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ed ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000451 ), + .R(sclr), + .Q(\blk00000003/sig0000053f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b8 ), + .R(sclr), + .Q(\blk00000003/sig000004ef ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000115 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b7 ), + .R(sclr), + .Q(\blk00000003/sig000004ed ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000114 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f6 ), + .R(sclr), + .Q(\blk00000003/sig000004e5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000113 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ba ), + .R(sclr), + .Q(\blk00000003/sig000004eb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000112 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002be ), + .R(sclr), + .Q(\blk00000003/sig000004e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000111 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c4 ), + .R(sclr), + .Q(\blk00000003/sig000004e7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000110 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f5 ), + .R(sclr), + .Q(\blk00000003/sig000004e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b1 ), + .R(sclr), + .Q(\blk00000003/sig000004f3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b0 ), + .R(sclr), + .Q(\blk00000003/sig000004f1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f3 ), + .R(sclr), + .Q(\blk00000003/sig000004f4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f1 ), + .R(sclr), + .Q(\blk00000003/sig000004f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004ef ), + .R(sclr), + .Q(\blk00000003/sig000004f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004ed ), + .R(sclr), + .Q(\blk00000003/sig000004ee ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000109 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004eb ), + .R(sclr), + .Q(\blk00000003/sig000004ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000108 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e9 ), + .R(sclr), + .Q(\blk00000003/sig000004ea ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000107 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e7 ), + .R(sclr), + .Q(\blk00000003/sig000004e8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000106 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e5 ), + .R(sclr), + .Q(\blk00000003/sig000004e6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000105 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e3 ), + .R(sclr), + .Q(\blk00000003/sig000004e4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000104 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e1 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004e2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000103 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000232 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004e1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000102 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004dd ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004e0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000101 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004dc ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004df ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000100 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004db ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004de ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026b ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004dd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000268 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004dc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000264 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004db ) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000fc ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000fc_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000fc_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000fc_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000fc_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000fc_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000fc_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000fc_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b , +\blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , \blk00000003/sig00000370 , +\blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , \blk00000003/sig00000375 , +\blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 , \blk00000003/sig00000379 , \blk00000003/sig0000037a , +\blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , \blk00000003/sig0000037e , \blk00000003/sig0000037f , +\blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , \blk00000003/sig00000383 , \blk00000003/sig00000384 , +\blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , \blk00000003/sig00000388 , \blk00000003/sig00000389 , +\blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , \blk00000003/sig0000038d , \blk00000003/sig0000038e , +\blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , \blk00000003/sig00000392 , \blk00000003/sig00000393 , +\blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000fc_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fc_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig00000469 , \blk00000003/sig0000046a , \blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d , +\blk00000003/sig0000046e , \blk00000003/sig0000046f , \blk00000003/sig00000470 , \blk00000003/sig00000471 , \blk00000003/sig00000472 , +\blk00000003/sig00000473 , \blk00000003/sig00000474 , \blk00000003/sig00000475 , \blk00000003/sig00000476 , \blk00000003/sig00000477 , +\blk00000003/sig00000478 , \blk00000003/sig00000479 , \blk00000003/sig0000047a }), + .BCOUT({\NLW_blk00000003/blk000000fc_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000004ab , \blk00000003/sig000004ab , \blk00000003/sig000004ac , \blk00000003/sig000004ad , \blk00000003/sig000004ae , +\blk00000003/sig000004af , \blk00000003/sig000004b0 , \blk00000003/sig000004b1 , \blk00000003/sig000004b2 , \blk00000003/sig000004b3 , +\blk00000003/sig000004b4 , \blk00000003/sig000004b5 , \blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , +\blk00000003/sig000004b9 , \blk00000003/sig000004ba , \blk00000003/sig000004bb , \blk00000003/sig000004bc , \blk00000003/sig000004bd , +\blk00000003/sig000004be , \blk00000003/sig000004bf , \blk00000003/sig000004c0 , \blk00000003/sig000004c1 , \blk00000003/sig000004c2 }), + .P({\NLW_blk00000003/blk000000fc_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000004c3 , \blk00000003/sig000004c3 , \blk00000003/sig000004c3 , \blk00000003/sig000004c3 , \blk00000003/sig000004c3 , +\blk00000003/sig000004c3 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , \blk00000003/sig000004c5 , \blk00000003/sig000004c6 , +\blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , \blk00000003/sig000004ca , \blk00000003/sig000004cb , +\blk00000003/sig000004cc , \blk00000003/sig000004cd , \blk00000003/sig000004ce , \blk00000003/sig000004cf , \blk00000003/sig000004d0 , +\blk00000003/sig000004d1 , \blk00000003/sig000004d2 , \blk00000003/sig000004d3 , \blk00000003/sig000004d4 , \blk00000003/sig000004d5 , +\blk00000003/sig000004d6 , \blk00000003/sig000004d7 , \blk00000003/sig000004d8 , \blk00000003/sig000004d9 , \blk00000003/sig000004da }), + .PCOUT({\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d , +\blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , \blk00000003/sig00000412 , +\blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , \blk00000003/sig00000417 , +\blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , \blk00000003/sig0000041b , \blk00000003/sig0000041c , +\blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , \blk00000003/sig00000420 , \blk00000003/sig00000421 , +\blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , \blk00000003/sig00000425 , \blk00000003/sig00000426 , +\blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , \blk00000003/sig0000042a , \blk00000003/sig0000042b , +\blk00000003/sig0000042c , \blk00000003/sig0000042d , \blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , +\blk00000003/sig00000431 , \blk00000003/sig00000432 , \blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , +\blk00000003/sig00000436 , \blk00000003/sig00000437 , \blk00000003/sig00000438 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000fb ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000fb_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000fb_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000fb_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000fb_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000fb_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000fb_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000fb_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b , +\blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , \blk00000003/sig00000310 , +\blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , \blk00000003/sig00000315 , +\blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 , \blk00000003/sig00000319 , \blk00000003/sig0000031a , +\blk00000003/sig0000031b , \blk00000003/sig0000031c , \blk00000003/sig0000031d , \blk00000003/sig0000031e , \blk00000003/sig0000031f , +\blk00000003/sig00000320 , \blk00000003/sig00000321 , \blk00000003/sig00000322 , \blk00000003/sig00000323 , \blk00000003/sig00000324 , +\blk00000003/sig00000325 , \blk00000003/sig00000326 , \blk00000003/sig00000327 , \blk00000003/sig00000328 , \blk00000003/sig00000329 , +\blk00000003/sig0000032a , \blk00000003/sig0000032b , \blk00000003/sig0000032c , \blk00000003/sig0000032d , \blk00000003/sig0000032e , +\blk00000003/sig0000032f , \blk00000003/sig00000330 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , \blk00000003/sig00000333 , +\blk00000003/sig00000334 , \blk00000003/sig00000335 , \blk00000003/sig00000336 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000fb_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fb_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fb_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig00000469 , \blk00000003/sig0000046a , \blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d , +\blk00000003/sig0000046e , \blk00000003/sig0000046f , \blk00000003/sig00000470 , \blk00000003/sig00000471 , \blk00000003/sig00000472 , +\blk00000003/sig00000473 , \blk00000003/sig00000474 , \blk00000003/sig00000475 , \blk00000003/sig00000476 , \blk00000003/sig00000477 , +\blk00000003/sig00000478 , \blk00000003/sig00000479 , \blk00000003/sig0000047a }), + .BCOUT({\NLW_blk00000003/blk000000fb_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig0000047b , \blk00000003/sig0000047b , \blk00000003/sig0000047c , \blk00000003/sig0000047d , \blk00000003/sig0000047e , +\blk00000003/sig0000047f , \blk00000003/sig00000480 , \blk00000003/sig00000481 , \blk00000003/sig00000482 , \blk00000003/sig00000483 , +\blk00000003/sig00000484 , \blk00000003/sig00000485 , \blk00000003/sig00000486 , \blk00000003/sig00000487 , \blk00000003/sig00000488 , +\blk00000003/sig00000489 , \blk00000003/sig0000048a , \blk00000003/sig0000048b , \blk00000003/sig0000048c , \blk00000003/sig0000048d , +\blk00000003/sig0000048e , \blk00000003/sig0000048f , \blk00000003/sig00000490 , \blk00000003/sig00000491 , \blk00000003/sig00000492 }), + .P({\NLW_blk00000003/blk000000fb_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000493 , \blk00000003/sig00000493 , \blk00000003/sig00000493 , \blk00000003/sig00000493 , \blk00000003/sig00000493 , +\blk00000003/sig00000493 , \blk00000003/sig00000493 , \blk00000003/sig00000494 , \blk00000003/sig00000495 , \blk00000003/sig00000496 , +\blk00000003/sig00000497 , \blk00000003/sig00000498 , \blk00000003/sig00000499 , \blk00000003/sig0000049a , \blk00000003/sig0000049b , +\blk00000003/sig0000049c , \blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , +\blk00000003/sig000004a1 , \blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , +\blk00000003/sig000004a6 , \blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa }), + .PCOUT({\blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , +\blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , +\blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , +\blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa , +\blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , +\blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , \blk00000003/sig000003b4 , +\blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , \blk00000003/sig000003b9 , +\blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000fa ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000fa_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000fa_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000fa_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000fa_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000fa_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000fa_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000fa_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d , +\blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , \blk00000003/sig00000412 , +\blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , \blk00000003/sig00000417 , +\blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , \blk00000003/sig0000041b , \blk00000003/sig0000041c , +\blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , \blk00000003/sig00000420 , \blk00000003/sig00000421 , +\blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , \blk00000003/sig00000425 , \blk00000003/sig00000426 , +\blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , \blk00000003/sig0000042a , \blk00000003/sig0000042b , +\blk00000003/sig0000042c , \blk00000003/sig0000042d , \blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , +\blk00000003/sig00000431 , \blk00000003/sig00000432 , \blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , +\blk00000003/sig00000436 , \blk00000003/sig00000437 , \blk00000003/sig00000438 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000fa_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fa_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , +\blk00000003/sig000003cc , \blk00000003/sig000003cd , \blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , +\blk00000003/sig000003d1 , \blk00000003/sig000003d2 , \blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , +\blk00000003/sig000003d6 , \blk00000003/sig000003d7 , \blk00000003/sig000003d8 }), + .BCOUT({\NLW_blk00000003/blk000000fa_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000439 , \blk00000003/sig00000439 , \blk00000003/sig0000043a , \blk00000003/sig0000043b , \blk00000003/sig0000043c , +\blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , \blk00000003/sig00000440 , \blk00000003/sig00000441 , +\blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , \blk00000003/sig00000445 , \blk00000003/sig00000446 , +\blk00000003/sig00000447 , \blk00000003/sig00000448 , \blk00000003/sig00000449 , \blk00000003/sig0000044a , \blk00000003/sig0000044b , +\blk00000003/sig0000044c , \blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , \blk00000003/sig00000450 }), + .P({\NLW_blk00000003/blk000000fa_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000451 , \blk00000003/sig00000451 , \blk00000003/sig00000451 , \blk00000003/sig00000451 , \blk00000003/sig00000451 , +\blk00000003/sig00000451 , \blk00000003/sig00000451 , \blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , +\blk00000003/sig00000455 , \blk00000003/sig00000456 , \blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , +\blk00000003/sig0000045a , \blk00000003/sig0000045b , \blk00000003/sig0000045c , \blk00000003/sig0000045d , \blk00000003/sig0000045e , +\blk00000003/sig0000045f , \blk00000003/sig00000460 , \blk00000003/sig00000461 , \blk00000003/sig00000462 , \blk00000003/sig00000463 , +\blk00000003/sig00000464 , \blk00000003/sig00000465 , \blk00000003/sig00000466 , \blk00000003/sig00000467 , \blk00000003/sig00000468 }), + .PCOUT({\blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , \blk00000003/sig000000c7 , +\blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , +\blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , +\blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , +\blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , +\blk00000003/sig000000dc , \blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , +\blk00000003/sig000000e1 , \blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , +\blk00000003/sig000000e6 , \blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , +\blk00000003/sig000000eb , \blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , +\blk00000003/sig000000f0 , \blk00000003/sig000000f1 , \blk00000003/sig000000f2 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f9 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f9_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f9_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f9_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f9_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f9_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f9_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f9_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , +\blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , +\blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , +\blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa , +\blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , +\blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , \blk00000003/sig000003b4 , +\blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , \blk00000003/sig000003b9 , +\blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f9_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f9_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , +\blk00000003/sig000003cc , \blk00000003/sig000003cd , \blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , +\blk00000003/sig000003d1 , \blk00000003/sig000003d2 , \blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , +\blk00000003/sig000003d6 , \blk00000003/sig000003d7 , \blk00000003/sig000003d8 }), + .BCOUT({\NLW_blk00000003/blk000000f9_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000003d9 , \blk00000003/sig000003d9 , \blk00000003/sig000003da , \blk00000003/sig000003db , \blk00000003/sig000003dc , +\blk00000003/sig000003dd , \blk00000003/sig000003de , \blk00000003/sig000003df , \blk00000003/sig000003e0 , \blk00000003/sig000003e1 , +\blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , \blk00000003/sig000003e5 , \blk00000003/sig000003e6 , +\blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , \blk00000003/sig000003ea , \blk00000003/sig000003eb , +\blk00000003/sig000003ec , \blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , \blk00000003/sig000003f0 }), + .P({\NLW_blk00000003/blk000000f9_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000003f1 , \blk00000003/sig000003f1 , \blk00000003/sig000003f1 , \blk00000003/sig000003f1 , \blk00000003/sig000003f1 , +\blk00000003/sig000003f1 , \blk00000003/sig000003f1 , \blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , +\blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , +\blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 }), + .PCOUT({\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , +\blk00000003/sig00000156 , \blk00000003/sig00000157 , \blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , +\blk00000003/sig0000015b , \blk00000003/sig0000015c , \blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , +\blk00000003/sig00000160 , \blk00000003/sig00000161 , \blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , +\blk00000003/sig00000165 , \blk00000003/sig00000166 , \blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , +\blk00000003/sig0000016a , \blk00000003/sig0000016b , \blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , +\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f8 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f8_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f8_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f8_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f8_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f8_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f8_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f8_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f8_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f8_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002c5 , \blk00000003/sig000002c6 , \blk00000003/sig000002c7 , \blk00000003/sig000002c8 , \blk00000003/sig000002c9 , +\blk00000003/sig000002ca , \blk00000003/sig000002cb , \blk00000003/sig000002cc , \blk00000003/sig000002cd , \blk00000003/sig000002ce , +\blk00000003/sig000002cf , \blk00000003/sig000002d0 , \blk00000003/sig000002d1 , \blk00000003/sig000002d2 , \blk00000003/sig000002d3 , +\blk00000003/sig000002d4 , \blk00000003/sig000002d5 , \blk00000003/sig000002d6 }), + .BCOUT({\NLW_blk00000003/blk000000f8_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000337 , \blk00000003/sig00000337 , \blk00000003/sig00000338 , \blk00000003/sig00000339 , \blk00000003/sig0000033a , +\blk00000003/sig0000033b , \blk00000003/sig0000033c , \blk00000003/sig0000033d , \blk00000003/sig0000033e , \blk00000003/sig0000033f , +\blk00000003/sig00000340 , \blk00000003/sig00000341 , \blk00000003/sig00000342 , \blk00000003/sig00000343 , \blk00000003/sig00000344 , +\blk00000003/sig00000345 , \blk00000003/sig00000346 , \blk00000003/sig00000347 , \blk00000003/sig00000348 , \blk00000003/sig00000349 , +\blk00000003/sig0000034a , \blk00000003/sig0000034b , \blk00000003/sig0000034c , \blk00000003/sig0000034d , \blk00000003/sig0000034e }), + .P({\NLW_blk00000003/blk000000f8_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000034f , \blk00000003/sig0000034f , \blk00000003/sig0000034f , \blk00000003/sig0000034f , \blk00000003/sig0000034f , +\blk00000003/sig0000034f , \blk00000003/sig0000034f , \blk00000003/sig00000350 , \blk00000003/sig00000351 , \blk00000003/sig00000352 , +\blk00000003/sig00000353 , \blk00000003/sig00000354 , \blk00000003/sig00000355 , \blk00000003/sig00000356 , \blk00000003/sig00000357 , +\blk00000003/sig00000358 , \blk00000003/sig00000359 , \blk00000003/sig0000035a , \blk00000003/sig0000035b , \blk00000003/sig0000035c , +\blk00000003/sig0000035d , \blk00000003/sig0000035e , \blk00000003/sig0000035f , \blk00000003/sig00000360 , \blk00000003/sig00000361 , +\blk00000003/sig00000362 , \blk00000003/sig00000363 , \blk00000003/sig00000364 , \blk00000003/sig00000365 , \blk00000003/sig00000366 }), + .PCOUT({\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b , +\blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , \blk00000003/sig00000370 , +\blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , \blk00000003/sig00000375 , +\blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 , \blk00000003/sig00000379 , \blk00000003/sig0000037a , +\blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , \blk00000003/sig0000037e , \blk00000003/sig0000037f , +\blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , \blk00000003/sig00000383 , \blk00000003/sig00000384 , +\blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , \blk00000003/sig00000388 , \blk00000003/sig00000389 , +\blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , \blk00000003/sig0000038d , \blk00000003/sig0000038e , +\blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , \blk00000003/sig00000392 , \blk00000003/sig00000393 , +\blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f7 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f7_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f7_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f7_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f7_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f7_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f7_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f7_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f7_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f7_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f7_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002c5 , \blk00000003/sig000002c6 , \blk00000003/sig000002c7 , \blk00000003/sig000002c8 , \blk00000003/sig000002c9 , +\blk00000003/sig000002ca , \blk00000003/sig000002cb , \blk00000003/sig000002cc , \blk00000003/sig000002cd , \blk00000003/sig000002ce , +\blk00000003/sig000002cf , \blk00000003/sig000002d0 , \blk00000003/sig000002d1 , \blk00000003/sig000002d2 , \blk00000003/sig000002d3 , +\blk00000003/sig000002d4 , \blk00000003/sig000002d5 , \blk00000003/sig000002d6 }), + .BCOUT({\NLW_blk00000003/blk000000f7_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000002d7 , \blk00000003/sig000002d7 , \blk00000003/sig000002d8 , \blk00000003/sig000002d9 , \blk00000003/sig000002da , +\blk00000003/sig000002db , \blk00000003/sig000002dc , \blk00000003/sig000002dd , \blk00000003/sig000002de , \blk00000003/sig000002df , +\blk00000003/sig000002e0 , \blk00000003/sig000002e1 , \blk00000003/sig000002e2 , \blk00000003/sig000002e3 , \blk00000003/sig000002e4 , +\blk00000003/sig000002e5 , \blk00000003/sig000002e6 , \blk00000003/sig000002e7 , \blk00000003/sig000002e8 , \blk00000003/sig000002e9 , +\blk00000003/sig000002ea , \blk00000003/sig000002eb , \blk00000003/sig000002ec , \blk00000003/sig000002ed , \blk00000003/sig000002ee }), + .P({\NLW_blk00000003/blk000000f7_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000002ef , \blk00000003/sig000002ef , \blk00000003/sig000002ef , \blk00000003/sig000002ef , \blk00000003/sig000002ef , +\blk00000003/sig000002ef , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , \blk00000003/sig000002f1 , \blk00000003/sig000002f2 , +\blk00000003/sig000002f3 , \blk00000003/sig000002f4 , \blk00000003/sig000002f5 , \blk00000003/sig000002f6 , \blk00000003/sig000002f7 , +\blk00000003/sig000002f8 , \blk00000003/sig000002f9 , \blk00000003/sig000002fa , \blk00000003/sig000002fb , \blk00000003/sig000002fc , +\blk00000003/sig000002fd , \blk00000003/sig000002fe , \blk00000003/sig000002ff , \blk00000003/sig00000300 , \blk00000003/sig00000301 , +\blk00000003/sig00000302 , \blk00000003/sig00000303 , \blk00000003/sig00000304 , \blk00000003/sig00000305 , \blk00000003/sig00000306 }), + .PCOUT({\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b , +\blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , \blk00000003/sig00000310 , +\blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , \blk00000003/sig00000315 , +\blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 , \blk00000003/sig00000319 , \blk00000003/sig0000031a , +\blk00000003/sig0000031b , \blk00000003/sig0000031c , \blk00000003/sig0000031d , \blk00000003/sig0000031e , \blk00000003/sig0000031f , +\blk00000003/sig00000320 , \blk00000003/sig00000321 , \blk00000003/sig00000322 , \blk00000003/sig00000323 , \blk00000003/sig00000324 , +\blk00000003/sig00000325 , \blk00000003/sig00000326 , \blk00000003/sig00000327 , \blk00000003/sig00000328 , \blk00000003/sig00000329 , +\blk00000003/sig0000032a , \blk00000003/sig0000032b , \blk00000003/sig0000032c , \blk00000003/sig0000032d , \blk00000003/sig0000032e , +\blk00000003/sig0000032f , \blk00000003/sig00000330 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , \blk00000003/sig00000333 , +\blk00000003/sig00000334 , \blk00000003/sig00000335 , \blk00000003/sig00000336 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cd ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig000002b9 ) + ); + XORCY \blk00000003/blk000000f3 ( + .CI(\blk00000003/sig000002bc ), + .LI(\blk00000003/sig000002bf ), + .O(\blk00000003/sig000002c0 ) + ); + MUXCY_D \blk00000003/blk000000f2 ( + .CI(\blk00000003/sig000002bc ), + .DI(\blk00000003/sig000002be ), + .S(\blk00000003/sig000002bf ), + .O(\NLW_blk00000003/blk000000f2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000f1 ( + .CI(\blk00000003/sig000002b9 ), + .LI(\blk00000003/sig000002bb ), + .O(\blk00000003/sig000002bd ) + ); + MUXCY_L \blk00000003/blk000000f0 ( + .CI(\blk00000003/sig000002b9 ), + .DI(\blk00000003/sig000002ba ), + .S(\blk00000003/sig000002bb ), + .LO(\blk00000003/sig000002bc ) + ); + MUXCY_L \blk00000003/blk000000ef ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002b8 ), + .S(\blk00000003/sig000002b2 ), + .LO(\blk00000003/sig000002b4 ) + ); + MUXCY_D \blk00000003/blk000000ee ( + .CI(\blk00000003/sig000002b4 ), + .DI(\blk00000003/sig000002b7 ), + .S(\blk00000003/sig000002b5 ), + .O(\NLW_blk00000003/blk000000ee_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000ee_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000ed ( + .CI(\blk00000003/sig000002b4 ), + .LI(\blk00000003/sig000002b5 ), + .O(\blk00000003/sig000002b6 ) + ); + XORCY \blk00000003/blk000000ec ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002b2 ), + .O(\blk00000003/sig000002b3 ) + ); + MUXCY_L \blk00000003/blk000000eb ( + .CI(\blk00000003/sig000002a9 ), + .DI(\blk00000003/sig000002b1 ), + .S(\blk00000003/sig000002aa ), + .LO(\blk00000003/sig000002ac ) + ); + MUXCY_D \blk00000003/blk000000ea ( + .CI(\blk00000003/sig000002ac ), + .DI(\blk00000003/sig000002b0 ), + .S(\blk00000003/sig000002ad ), + .O(\NLW_blk00000003/blk000000ea_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000ea_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000e9 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig000002af ), + .O(\blk00000003/sig000002a9 ) + ); + XORCY \blk00000003/blk000000e8 ( + .CI(\blk00000003/sig000002ac ), + .LI(\blk00000003/sig000002ad ), + .O(\blk00000003/sig000002ae ) + ); + XORCY \blk00000003/blk000000e7 ( + .CI(\blk00000003/sig000002a9 ), + .LI(\blk00000003/sig000002aa ), + .O(\blk00000003/sig000002ab ) + ); + FDE \blk00000003/blk000000e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a7 ), + .Q(\blk00000003/sig000002a8 ) + ); + MUXCY_L \blk00000003/blk000000e5 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002a6 ), + .S(\blk00000003/sig000002a0 ), + .LO(\blk00000003/sig000002a2 ) + ); + MUXCY_D \blk00000003/blk000000e4 ( + .CI(\blk00000003/sig000002a2 ), + .DI(\blk00000003/sig000002a5 ), + .S(\blk00000003/sig000002a3 ), + .O(\NLW_blk00000003/blk000000e4_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e4_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000e3 ( + .CI(\blk00000003/sig000002a2 ), + .LI(\blk00000003/sig000002a3 ), + .O(\blk00000003/sig000002a4 ) + ); + XORCY \blk00000003/blk000000e2 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002a0 ), + .O(\blk00000003/sig000002a1 ) + ); + MUXCY_L \blk00000003/blk000000e1 ( + .CI(\blk00000003/sig00000299 ), + .DI(\blk00000003/sig000001e7 ), + .S(\blk00000003/sig0000029a ), + .LO(\blk00000003/sig0000029c ) + ); + MUXCY_D \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig0000029c ), + .DI(\blk00000003/sig000001e6 ), + .S(\blk00000003/sig0000029d ), + .O(\NLW_blk00000003/blk000000e0_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e0_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000df ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig0000029f ), + .O(\blk00000003/sig00000299 ) + ); + XORCY \blk00000003/blk000000de ( + .CI(\blk00000003/sig0000029c ), + .LI(\blk00000003/sig0000029d ), + .O(\blk00000003/sig0000029e ) + ); + XORCY \blk00000003/blk000000dd ( + .CI(\blk00000003/sig00000299 ), + .LI(\blk00000003/sig0000029a ), + .O(\blk00000003/sig0000029b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000297 ), + .R(sclr), + .Q(\blk00000003/sig00000298 ) + ); + MUXCY_D \blk00000003/blk000000db ( + .CI(\blk00000003/sig00000294 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000296 ), + .O(\NLW_blk00000003/blk000000db_O_UNCONNECTED ), + .LO(\blk00000003/sig00000297 ) + ); + MUXCY_D \blk00000003/blk000000da ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000295 ), + .O(\blk00000003/sig00000292 ), + .LO(\NLW_blk00000003/blk000000da_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d9 ( + .CI(\blk00000003/sig00000292 ), + .DI(\blk00000003/sig00000291 ), + .S(\blk00000003/sig00000293 ), + .O(\blk00000003/sig00000294 ), + .LO(\blk00000003/sig00000290 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000290 ), + .R(sclr), + .Q(\blk00000003/sig00000291 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000281 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000280 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021c ) + ); + MUXCY_D \blk00000003/blk000000d5 ( + .CI(\blk00000003/sig0000021c ), + .DI(\blk00000003/sig0000028e ), + .S(\blk00000003/sig0000028f ), + .O(\blk00000003/sig0000028b ), + .LO(\NLW_blk00000003/blk000000d5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d4 ( + .CI(\blk00000003/sig0000028b ), + .DI(\blk00000003/sig0000028c ), + .S(\blk00000003/sig0000028d ), + .O(\blk00000003/sig00000289 ), + .LO(\NLW_blk00000003/blk000000d4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d3 ( + .CI(\blk00000003/sig00000289 ), + .DI(\blk00000003/sig0000027f ), + .S(\blk00000003/sig0000028a ), + .O(\blk00000003/sig00000286 ), + .LO(\NLW_blk00000003/blk000000d3_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d2 ( + .CI(\blk00000003/sig00000286 ), + .DI(\blk00000003/sig00000287 ), + .S(\blk00000003/sig00000288 ), + .O(\blk00000003/sig00000284 ), + .LO(\NLW_blk00000003/blk000000d2_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d1 ( + .CI(\blk00000003/sig00000284 ), + .DI(\blk00000003/sig00000244 ), + .S(\blk00000003/sig00000285 ), + .O(\blk00000003/sig00000282 ), + .LO(\NLW_blk00000003/blk000000d1_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d0 ( + .CI(\blk00000003/sig00000282 ), + .DI(\blk00000003/sig00000219 ), + .S(\blk00000003/sig00000283 ), + .O(\NLW_blk00000003/blk000000d0_O_UNCONNECTED ), + .LO(\blk00000003/sig00000280 ) + ); + XORCY \blk00000003/blk000000cf ( + .CI(\blk00000003/sig00000280 ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000281 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026f ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000027f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000001cd ) + ); + MUXCY_D \blk00000003/blk000000cc ( + .CI(\blk00000003/sig000001cd ), + .DI(\blk00000003/sig0000027d ), + .S(\blk00000003/sig0000027e ), + .O(\blk00000003/sig0000027b ), + .LO(\NLW_blk00000003/blk000000cc_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cb ( + .CI(\blk00000003/sig0000027b ), + .DI(\blk00000003/sig000001ce ), + .S(\blk00000003/sig0000027c ), + .O(\blk00000003/sig00000279 ), + .LO(\NLW_blk00000003/blk000000cb_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000ca ( + .CI(\blk00000003/sig00000279 ), + .DI(\blk00000003/sig000001cd ), + .S(\blk00000003/sig0000027a ), + .O(\blk00000003/sig00000276 ), + .LO(\NLW_blk00000003/blk000000ca_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c9 ( + .CI(\blk00000003/sig00000276 ), + .DI(\blk00000003/sig00000277 ), + .S(\blk00000003/sig00000278 ), + .O(\blk00000003/sig00000274 ), + .LO(\NLW_blk00000003/blk000000c9_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c8 ( + .CI(\blk00000003/sig00000274 ), + .DI(\blk00000003/sig0000021f ), + .S(\blk00000003/sig00000275 ), + .O(\blk00000003/sig00000270 ), + .LO(\NLW_blk00000003/blk000000c8_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c7 ( + .CI(\blk00000003/sig00000272 ), + .DI(\blk00000003/sig0000021f ), + .S(\blk00000003/sig00000273 ), + .O(\NLW_blk00000003/blk000000c7_O_UNCONNECTED ), + .LO(\blk00000003/sig0000026e ) + ); + MUXCY_D \blk00000003/blk000000c6 ( + .CI(\blk00000003/sig00000270 ), + .DI(\blk00000003/sig00000239 ), + .S(\blk00000003/sig00000271 ), + .O(\blk00000003/sig00000272 ), + .LO(\NLW_blk00000003/blk000000c6_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c5 ( + .CI(\blk00000003/sig0000026e ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig0000026f ) + ); + FDE \blk00000003/blk000000c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026c ), + .Q(\blk00000003/sig0000026d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000026b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000263 ) + ); + XORCY \blk00000003/blk000000c1 ( + .CI(\blk00000003/sig00000266 ), + .LI(\blk00000003/sig00000269 ), + .O(\blk00000003/sig0000026a ) + ); + MUXCY_D \blk00000003/blk000000c0 ( + .CI(\blk00000003/sig00000266 ), + .DI(\blk00000003/sig00000268 ), + .S(\blk00000003/sig00000269 ), + .O(\NLW_blk00000003/blk000000c0_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c0_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000bf ( + .CI(\blk00000003/sig00000263 ), + .LI(\blk00000003/sig00000265 ), + .O(\blk00000003/sig00000267 ) + ); + MUXCY_L \blk00000003/blk000000be ( + .CI(\blk00000003/sig00000263 ), + .DI(\blk00000003/sig00000264 ), + .S(\blk00000003/sig00000265 ), + .LO(\blk00000003/sig00000266 ) + ); + MUXCY_L \blk00000003/blk000000bd ( + .CI(\blk00000003/sig0000025a ), + .DI(\blk00000003/sig00000262 ), + .S(\blk00000003/sig0000025b ), + .LO(\blk00000003/sig0000025d ) + ); + MUXCY_D \blk00000003/blk000000bc ( + .CI(\blk00000003/sig0000025d ), + .DI(\blk00000003/sig00000261 ), + .S(\blk00000003/sig0000025e ), + .O(\NLW_blk00000003/blk000000bc_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000bc_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000bb ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000260 ), + .O(\blk00000003/sig0000025a ) + ); + XORCY \blk00000003/blk000000ba ( + .CI(\blk00000003/sig0000025d ), + .LI(\blk00000003/sig0000025e ), + .O(\blk00000003/sig0000025f ) + ); + XORCY \blk00000003/blk000000b9 ( + .CI(\blk00000003/sig0000025a ), + .LI(\blk00000003/sig0000025b ), + .O(\blk00000003/sig0000025c ) + ); + MUXCY_L \blk00000003/blk000000b8 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000259 ), + .S(\blk00000003/sig00000257 ), + .LO(\blk00000003/sig00000253 ) + ); + XORCY \blk00000003/blk000000b7 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000257 ), + .O(\blk00000003/sig00000258 ) + ); + MUXCY_D \blk00000003/blk000000b6 ( + .CI(\blk00000003/sig00000253 ), + .DI(\blk00000003/sig00000256 ), + .S(\blk00000003/sig00000254 ), + .O(\NLW_blk00000003/blk000000b6_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b6_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000b5 ( + .CI(\blk00000003/sig00000253 ), + .LI(\blk00000003/sig00000254 ), + .O(\blk00000003/sig00000255 ) + ); + MUXCY_L \blk00000003/blk000000b4 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000252 ), + .S(\blk00000003/sig00000250 ), + .LO(\blk00000003/sig0000024c ) + ); + XORCY \blk00000003/blk000000b3 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000250 ), + .O(\blk00000003/sig00000251 ) + ); + MUXCY_D \blk00000003/blk000000b2 ( + .CI(\blk00000003/sig0000024c ), + .DI(\blk00000003/sig0000024f ), + .S(\blk00000003/sig0000024d ), + .O(\NLW_blk00000003/blk000000b2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000b1 ( + .CI(\blk00000003/sig0000024c ), + .LI(\blk00000003/sig0000024d ), + .O(\blk00000003/sig0000024e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b0 ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig0000024b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig0000024a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e0 ), + .Q(\blk00000003/sig0000023e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000249 ), + .Q(\blk00000003/sig00000231 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000247 ), + .Q(\blk00000003/sig00000248 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000246 ), + .Q(\blk00000003/sig0000022f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000245 ), + .Q(\blk00000003/sig0000023c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000243 ), + .Q(\blk00000003/sig00000244 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000241 ), + .Q(\blk00000003/sig00000242 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023f ), + .Q(\blk00000003/sig00000240 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023e ), + .Q(\blk00000003/sig0000023a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023c ), + .Q(\blk00000003/sig0000023d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023a ), + .Q(\blk00000003/sig0000023b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021b ), + .Q(\blk00000003/sig00000239 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000234 ), + .Q(\blk00000003/sig00000238 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022e ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a1_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022c ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a0_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000228 ), + .R(coef_ld), + .Q(\blk00000003/sig00000227 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000224 ), + .R(coef_ld), + .Q(\blk00000003/sig00000222 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000237 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000235 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000236 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000233 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000234 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000231 ), + .Q(\blk00000003/sig00000232 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000099 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022f ), + .Q(\blk00000003/sig00000230 ) + ); + MUXCY_D \blk00000003/blk00000098 ( + .CI(\blk00000003/sig0000022b ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022d ), + .O(\NLW_blk00000003/blk00000098_O_UNCONNECTED ), + .LO(\blk00000003/sig0000022e ) + ); + MUXCY_D \blk00000003/blk00000097 ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022a ), + .O(\blk00000003/sig0000022b ), + .LO(\blk00000003/sig0000022c ) + ); + MUXCY_D \blk00000003/blk00000096 ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000229 ), + .O(\blk00000003/sig00000226 ), + .LO(\NLW_blk00000003/blk00000096_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000095 ( + .CI(\blk00000003/sig00000226 ), + .DI(\blk00000003/sig00000227 ), + .S(coef_we), + .O(\NLW_blk00000003/blk00000095_O_UNCONNECTED ), + .LO(\blk00000003/sig00000228 ) + ); + MUXCY_D \blk00000003/blk00000094 ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000225 ), + .O(\blk00000003/sig00000221 ), + .LO(\NLW_blk00000003/blk00000094_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000093 ( + .CI(\blk00000003/sig00000221 ), + .DI(\blk00000003/sig00000222 ), + .S(\blk00000003/sig00000223 ), + .O(\NLW_blk00000003/blk00000093_O_UNCONNECTED ), + .LO(\blk00000003/sig00000224 ) + ); + XORCY \blk00000003/blk00000092 ( + .CI(\blk00000003/sig0000021a ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000218 ) + ); + MUXCY_D \blk00000003/blk00000091 ( + .CI(\blk00000003/sig0000021e ), + .DI(\blk00000003/sig0000021f ), + .S(\blk00000003/sig00000220 ), + .O(\NLW_blk00000003/blk00000091_O_UNCONNECTED ), + .LO(\blk00000003/sig0000021a ) + ); + MUXCY_D \blk00000003/blk00000090 ( + .CI(\blk00000003/sig0000021b ), + .DI(\blk00000003/sig0000021c ), + .S(\blk00000003/sig0000021d ), + .O(\blk00000003/sig0000021e ), + .LO(\NLW_blk00000003/blk00000090_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000008f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021b ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000008e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000218 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000219 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e5 ), + .R(sclr), + .Q(\blk00000003/sig000001e4 ) + ); + FDR #( + .INIT ( 1'b1 )) + \blk00000003/blk00000029 ( + .C(clk), + .D(\blk00000003/sig000000b7 ), + .R(sclr), + .Q(\blk00000003/sig000000b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000028 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e4 ), + .R(sclr), + .Q(\blk00000003/sig000001e1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e3 ), + .R(\blk00000003/sig000001de ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e1 ), + .R(sclr), + .Q(\blk00000003/sig000001e2 ) + ); + FDRE \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001df ), + .R(sclr), + .Q(\blk00000003/sig000001e0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001dd ), + .R(\blk00000003/sig000001de ), + .Q(rdy) + ); + FDSE \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001db ), + .S(sclr), + .Q(\blk00000003/sig000001dc ) + ); + FDRE \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d9 ), + .R(sclr), + .Q(\blk00000003/sig000001da ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000021 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cb ), + .S(sclr), + .Q(NlwRenamedSig_OI_rfd) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000020 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001c9 ), + .R(sclr), + .Q(\blk00000003/sig000001d8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d7 ), + .R(sclr), + .Q(\blk00000003/sig000001c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001c5 ), + .R(sclr), + .Q(\blk00000003/sig000001d6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d5 ), + .R(sclr), + .Q(\blk00000003/sig000001c3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d3 ), + .R(sclr), + .Q(\blk00000003/sig000001d4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d1 ), + .R(sclr), + .Q(\blk00000003/sig000001d2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cf ), + .R(sclr), + .Q(\NLW_blk00000003/blk0000001a_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000019 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cf ), + .R(sclr), + .Q(\blk00000003/sig000001d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000018 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cd ), + .Q(\blk00000003/sig000001ce ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000017 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c1 ), + .R(sclr), + .Q(\blk00000003/sig000000bf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000016 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000bc ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000016_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000015 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000bd ), + .S(sclr), + .Q(\blk00000003/sig000001cc ) + ); + MUXCY \blk00000003/blk00000014 ( + .CI(\blk00000003/sig000001c8 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig000001ca ), + .O(\blk00000003/sig000001cb ) + ); + MUXCY_D \blk00000003/blk00000013 ( + .CI(\blk00000003/sig000001c6 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001c7 ), + .O(\blk00000003/sig000001c8 ), + .LO(\blk00000003/sig000001c9 ) + ); + MUXCY_D \blk00000003/blk00000012 ( + .CI(\blk00000003/sig000001c3 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001c4 ), + .O(\NLW_blk00000003/blk00000012_O_UNCONNECTED ), + .LO(\blk00000003/sig000001c5 ) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000011 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000011_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk00000011_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000011_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000011_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000011_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000011_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000011_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b1 , \blk00000003/sig00000049 , \blk00000003/sig000000b5 , +\blk00000003/sig000000b3 , \blk00000003/sig000000b5 }), + .PCIN({\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , +\blk00000003/sig00000156 , \blk00000003/sig00000157 , \blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , +\blk00000003/sig0000015b , \blk00000003/sig0000015c , \blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , +\blk00000003/sig00000160 , \blk00000003/sig00000161 , \blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , +\blk00000003/sig00000165 , \blk00000003/sig00000166 , \blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , +\blk00000003/sig0000016a , \blk00000003/sig0000016b , \blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , +\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000011_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000011_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000011_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000011_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , \blk00000003/sig000000f7 , +\blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , \blk00000003/sig000000fb , \blk00000003/sig000000fc , +\blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , +\blk00000003/sig00000102 , \blk00000003/sig00000103 , \blk00000003/sig00000104 }), + .BCOUT({\NLW_blk00000003/blk00000011_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000011_P<47>_UNCONNECTED , \blk00000003/sig0000017c , \blk00000003/sig0000017d , \blk00000003/sig0000017e , +\blk00000003/sig0000017f , \blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 , \blk00000003/sig00000183 , +\blk00000003/sig00000184 , \blk00000003/sig00000185 , \blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , +\blk00000003/sig00000189 , \blk00000003/sig0000018a , \blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , +\blk00000003/sig0000018e , \blk00000003/sig0000018f , \blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , +\blk00000003/sig00000193 , \blk00000003/sig00000194 , \blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , +\blk00000003/sig00000198 , \blk00000003/sig00000199 , \blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , +\blk00000003/sig0000019d , \blk00000003/sig0000019e , \blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , +\blk00000003/sig000001a2 , \blk00000003/sig000001a3 , \blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , +\blk00000003/sig000001a7 , \blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa }), + .A({\blk00000003/sig000001ab , \blk00000003/sig000001ab , \blk00000003/sig000001ab , \blk00000003/sig000001ab , \blk00000003/sig000001ab , +\blk00000003/sig000001ab , \blk00000003/sig000001ab , \blk00000003/sig000001ac , \blk00000003/sig000001ad , \blk00000003/sig000001ae , +\blk00000003/sig000001af , \blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , +\blk00000003/sig000001b4 , \blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , +\blk00000003/sig000001b9 , \blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , +\blk00000003/sig000001be , \blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 , \blk00000003/sig000001c2 }), + .PCOUT({\NLW_blk00000003/blk00000011_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000010 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000010_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk00000010_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000010_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000010_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000010_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000010_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000010_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b1 , \blk00000003/sig00000049 , \blk00000003/sig000000b5 , +\blk00000003/sig000000b3 , \blk00000003/sig000000b5 }), + .PCIN({\blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , \blk00000003/sig000000c7 , +\blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , +\blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , +\blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , +\blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , +\blk00000003/sig000000dc , \blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , +\blk00000003/sig000000e1 , \blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , +\blk00000003/sig000000e6 , \blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , +\blk00000003/sig000000eb , \blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , +\blk00000003/sig000000f0 , \blk00000003/sig000000f1 , \blk00000003/sig000000f2 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000010_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000010_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000010_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000010_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , \blk00000003/sig000000f7 , +\blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , \blk00000003/sig000000fb , \blk00000003/sig000000fc , +\blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , +\blk00000003/sig00000102 , \blk00000003/sig00000103 , \blk00000003/sig00000104 }), + .BCOUT({\NLW_blk00000003/blk00000010_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000010_P<47>_UNCONNECTED , \blk00000003/sig00000105 , \blk00000003/sig00000106 , \blk00000003/sig00000107 , +\blk00000003/sig00000108 , \blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b , \blk00000003/sig0000010c , +\blk00000003/sig0000010d , \blk00000003/sig0000010e , \blk00000003/sig0000010f , \blk00000003/sig00000110 , \blk00000003/sig00000111 , +\blk00000003/sig00000112 , \blk00000003/sig00000113 , \blk00000003/sig00000114 , \blk00000003/sig00000115 , \blk00000003/sig00000116 , +\blk00000003/sig00000117 , \blk00000003/sig00000118 , \blk00000003/sig00000119 , \blk00000003/sig0000011a , \blk00000003/sig0000011b , +\blk00000003/sig0000011c , \blk00000003/sig0000011d , \blk00000003/sig0000011e , \blk00000003/sig0000011f , \blk00000003/sig00000120 , +\blk00000003/sig00000121 , \blk00000003/sig00000122 , \blk00000003/sig00000123 , \blk00000003/sig00000124 , \blk00000003/sig00000125 , +\blk00000003/sig00000126 , \blk00000003/sig00000127 , \blk00000003/sig00000128 , \blk00000003/sig00000129 , \blk00000003/sig0000012a , +\blk00000003/sig0000012b , \blk00000003/sig0000012c , \blk00000003/sig0000012d , \blk00000003/sig0000012e , \blk00000003/sig0000012f , +\blk00000003/sig00000130 , \blk00000003/sig00000131 , \blk00000003/sig00000132 , \blk00000003/sig00000133 }), + .A({\blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , +\blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000135 , \blk00000003/sig00000136 , \blk00000003/sig00000137 , +\blk00000003/sig00000138 , \blk00000003/sig00000139 , \blk00000003/sig0000013a , \blk00000003/sig0000013b , \blk00000003/sig0000013c , +\blk00000003/sig0000013d , \blk00000003/sig0000013e , \blk00000003/sig0000013f , \blk00000003/sig00000140 , \blk00000003/sig00000141 , +\blk00000003/sig00000142 , \blk00000003/sig00000143 , \blk00000003/sig00000144 , \blk00000003/sig00000145 , \blk00000003/sig00000146 , +\blk00000003/sig00000147 , \blk00000003/sig00000148 , \blk00000003/sig00000149 , \blk00000003/sig0000014a , \blk00000003/sig0000014b }), + .PCOUT({\NLW_blk00000003/blk00000010_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + MUXCY_D \blk00000003/blk0000000f ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000c2 ), + .O(\blk00000003/sig000000be ), + .LO(\NLW_blk00000003/blk0000000f_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000000e ( + .CI(\blk00000003/sig000000be ), + .DI(\blk00000003/sig000000bf ), + .S(\blk00000003/sig000000c0 ), + .O(\blk00000003/sig000000b6 ), + .LO(\blk00000003/sig000000c1 ) + ); + XORCY \blk00000003/blk0000000d ( + .CI(\blk00000003/sig000000bc ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig000000bd ) + ); + MUXCY_D \blk00000003/blk0000000c ( + .CI(\blk00000003/sig000000b9 ), + .DI(\blk00000003/sig000000ba ), + .S(\blk00000003/sig000000bb ), + .O(\NLW_blk00000003/blk0000000c_O_UNCONNECTED ), + .LO(\blk00000003/sig000000bc ) + ); + MUXCY_D \blk00000003/blk0000000b ( + .CI(\blk00000003/sig000000b6 ), + .DI(\blk00000003/sig000000b7 ), + .S(\blk00000003/sig000000b8 ), + .O(\blk00000003/sig000000b9 ), + .LO(\NLW_blk00000003/blk0000000b_LO_UNCONNECTED ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000a ( + .C(clk), + .D(\blk00000003/sig000000b4 ), + .Q(\blk00000003/sig000000b5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000009 ( + .C(clk), + .D(\blk00000003/sig000000b2 ), + .Q(\blk00000003/sig000000b3 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000008 ( + .C(clk), + .D(\blk00000003/sig000000b0 ), + .Q(\blk00000003/sig000000b1 ) + ); + XORCY \blk00000003/blk00000007 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig000000af ) + ); + MUXCY_D \blk00000003/blk00000006 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ad ), + .S(\blk00000003/sig000000ae ), + .O(\NLW_blk00000003/blk00000006_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000006_LO_UNCONNECTED ) + ); + VCC \blk00000003/blk00000005 ( + .P(\blk00000003/sig000000ac ) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000002b/blk0000008d ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk0000002b/sig00000800 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000008c ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000008c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fe ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000008b ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000008a ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ff ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000089 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000088 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fa ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000087 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000086 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000085 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000084 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000083 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000082 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000081 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000080 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007f ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007e ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007d ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ef ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007c ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ee ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007b ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007a ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ec ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000079 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007eb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000078 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ed ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000077 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000076 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000075 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ea ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000074 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000073 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000072 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000071 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000070 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006f ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006e ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006d ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007df ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006c ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006b ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007dd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006a ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007dc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000069 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007de ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000068 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007da ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000067 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000066 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000066_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007db ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000065 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000065_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000064 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000064_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000063 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000063_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000062 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000062_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000061 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000061_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000060 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000060_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000005f ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000005f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000005e ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000005e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000005d ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000005d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000005c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ff ), + .Q(\blk00000003/sig000001e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fe ), + .Q(\blk00000003/sig000001e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fd ), + .Q(\blk00000003/sig000001ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fc ), + .Q(\blk00000003/sig000001eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fb ), + .Q(\blk00000003/sig000001ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fa ), + .Q(\blk00000003/sig000001ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f9 ), + .Q(\blk00000003/sig000001ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f8 ), + .Q(\blk00000003/sig000001ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f7 ), + .Q(\blk00000003/sig000001f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f6 ), + .Q(\blk00000003/sig000001f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f5 ), + .Q(\blk00000003/sig000001f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f4 ), + .Q(\blk00000003/sig000001f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f3 ), + .Q(\blk00000003/sig000001f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f2 ), + .Q(\blk00000003/sig000001f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f1 ), + .Q(\blk00000003/sig000001f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f0 ), + .Q(\blk00000003/sig000001f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ef ), + .Q(\blk00000003/sig000001f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ee ), + .Q(\blk00000003/sig000001f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ed ), + .Q(\blk00000003/sig000001fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ec ), + .Q(\blk00000003/sig000001fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007eb ), + .Q(\blk00000003/sig000001fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ea ), + .Q(\blk00000003/sig000001fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e9 ), + .Q(\blk00000003/sig000001fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e8 ), + .Q(\blk00000003/sig000001ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e7 ), + .Q(\blk00000003/sig00000200 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e6 ), + .Q(\blk00000003/sig00000201 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e5 ), + .Q(\blk00000003/sig00000202 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e4 ), + .Q(\blk00000003/sig00000203 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e3 ), + .Q(\blk00000003/sig00000204 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e2 ), + .Q(\blk00000003/sig00000205 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e1 ), + .Q(\blk00000003/sig00000206 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e0 ), + .Q(\blk00000003/sig00000207 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007df ), + .Q(\blk00000003/sig00000208 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007de ), + .Q(\blk00000003/sig00000209 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007dd ), + .Q(\blk00000003/sig0000020a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007dc ), + .Q(\blk00000003/sig0000020b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007db ), + .Q(\blk00000003/sig0000020c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007da ), + .Q(\blk00000003/sig0000020d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000036 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d9 ), + .Q(\blk00000003/sig0000020e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000035 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d8 ), + .Q(\blk00000003/sig0000020f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000034 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d7 ), + .Q(\blk00000003/sig00000210 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d6 ), + .Q(\blk00000003/sig00000211 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d5 ), + .Q(\blk00000003/sig00000212 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d4 ), + .Q(\blk00000003/sig00000213 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d3 ), + .Q(\blk00000003/sig00000214 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d2 ), + .Q(\blk00000003/sig00000215 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d1 ), + .Q(\blk00000003/sig00000216 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000002d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d0 ), + .Q(\blk00000003/sig00000217 ) + ); + GND \blk00000003/blk0000002b/blk0000002c ( + .G(\blk00000003/blk0000002b/sig000007cf ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000117/blk00000149 ( + .I0(ce), + .I1(\blk00000003/sig000004e6 ), + .O(\blk00000003/blk00000117/sig0000084f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000148 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047c ), + .Q(\blk00000003/blk00000117/sig0000084d ), + .Q15(\NLW_blk00000003/blk00000117/blk00000148_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000147 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047d ), + .Q(\blk00000003/blk00000117/sig0000084c ), + .Q15(\NLW_blk00000003/blk00000117/blk00000147_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000146 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047b ), + .Q(\blk00000003/blk00000117/sig0000084e ), + .Q15(\NLW_blk00000003/blk00000117/blk00000146_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000145 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047f ), + .Q(\blk00000003/blk00000117/sig0000084a ), + .Q15(\NLW_blk00000003/blk00000117/blk00000145_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000144 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000480 ), + .Q(\blk00000003/blk00000117/sig00000849 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000144_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000143 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047e ), + .Q(\blk00000003/blk00000117/sig0000084b ), + .Q15(\NLW_blk00000003/blk00000117/blk00000143_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000142 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000482 ), + .Q(\blk00000003/blk00000117/sig00000847 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000142_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000141 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000483 ), + .Q(\blk00000003/blk00000117/sig00000846 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000141_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000140 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000481 ), + .Q(\blk00000003/blk00000117/sig00000848 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000140_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013f ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000485 ), + .Q(\blk00000003/blk00000117/sig00000844 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013e ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000486 ), + .Q(\blk00000003/blk00000117/sig00000843 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013d ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000484 ), + .Q(\blk00000003/blk00000117/sig00000845 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013c ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000488 ), + .Q(\blk00000003/blk00000117/sig00000841 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013b ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000489 ), + .Q(\blk00000003/blk00000117/sig00000840 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013a ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000487 ), + .Q(\blk00000003/blk00000117/sig00000842 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000139 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048b ), + .Q(\blk00000003/blk00000117/sig0000083e ), + .Q15(\NLW_blk00000003/blk00000117/blk00000139_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000138 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048c ), + .Q(\blk00000003/blk00000117/sig0000083d ), + .Q15(\NLW_blk00000003/blk00000117/blk00000138_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000137 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048a ), + .Q(\blk00000003/blk00000117/sig0000083f ), + .Q15(\NLW_blk00000003/blk00000117/blk00000137_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000136 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048e ), + .Q(\blk00000003/blk00000117/sig0000083b ), + .Q15(\NLW_blk00000003/blk00000117/blk00000136_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000135 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048f ), + .Q(\blk00000003/blk00000117/sig0000083a ), + .Q15(\NLW_blk00000003/blk00000117/blk00000135_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000134 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048d ), + .Q(\blk00000003/blk00000117/sig0000083c ), + .Q15(\NLW_blk00000003/blk00000117/blk00000134_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000133 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000491 ), + .Q(\blk00000003/blk00000117/sig00000838 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000133_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000132 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000492 ), + .Q(\blk00000003/blk00000117/sig00000837 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000132_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000131 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000490 ), + .Q(\blk00000003/blk00000117/sig00000839 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000131_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000130 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084e ), + .Q(\blk00000003/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084d ), + .Q(\blk00000003/sig000003da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084c ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084b ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084a ), + .Q(\blk00000003/sig000003dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000849 ), + .Q(\blk00000003/sig000003de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000848 ), + .Q(\blk00000003/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000847 ), + .Q(\blk00000003/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000846 ), + .Q(\blk00000003/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000845 ), + .Q(\blk00000003/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000844 ), + .Q(\blk00000003/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000843 ), + .Q(\blk00000003/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000842 ), + .Q(\blk00000003/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000841 ), + .Q(\blk00000003/sig000003e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000840 ), + .Q(\blk00000003/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000121 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083f ), + .Q(\blk00000003/sig000003e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000120 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083e ), + .Q(\blk00000003/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083d ), + .Q(\blk00000003/sig000003ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083c ), + .Q(\blk00000003/sig000003eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083b ), + .Q(\blk00000003/sig000003ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083a ), + .Q(\blk00000003/sig000003ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000839 ), + .Q(\blk00000003/sig000003ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000838 ), + .Q(\blk00000003/sig000003ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000119 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000837 ), + .Q(\blk00000003/sig000003f0 ) + ); + GND \blk00000003/blk00000117/blk00000118 ( + .G(\blk00000003/blk00000117/sig00000836 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000014a/blk0000017c ( + .I0(ce), + .I1(\blk00000003/sig000004e4 ), + .O(\blk00000003/blk0000014a/sig0000089e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000017b ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004f8 ), + .Q(\blk00000003/blk0000014a/sig0000089c ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000017b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000017a ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004f9 ), + .Q(\blk00000003/blk0000014a/sig0000089b ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000017a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000179 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004f7 ), + .Q(\blk00000003/blk0000014a/sig0000089d ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000179_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000178 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fb ), + .Q(\blk00000003/blk0000014a/sig00000899 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000178_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000177 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fc ), + .Q(\blk00000003/blk0000014a/sig00000898 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000177_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000176 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fa ), + .Q(\blk00000003/blk0000014a/sig0000089a ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000176_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000175 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fe ), + .Q(\blk00000003/blk0000014a/sig00000896 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000175_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000174 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004ff ), + .Q(\blk00000003/blk0000014a/sig00000895 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000173 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fd ), + .Q(\blk00000003/blk0000014a/sig00000897 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000172 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000501 ), + .Q(\blk00000003/blk0000014a/sig00000893 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000172_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000171 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000502 ), + .Q(\blk00000003/blk0000014a/sig00000892 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000171_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000170 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000500 ), + .Q(\blk00000003/blk0000014a/sig00000894 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000170_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016f ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000504 ), + .Q(\blk00000003/blk0000014a/sig00000890 ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016e ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000505 ), + .Q(\blk00000003/blk0000014a/sig0000088f ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016d ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000503 ), + .Q(\blk00000003/blk0000014a/sig00000891 ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016c ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000507 ), + .Q(\blk00000003/blk0000014a/sig0000088d ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016b ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000508 ), + .Q(\blk00000003/blk0000014a/sig0000088c ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016a ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000506 ), + .Q(\blk00000003/blk0000014a/sig0000088e ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000169 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050a ), + .Q(\blk00000003/blk0000014a/sig0000088a ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000169_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000168 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050b ), + .Q(\blk00000003/blk0000014a/sig00000889 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000168_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000167 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000509 ), + .Q(\blk00000003/blk0000014a/sig0000088b ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000167_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000166 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050d ), + .Q(\blk00000003/blk0000014a/sig00000887 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000166_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000165 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050e ), + .Q(\blk00000003/blk0000014a/sig00000886 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000165_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000164 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050c ), + .Q(\blk00000003/blk0000014a/sig00000888 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000164_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000089d ), + .Q(\blk00000003/sig000003f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000089c ), + .Q(\blk00000003/sig000003f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000161 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000089b ), + .Q(\blk00000003/sig000003f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000160 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000089a ), + .Q(\blk00000003/sig000003f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000899 ), + .Q(\blk00000003/sig000003f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000898 ), + .Q(\blk00000003/sig000003f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000897 ), + .Q(\blk00000003/sig000003f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000896 ), + .Q(\blk00000003/sig000003f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000895 ), + .Q(\blk00000003/sig000003f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000894 ), + .Q(\blk00000003/sig000003fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000159 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000893 ), + .Q(\blk00000003/sig000003fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000158 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000892 ), + .Q(\blk00000003/sig000003fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000157 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000891 ), + .Q(\blk00000003/sig000003fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000156 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000890 ), + .Q(\blk00000003/sig000003fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000155 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088f ), + .Q(\blk00000003/sig000003ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000154 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088e ), + .Q(\blk00000003/sig00000400 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000153 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088d ), + .Q(\blk00000003/sig00000401 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000152 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088c ), + .Q(\blk00000003/sig00000402 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000151 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088b ), + .Q(\blk00000003/sig00000403 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000150 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088a ), + .Q(\blk00000003/sig00000404 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000014f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000889 ), + .Q(\blk00000003/sig00000405 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000014e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000888 ), + .Q(\blk00000003/sig00000406 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000014d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000887 ), + .Q(\blk00000003/sig00000407 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000014c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000886 ), + .Q(\blk00000003/sig00000408 ) + ); + GND \blk00000003/blk0000014a/blk0000014b ( + .G(\blk00000003/blk0000014a/sig00000885 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000017d/blk000001af ( + .I0(ce), + .I1(\blk00000003/sig000004e6 ), + .O(\blk00000003/blk0000017d/sig000008ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001ae ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ac ), + .Q(\blk00000003/blk0000017d/sig000008eb ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001ad ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ad ), + .Q(\blk00000003/blk0000017d/sig000008ea ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001ac ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ab ), + .Q(\blk00000003/blk0000017d/sig000008ec ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001ab ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004af ), + .Q(\blk00000003/blk0000017d/sig000008e8 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001aa ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b0 ), + .Q(\blk00000003/blk0000017d/sig000008e7 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a9 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ae ), + .Q(\blk00000003/blk0000017d/sig000008e9 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a8 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b2 ), + .Q(\blk00000003/blk0000017d/sig000008e5 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a7 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b3 ), + .Q(\blk00000003/blk0000017d/sig000008e4 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a6 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b1 ), + .Q(\blk00000003/blk0000017d/sig000008e6 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a5 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b5 ), + .Q(\blk00000003/blk0000017d/sig000008e2 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a4 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b6 ), + .Q(\blk00000003/blk0000017d/sig000008e1 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a3 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b4 ), + .Q(\blk00000003/blk0000017d/sig000008e3 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a2 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b8 ), + .Q(\blk00000003/blk0000017d/sig000008df ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a1 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b9 ), + .Q(\blk00000003/blk0000017d/sig000008de ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a0 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b7 ), + .Q(\blk00000003/blk0000017d/sig000008e0 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019f ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004bb ), + .Q(\blk00000003/blk0000017d/sig000008dc ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019e ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004bc ), + .Q(\blk00000003/blk0000017d/sig000008db ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019d ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ba ), + .Q(\blk00000003/blk0000017d/sig000008dd ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019c ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004be ), + .Q(\blk00000003/blk0000017d/sig000008d9 ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019b ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004bf ), + .Q(\blk00000003/blk0000017d/sig000008d8 ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019a ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004bd ), + .Q(\blk00000003/blk0000017d/sig000008da ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk00000199 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004c1 ), + .Q(\blk00000003/blk0000017d/sig000008d6 ), + .Q15(\NLW_blk00000003/blk0000017d/blk00000199_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk00000198 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004c2 ), + .Q(\blk00000003/blk0000017d/sig000008d5 ), + .Q15(\NLW_blk00000003/blk0000017d/blk00000198_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk00000197 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004c0 ), + .Q(\blk00000003/blk0000017d/sig000008d7 ), + .Q15(\NLW_blk00000003/blk0000017d/blk00000197_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000196 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008ec ), + .Q(\blk00000003/sig00000439 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000195 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008eb ), + .Q(\blk00000003/sig0000043a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000194 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008ea ), + .Q(\blk00000003/sig0000043b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000193 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e9 ), + .Q(\blk00000003/sig0000043c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000192 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e8 ), + .Q(\blk00000003/sig0000043d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000191 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e7 ), + .Q(\blk00000003/sig0000043e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000190 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e6 ), + .Q(\blk00000003/sig0000043f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e5 ), + .Q(\blk00000003/sig00000440 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e4 ), + .Q(\blk00000003/sig00000441 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e3 ), + .Q(\blk00000003/sig00000442 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e2 ), + .Q(\blk00000003/sig00000443 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e1 ), + .Q(\blk00000003/sig00000444 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e0 ), + .Q(\blk00000003/sig00000445 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000189 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008df ), + .Q(\blk00000003/sig00000446 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000188 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008de ), + .Q(\blk00000003/sig00000447 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000187 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008dd ), + .Q(\blk00000003/sig00000448 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000186 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008dc ), + .Q(\blk00000003/sig00000449 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000185 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008db ), + .Q(\blk00000003/sig0000044a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000184 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008da ), + .Q(\blk00000003/sig0000044b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000183 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d9 ), + .Q(\blk00000003/sig0000044c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000182 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d8 ), + .Q(\blk00000003/sig0000044d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000181 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d7 ), + .Q(\blk00000003/sig0000044e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000180 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d6 ), + .Q(\blk00000003/sig0000044f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000017f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d5 ), + .Q(\blk00000003/sig00000450 ) + ); + GND \blk00000003/blk0000017d/blk0000017e ( + .G(\blk00000003/blk0000017d/sig000008d4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001b0/blk000001e2 ( + .I0(ce), + .I1(\blk00000003/sig000004e4 ), + .O(\blk00000003/blk000001b0/sig0000093c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001e1 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000510 ), + .Q(\blk00000003/blk000001b0/sig0000093a ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001e0 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000511 ), + .Q(\blk00000003/blk000001b0/sig00000939 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001df ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000050f ), + .Q(\blk00000003/blk000001b0/sig0000093b ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001de ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000513 ), + .Q(\blk00000003/blk000001b0/sig00000937 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001dd ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000514 ), + .Q(\blk00000003/blk000001b0/sig00000936 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001dc ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000512 ), + .Q(\blk00000003/blk000001b0/sig00000938 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001db ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000516 ), + .Q(\blk00000003/blk000001b0/sig00000934 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001da ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000517 ), + .Q(\blk00000003/blk000001b0/sig00000933 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d9 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000515 ), + .Q(\blk00000003/blk000001b0/sig00000935 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d8 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000519 ), + .Q(\blk00000003/blk000001b0/sig00000931 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d7 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051a ), + .Q(\blk00000003/blk000001b0/sig00000930 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d6 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000518 ), + .Q(\blk00000003/blk000001b0/sig00000932 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d5 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051c ), + .Q(\blk00000003/blk000001b0/sig0000092e ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d4 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051d ), + .Q(\blk00000003/blk000001b0/sig0000092d ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d3 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051b ), + .Q(\blk00000003/blk000001b0/sig0000092f ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d2 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051f ), + .Q(\blk00000003/blk000001b0/sig0000092b ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d1 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000520 ), + .Q(\blk00000003/blk000001b0/sig0000092a ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d0 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051e ), + .Q(\blk00000003/blk000001b0/sig0000092c ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001cf ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000522 ), + .Q(\blk00000003/blk000001b0/sig00000928 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001ce ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000523 ), + .Q(\blk00000003/blk000001b0/sig00000927 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001cd ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000521 ), + .Q(\blk00000003/blk000001b0/sig00000929 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001cc ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000525 ), + .Q(\blk00000003/blk000001b0/sig00000925 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001cb ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000526 ), + .Q(\blk00000003/blk000001b0/sig00000924 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001ca ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000524 ), + .Q(\blk00000003/blk000001b0/sig00000926 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000093b ), + .Q(\blk00000003/sig00000451 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000093a ), + .Q(\blk00000003/sig00000452 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000939 ), + .Q(\blk00000003/sig00000453 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000938 ), + .Q(\blk00000003/sig00000454 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000937 ), + .Q(\blk00000003/sig00000455 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000936 ), + .Q(\blk00000003/sig00000456 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000935 ), + .Q(\blk00000003/sig00000457 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000934 ), + .Q(\blk00000003/sig00000458 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000933 ), + .Q(\blk00000003/sig00000459 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000932 ), + .Q(\blk00000003/sig0000045a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000931 ), + .Q(\blk00000003/sig0000045b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000930 ), + .Q(\blk00000003/sig0000045c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092f ), + .Q(\blk00000003/sig0000045d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092e ), + .Q(\blk00000003/sig0000045e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092d ), + .Q(\blk00000003/sig0000045f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092c ), + .Q(\blk00000003/sig00000460 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092b ), + .Q(\blk00000003/sig00000461 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092a ), + .Q(\blk00000003/sig00000462 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000929 ), + .Q(\blk00000003/sig00000463 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000928 ), + .Q(\blk00000003/sig00000464 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000927 ), + .Q(\blk00000003/sig00000465 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000926 ), + .Q(\blk00000003/sig00000466 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000925 ), + .Q(\blk00000003/sig00000467 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000924 ), + .Q(\blk00000003/sig00000468 ) + ); + GND \blk00000003/blk000001b0/blk000001b1 ( + .G(\blk00000003/blk000001b0/sig00000923 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001e3/blk00000215 ( + .I0(ce), + .I1(\blk00000003/sig000004e5 ), + .O(\blk00000003/blk000001e3/sig0000098b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000214 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/blk000001e3/sig00000989 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000214_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000213 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/blk000001e3/sig00000988 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000213_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000212 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/blk000001e3/sig0000098a ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000212_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000211 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/blk000001e3/sig00000986 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000211_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000210 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/blk000001e3/sig00000985 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000210_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020f ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/blk000001e3/sig00000987 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020e ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/blk000001e3/sig00000983 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020d ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/blk000001e3/sig00000982 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020c ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/blk000001e3/sig00000984 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020b ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/blk000001e3/sig00000980 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020a ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/blk000001e3/sig0000097f ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000209 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/blk000001e3/sig00000981 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000209_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000208 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/blk000001e3/sig0000097d ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000208_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000207 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/blk000001e3/sig0000097c ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000207_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000206 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/blk000001e3/sig0000097e ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000206_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000205 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/blk000001e3/sig0000097a ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000205_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000204 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/blk000001e3/sig00000979 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000204_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000203 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/blk000001e3/sig0000097b ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000203_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000202 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002ea ), + .Q(\blk00000003/blk000001e3/sig00000977 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000202_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000201 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002eb ), + .Q(\blk00000003/blk000001e3/sig00000976 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000201_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000200 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e9 ), + .Q(\blk00000003/blk000001e3/sig00000978 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000200_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk000001ff ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002ed ), + .Q(\blk00000003/blk000001e3/sig00000974 ), + .Q15(\NLW_blk00000003/blk000001e3/blk000001ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk000001fe ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002ee ), + .Q(\blk00000003/blk000001e3/sig00000973 ), + .Q15(\NLW_blk00000003/blk000001e3/blk000001fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk000001fd ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002ec ), + .Q(\blk00000003/blk000001e3/sig00000975 ), + .Q15(\NLW_blk00000003/blk000001e3/blk000001fd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000098a ), + .Q(\blk00000003/sig0000047b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000989 ), + .Q(\blk00000003/sig0000047c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000988 ), + .Q(\blk00000003/sig0000047d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000987 ), + .Q(\blk00000003/sig0000047e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000986 ), + .Q(\blk00000003/sig0000047f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000985 ), + .Q(\blk00000003/sig00000480 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000984 ), + .Q(\blk00000003/sig00000481 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000983 ), + .Q(\blk00000003/sig00000482 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000982 ), + .Q(\blk00000003/sig00000483 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000981 ), + .Q(\blk00000003/sig00000484 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000980 ), + .Q(\blk00000003/sig00000485 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097f ), + .Q(\blk00000003/sig00000486 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097e ), + .Q(\blk00000003/sig00000487 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097d ), + .Q(\blk00000003/sig00000488 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097c ), + .Q(\blk00000003/sig00000489 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097b ), + .Q(\blk00000003/sig0000048a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097a ), + .Q(\blk00000003/sig0000048b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000979 ), + .Q(\blk00000003/sig0000048c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000978 ), + .Q(\blk00000003/sig0000048d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000977 ), + .Q(\blk00000003/sig0000048e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000976 ), + .Q(\blk00000003/sig0000048f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000975 ), + .Q(\blk00000003/sig00000490 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000974 ), + .Q(\blk00000003/sig00000491 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000973 ), + .Q(\blk00000003/sig00000492 ) + ); + GND \blk00000003/blk000001e3/blk000001e4 ( + .G(\blk00000003/blk000001e3/sig00000972 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000216/blk00000248 ( + .I0(ce), + .I1(\blk00000003/sig000004e3 ), + .O(\blk00000003/blk00000216/sig000009da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000247 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000528 ), + .Q(\blk00000003/blk00000216/sig000009d8 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000247_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000246 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000529 ), + .Q(\blk00000003/blk00000216/sig000009d7 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000245 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000527 ), + .Q(\blk00000003/blk00000216/sig000009d9 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000244 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052b ), + .Q(\blk00000003/blk00000216/sig000009d5 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000244_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000243 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052c ), + .Q(\blk00000003/blk00000216/sig000009d4 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000243_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000242 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052a ), + .Q(\blk00000003/blk00000216/sig000009d6 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000242_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000241 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052e ), + .Q(\blk00000003/blk00000216/sig000009d2 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000241_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000240 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052f ), + .Q(\blk00000003/blk00000216/sig000009d1 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000240_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023f ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052d ), + .Q(\blk00000003/blk00000216/sig000009d3 ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023e ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000531 ), + .Q(\blk00000003/blk00000216/sig000009cf ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023d ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000532 ), + .Q(\blk00000003/blk00000216/sig000009ce ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023c ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000530 ), + .Q(\blk00000003/blk00000216/sig000009d0 ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023b ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000534 ), + .Q(\blk00000003/blk00000216/sig000009cc ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023a ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000535 ), + .Q(\blk00000003/blk00000216/sig000009cb ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000239 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000533 ), + .Q(\blk00000003/blk00000216/sig000009cd ), + .Q15(\NLW_blk00000003/blk00000216/blk00000239_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000238 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000537 ), + .Q(\blk00000003/blk00000216/sig000009c9 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000238_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000237 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000538 ), + .Q(\blk00000003/blk00000216/sig000009c8 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000237_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000236 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000536 ), + .Q(\blk00000003/blk00000216/sig000009ca ), + .Q15(\NLW_blk00000003/blk00000216/blk00000236_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000235 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053a ), + .Q(\blk00000003/blk00000216/sig000009c6 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000235_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000234 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053b ), + .Q(\blk00000003/blk00000216/sig000009c5 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000234_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000233 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000539 ), + .Q(\blk00000003/blk00000216/sig000009c7 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000233_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000232 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053d ), + .Q(\blk00000003/blk00000216/sig000009c3 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000232_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000231 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053e ), + .Q(\blk00000003/blk00000216/sig000009c2 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000231_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000230 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053c ), + .Q(\blk00000003/blk00000216/sig000009c4 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000230_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d9 ), + .Q(\blk00000003/sig00000493 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d8 ), + .Q(\blk00000003/sig00000494 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d7 ), + .Q(\blk00000003/sig00000495 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d6 ), + .Q(\blk00000003/sig00000496 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d5 ), + .Q(\blk00000003/sig00000497 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d4 ), + .Q(\blk00000003/sig00000498 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000229 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d3 ), + .Q(\blk00000003/sig00000499 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000228 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d2 ), + .Q(\blk00000003/sig0000049a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000227 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d1 ), + .Q(\blk00000003/sig0000049b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000226 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d0 ), + .Q(\blk00000003/sig0000049c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000225 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009cf ), + .Q(\blk00000003/sig0000049d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000224 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009ce ), + .Q(\blk00000003/sig0000049e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000223 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009cd ), + .Q(\blk00000003/sig0000049f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000222 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009cc ), + .Q(\blk00000003/sig000004a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000221 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009cb ), + .Q(\blk00000003/sig000004a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000220 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009ca ), + .Q(\blk00000003/sig000004a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c9 ), + .Q(\blk00000003/sig000004a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c8 ), + .Q(\blk00000003/sig000004a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c7 ), + .Q(\blk00000003/sig000004a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c6 ), + .Q(\blk00000003/sig000004a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c5 ), + .Q(\blk00000003/sig000004a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c4 ), + .Q(\blk00000003/sig000004a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000219 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c3 ), + .Q(\blk00000003/sig000004a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000218 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c2 ), + .Q(\blk00000003/sig000004aa ) + ); + GND \blk00000003/blk00000216/blk00000217 ( + .G(\blk00000003/blk00000216/sig000009c1 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000249/blk0000027b ( + .I0(ce), + .I1(\blk00000003/sig000004e5 ), + .O(\blk00000003/blk00000249/sig00000a29 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000027a ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000338 ), + .Q(\blk00000003/blk00000249/sig00000a27 ), + .Q15(\NLW_blk00000003/blk00000249/blk0000027a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000279 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000339 ), + .Q(\blk00000003/blk00000249/sig00000a26 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000279_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000278 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000337 ), + .Q(\blk00000003/blk00000249/sig00000a28 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000278_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000277 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033b ), + .Q(\blk00000003/blk00000249/sig00000a24 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000277_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000276 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033c ), + .Q(\blk00000003/blk00000249/sig00000a23 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000276_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000275 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033a ), + .Q(\blk00000003/blk00000249/sig00000a25 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000275_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000274 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033e ), + .Q(\blk00000003/blk00000249/sig00000a21 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000274_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000273 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033f ), + .Q(\blk00000003/blk00000249/sig00000a20 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000273_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000272 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033d ), + .Q(\blk00000003/blk00000249/sig00000a22 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000272_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000271 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000341 ), + .Q(\blk00000003/blk00000249/sig00000a1e ), + .Q15(\NLW_blk00000003/blk00000249/blk00000271_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000270 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000342 ), + .Q(\blk00000003/blk00000249/sig00000a1d ), + .Q15(\NLW_blk00000003/blk00000249/blk00000270_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026f ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000340 ), + .Q(\blk00000003/blk00000249/sig00000a1f ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026e ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000344 ), + .Q(\blk00000003/blk00000249/sig00000a1b ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026d ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000345 ), + .Q(\blk00000003/blk00000249/sig00000a1a ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026c ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000343 ), + .Q(\blk00000003/blk00000249/sig00000a1c ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026b ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000347 ), + .Q(\blk00000003/blk00000249/sig00000a18 ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026a ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000348 ), + .Q(\blk00000003/blk00000249/sig00000a17 ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000269 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000346 ), + .Q(\blk00000003/blk00000249/sig00000a19 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000269_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000268 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034a ), + .Q(\blk00000003/blk00000249/sig00000a15 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000268_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000267 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034b ), + .Q(\blk00000003/blk00000249/sig00000a14 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000267_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000266 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000349 ), + .Q(\blk00000003/blk00000249/sig00000a16 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000266_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000265 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034d ), + .Q(\blk00000003/blk00000249/sig00000a12 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000265_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000264 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034e ), + .Q(\blk00000003/blk00000249/sig00000a11 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000264_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000263 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034c ), + .Q(\blk00000003/blk00000249/sig00000a13 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000263_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000262 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a28 ), + .Q(\blk00000003/sig000004ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000261 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a27 ), + .Q(\blk00000003/sig000004ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000260 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a26 ), + .Q(\blk00000003/sig000004ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a25 ), + .Q(\blk00000003/sig000004ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a24 ), + .Q(\blk00000003/sig000004af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a23 ), + .Q(\blk00000003/sig000004b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a22 ), + .Q(\blk00000003/sig000004b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a21 ), + .Q(\blk00000003/sig000004b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a20 ), + .Q(\blk00000003/sig000004b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1f ), + .Q(\blk00000003/sig000004b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1e ), + .Q(\blk00000003/sig000004b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1d ), + .Q(\blk00000003/sig000004b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000256 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1c ), + .Q(\blk00000003/sig000004b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000255 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1b ), + .Q(\blk00000003/sig000004b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000254 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1a ), + .Q(\blk00000003/sig000004b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000253 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a19 ), + .Q(\blk00000003/sig000004ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000252 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a18 ), + .Q(\blk00000003/sig000004bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000251 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a17 ), + .Q(\blk00000003/sig000004bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000250 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a16 ), + .Q(\blk00000003/sig000004bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a15 ), + .Q(\blk00000003/sig000004be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a14 ), + .Q(\blk00000003/sig000004bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a13 ), + .Q(\blk00000003/sig000004c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a12 ), + .Q(\blk00000003/sig000004c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a11 ), + .Q(\blk00000003/sig000004c2 ) + ); + GND \blk00000003/blk00000249/blk0000024a ( + .G(\blk00000003/blk00000249/sig00000a10 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000027c/blk000002ae ( + .I0(ce), + .I1(\blk00000003/sig000004e3 ), + .O(\blk00000003/blk0000027c/sig00000a78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002ad ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000540 ), + .Q(\blk00000003/blk0000027c/sig00000a76 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002ac ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000541 ), + .Q(\blk00000003/blk0000027c/sig00000a75 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002ab ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000053f ), + .Q(\blk00000003/blk0000027c/sig00000a77 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002aa ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000543 ), + .Q(\blk00000003/blk0000027c/sig00000a73 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a9 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000544 ), + .Q(\blk00000003/blk0000027c/sig00000a72 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a8 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000542 ), + .Q(\blk00000003/blk0000027c/sig00000a74 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a7 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000546 ), + .Q(\blk00000003/blk0000027c/sig00000a70 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a6 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000547 ), + .Q(\blk00000003/blk0000027c/sig00000a6f ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a5 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000545 ), + .Q(\blk00000003/blk0000027c/sig00000a71 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a4 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000549 ), + .Q(\blk00000003/blk0000027c/sig00000a6d ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a3 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054a ), + .Q(\blk00000003/blk0000027c/sig00000a6c ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a2 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000548 ), + .Q(\blk00000003/blk0000027c/sig00000a6e ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a1 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054c ), + .Q(\blk00000003/blk0000027c/sig00000a6a ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a0 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054d ), + .Q(\blk00000003/blk0000027c/sig00000a69 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029f ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054b ), + .Q(\blk00000003/blk0000027c/sig00000a6b ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029e ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054f ), + .Q(\blk00000003/blk0000027c/sig00000a67 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029d ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000550 ), + .Q(\blk00000003/blk0000027c/sig00000a66 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029c ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054e ), + .Q(\blk00000003/blk0000027c/sig00000a68 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029b ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000552 ), + .Q(\blk00000003/blk0000027c/sig00000a64 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029a ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000553 ), + .Q(\blk00000003/blk0000027c/sig00000a63 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk00000299 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000551 ), + .Q(\blk00000003/blk0000027c/sig00000a65 ), + .Q15(\NLW_blk00000003/blk0000027c/blk00000299_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk00000298 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000555 ), + .Q(\blk00000003/blk0000027c/sig00000a61 ), + .Q15(\NLW_blk00000003/blk0000027c/blk00000298_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk00000297 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000556 ), + .Q(\blk00000003/blk0000027c/sig00000a60 ), + .Q15(\NLW_blk00000003/blk0000027c/blk00000297_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk00000296 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000554 ), + .Q(\blk00000003/blk0000027c/sig00000a62 ), + .Q15(\NLW_blk00000003/blk0000027c/blk00000296_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000295 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a77 ), + .Q(\blk00000003/sig000004c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000294 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a76 ), + .Q(\blk00000003/sig000004c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000293 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a75 ), + .Q(\blk00000003/sig000004c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000292 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a74 ), + .Q(\blk00000003/sig000004c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000291 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a73 ), + .Q(\blk00000003/sig000004c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000290 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a72 ), + .Q(\blk00000003/sig000004c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a71 ), + .Q(\blk00000003/sig000004c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a70 ), + .Q(\blk00000003/sig000004ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6f ), + .Q(\blk00000003/sig000004cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6e ), + .Q(\blk00000003/sig000004cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6d ), + .Q(\blk00000003/sig000004cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6c ), + .Q(\blk00000003/sig000004ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000289 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6b ), + .Q(\blk00000003/sig000004cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000288 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6a ), + .Q(\blk00000003/sig000004d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000287 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a69 ), + .Q(\blk00000003/sig000004d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000286 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a68 ), + .Q(\blk00000003/sig000004d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000285 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a67 ), + .Q(\blk00000003/sig000004d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000284 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a66 ), + .Q(\blk00000003/sig000004d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000283 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a65 ), + .Q(\blk00000003/sig000004d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000282 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a64 ), + .Q(\blk00000003/sig000004d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000281 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a63 ), + .Q(\blk00000003/sig000004d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000280 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a62 ), + .Q(\blk00000003/sig000004d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000027f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a61 ), + .Q(\blk00000003/sig000004d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000027e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a60 ), + .Q(\blk00000003/sig000004da ) + ); + GND \blk00000003/blk0000027c/blk0000027d ( + .G(\blk00000003/blk0000027c/sig00000a5f ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002af/blk000002e1 ( + .I0(ce), + .I1(\blk00000003/sig000004f6 ), + .O(\blk00000003/blk000002af/sig00000ac7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002e0 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000558 ), + .Q(\blk00000003/blk000002af/sig00000ac5 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002df ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000559 ), + .Q(\blk00000003/blk000002af/sig00000ac4 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002de ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000557 ), + .Q(\blk00000003/blk000002af/sig00000ac6 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002dd ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055b ), + .Q(\blk00000003/blk000002af/sig00000ac2 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002dc ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055c ), + .Q(\blk00000003/blk000002af/sig00000ac1 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002db ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055a ), + .Q(\blk00000003/blk000002af/sig00000ac3 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002da ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055e ), + .Q(\blk00000003/blk000002af/sig00000abf ), + .Q15(\NLW_blk00000003/blk000002af/blk000002da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d9 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055f ), + .Q(\blk00000003/blk000002af/sig00000abe ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d8 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055d ), + .Q(\blk00000003/blk000002af/sig00000ac0 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d7 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000561 ), + .Q(\blk00000003/blk000002af/sig00000abc ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d6 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000562 ), + .Q(\blk00000003/blk000002af/sig00000abb ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d5 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000560 ), + .Q(\blk00000003/blk000002af/sig00000abd ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d4 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000564 ), + .Q(\blk00000003/blk000002af/sig00000ab9 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d3 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000565 ), + .Q(\blk00000003/blk000002af/sig00000ab8 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d2 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000563 ), + .Q(\blk00000003/blk000002af/sig00000aba ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d1 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000567 ), + .Q(\blk00000003/blk000002af/sig00000ab6 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d0 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000568 ), + .Q(\blk00000003/blk000002af/sig00000ab5 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002cf ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000566 ), + .Q(\blk00000003/blk000002af/sig00000ab7 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002ce ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056a ), + .Q(\blk00000003/blk000002af/sig00000ab3 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002cd ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056b ), + .Q(\blk00000003/blk000002af/sig00000ab2 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002cc ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000569 ), + .Q(\blk00000003/blk000002af/sig00000ab4 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002cb ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056d ), + .Q(\blk00000003/blk000002af/sig00000ab0 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002ca ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056e ), + .Q(\blk00000003/blk000002af/sig00000aaf ), + .Q15(\NLW_blk00000003/blk000002af/blk000002ca_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002c9 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056c ), + .Q(\blk00000003/blk000002af/sig00000ab1 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002c9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac6 ), + .Q(\blk00000003/sig000002d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac5 ), + .Q(\blk00000003/sig000002d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac4 ), + .Q(\blk00000003/sig000002d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac3 ), + .Q(\blk00000003/sig000002da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac2 ), + .Q(\blk00000003/sig000002db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac1 ), + .Q(\blk00000003/sig000002dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac0 ), + .Q(\blk00000003/sig000002dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abf ), + .Q(\blk00000003/sig000002de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abe ), + .Q(\blk00000003/sig000002df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abd ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abc ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abb ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000aba ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab9 ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab8 ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab7 ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab6 ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab5 ), + .Q(\blk00000003/sig000002e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab4 ), + .Q(\blk00000003/sig000002e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab3 ), + .Q(\blk00000003/sig000002ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab2 ), + .Q(\blk00000003/sig000002eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab1 ), + .Q(\blk00000003/sig000002ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab0 ), + .Q(\blk00000003/sig000002ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000aaf ), + .Q(\blk00000003/sig000002ee ) + ); + GND \blk00000003/blk000002af/blk000002b0 ( + .G(\blk00000003/blk000002af/sig00000aae ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002e2/blk00000314 ( + .I0(ce), + .I1(\blk00000003/sig000004f5 ), + .O(\blk00000003/blk000002e2/sig00000b16 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000313 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000570 ), + .Q(\blk00000003/blk000002e2/sig00000b14 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000313_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000312 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000571 ), + .Q(\blk00000003/blk000002e2/sig00000b13 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000312_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000311 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000056f ), + .Q(\blk00000003/blk000002e2/sig00000b15 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000311_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000310 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000573 ), + .Q(\blk00000003/blk000002e2/sig00000b11 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000310_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000574 ), + .Q(\blk00000003/blk000002e2/sig00000b10 ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000572 ), + .Q(\blk00000003/blk000002e2/sig00000b12 ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000576 ), + .Q(\blk00000003/blk000002e2/sig00000b0e ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000577 ), + .Q(\blk00000003/blk000002e2/sig00000b0d ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000575 ), + .Q(\blk00000003/blk000002e2/sig00000b0f ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000579 ), + .Q(\blk00000003/blk000002e2/sig00000b0b ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000309 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057a ), + .Q(\blk00000003/blk000002e2/sig00000b0a ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000309_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000308 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000578 ), + .Q(\blk00000003/blk000002e2/sig00000b0c ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000308_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000307 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057c ), + .Q(\blk00000003/blk000002e2/sig00000b08 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000307_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000306 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057d ), + .Q(\blk00000003/blk000002e2/sig00000b07 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000306_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000305 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057b ), + .Q(\blk00000003/blk000002e2/sig00000b09 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000305_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000304 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057f ), + .Q(\blk00000003/blk000002e2/sig00000b05 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000304_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000303 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000580 ), + .Q(\blk00000003/blk000002e2/sig00000b04 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000303_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000302 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057e ), + .Q(\blk00000003/blk000002e2/sig00000b06 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000302_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000301 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000582 ), + .Q(\blk00000003/blk000002e2/sig00000b02 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000301_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000300 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000583 ), + .Q(\blk00000003/blk000002e2/sig00000b01 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000300_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk000002ff ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000581 ), + .Q(\blk00000003/blk000002e2/sig00000b03 ), + .Q15(\NLW_blk00000003/blk000002e2/blk000002ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk000002fe ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000585 ), + .Q(\blk00000003/blk000002e2/sig00000aff ), + .Q15(\NLW_blk00000003/blk000002e2/blk000002fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk000002fd ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000586 ), + .Q(\blk00000003/blk000002e2/sig00000afe ), + .Q15(\NLW_blk00000003/blk000002e2/blk000002fd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk000002fc ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000584 ), + .Q(\blk00000003/blk000002e2/sig00000b00 ), + .Q15(\NLW_blk00000003/blk000002e2/blk000002fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b15 ), + .Q(\blk00000003/sig000002ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b14 ), + .Q(\blk00000003/sig000002f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b13 ), + .Q(\blk00000003/sig000002f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b12 ), + .Q(\blk00000003/sig000002f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b11 ), + .Q(\blk00000003/sig000002f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b10 ), + .Q(\blk00000003/sig000002f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0f ), + .Q(\blk00000003/sig000002f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0e ), + .Q(\blk00000003/sig000002f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0d ), + .Q(\blk00000003/sig000002f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0c ), + .Q(\blk00000003/sig000002f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0b ), + .Q(\blk00000003/sig000002f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0a ), + .Q(\blk00000003/sig000002fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b09 ), + .Q(\blk00000003/sig000002fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b08 ), + .Q(\blk00000003/sig000002fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b07 ), + .Q(\blk00000003/sig000002fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b06 ), + .Q(\blk00000003/sig000002fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b05 ), + .Q(\blk00000003/sig000002ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b04 ), + .Q(\blk00000003/sig00000300 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b03 ), + .Q(\blk00000003/sig00000301 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b02 ), + .Q(\blk00000003/sig00000302 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b01 ), + .Q(\blk00000003/sig00000303 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b00 ), + .Q(\blk00000003/sig00000304 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000aff ), + .Q(\blk00000003/sig00000305 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000afe ), + .Q(\blk00000003/sig00000306 ) + ); + GND \blk00000003/blk000002e2/blk000002e3 ( + .G(\blk00000003/blk000002e2/sig00000afd ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000315/blk00000347 ( + .I0(ce), + .I1(\blk00000003/sig000004f6 ), + .O(\blk00000003/blk00000315/sig00000b65 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000346 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000588 ), + .Q(\blk00000003/blk00000315/sig00000b63 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000346_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000345 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000589 ), + .Q(\blk00000003/blk00000315/sig00000b62 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000345_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000344 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000587 ), + .Q(\blk00000003/blk00000315/sig00000b64 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000344_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000343 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058b ), + .Q(\blk00000003/blk00000315/sig00000b60 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000343_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000342 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058c ), + .Q(\blk00000003/blk00000315/sig00000b5f ), + .Q15(\NLW_blk00000003/blk00000315/blk00000342_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000341 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058a ), + .Q(\blk00000003/blk00000315/sig00000b61 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000341_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000340 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058e ), + .Q(\blk00000003/blk00000315/sig00000b5d ), + .Q15(\NLW_blk00000003/blk00000315/blk00000340_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033f ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058f ), + .Q(\blk00000003/blk00000315/sig00000b5c ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033e ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058d ), + .Q(\blk00000003/blk00000315/sig00000b5e ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033d ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000591 ), + .Q(\blk00000003/blk00000315/sig00000b5a ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033c ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000592 ), + .Q(\blk00000003/blk00000315/sig00000b59 ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033b ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000590 ), + .Q(\blk00000003/blk00000315/sig00000b5b ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033a ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000594 ), + .Q(\blk00000003/blk00000315/sig00000b57 ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000339 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000595 ), + .Q(\blk00000003/blk00000315/sig00000b56 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000339_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000338 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000593 ), + .Q(\blk00000003/blk00000315/sig00000b58 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000338_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000337 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000597 ), + .Q(\blk00000003/blk00000315/sig00000b54 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000337_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000336 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000598 ), + .Q(\blk00000003/blk00000315/sig00000b53 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000336_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000335 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000596 ), + .Q(\blk00000003/blk00000315/sig00000b55 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000335_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000334 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059a ), + .Q(\blk00000003/blk00000315/sig00000b51 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000334_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000333 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059b ), + .Q(\blk00000003/blk00000315/sig00000b50 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000333_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000332 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000599 ), + .Q(\blk00000003/blk00000315/sig00000b52 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000332_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000331 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059d ), + .Q(\blk00000003/blk00000315/sig00000b4e ), + .Q15(\NLW_blk00000003/blk00000315/blk00000331_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000330 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059e ), + .Q(\blk00000003/blk00000315/sig00000b4d ), + .Q15(\NLW_blk00000003/blk00000315/blk00000330_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000032f ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059c ), + .Q(\blk00000003/blk00000315/sig00000b4f ), + .Q15(\NLW_blk00000003/blk00000315/blk0000032f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b64 ), + .Q(\blk00000003/sig00000337 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b63 ), + .Q(\blk00000003/sig00000338 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b62 ), + .Q(\blk00000003/sig00000339 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b61 ), + .Q(\blk00000003/sig0000033a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b60 ), + .Q(\blk00000003/sig0000033b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000329 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5f ), + .Q(\blk00000003/sig0000033c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000328 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5e ), + .Q(\blk00000003/sig0000033d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000327 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5d ), + .Q(\blk00000003/sig0000033e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000326 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5c ), + .Q(\blk00000003/sig0000033f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000325 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5b ), + .Q(\blk00000003/sig00000340 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000324 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5a ), + .Q(\blk00000003/sig00000341 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000323 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b59 ), + .Q(\blk00000003/sig00000342 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000322 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b58 ), + .Q(\blk00000003/sig00000343 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000321 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b57 ), + .Q(\blk00000003/sig00000344 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000320 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b56 ), + .Q(\blk00000003/sig00000345 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b55 ), + .Q(\blk00000003/sig00000346 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b54 ), + .Q(\blk00000003/sig00000347 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b53 ), + .Q(\blk00000003/sig00000348 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b52 ), + .Q(\blk00000003/sig00000349 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b51 ), + .Q(\blk00000003/sig0000034a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b50 ), + .Q(\blk00000003/sig0000034b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000319 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b4f ), + .Q(\blk00000003/sig0000034c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000318 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b4e ), + .Q(\blk00000003/sig0000034d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000317 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b4d ), + .Q(\blk00000003/sig0000034e ) + ); + GND \blk00000003/blk00000315/blk00000316 ( + .G(\blk00000003/blk00000315/sig00000b4c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000348/blk0000037a ( + .I0(ce), + .I1(\blk00000003/sig000004f5 ), + .O(\blk00000003/blk00000348/sig00000bb4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000379 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a0 ), + .Q(\blk00000003/blk00000348/sig00000bb2 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000379_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000378 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a1 ), + .Q(\blk00000003/blk00000348/sig00000bb1 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000378_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000377 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig0000059f ), + .Q(\blk00000003/blk00000348/sig00000bb3 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000377_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000376 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a3 ), + .Q(\blk00000003/blk00000348/sig00000baf ), + .Q15(\NLW_blk00000003/blk00000348/blk00000376_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000375 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a4 ), + .Q(\blk00000003/blk00000348/sig00000bae ), + .Q15(\NLW_blk00000003/blk00000348/blk00000375_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000374 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a2 ), + .Q(\blk00000003/blk00000348/sig00000bb0 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000374_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000373 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a6 ), + .Q(\blk00000003/blk00000348/sig00000bac ), + .Q15(\NLW_blk00000003/blk00000348/blk00000373_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000372 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a7 ), + .Q(\blk00000003/blk00000348/sig00000bab ), + .Q15(\NLW_blk00000003/blk00000348/blk00000372_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000371 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a5 ), + .Q(\blk00000003/blk00000348/sig00000bad ), + .Q15(\NLW_blk00000003/blk00000348/blk00000371_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000370 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a9 ), + .Q(\blk00000003/blk00000348/sig00000ba9 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000370_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005aa ), + .Q(\blk00000003/blk00000348/sig00000ba8 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a8 ), + .Q(\blk00000003/blk00000348/sig00000baa ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005ac ), + .Q(\blk00000003/blk00000348/sig00000ba6 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005ad ), + .Q(\blk00000003/blk00000348/sig00000ba5 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005ab ), + .Q(\blk00000003/blk00000348/sig00000ba7 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005af ), + .Q(\blk00000003/blk00000348/sig00000ba3 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000369 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b0 ), + .Q(\blk00000003/blk00000348/sig00000ba2 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000369_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000368 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005ae ), + .Q(\blk00000003/blk00000348/sig00000ba4 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000368_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000367 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b2 ), + .Q(\blk00000003/blk00000348/sig00000ba0 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000367_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000366 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b3 ), + .Q(\blk00000003/blk00000348/sig00000b9f ), + .Q15(\NLW_blk00000003/blk00000348/blk00000366_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000365 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b1 ), + .Q(\blk00000003/blk00000348/sig00000ba1 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000365_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000364 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b5 ), + .Q(\blk00000003/blk00000348/sig00000b9d ), + .Q15(\NLW_blk00000003/blk00000348/blk00000364_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000363 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b6 ), + .Q(\blk00000003/blk00000348/sig00000b9c ), + .Q15(\NLW_blk00000003/blk00000348/blk00000363_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000362 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b4 ), + .Q(\blk00000003/blk00000348/sig00000b9e ), + .Q15(\NLW_blk00000003/blk00000348/blk00000362_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000361 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bb3 ), + .Q(\blk00000003/sig0000034f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000360 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bb2 ), + .Q(\blk00000003/sig00000350 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bb1 ), + .Q(\blk00000003/sig00000351 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bb0 ), + .Q(\blk00000003/sig00000352 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000baf ), + .Q(\blk00000003/sig00000353 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bae ), + .Q(\blk00000003/sig00000354 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bad ), + .Q(\blk00000003/sig00000355 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bac ), + .Q(\blk00000003/sig00000356 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000359 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bab ), + .Q(\blk00000003/sig00000357 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000358 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000baa ), + .Q(\blk00000003/sig00000358 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000357 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba9 ), + .Q(\blk00000003/sig00000359 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000356 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba8 ), + .Q(\blk00000003/sig0000035a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000355 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba7 ), + .Q(\blk00000003/sig0000035b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000354 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba6 ), + .Q(\blk00000003/sig0000035c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000353 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba5 ), + .Q(\blk00000003/sig0000035d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000352 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba4 ), + .Q(\blk00000003/sig0000035e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000351 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba3 ), + .Q(\blk00000003/sig0000035f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000350 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba2 ), + .Q(\blk00000003/sig00000360 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba1 ), + .Q(\blk00000003/sig00000361 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba0 ), + .Q(\blk00000003/sig00000362 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000b9f ), + .Q(\blk00000003/sig00000363 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000b9e ), + .Q(\blk00000003/sig00000364 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000b9d ), + .Q(\blk00000003/sig00000365 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000b9c ), + .Q(\blk00000003/sig00000366 ) + ); + GND \blk00000003/blk00000348/blk00000349 ( + .G(\blk00000003/blk00000348/sig00000b9b ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000037b/blk000003b3 ( + .I0(ce), + .I1(\blk00000003/sig00000232 ), + .O(\blk00000003/blk0000037b/sig00000c19 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003b2 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005b7 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c06 ), + .DPO(\blk00000003/blk0000037b/sig00000c18 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003b1 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005b8 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c05 ), + .DPO(\blk00000003/blk0000037b/sig00000c17 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003b0 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005b9 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c04 ), + .DPO(\blk00000003/blk0000037b/sig00000c16 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003af ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005ba ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c03 ), + .DPO(\blk00000003/blk0000037b/sig00000c15 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003ae ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005bb ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c02 ), + .DPO(\blk00000003/blk0000037b/sig00000c14 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003ad ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005bc ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c01 ), + .DPO(\blk00000003/blk0000037b/sig00000c13 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003ac ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005be ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bff ), + .DPO(\blk00000003/blk0000037b/sig00000c11 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000D )) + \blk00000003/blk0000037b/blk000003ab ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005bf ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfe ), + .DPO(\blk00000003/blk0000037b/sig00000c10 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003aa ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005bd ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c00 ), + .DPO(\blk00000003/blk0000037b/sig00000c12 ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk0000037b/blk000003a9 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c0 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfd ), + .DPO(\blk00000003/blk0000037b/sig00000c0f ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000037b/blk000003a8 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c1 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfc ), + .DPO(\blk00000003/blk0000037b/sig00000c0e ) + ); + RAM32X1D #( + .INIT ( 32'h0000000F )) + \blk00000003/blk0000037b/blk000003a7 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c2 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfb ), + .DPO(\blk00000003/blk0000037b/sig00000c0d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000037b/blk000003a6 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c3 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfa ), + .DPO(\blk00000003/blk0000037b/sig00000c0c ) + ); + RAM32X1D #( + .INIT ( 32'h00000008 )) + \blk00000003/blk0000037b/blk000003a5 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c4 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf9 ), + .DPO(\blk00000003/blk0000037b/sig00000c0b ) + ); + RAM32X1D #( + .INIT ( 32'h00000004 )) + \blk00000003/blk0000037b/blk000003a4 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c5 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf8 ), + .DPO(\blk00000003/blk0000037b/sig00000c0a ) + ); + RAM32X1D #( + .INIT ( 32'h0000000B )) + \blk00000003/blk0000037b/blk000003a3 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c7 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf6 ), + .DPO(\blk00000003/blk0000037b/sig00000c08 ) + ); + RAM32X1D #( + .INIT ( 32'h00000008 )) + \blk00000003/blk0000037b/blk000003a2 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c8 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf5 ), + .DPO(\blk00000003/blk0000037b/sig00000c07 ) + ); + RAM32X1D #( + .INIT ( 32'h00000008 )) + \blk00000003/blk0000037b/blk000003a1 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c6 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf7 ), + .DPO(\blk00000003/blk0000037b/sig00000c09 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk000003a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c18 ), + .Q(\blk00000003/sig000002c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c17 ), + .Q(\blk00000003/sig000002c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c16 ), + .Q(\blk00000003/sig000002c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c15 ), + .Q(\blk00000003/sig000002c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c14 ), + .Q(\blk00000003/sig000002c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c13 ), + .Q(\blk00000003/sig000002ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c12 ), + .Q(\blk00000003/sig000002cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000399 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c11 ), + .Q(\blk00000003/sig000002cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000398 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c10 ), + .Q(\blk00000003/sig000002cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000397 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0f ), + .Q(\blk00000003/sig000002ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000396 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0e ), + .Q(\blk00000003/sig000002cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000395 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0d ), + .Q(\blk00000003/sig000002d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000394 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0c ), + .Q(\blk00000003/sig000002d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000393 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0b ), + .Q(\blk00000003/sig000002d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000392 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0a ), + .Q(\blk00000003/sig000002d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000391 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c09 ), + .Q(\blk00000003/sig000002d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000390 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c08 ), + .Q(\blk00000003/sig000002d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c07 ), + .Q(\blk00000003/sig000002d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c06 ), + .Q(\blk00000003/sig000005c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c05 ), + .Q(\blk00000003/sig000005ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c04 ), + .Q(\blk00000003/sig000005cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c03 ), + .Q(\blk00000003/sig000005cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c02 ), + .Q(\blk00000003/sig000005cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000389 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c01 ), + .Q(\blk00000003/sig000005ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000388 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c00 ), + .Q(\blk00000003/sig000005cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000387 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bff ), + .Q(\blk00000003/sig000005d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000386 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfe ), + .Q(\blk00000003/sig000005d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000385 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfd ), + .Q(\blk00000003/sig000005d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000384 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfc ), + .Q(\blk00000003/sig000005d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000383 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfb ), + .Q(\blk00000003/sig000005d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000382 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfa ), + .Q(\blk00000003/sig000005d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000381 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf9 ), + .Q(\blk00000003/sig000005d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000380 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf8 ), + .Q(\blk00000003/sig000005d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000037f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf7 ), + .Q(\blk00000003/sig000005d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000037e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf6 ), + .Q(\blk00000003/sig000005d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000037d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf5 ), + .Q(\blk00000003/sig000005da ) + ); + GND \blk00000003/blk0000037b/blk0000037c ( + .G(\blk00000003/blk0000037b/sig00000bf4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003b4/blk000003ec ( + .I0(ce), + .I1(\blk00000003/sig000004e1 ), + .O(\blk00000003/blk000003b4/sig00000c7e ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003eb ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005c9 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c6b ), + .DPO(\blk00000003/blk000003b4/sig00000c7d ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003ea ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005ca ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c6a ), + .DPO(\blk00000003/blk000003b4/sig00000c7c ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003e9 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005cb ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c69 ), + .DPO(\blk00000003/blk000003b4/sig00000c7b ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003e8 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005cc ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c68 ), + .DPO(\blk00000003/blk000003b4/sig00000c7a ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003e7 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005cd ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c67 ), + .DPO(\blk00000003/blk000003b4/sig00000c79 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000D )) + \blk00000003/blk000003b4/blk000003e6 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005ce ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c66 ), + .DPO(\blk00000003/blk000003b4/sig00000c78 ) + ); + RAM32X1D #( + .INIT ( 32'h00000008 )) + \blk00000003/blk000003b4/blk000003e5 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d0 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c64 ), + .DPO(\blk00000003/blk000003b4/sig00000c76 ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk000003b4/blk000003e4 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d1 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c63 ), + .DPO(\blk00000003/blk000003b4/sig00000c75 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000003b4/blk000003e3 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005cf ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c65 ), + .DPO(\blk00000003/blk000003b4/sig00000c77 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000A )) + \blk00000003/blk000003b4/blk000003e2 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d2 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c62 ), + .DPO(\blk00000003/blk000003b4/sig00000c74 ) + ); + RAM32X1D #( + .INIT ( 32'h00000006 )) + \blk00000003/blk000003b4/blk000003e1 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d3 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c61 ), + .DPO(\blk00000003/blk000003b4/sig00000c73 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000C )) + \blk00000003/blk000003b4/blk000003e0 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d4 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c60 ), + .DPO(\blk00000003/blk000003b4/sig00000c72 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000A )) + \blk00000003/blk000003b4/blk000003df ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d5 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5f ), + .DPO(\blk00000003/blk000003b4/sig00000c71 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000003b4/blk000003de ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d6 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5e ), + .DPO(\blk00000003/blk000003b4/sig00000c70 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000003b4/blk000003dd ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d7 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5d ), + .DPO(\blk00000003/blk000003b4/sig00000c6f ) + ); + RAM32X1D #( + .INIT ( 32'h0000000B )) + \blk00000003/blk000003b4/blk000003dc ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d9 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5b ), + .DPO(\blk00000003/blk000003b4/sig00000c6d ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000003b4/blk000003db ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005da ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5a ), + .DPO(\blk00000003/blk000003b4/sig00000c6c ) + ); + RAM32X1D #( + .INIT ( 32'h0000000F )) + \blk00000003/blk000003b4/blk000003da ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d8 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5c ), + .DPO(\blk00000003/blk000003b4/sig00000c6e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c7d ), + .Q(\blk00000003/sig00000469 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c7c ), + .Q(\blk00000003/sig0000046a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c7b ), + .Q(\blk00000003/sig0000046b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c7a ), + .Q(\blk00000003/sig0000046c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c79 ), + .Q(\blk00000003/sig0000046d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c78 ), + .Q(\blk00000003/sig0000046e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c77 ), + .Q(\blk00000003/sig0000046f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c76 ), + .Q(\blk00000003/sig00000470 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c75 ), + .Q(\blk00000003/sig00000471 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c74 ), + .Q(\blk00000003/sig00000472 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c73 ), + .Q(\blk00000003/sig00000473 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c72 ), + .Q(\blk00000003/sig00000474 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c71 ), + .Q(\blk00000003/sig00000475 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c70 ), + .Q(\blk00000003/sig00000476 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6f ), + .Q(\blk00000003/sig00000477 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6e ), + .Q(\blk00000003/sig00000478 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6d ), + .Q(\blk00000003/sig00000479 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6c ), + .Q(\blk00000003/sig0000047a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6b ), + .Q(\blk00000003/sig000005db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6a ), + .Q(\blk00000003/sig000005dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c69 ), + .Q(\blk00000003/sig000005dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c68 ), + .Q(\blk00000003/sig000005de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c67 ), + .Q(\blk00000003/sig000005df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c66 ), + .Q(\blk00000003/sig000005e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c65 ), + .Q(\blk00000003/sig000005e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c64 ), + .Q(\blk00000003/sig000005e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c63 ), + .Q(\blk00000003/sig000005e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c62 ), + .Q(\blk00000003/sig000005e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c61 ), + .Q(\blk00000003/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c60 ), + .Q(\blk00000003/sig000005e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5f ), + .Q(\blk00000003/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5e ), + .Q(\blk00000003/sig000005e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5d ), + .Q(\blk00000003/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5c ), + .Q(\blk00000003/sig000005ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5b ), + .Q(\blk00000003/sig000005eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5a ), + .Q(\blk00000003/sig000005ec ) + ); + GND \blk00000003/blk000003b4/blk000003b5 ( + .G(\blk00000003/blk000003b4/sig00000c59 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000044d/blk00000473 ( + .I0(ce), + .I1(\blk00000003/sig000004e2 ), + .O(\blk00000003/blk0000044d/sig00000cbf ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000044d/blk00000472 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005db ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000472_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cbe ) + ); + RAM32X1D #( + .INIT ( 32'h0000000D )) + \blk00000003/blk0000044d/blk00000471 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005dc ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000471_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cbd ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000044d/blk00000470 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005dd ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000470_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cbc ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk0000044d/blk0000046f ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005de ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cbb ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000044d/blk0000046e ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005df ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cba ) + ); + RAM32X1D #( + .INIT ( 32'h00000007 )) + \blk00000003/blk0000044d/blk0000046d ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e0 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk0000044d/blk0000046c ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e2 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000044d/blk0000046b ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e3 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000007 )) + \blk00000003/blk0000044d/blk0000046a ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e1 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000044d/blk00000469 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e4 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000469_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000044d/blk00000468 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e5 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000468_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb4 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000C )) + \blk00000003/blk0000044d/blk00000467 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e6 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000467_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000044d/blk00000466 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e7 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000466_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000044d/blk00000465 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e8 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000465_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000007 )) + \blk00000003/blk0000044d/blk00000464 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e9 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000464_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000044d/blk00000463 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005eb ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000463_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cae ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk0000044d/blk00000462 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005ec ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000462_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cad ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000044d/blk00000461 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005ea ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000461_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000caf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000460 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cbe ), + .Q(\blk00000003/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cbd ), + .Q(\blk00000003/sig000003c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cbc ), + .Q(\blk00000003/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cbb ), + .Q(\blk00000003/sig000003ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cba ), + .Q(\blk00000003/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb9 ), + .Q(\blk00000003/sig000003cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb8 ), + .Q(\blk00000003/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000459 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb7 ), + .Q(\blk00000003/sig000003ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000458 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb6 ), + .Q(\blk00000003/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000457 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb5 ), + .Q(\blk00000003/sig000003d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000456 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb4 ), + .Q(\blk00000003/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000455 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb3 ), + .Q(\blk00000003/sig000003d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000454 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb2 ), + .Q(\blk00000003/sig000003d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000453 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb1 ), + .Q(\blk00000003/sig000003d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000452 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb0 ), + .Q(\blk00000003/sig000003d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000451 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000caf ), + .Q(\blk00000003/sig000003d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000450 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cae ), + .Q(\blk00000003/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000044f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cad ), + .Q(\blk00000003/sig000003d8 ) + ); + GND \blk00000003/blk0000044d/blk0000044e ( + .G(\blk00000003/blk0000044d/sig00000cac ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004a4/blk000004ca ( + .I0(ce), + .I1(\blk00000003/sig00000230 ), + .O(\blk00000003/blk000004a4/sig00000cfc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000004a4/blk000004c9 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005b7 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cfb ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c8 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005b8 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cfa ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c7 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005b9 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c6 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005ba ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c5 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005bb ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c4 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005bc ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c4_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c3 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005be ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c3_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c2 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005bf ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c2_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c1 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005bd ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c1_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c0 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c0 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c0_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004bf ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c1 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004bf_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004be ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c2 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004be_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004bd ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c3 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004bd_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cef ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004bc ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c4 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004bc_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cee ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004bb ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c5 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004bb_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000ced ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004ba ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c7 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004ba_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000ceb ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004b9 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c8 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004b9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cea ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004b8 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c6 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004b8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cfb ), + .Q(\blk00000003/sig000000f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cfa ), + .Q(\blk00000003/sig000000f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf9 ), + .Q(\blk00000003/sig000000f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf8 ), + .Q(\blk00000003/sig000000f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf7 ), + .Q(\blk00000003/sig000000f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf6 ), + .Q(\blk00000003/sig000000f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf5 ), + .Q(\blk00000003/sig000000f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf4 ), + .Q(\blk00000003/sig000000fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf3 ), + .Q(\blk00000003/sig000000fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf2 ), + .Q(\blk00000003/sig000000fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf1 ), + .Q(\blk00000003/sig000000fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf0 ), + .Q(\blk00000003/sig000000fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cef ), + .Q(\blk00000003/sig000000ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cee ), + .Q(\blk00000003/sig00000100 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000ced ), + .Q(\blk00000003/sig00000101 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cec ), + .Q(\blk00000003/sig00000102 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000ceb ), + .Q(\blk00000003/sig00000103 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cea ), + .Q(\blk00000003/sig00000104 ) + ); + GND \blk00000003/blk000004a4/blk000004a5 ( + .G(\blk00000003/blk000004a4/sig00000ce9 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.ngc b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.ngc new file mode 100644 index 000000000..5eaff1030 --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$0dg2~753-Xnzd}foo8#5+421).97 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155289;j6`;3081<>=h9::i6=4+4209566a3g>8=7<6;:m275g=83.???4>31d8j1562;k07b?<0083>!24:3;85$511>457n2d??<4=c:9l57ce290/8><5122e?k24938o76a>2d294?"3;;0:?=h4n512>7c<3f;9hk4?:%606?748o1e8>?52g98k454i3:1(9==:0174>h3;80;76a>32;94?"3;;0:?9>4n512>4=5$511>45382d??<4=;:m2761=83.???4>3528j1562:10c<=<6;29 155289?<6`;3087?>i6;:?1<7*;3382716=50;&777<6;=:0b9=>:698k45493:1(9==:0174>h3;80376a>32294?"3;;0:?9>4n512><=5$511>45382d??<4n;:m277c=83.???4>3528j1562k10c<==d;29 155289?<6`;308`?>i6;;i1<7*;3382716:g98k45513:1(9==:0174>h3;80:<65`120;>5<#<:81=>:?;o605?7632e:??850;&777<6;=:0b9=>:008?j74:<0;6):<2;3005=i<:;1=>54o0110?6=,=996<=;0:l774<6<21d=><<:18'064=9:>;7c:<1;36?>i6;;81<7*;33827168>7?<419m067=9>10c<==0;29 155289?<6`;3082<>=h9:;m6=4+420956273g>8=7?6;:m274c=83.???4>3528j15628k07b?<1e83>!24:3;88=5a42395g=5$511>45382d??<4>c:9l567f290/8><51263?k2493;o76a>30;94?"3;;0:?9>4n512>4c<3f;8=54?:%606?74<91e8>?51g98k456?3:1(9==:0174>h3;809<65`1235>5<#<:81=>:?;o605?4632e:?<;50;&777<6;=:0b9=>:308?j749=0;6):<2;3005=i<:;1>>54o0127?6=,=996<=;0:l774<5<21d=>?=:18'064=9:>;7c:<1;06?>i6;:l1<7*;33827168>7?<419m067=:>10c<==h9:9h6=4+420956273g>8=7<6;:m276d=83.???4>3528j1562;k07b?<3383>!24:3;88=5a42396g=5$511>45382d??<4=c:9l567d290/8><51263?k24938o76a>30394?"3;;0:?9>4n512>7c<3f;8==4?:%606?74<91e8>?52g98k451j3:1(9==:0145>h3;80;76a>37c94?"3;;0:?:?4n512>4=5$511>45092d??<4=;:m273>=83.???4>3638j1562:10c<=97;29 155289<=6`;3087?>i6;?<1<7*;3382727;0b9=>:698k451:3:1(9==:0145>h3;80376a>37394?"3;;0:?:?4n512><=5$511>45092d??<4n;:m270`=83.???4>3638j1562k10c<=:e;29 155289<=6`;308`?>i6;;0b9=>:g98k452i3:1(9==:0145>h3;80:<65`127:>5<#<:81=>9>;o605?7632e:?8950;&777<6;>;0b9=>:008?j74=?0;6):<2;3034=i<:;1=>54o0161?6=,=996<=81:l774<6<21d=>;;:18'064=9:=:7c:<1;36?>i6;<91<7*;33827278>7?<709m067=9>10c<=:1;29 155289<=6`;3082<>=h9:?;6=4+420956163g>8=7?6;:m271`=83.???4>3638j15628k07b?<4d83>!24:3;8;<5a42395g=5$511>45092d??<4>c:9l562e290/8><51252?k2493;o76a>35c94?"3;;0:?:?4n512>4c<3f;8844?:%606?74?81e8>?51g98k45303:1(9==:0145>h3;809<65`1264>5<#<:81=>9>;o605?4632e:?9850;&777<6;>;0b9=>:308?j74<<0;6):<2;3034=i<:;1>>54o0170?6=,=996<=81:l774<5<21d=>:<:18'064=9:=:7c:<1;06?>i6;>:1<7*;33827278>7?<709m067=:>10c<=9e;29 155289<=6`;3081<>=h9:8=7<6;:m273e=83.???4>3638j1562;k07b?<6283>!24:3;8;<5a42396g=47>5$511>45092d??<4=c:9l562c290/8><51252?k24938o76a>35094?"3;;0:?:?4n512>7c<3f;88<4?:%606?74?81e8>?52g98md`02900c<=6c;29 155289j>6`;3083?>i6;0h1<7*;33827d4:298k45>03:1(9==:01b6>h3;80?76a>38594?"3;;0:?l<4n512>0=5$511>45f:2d??<49;:m27<3=83.???4>3`08j1562>10c<=63;29 155289j>6`;308;?>i6;081<7*;33827d450;&777<6;h80b9=>:c98k45?n3:1(9==:01b6>h3;80h76a>39g94?"3;;0:?l<4n512>a=5$511>45f:2d??<4j;:m27=e=83.???4>3`08j1562o10c<=7b;29 155289j>6`;30824>=h9:2j6=4+420956g53g>8=7?>;:m27=>=83.???4>3`08j15628807b?<8683>!24:3;8m?5a423956=5$511>45f:2d??<4>4:9l56>2290/8><512c1?k2493;>76a>39694?"3;;0:?l<4n512>40<3f;84>4?:%606?74i;1e8>?51698k45?:3:1(9==:01b6>h3;80:465`12:2>5<#<:81=>o=;o605?7>32e:?5>50;&777<6;h80b9=>:0c8?j74?o0;6):<2;30e7=i<:;1=o54o014`?6=,=996<=n2:l774<6k21d=>9l:18'064=9:k97c:<1;3g?>i6;>h1<7*;33827d48>7?6`;30814>=h9:=36=4+420956g53g>8=7<>;:m2721=83.???4>3`08j1562;807b?<7783>!24:3;8m?5a423966=5$511>45f:2d??<4=4:9l5613290/8><512c1?k24938>76a>3`394?"3;;0:?l<4n512>70<3f;8m=4?:%606?74i;1e8>?52698k45>n3:1(9==:01b6>h3;809465`12;f>5<#<:81=>o=;o605?4>32e:?4j50;&777<6;h80b9=>:3c8?j741=0;6):<2;30e7=i<:;1>o54o01;=?6=,=996<=n2:l774<5k21d=>9j:18'064=9:k97c:<1;0g?>i6;>91<7*;33827d48>7?i6;ji1<7*;33827a5:298k45d13:1(9==:01g7>h3;80?76a>3b:94?"3;;0:?i=4n512>0=5$511>45c;2d??<49;:m27f0=83.???4>3e18j1562>10c<=l4;29 155289o?6`;308;?>i6;j91<7*;33827a5:c98k45d83:1(9==:01g7>h3;80h76a>3cd94?"3;;0:?i=4n512>a=5$511>45c;2d??<4j;:m27gb=83.???4>3e18j1562o10c<=mc;29 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h<5>4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<594?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<584?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5;4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5:4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<554?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<544?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5l4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5o4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5n4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5i4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5h4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5k4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3tho7;t3181f?562;o1>k4ri02:>5<#<:81==64n512>5=5<#<:81>=l4n512>4=5<#<:81>=l4n512>6=5<#<:81>=l4n512>0=6=4+420965d5<#<:81>=l4n512>2=5<#<:81>=l4n512><=5<#<:81>=l4n512>g=5<#<:81>=l4n512>a=6=4+420965d5<#<:81>=l4n512>c=4;h037?6=,=996?>m;o605?7632c:==4?:%606?77n2d??<4?;:k71<<722c:5h4?::k701<722c:mk4?::m17`<72->8>7<;:m17g<72->8>7<8>7<8>7<8>7<8>7<4?:%606?44l2d??<4m;:m127<72->8>7<8>7<8>7<>;50;&777<5;m1e8>?51098k717290/8><527d8j1562910c?8j:18'064=:?l0b9=>:098k70c290/8><527d8j1562;10c?8l:18'064=:?l0b9=>:298k70e290/8><527d8j1562=10c?8n:18'064=:?l0b9=>:498k70>290/8><527d8j1562?10c?87:18'064=:?l0b9=>:698k7??290/8><527d8j1562110c?78:18'064=:?l0b9=>:898k7?1290/8><527d8j1562h10c?7::18'064=:?l0b9=>:c98k7?3290/8><527d8j1562j10c?7<:18'064=:?l0b9=>:e98k7>>290/8><527d8j1562l10c?9j:18'064=:?l0b9=>:g98k714290/8><527d8j15628:07b<97;29 1552;d0lo0;6<4?:1y'01b=:k=0D9;l;I664>i5j?0;66sm7d294?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l;1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7d094?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l91<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7d694?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l?1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7d494?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l=1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7d:94?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l31<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7dc94?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?lh1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7da94?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?ln1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7dg94?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?ll1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7g294?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?o;1<7:50;2x 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\ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.v b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.v new file mode 100644 index 000000000..cd6e39d9f --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.v @@ -0,0 +1,20014 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: P.49d +// \ \ Application: netgen +// / / Filename: hbdec3.v +// /___/ /\ Timestamp: Wed Dec 4 13:32:32 2013 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/hbdec3.ngc ./tmp/_cg/hbdec3.v +// Device : 7k325tffg900-2 +// Input file : ./tmp/_cg/hbdec3.ngc +// Output file : ./tmp/_cg/hbdec3.v +// # of Modules : 1 +// Design Name : hbdec3 +// Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module hbdec3 ( + sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk, coef_ld, dout_1, dout_2, din_1, din_2, coef_din +)/* synthesis syn_black_box syn_noprune=1 */; + input sclr; + input ce; + output rfd; + output rdy; + output data_valid; + input coef_we; + input nd; + input clk; + input coef_ld; + output [47 : 0] dout_1; + output [47 : 0] dout_2; + input [23 : 0] din_1; + input [23 : 0] din_2; + input [17 : 0] coef_din; + + // synthesis translate_off + + wire NlwRenamedSig_OI_rfd; + wire \blk00000003/sig00000664 ; + wire \blk00000003/sig00000663 ; + wire \blk00000003/sig00000662 ; + wire \blk00000003/sig00000661 ; + wire \blk00000003/sig00000660 ; + wire \blk00000003/sig0000065f ; + wire \blk00000003/sig0000065e ; + wire \blk00000003/sig0000065d ; + wire \blk00000003/sig0000065c ; + wire \blk00000003/sig0000065b ; + wire \blk00000003/sig0000065a ; + wire \blk00000003/sig00000659 ; + wire \blk00000003/sig00000658 ; + wire \blk00000003/sig00000657 ; + wire \blk00000003/sig00000656 ; + wire \blk00000003/sig00000655 ; + wire \blk00000003/sig00000654 ; + wire \blk00000003/sig00000653 ; + wire \blk00000003/sig00000652 ; + wire \blk00000003/sig00000651 ; + wire \blk00000003/sig00000650 ; + wire \blk00000003/sig0000064f ; + wire \blk00000003/sig0000064e ; + wire \blk00000003/sig0000064d ; + wire \blk00000003/sig0000064c ; + wire \blk00000003/sig0000064b ; + wire \blk00000003/sig0000064a ; + wire \blk00000003/sig00000649 ; + wire \blk00000003/sig00000648 ; + wire \blk00000003/sig00000647 ; + wire \blk00000003/sig00000646 ; + wire \blk00000003/sig00000645 ; + wire \blk00000003/sig00000644 ; + wire \blk00000003/sig00000643 ; + wire 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\blk00000003/blk000002b1/sig000009c7 ; + wire \blk00000003/blk000002b1/sig000009c6 ; + wire \blk00000003/blk000002b1/sig000009c5 ; + wire \blk00000003/blk000002b1/sig000009c4 ; + wire \blk00000003/blk000002b1/sig000009c3 ; + wire \blk00000003/blk000002b1/sig000009c2 ; + wire \blk00000003/blk000002b1/sig000009c1 ; + wire \blk00000003/blk000002b1/sig000009c0 ; + wire \blk00000003/blk000002b1/sig000009bf ; + wire \blk00000003/blk000002ea/sig00000a27 ; + wire \blk00000003/blk000002ea/sig00000a26 ; + wire \blk00000003/blk000002ea/sig00000a25 ; + wire \blk00000003/blk000002ea/sig00000a24 ; + wire \blk00000003/blk000002ea/sig00000a23 ; + wire \blk00000003/blk000002ea/sig00000a22 ; + wire \blk00000003/blk000002ea/sig00000a21 ; + wire \blk00000003/blk000002ea/sig00000a20 ; + wire \blk00000003/blk000002ea/sig00000a1f ; + wire \blk00000003/blk000002ea/sig00000a1e ; + wire \blk00000003/blk000002ea/sig00000a1d ; + wire \blk00000003/blk000002ea/sig00000a1c ; + wire \blk00000003/blk000002ea/sig00000a1b ; + wire \blk00000003/blk000002ea/sig00000a1a ; + wire \blk00000003/blk000002ea/sig00000a19 ; + wire \blk00000003/blk000002ea/sig00000a18 ; + wire \blk00000003/blk000002ea/sig00000a17 ; + wire \blk00000003/blk000002ea/sig00000a16 ; + wire \blk00000003/blk000002ea/sig00000a15 ; + wire \blk00000003/blk000002ea/sig00000a14 ; + wire \blk00000003/blk00000371/sig00000a64 ; + wire \blk00000003/blk00000371/sig00000a63 ; + wire \blk00000003/blk00000371/sig00000a62 ; + wire \blk00000003/blk00000371/sig00000a61 ; + wire \blk00000003/blk00000371/sig00000a60 ; + wire \blk00000003/blk00000371/sig00000a5f ; + wire \blk00000003/blk00000371/sig00000a5e ; + wire \blk00000003/blk00000371/sig00000a5d ; + wire \blk00000003/blk00000371/sig00000a5c ; + wire \blk00000003/blk00000371/sig00000a5b ; + wire \blk00000003/blk00000371/sig00000a5a ; + wire \blk00000003/blk00000371/sig00000a59 ; + wire \blk00000003/blk00000371/sig00000a58 ; + wire \blk00000003/blk00000371/sig00000a57 ; + wire \blk00000003/blk00000371/sig00000a56 ; + wire \blk00000003/blk00000371/sig00000a55 ; + wire \blk00000003/blk00000371/sig00000a54 ; + wire \blk00000003/blk00000371/sig00000a53 ; + wire \blk00000003/blk00000371/sig00000a52 ; + wire \blk00000003/blk00000371/sig00000a51 ; + wire NLW_blk00000001_P_UNCONNECTED; + wire NLW_blk00000002_G_UNCONNECTED; + wire \NLW_blk00000003/blk0000065a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000658_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000656_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000654_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000652_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000650_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000648_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000646_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000644_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000642_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000640_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000638_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000636_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000634_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000632_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000630_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000626_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000624_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000622_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000620_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000061e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000061c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000061a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000618_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000616_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000614_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000612_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000610_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000060e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000060c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000060a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000608_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000606_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000604_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000600_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005fa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ee_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ec_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005be_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000059e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000059c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000059a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000598_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000596_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000594_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000592_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000590_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000058e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000058c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000058a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000588_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000586_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000584_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000580_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000057e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000057c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000057a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000578_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000576_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000574_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000572_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000570_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000056e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000056c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000056a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000568_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000566_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000564_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000562_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000560_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000055e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000055c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000055a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000558_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000556_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000554_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000552_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000550_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000548_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000546_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000544_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000542_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000540_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000538_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000536_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000534_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000532_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000530_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000052e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000052c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000052a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000528_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000526_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000524_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000522_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000520_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000518_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000516_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000514_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000512_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000510_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000050e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000050c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000050a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000508_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000506_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000504_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000409_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000409_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000039d_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000039d_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dd_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cf_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ce_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ca_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c9_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bd_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a0_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009e_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000096_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000095_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000094_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000093_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000092_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000090_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000008f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000019_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000d_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000a_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000009_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000066_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000065_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000064_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000063_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000062_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000061_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000060_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000005f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000005e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000005d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000005c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000014a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000149_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000148_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000147_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000146_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000145_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000144_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000143_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000142_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000141_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000140_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000139_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000138_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000137_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000136_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000135_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000134_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000133_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000017d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000017c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000017b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000017a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000179_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000178_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000177_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000176_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000175_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000171_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000170_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000169_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000168_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000167_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000166_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk00000199_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000216_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000215_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000214_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000213_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000212_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000211_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000210_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000209_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000208_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000207_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000206_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000205_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000204_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000203_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000202_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000201_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000200_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk000001ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000249_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000248_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000247_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000243_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000242_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000241_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000240_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000239_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000238_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000237_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000236_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000235_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000234_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000233_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000232_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000027c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000027b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000027a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000279_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000278_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000277_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000276_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000275_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000274_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000273_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000272_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000271_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000270_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000269_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000268_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000267_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000266_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000265_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk00000299_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk00000298_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000309_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000308_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000307_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000306_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000305_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000304_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000303_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000302_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000301_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000300_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk000002ff_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk000002fe_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000396_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000395_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000394_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000393_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000392_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000391_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000390_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000389_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000388_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000387_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000386_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000385_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [47 : 0] NlwRenamedSig_OI_dout_1; + wire [47 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[47] = NlwRenamedSig_OI_dout_1[47], + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[47] = NlwRenamedSig_OI_dout_2[47], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000664 ), + .Q(\blk00000003/sig00000579 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000065a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000434 ), + .Q(\blk00000003/sig00000664 ), + .Q15(\NLW_blk00000003/blk0000065a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000659 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000663 ), + .Q(\blk00000003/sig00000502 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000658 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000042e ), + .Q(\blk00000003/sig00000663 ), + .Q15(\NLW_blk00000003/blk00000658_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000657 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000662 ), + .Q(\blk00000003/sig000001c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000656 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000630 ), + .Q(\blk00000003/sig00000662 ), + .Q15(\NLW_blk00000003/blk00000656_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000655 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000661 ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000654 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000062e ), + .Q(\blk00000003/sig00000661 ), + .Q15(\NLW_blk00000003/blk00000654_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000653 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000660 ), + .Q(\blk00000003/sig000001c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000652 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000062c ), + .Q(\blk00000003/sig00000660 ), + .Q15(\NLW_blk00000003/blk00000652_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000651 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065f ), + .Q(\blk00000003/sig000001c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000650 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000062a ), + .Q(\blk00000003/sig0000065f ), + .Q15(\NLW_blk00000003/blk00000650_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065e ), + .Q(\blk00000003/sig000001be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000628 ), + .Q(\blk00000003/sig0000065e ), + .Q15(\NLW_blk00000003/blk0000064e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065d ), + .Q(\blk00000003/sig000001bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000626 ), + .Q(\blk00000003/sig0000065d ), + .Q15(\NLW_blk00000003/blk0000064c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065c ), + .Q(\blk00000003/sig000001bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000624 ), + .Q(\blk00000003/sig0000065c ), + .Q15(\NLW_blk00000003/blk0000064a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000649 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065b ), + .Q(\blk00000003/sig000001bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000648 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000061e ), + .Q(\blk00000003/sig0000065b ), + .Q15(\NLW_blk00000003/blk00000648_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000647 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065a ), + .Q(\blk00000003/sig000001bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000646 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000622 ), + .Q(\blk00000003/sig0000065a ), + .Q15(\NLW_blk00000003/blk00000646_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000645 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000659 ), + .Q(\blk00000003/sig000001b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000644 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000618 ), + .Q(\blk00000003/sig00000659 ), + .Q15(\NLW_blk00000003/blk00000644_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000643 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000658 ), + .Q(\blk00000003/sig000001b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000642 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000061c ), + .Q(\blk00000003/sig00000658 ), + .Q15(\NLW_blk00000003/blk00000642_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000641 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000657 ), + .Q(\blk00000003/sig000001ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000640 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000620 ), + .Q(\blk00000003/sig00000657 ), + .Q15(\NLW_blk00000003/blk00000640_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000656 ), + .Q(\blk00000003/sig000001b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000616 ), + .Q(\blk00000003/sig00000656 ), + .Q15(\NLW_blk00000003/blk0000063e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000655 ), + .Q(\blk00000003/sig000001b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000614 ), + .Q(\blk00000003/sig00000655 ), + .Q15(\NLW_blk00000003/blk0000063c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000654 ), + .Q(\blk00000003/sig000001b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000061a ), + .Q(\blk00000003/sig00000654 ), + .Q15(\NLW_blk00000003/blk0000063a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000639 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000653 ), + .Q(\blk00000003/sig000001b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000638 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000612 ), + .Q(\blk00000003/sig00000653 ), + .Q15(\NLW_blk00000003/blk00000638_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000637 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000652 ), + .Q(\blk00000003/sig000001b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000636 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000610 ), + .Q(\blk00000003/sig00000652 ), + .Q15(\NLW_blk00000003/blk00000636_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000635 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000651 ), + .Q(\blk00000003/sig000001b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000634 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000060e ), + .Q(\blk00000003/sig00000651 ), + .Q15(\NLW_blk00000003/blk00000634_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000633 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000650 ), + .Q(\blk00000003/sig000001b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000632 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000608 ), + .Q(\blk00000003/sig00000650 ), + .Q15(\NLW_blk00000003/blk00000632_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064f ), + .Q(\blk00000003/sig000001b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000630 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000060c ), + .Q(\blk00000003/sig0000064f ), + .Q15(\NLW_blk00000003/blk00000630_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064e ), + .Q(\blk00000003/sig000001ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000602 ), + .Q(\blk00000003/sig0000064e ), + .Q15(\NLW_blk00000003/blk0000062e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064d ), + .Q(\blk00000003/sig000001ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000606 ), + .Q(\blk00000003/sig0000064d ), + .Q15(\NLW_blk00000003/blk0000062c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064c ), + .Q(\blk00000003/sig000001af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000060a ), + .Q(\blk00000003/sig0000064c ), + .Q15(\NLW_blk00000003/blk0000062a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000629 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064b ), + .Q(\blk00000003/sig0000014b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000600 ), + .Q(\blk00000003/sig0000064b ), + .Q15(\NLW_blk00000003/blk00000628_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000627 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064a ), + .Q(\blk00000003/sig0000014a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000626 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005fe ), + .Q(\blk00000003/sig0000064a ), + .Q15(\NLW_blk00000003/blk00000626_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000625 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000649 ), + .Q(\blk00000003/sig000001ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000624 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000604 ), + .Q(\blk00000003/sig00000649 ), + .Q15(\NLW_blk00000003/blk00000624_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000623 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000648 ), + .Q(\blk00000003/sig00000148 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000622 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005fc ), + .Q(\blk00000003/sig00000648 ), + .Q15(\NLW_blk00000003/blk00000622_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000647 ), + .Q(\blk00000003/sig00000147 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000620 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005fa ), + .Q(\blk00000003/sig00000647 ), + .Q15(\NLW_blk00000003/blk00000620_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000646 ), + .Q(\blk00000003/sig00000149 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000061e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f8 ), + .Q(\blk00000003/sig00000646 ), + .Q15(\NLW_blk00000003/blk0000061e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000645 ), + .Q(\blk00000003/sig00000146 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000061c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f2 ), + .Q(\blk00000003/sig00000645 ), + .Q15(\NLW_blk00000003/blk0000061c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000644 ), + .Q(\blk00000003/sig00000145 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000061a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f6 ), + .Q(\blk00000003/sig00000644 ), + .Q15(\NLW_blk00000003/blk0000061a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000619 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000643 ), + .Q(\blk00000003/sig00000143 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000618 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005ec ), + .Q(\blk00000003/sig00000643 ), + .Q15(\NLW_blk00000003/blk00000618_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000617 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000642 ), + .Q(\blk00000003/sig00000142 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000616 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f0 ), + .Q(\blk00000003/sig00000642 ), + .Q15(\NLW_blk00000003/blk00000616_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000641 ), + .Q(\blk00000003/sig00000144 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000614 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f4 ), + .Q(\blk00000003/sig00000641 ), + .Q15(\NLW_blk00000003/blk00000614_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000613 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000640 ), + .Q(\blk00000003/sig00000140 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000612 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005ea ), + .Q(\blk00000003/sig00000640 ), + .Q15(\NLW_blk00000003/blk00000612_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000611 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063f ), + .Q(\blk00000003/sig0000013f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000610 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e8 ), + .Q(\blk00000003/sig0000063f ), + .Q15(\NLW_blk00000003/blk00000610_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063e ), + .Q(\blk00000003/sig00000141 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000060e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005ee ), + .Q(\blk00000003/sig0000063e ), + .Q15(\NLW_blk00000003/blk0000060e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063d ), + .Q(\blk00000003/sig0000013d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000060c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e6 ), + .Q(\blk00000003/sig0000063d ), + .Q15(\NLW_blk00000003/blk0000060c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063c ), + .Q(\blk00000003/sig0000013c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000060a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e4 ), + .Q(\blk00000003/sig0000063c ), + .Q15(\NLW_blk00000003/blk0000060a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000609 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063b ), + .Q(\blk00000003/sig0000013e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000608 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e2 ), + .Q(\blk00000003/sig0000063b ), + .Q15(\NLW_blk00000003/blk00000608_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000607 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063a ), + .Q(\blk00000003/sig0000013b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000606 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e0 ), + .Q(\blk00000003/sig0000063a ), + .Q15(\NLW_blk00000003/blk00000606_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000605 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000639 ), + .Q(\blk00000003/sig0000013a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000604 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005de ), + .Q(\blk00000003/sig00000639 ), + .Q15(\NLW_blk00000003/blk00000604_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000603 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000638 ), + .Q(\blk00000003/sig00000138 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005dc ), + .Q(\blk00000003/sig00000638 ), + .Q15(\NLW_blk00000003/blk00000602_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000601 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000637 ), + .Q(\blk00000003/sig00000137 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000600 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005da ), + .Q(\blk00000003/sig00000637 ), + .Q15(\NLW_blk00000003/blk00000600_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000636 ), + .Q(\blk00000003/sig00000139 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005fe ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005d8 ), + .Q(\blk00000003/sig00000636 ), + .Q15(\NLW_blk00000003/blk000005fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000635 ), + .Q(\blk00000003/sig00000136 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005fc ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005d6 ), + .Q(\blk00000003/sig00000635 ), + .Q15(\NLW_blk00000003/blk000005fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000634 ), + .Q(\blk00000003/sig00000135 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005fa ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005d4 ), + .Q(\blk00000003/sig00000634 ), + .Q15(\NLW_blk00000003/blk000005fa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000633 ), + .Q(\blk00000003/sig00000134 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f8 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005d0 ), + .Q(\blk00000003/sig00000633 ), + .Q15(\NLW_blk00000003/blk000005f8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000632 ), + .Q(\blk00000003/sig00000434 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e1 ), + .Q(\blk00000003/sig00000632 ), + .Q15(\NLW_blk00000003/blk000005f6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000631 ), + .Q(\blk00000003/sig0000057a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ae ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001c4 ), + .Q(\blk00000003/sig00000631 ), + .Q15(\NLW_blk00000003/blk000005f4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000062f ), + .Q(\blk00000003/sig00000630 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000219 ), + .Q(\blk00000003/sig0000062f ), + .Q15(\NLW_blk00000003/blk000005f2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000062d ), + .Q(\blk00000003/sig0000062e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000218 ), + .Q(\blk00000003/sig0000062d ), + .Q15(\NLW_blk00000003/blk000005f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000062b ), + .Q(\blk00000003/sig0000062c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ee ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig0000062b ), + .Q15(\NLW_blk00000003/blk000005ee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ed ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000629 ), + .Q(\blk00000003/sig0000062a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ec ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig00000629 ), + .Q15(\NLW_blk00000003/blk000005ec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005eb ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000627 ), + .Q(\blk00000003/sig00000628 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ea ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig00000627 ), + .Q15(\NLW_blk00000003/blk000005ea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000625 ), + .Q(\blk00000003/sig00000626 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig00000625 ), + .Q15(\NLW_blk00000003/blk000005e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000623 ), + .Q(\blk00000003/sig00000624 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig00000623 ), + .Q15(\NLW_blk00000003/blk000005e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000621 ), + .Q(\blk00000003/sig00000622 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000621 ), + .Q15(\NLW_blk00000003/blk000005e4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000061f ), + .Q(\blk00000003/sig00000620 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig0000061f ), + .Q15(\NLW_blk00000003/blk000005e2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000061d ), + .Q(\blk00000003/sig0000061e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig0000061d ), + .Q15(\NLW_blk00000003/blk000005e0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005df ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000061b ), + .Q(\blk00000003/sig0000061c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005de ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig0000061b ), + .Q15(\NLW_blk00000003/blk000005de_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dd ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000619 ), + .Q(\blk00000003/sig0000061a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig00000619 ), + .Q15(\NLW_blk00000003/blk000005dc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005db ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000617 ), + .Q(\blk00000003/sig00000618 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005da ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig00000617 ), + .Q15(\NLW_blk00000003/blk000005da_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000615 ), + .Q(\blk00000003/sig00000616 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig00000615 ), + .Q15(\NLW_blk00000003/blk000005d8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000613 ), + .Q(\blk00000003/sig00000614 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig00000613 ), + .Q15(\NLW_blk00000003/blk000005d6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000611 ), + .Q(\blk00000003/sig00000612 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig00000611 ), + .Q15(\NLW_blk00000003/blk000005d4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000060f ), + .Q(\blk00000003/sig00000610 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig0000060f ), + .Q15(\NLW_blk00000003/blk000005d2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000060d ), + .Q(\blk00000003/sig0000060e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig0000060d ), + .Q15(\NLW_blk00000003/blk000005d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005cf ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000060b ), + .Q(\blk00000003/sig0000060c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ce ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig0000060b ), + .Q15(\NLW_blk00000003/blk000005ce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005cd ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000609 ), + .Q(\blk00000003/sig0000060a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005cc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig00000609 ), + .Q15(\NLW_blk00000003/blk000005cc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005cb ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000607 ), + .Q(\blk00000003/sig00000608 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ca ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig00000607 ), + .Q15(\NLW_blk00000003/blk000005ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000605 ), + .Q(\blk00000003/sig00000606 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig00000605 ), + .Q15(\NLW_blk00000003/blk000005c8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000603 ), + .Q(\blk00000003/sig00000604 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig00000603 ), + .Q15(\NLW_blk00000003/blk000005c6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000601 ), + .Q(\blk00000003/sig00000602 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig00000601 ), + .Q15(\NLW_blk00000003/blk000005c4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005ff ), + .Q(\blk00000003/sig00000600 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000005ff ), + .Q15(\NLW_blk00000003/blk000005c2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005fd ), + .Q(\blk00000003/sig000005fe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000005fd ), + .Q15(\NLW_blk00000003/blk000005c0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005bf ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005fb ), + .Q(\blk00000003/sig000005fc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005be ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000005fb ), + .Q15(\NLW_blk00000003/blk000005be_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005bd ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f9 ), + .Q(\blk00000003/sig000005fa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005bc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000005f9 ), + .Q15(\NLW_blk00000003/blk000005bc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005bb ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f7 ), + .Q(\blk00000003/sig000005f8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ba ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000005f7 ), + .Q15(\NLW_blk00000003/blk000005ba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f5 ), + .Q(\blk00000003/sig000005f6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000005f5 ), + .Q15(\NLW_blk00000003/blk000005b8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f3 ), + .Q(\blk00000003/sig000005f4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000005f3 ), + .Q15(\NLW_blk00000003/blk000005b6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f1 ), + .Q(\blk00000003/sig000005f2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000005f1 ), + .Q15(\NLW_blk00000003/blk000005b4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005ef ), + .Q(\blk00000003/sig000005f0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000005ef ), + .Q15(\NLW_blk00000003/blk000005b2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005ed ), + .Q(\blk00000003/sig000005ee ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000005ed ), + .Q15(\NLW_blk00000003/blk000005b0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005af ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005eb ), + .Q(\blk00000003/sig000005ec ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ae ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000005eb ), + .Q15(\NLW_blk00000003/blk000005ae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ad ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e9 ), + .Q(\blk00000003/sig000005ea ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ac ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000005e9 ), + .Q15(\NLW_blk00000003/blk000005ac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ab ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e7 ), + .Q(\blk00000003/sig000005e8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005aa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000005e7 ), + .Q15(\NLW_blk00000003/blk000005aa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e5 ), + .Q(\blk00000003/sig000005e6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000005e5 ), + .Q15(\NLW_blk00000003/blk000005a8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e3 ), + .Q(\blk00000003/sig000005e4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000005e3 ), + .Q15(\NLW_blk00000003/blk000005a6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e1 ), + .Q(\blk00000003/sig000005e2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000005e1 ), + .Q15(\NLW_blk00000003/blk000005a4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005df ), + .Q(\blk00000003/sig000005e0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000005df ), + .Q15(\NLW_blk00000003/blk000005a2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005dd ), + .Q(\blk00000003/sig000005de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000005dd ), + .Q15(\NLW_blk00000003/blk000005a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000059f ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005db ), + .Q(\blk00000003/sig000005dc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000059e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000005db ), + .Q15(\NLW_blk00000003/blk0000059e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000059d ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005d9 ), + .Q(\blk00000003/sig000005da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000059c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000005d9 ), + .Q15(\NLW_blk00000003/blk0000059c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000059b ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005d7 ), + .Q(\blk00000003/sig000005d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000059a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000005d7 ), + .Q15(\NLW_blk00000003/blk0000059a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000599 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005d5 ), + .Q(\blk00000003/sig000005d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000598 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000005d5 ), + .Q15(\NLW_blk00000003/blk00000598_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000597 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005d3 ), + .Q(\blk00000003/sig000005d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000596 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000005d3 ), + .Q15(\NLW_blk00000003/blk00000596_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000595 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005d2 ), + .Q(\blk00000003/sig00000581 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000594 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000435 ), + .Q(\blk00000003/sig000005d2 ), + .Q15(\NLW_blk00000003/blk00000594_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000593 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005d1 ), + .Q(\blk00000003/sig00000480 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000592 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000219 ), + .Q(\blk00000003/sig000005d1 ), + .Q15(\NLW_blk00000003/blk00000592_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000591 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005cf ), + .Q(\blk00000003/sig000005d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000590 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig000005cf ), + .Q15(\NLW_blk00000003/blk00000590_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000058f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ce ), + .Q(\blk00000003/sig0000047e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000058e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig000005ce ), + .Q15(\NLW_blk00000003/blk0000058e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000058d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005cd ), + .Q(\blk00000003/sig0000047d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000058c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig000005cd ), + .Q15(\NLW_blk00000003/blk0000058c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000058b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005cc ), + .Q(\blk00000003/sig0000047f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000058a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000218 ), + .Q(\blk00000003/sig000005cc ), + .Q15(\NLW_blk00000003/blk0000058a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000589 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005cb ), + .Q(\blk00000003/sig0000047b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000588 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig000005cb ), + .Q15(\NLW_blk00000003/blk00000588_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000587 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ca ), + .Q(\blk00000003/sig0000047a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000586 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig000005ca ), + .Q15(\NLW_blk00000003/blk00000586_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000585 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c9 ), + .Q(\blk00000003/sig0000047c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000584 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig000005c9 ), + .Q15(\NLW_blk00000003/blk00000584_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000583 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c8 ), + .Q(\blk00000003/sig00000479 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig000005c8 ), + .Q15(\NLW_blk00000003/blk00000582_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000581 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c7 ), + .Q(\blk00000003/sig00000478 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000580 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig000005c7 ), + .Q15(\NLW_blk00000003/blk00000580_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000057f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c6 ), + .Q(\blk00000003/sig00000476 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000057e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig000005c6 ), + .Q15(\NLW_blk00000003/blk0000057e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000057d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c5 ), + .Q(\blk00000003/sig00000475 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000057c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig000005c5 ), + .Q15(\NLW_blk00000003/blk0000057c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000057b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c4 ), + .Q(\blk00000003/sig00000477 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000057a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig000005c4 ), + .Q15(\NLW_blk00000003/blk0000057a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000579 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c3 ), + .Q(\blk00000003/sig00000473 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000578 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig000005c3 ), + .Q15(\NLW_blk00000003/blk00000578_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000577 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c2 ), + .Q(\blk00000003/sig00000472 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000576 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig000005c2 ), + .Q15(\NLW_blk00000003/blk00000576_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000575 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c1 ), + .Q(\blk00000003/sig00000474 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000574 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig000005c1 ), + .Q15(\NLW_blk00000003/blk00000574_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000573 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c0 ), + .Q(\blk00000003/sig00000470 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000572 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig000005c0 ), + .Q15(\NLW_blk00000003/blk00000572_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000571 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005bf ), + .Q(\blk00000003/sig0000046f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000570 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig000005bf ), + .Q15(\NLW_blk00000003/blk00000570_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005be ), + .Q(\blk00000003/sig00000471 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000056e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig000005be ), + .Q15(\NLW_blk00000003/blk0000056e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005bd ), + .Q(\blk00000003/sig0000046e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000056c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig000005bd ), + .Q15(\NLW_blk00000003/blk0000056c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005bc ), + .Q(\blk00000003/sig0000046d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000056a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig000005bc ), + .Q15(\NLW_blk00000003/blk0000056a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005bb ), + .Q(\blk00000003/sig0000046b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000568 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig000005bb ), + .Q15(\NLW_blk00000003/blk00000568_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000567 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ba ), + .Q(\blk00000003/sig0000046a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000566 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig000005ba ), + .Q15(\NLW_blk00000003/blk00000566_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000565 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b9 ), + .Q(\blk00000003/sig0000046c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000564 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig000005b9 ), + .Q15(\NLW_blk00000003/blk00000564_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000563 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b8 ), + .Q(\blk00000003/sig000004b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000562 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000005b8 ), + .Q15(\NLW_blk00000003/blk00000562_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000561 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b7 ), + .Q(\blk00000003/sig000004af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000560 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000005b7 ), + .Q15(\NLW_blk00000003/blk00000560_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b6 ), + .Q(\blk00000003/sig00000469 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000055e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig000005b6 ), + .Q15(\NLW_blk00000003/blk0000055e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b5 ), + .Q(\blk00000003/sig000004ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000055c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000005b5 ), + .Q15(\NLW_blk00000003/blk0000055c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b4 ), + .Q(\blk00000003/sig000004ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000055a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000005b4 ), + .Q15(\NLW_blk00000003/blk0000055a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000559 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b3 ), + .Q(\blk00000003/sig000004ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000558 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000005b3 ), + .Q15(\NLW_blk00000003/blk00000558_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000557 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b2 ), + .Q(\blk00000003/sig000004ab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000556 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000005b2 ), + .Q15(\NLW_blk00000003/blk00000556_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000555 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b1 ), + .Q(\blk00000003/sig000004aa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000554 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000005b1 ), + .Q15(\NLW_blk00000003/blk00000554_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000553 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b0 ), + .Q(\blk00000003/sig000004a8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000552 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000005b0 ), + .Q15(\NLW_blk00000003/blk00000552_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000551 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005af ), + .Q(\blk00000003/sig000004a7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000550 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000005af ), + .Q15(\NLW_blk00000003/blk00000550_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ae ), + .Q(\blk00000003/sig000004a9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000005ae ), + .Q15(\NLW_blk00000003/blk0000054e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ad ), + .Q(\blk00000003/sig000004a6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000005ad ), + .Q15(\NLW_blk00000003/blk0000054c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ac ), + .Q(\blk00000003/sig000004a5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000005ac ), + .Q15(\NLW_blk00000003/blk0000054a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000549 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ab ), + .Q(\blk00000003/sig000004a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000548 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000005ab ), + .Q15(\NLW_blk00000003/blk00000548_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000547 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005aa ), + .Q(\blk00000003/sig000004a2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000546 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000005aa ), + .Q15(\NLW_blk00000003/blk00000546_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000545 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a9 ), + .Q(\blk00000003/sig000004a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000544 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000005a9 ), + .Q15(\NLW_blk00000003/blk00000544_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000543 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a8 ), + .Q(\blk00000003/sig000004a1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000542 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000005a8 ), + .Q15(\NLW_blk00000003/blk00000542_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000541 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a7 ), + .Q(\blk00000003/sig000004a0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000540 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000005a7 ), + .Q15(\NLW_blk00000003/blk00000540_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a6 ), + .Q(\blk00000003/sig0000049e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000053e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000005a6 ), + .Q15(\NLW_blk00000003/blk0000053e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a5 ), + .Q(\blk00000003/sig0000049d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000053c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000005a5 ), + .Q15(\NLW_blk00000003/blk0000053c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a4 ), + .Q(\blk00000003/sig0000049f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000053a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000005a4 ), + .Q15(\NLW_blk00000003/blk0000053a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000539 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a3 ), + .Q(\blk00000003/sig0000049b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000538 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000005a3 ), + .Q15(\NLW_blk00000003/blk00000538_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000537 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a2 ), + .Q(\blk00000003/sig0000049a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000536 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000005a2 ), + .Q15(\NLW_blk00000003/blk00000536_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000535 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a1 ), + .Q(\blk00000003/sig0000049c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000534 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000005a1 ), + .Q15(\NLW_blk00000003/blk00000534_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a0 ), + .Q(\blk00000003/sig000002de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000532 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d6 ), + .Q(\blk00000003/sig000005a0 ), + .Q15(\NLW_blk00000003/blk00000532_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000531 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059f ), + .Q(\blk00000003/sig000002df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b9 ), + .Q(\blk00000003/sig0000059f ), + .Q15(\NLW_blk00000003/blk00000530_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059e ), + .Q(\blk00000003/sig00000499 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000052e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig0000059e ), + .Q15(\NLW_blk00000003/blk0000052e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059d ), + .Q(\blk00000003/sig00000580 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000052c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d2 ), + .Q(\blk00000003/sig0000059d ), + .Q15(\NLW_blk00000003/blk0000052c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059c ), + .Q(\blk00000003/sig000004da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000052a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig0000059c ), + .Q15(\NLW_blk00000003/blk0000052a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000529 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059b ), + .Q(\blk00000003/sig000004d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000528 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig0000059b ), + .Q15(\NLW_blk00000003/blk00000528_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000527 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059a ), + .Q(\blk00000003/sig000004d7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000526 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig0000059a ), + .Q15(\NLW_blk00000003/blk00000526_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000525 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000599 ), + .Q(\blk00000003/sig000004d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000524 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig00000599 ), + .Q15(\NLW_blk00000003/blk00000524_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000523 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000598 ), + .Q(\blk00000003/sig000004d5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000522 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig00000598 ), + .Q15(\NLW_blk00000003/blk00000522_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000521 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000597 ), + .Q(\blk00000003/sig000004d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000520 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig00000597 ), + .Q15(\NLW_blk00000003/blk00000520_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000596 ), + .Q(\blk00000003/sig000004d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig00000596 ), + .Q15(\NLW_blk00000003/blk0000051e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000595 ), + .Q(\blk00000003/sig000004d2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig00000595 ), + .Q15(\NLW_blk00000003/blk0000051c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000594 ), + .Q(\blk00000003/sig000004d1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig00000594 ), + .Q15(\NLW_blk00000003/blk0000051a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000519 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000593 ), + .Q(\blk00000003/sig000004d3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000518 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig00000593 ), + .Q15(\NLW_blk00000003/blk00000518_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000517 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000592 ), + .Q(\blk00000003/sig000004d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000516 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig00000592 ), + .Q15(\NLW_blk00000003/blk00000516_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000515 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000591 ), + .Q(\blk00000003/sig000004cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000514 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig00000591 ), + .Q15(\NLW_blk00000003/blk00000514_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000513 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000590 ), + .Q(\blk00000003/sig000004cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000512 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig00000590 ), + .Q15(\NLW_blk00000003/blk00000512_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000511 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058f ), + .Q(\blk00000003/sig000004cc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000510 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig0000058f ), + .Q15(\NLW_blk00000003/blk00000510_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058e ), + .Q(\blk00000003/sig000004ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000050e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig0000058e ), + .Q15(\NLW_blk00000003/blk0000050e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058d ), + .Q(\blk00000003/sig000004ca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000050c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig0000058d ), + .Q15(\NLW_blk00000003/blk0000050c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058c ), + .Q(\blk00000003/sig000004c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000050a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig0000058c ), + .Q15(\NLW_blk00000003/blk0000050a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000509 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058b ), + .Q(\blk00000003/sig000004cb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig0000058b ), + .Q15(\NLW_blk00000003/blk00000508_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000507 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058a ), + .Q(\blk00000003/sig000001e1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000506 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e3 ), + .Q(\blk00000003/sig0000058a ), + .Q15(\NLW_blk00000003/blk00000506_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000505 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000589 ), + .Q(\blk00000003/sig0000042e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000504 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d8 ), + .Q(\blk00000003/sig00000589 ), + .Q15(\NLW_blk00000003/blk00000504_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk00000503 ( + .I(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000288 ) + ); + INV \blk00000003/blk00000502 ( + .I(\blk00000003/sig00000291 ), + .O(\blk00000003/sig00000281 ) + ); + INV \blk00000003/blk00000501 ( + .I(\blk00000003/sig000001cf ), + .O(\blk00000003/sig00000296 ) + ); + INV \blk00000003/blk00000500 ( + .I(\blk00000003/sig00000298 ), + .O(\blk00000003/sig00000287 ) + ); + INV \blk00000003/blk000004ff ( + .I(\blk00000003/sig000004fd ), + .O(\blk00000003/sig00000578 ) + ); + INV \blk00000003/blk000004fe ( + .I(\blk00000003/sig00000244 ), + .O(\blk00000003/sig00000299 ) + ); + INV \blk00000003/blk000004fd ( + .I(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000282 ) + ); + INV \blk00000003/blk000004fc ( + .I(\blk00000003/sig0000021d ), + .O(\blk00000003/sig00000245 ) + ); + INV \blk00000003/blk000004fb ( + .I(\blk00000003/sig00000267 ), + .O(\blk00000003/sig00000227 ) + ); + INV \blk00000003/blk000004fa ( + .I(\blk00000003/sig000001cd ), + .O(\blk00000003/sig000000b9 ) + ); + INV \blk00000003/blk000004f9 ( + .I(\blk00000003/sig000000b6 ), + .O(\blk00000003/sig000000b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000502 ), + .Q(\blk00000003/sig0000057c ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk000004f7 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000236 ), + .I2(\blk00000003/sig0000024d ), + .O(\blk00000003/sig00000249 ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk000004f6 ( + .I0(\blk00000003/sig0000024a ), + .I1(\blk00000003/sig0000023e ), + .I2(\blk00000003/sig0000024d ), + .I3(coef_ld), + .I4(\blk00000003/sig00000236 ), + .O(\blk00000003/sig00000241 ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk000004f5 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000238 ), + .I2(coef_we), + .I3(\blk00000003/sig00000236 ), + .O(\blk00000003/sig00000248 ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk000004f4 ( + .I0(\blk00000003/sig00000236 ), + .I1(\blk00000003/sig00000238 ), + .I2(coef_we), + .I3(\blk00000003/sig0000024d ), + .I4(coef_ld), + .O(\blk00000003/sig00000247 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000004f3 ( + .I0(\blk00000003/sig00000291 ), + .I1(ce), + .I2(\blk00000003/sig0000023e ), + .I3(\blk00000003/sig0000021b ), + .O(\blk00000003/sig00000588 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000004f2 ( + .I0(\blk00000003/sig00000298 ), + .I1(ce), + .I2(\blk00000003/sig0000023c ), + .I3(\blk00000003/sig00000289 ), + .O(\blk00000003/sig00000587 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000004f1 ( + .I0(\blk00000003/sig0000057b ), + .I1(ce), + .I2(\blk00000003/sig000001d6 ), + .I3(\blk00000003/sig000001d8 ), + .O(\blk00000003/sig00000585 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk000004f0 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig0000057f ), + .O(\blk00000003/sig00000584 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk000004ef ( + .I0(ce), + .I1(\blk00000003/sig0000024d ), + .I2(\blk00000003/sig0000057d ), + .O(\blk00000003/sig00000583 ) + ); + LUT5 #( + .INIT ( 32'h6AAAAAAA )) + \blk00000003/blk000004ee ( + .I0(\blk00000003/sig0000057e ), + .I1(\blk00000003/sig000002a2 ), + .I2(ce), + .I3(nd), + .I4(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000586 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000004ed ( + .C(clk), + .D(\blk00000003/sig00000588 ), + .Q(\blk00000003/sig00000291 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000004ec ( + .C(clk), + .D(\blk00000003/sig00000587 ), + .Q(\blk00000003/sig00000298 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000004eb ( + .C(clk), + .D(\blk00000003/sig00000586 ), + .R(sclr), + .Q(\blk00000003/sig0000057e ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ea ( + .C(clk), + .D(\blk00000003/sig00000585 ), + .R(sclr), + .Q(\blk00000003/sig0000057b ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e9 ( + .I0(\blk00000003/sig00000500 ), + .O(\blk00000003/sig000004fb ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e8 ( + .I0(\blk00000003/sig000004ff ), + .O(\blk00000003/sig000004f8 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e7 ( + .I0(\blk00000003/sig000004fe ), + .O(\blk00000003/sig000004f5 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e6 ( + .I0(\blk00000003/sig000004fd ), + .O(\blk00000003/sig000004f2 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e5 ( + .I0(\blk00000003/sig000002da ), + .O(\blk00000003/sig000002db ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e4 ( + .I0(\blk00000003/sig000002d7 ), + .O(\blk00000003/sig000002d8 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e3 ( + .I0(\blk00000003/sig000002d3 ), + .O(\blk00000003/sig000002d4 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e2 ( + .I0(\blk00000003/sig000002b7 ), + .O(\blk00000003/sig000002b1 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e1 ( + .I0(\blk00000003/sig0000057e ), + .O(\blk00000003/sig000002a7 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e0 ( + .I0(\blk00000003/sig0000029f ), + .O(\blk00000003/sig0000029d ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004df ( + .I0(\blk00000003/sig00000271 ), + .O(\blk00000003/sig00000272 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004de ( + .I0(\blk00000003/sig0000026e ), + .O(\blk00000003/sig0000026f ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004dd ( + .I0(\blk00000003/sig0000026a ), + .O(\blk00000003/sig0000026b ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004dc ( + .I0(\blk00000003/sig00000260 ), + .O(\blk00000003/sig0000025d ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004db ( + .I0(\blk00000003/sig0000025f ), + .O(\blk00000003/sig0000025a ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004da ( + .I0(\blk00000003/sig00000255 ), + .O(\blk00000003/sig00000252 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004d9 ( + .I0(\blk00000003/sig00000254 ), + .O(\blk00000003/sig0000024f ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk000004d8 ( + .I0(\blk00000003/sig00000254 ), + .I1(\blk00000003/sig00000255 ), + .I2(\blk00000003/sig00000258 ), + .O(\blk00000003/sig0000022f ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004d7 ( + .I0(\blk00000003/sig00000267 ), + .O(\blk00000003/sig00000229 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004d6 ( + .I0(\blk00000003/sig000001cd ), + .O(\blk00000003/sig000000ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000572 ), + .R(sclr), + .Q(\blk00000003/sig00000577 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000056f ), + .R(sclr), + .Q(\blk00000003/sig00000576 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000056c ), + .R(sclr), + .Q(\blk00000003/sig00000575 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000569 ), + .R(sclr), + .Q(\blk00000003/sig00000574 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000566 ), + .R(sclr), + .Q(\blk00000003/sig00000573 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f0 ), + .S(sclr), + .Q(\blk00000003/sig00000501 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004fc ), + .S(sclr), + .Q(\blk00000003/sig00000500 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f9 ), + .R(sclr), + .Q(\blk00000003/sig000004ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f6 ), + .R(sclr), + .Q(\blk00000003/sig000004fe ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f3 ), + .S(sclr), + .Q(\blk00000003/sig000004fd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002dd ), + .R(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig000002da ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002dc ), + .R(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig000002d7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d6 ), + .R(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig000002d3 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c8 ), + .S(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002d1 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ce ), + .S(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002d0 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002cb ), + .S(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002cf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002bc ), + .R(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c2 ), + .R(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002c5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002bf ), + .R(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002c4 ) + ); + FDR \blk00000003/blk000004c2 ( + .C(clk), + .D(\blk00000003/sig00000584 ), + .R(ce), + .Q(\blk00000003/sig0000057f ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b2 ), + .S(sclr), + .Q(\blk00000003/sig000002b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b5 ), + .R(sclr), + .Q(\blk00000003/sig000002b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ac ), + .R(sclr), + .Q(\blk00000003/sig000001e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002af ), + .R(sclr), + .Q(\blk00000003/sig000001e8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029b ), + .R(sclr), + .Q(\blk00000003/sig000002a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029e ), + .R(sclr), + .Q(\blk00000003/sig0000029f ) + ); + FDR \blk00000003/blk000004bb ( + .C(clk), + .D(\blk00000003/sig00000583 ), + .R(ce), + .Q(\blk00000003/sig0000057d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000274 ), + .R(\blk00000003/sig00000277 ), + .Q(\blk00000003/sig00000271 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000273 ), + .R(\blk00000003/sig00000277 ), + .Q(\blk00000003/sig0000026e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026d ), + .R(\blk00000003/sig00000277 ), + .Q(\blk00000003/sig0000026a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000266 ), + .R(coef_ld), + .Q(\blk00000003/sig00000267 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000262 ), + .R(sclr), + .Q(\blk00000003/sig00000263 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025e ), + .R(sclr), + .Q(\blk00000003/sig00000260 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025b ), + .R(sclr), + .Q(\blk00000003/sig0000025f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000257 ), + .R(coef_ld), + .Q(\blk00000003/sig00000258 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000253 ), + .R(coef_ld), + .Q(\blk00000003/sig00000255 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000250 ), + .R(coef_ld), + .Q(\blk00000003/sig00000254 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000004b0 ( + .I0(\blk00000003/sig00000573 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig00000565 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000004af ( + .I0(\blk00000003/sig00000574 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig00000568 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000004ae ( + .I0(\blk00000003/sig00000575 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig0000056b ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000004ad ( + .I0(\blk00000003/sig00000576 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig0000056e ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk000004ac ( + .I0(\blk00000003/sig00000577 ), + .I1(\blk00000003/sig000004fd ), + .I2(\blk00000003/sig000001df ), + .O(\blk00000003/sig00000571 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk000004ab ( + .I0(\blk00000003/sig000001df ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig000004fd ), + .O(\blk00000003/sig00000563 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004aa ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000104 ), + .I3(NlwRenamedSig_OI_dout_2[47]), + .O(\blk00000003/sig00000562 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a9 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000105 ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig00000561 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a8 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000107 ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig0000055f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a7 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000106 ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig00000560 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a6 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000108 ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig0000055e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a5 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010a ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig0000055c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a4 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000109 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig0000055d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a3 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010b ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig0000055b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a2 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010d ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig00000559 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a1 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010c ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig0000055a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a0 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010e ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig00000558 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000110 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig00000556 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010f ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig00000557 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000111 ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig00000555 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000113 ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig00000553 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000112 ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig00000554 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000114 ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig00000552 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000499 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000116 ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig00000550 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000498 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000115 ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig00000551 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000497 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000117 ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig0000054f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000496 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000119 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig0000054d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000495 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000118 ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig0000054e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000494 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011a ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig0000054c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000493 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011c ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig0000054a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000492 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011b ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig0000054b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000491 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011d ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig00000549 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000490 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011f ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig00000547 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011e ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig00000548 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000120 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig00000546 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000122 ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig00000544 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000121 ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig00000545 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000123 ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig00000543 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000125 ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig00000541 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000489 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000124 ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig00000542 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000488 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000126 ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig00000540 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000487 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000128 ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig0000053e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000486 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000127 ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig0000053f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000485 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000129 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig0000053d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000484 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012b ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig0000053b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000483 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012a ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig0000053c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000482 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012c ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig0000053a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000481 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012e ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig00000538 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000480 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012d ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig00000539 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012f ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig00000537 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000131 ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig00000535 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000130 ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig00000536 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000132 ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig00000534 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000133 ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig00000533 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000017c ), + .I3(NlwRenamedSig_OI_dout_1[47]), + .O(\blk00000003/sig00000532 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000479 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000017e ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig00000530 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000478 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000017d ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig00000531 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000477 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000017f ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig0000052f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000476 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000181 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig0000052d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000475 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000180 ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig0000052e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000474 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000182 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig0000052c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000473 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000184 ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig0000052a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000472 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000183 ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig0000052b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000471 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000185 ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig00000529 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000470 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000187 ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig00000527 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000186 ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig00000528 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000188 ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig00000526 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018a ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig00000524 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000189 ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig00000525 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018b ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig00000523 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018d ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig00000521 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000469 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018c ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig00000522 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000468 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018e ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig00000520 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000467 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000190 ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig0000051e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000466 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018f ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig0000051f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000465 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000191 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig0000051d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000464 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000193 ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig0000051b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000463 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000192 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig0000051c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000462 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000194 ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig0000051a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000461 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000196 ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig00000518 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000460 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000195 ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig00000519 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000197 ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig00000517 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000199 ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig00000515 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000198 ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig00000516 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019a ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig00000514 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019c ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig00000512 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019b ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig00000513 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000459 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019d ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig00000511 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000458 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019f ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig0000050f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000457 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019e ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig00000510 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000456 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a0 ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig0000050e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000455 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a2 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig0000050c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000454 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a1 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig0000050d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000453 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a3 ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig0000050b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000452 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a5 ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig00000509 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000451 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a4 ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig0000050a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000450 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a6 ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig00000508 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a8 ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig00000506 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a7 ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig00000507 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a9 ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig00000505 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001ab ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig00000503 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001aa ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig00000504 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000044a ( + .I0(\blk00000003/sig00000501 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig000004ef ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000449 ( + .I0(ce), + .I1(\blk00000003/sig000001e1 ), + .O(\blk00000003/sig00000582 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000448 ( + .I0(ce), + .I1(\blk00000003/sig0000042f ), + .O(\blk00000003/sig000004ee ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000447 ( + .I0(ce), + .I1(\blk00000003/sig00000581 ), + .O(\blk00000003/sig000004ed ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000446 ( + .I0(\blk00000003/sig000002cf ), + .I1(\blk00000003/sig000002de ), + .O(\blk00000003/sig000002ca ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000445 ( + .I0(\blk00000003/sig000002de ), + .I1(\blk00000003/sig000002d1 ), + .O(\blk00000003/sig000002c7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000444 ( + .I0(\blk00000003/sig000002de ), + .I1(\blk00000003/sig000002d0 ), + .O(\blk00000003/sig000002cd ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000443 ( + .I0(\blk00000003/sig000002de ), + .I1(\blk00000003/sig00000580 ), + .O(\blk00000003/sig000002c3 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk00000442 ( + .I0(\blk00000003/sig000002c4 ), + .I1(\blk00000003/sig000002de ), + .I2(\blk00000003/sig00000580 ), + .O(\blk00000003/sig000002be ) + ); + LUT3 #( + .INIT ( 8'hF8 )) + \blk00000003/blk00000441 ( + .I0(\blk00000003/sig00000580 ), + .I1(\blk00000003/sig000002de ), + .I2(\blk00000003/sig000002c5 ), + .O(\blk00000003/sig000002c1 ) + ); + LUT3 #( + .INIT ( 8'hBC )) + \blk00000003/blk00000440 ( + .I0(\blk00000003/sig00000580 ), + .I1(\blk00000003/sig000002de ), + .I2(\blk00000003/sig000002c6 ), + .O(\blk00000003/sig000002bb ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000043f ( + .I0(sclr), + .I1(\blk00000003/sig0000057f ), + .O(\blk00000003/sig000002b8 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000043e ( + .I0(\blk00000003/sig000002b6 ), + .I1(\blk00000003/sig000001d8 ), + .O(\blk00000003/sig000002b4 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000043d ( + .I0(nd), + .I1(\blk00000003/sig000002a9 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002b0 ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk0000043c ( + .I0(\blk00000003/sig000001e8 ), + .I1(nd), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000002a9 ), + .O(\blk00000003/sig000002ae ) + ); + LUT4 #( + .INIT ( 16'hDFA0 )) + \blk00000003/blk0000043b ( + .I0(nd), + .I1(\blk00000003/sig000002a9 ), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000001e9 ), + .O(\blk00000003/sig000002ab ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000043a ( + .I0(nd), + .I1(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002a4 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk00000439 ( + .I0(\blk00000003/sig0000057e ), + .I1(\blk00000003/sig000001e8 ), + .I2(\blk00000003/sig000001e9 ), + .O(\blk00000003/sig000002a6 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000438 ( + .I0(\blk00000003/sig000002a0 ), + .I1(\blk00000003/sig000001c7 ), + .O(\blk00000003/sig0000029a ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000437 ( + .I0(\blk00000003/sig0000023d ), + .I1(\blk00000003/sig00000244 ), + .O(\blk00000003/sig00000297 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000436 ( + .I0(\blk00000003/sig00000244 ), + .I1(\blk00000003/sig0000023c ), + .O(\blk00000003/sig00000294 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000435 ( + .I0(\blk00000003/sig00000244 ), + .I1(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000292 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000434 ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig0000024a ), + .I2(\blk00000003/sig00000244 ), + .O(\blk00000003/sig0000028d ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000433 ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig00000240 ), + .I2(\blk00000003/sig00000244 ), + .O(\blk00000003/sig0000028f ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000432 ( + .I0(\blk00000003/sig0000023d ), + .I1(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000286 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000431 ( + .I0(\blk00000003/sig0000023c ), + .I1(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000284 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000430 ( + .I0(\blk00000003/sig0000023a ), + .I1(\blk00000003/sig00000244 ), + .I2(\blk00000003/sig00000240 ), + .O(\blk00000003/sig0000027f ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000042f ( + .I0(\blk00000003/sig0000023f ), + .I1(\blk00000003/sig00000240 ), + .O(\blk00000003/sig0000027b ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000042e ( + .I0(\blk00000003/sig0000023e ), + .I1(\blk00000003/sig00000240 ), + .I2(\blk00000003/sig0000024a ), + .O(\blk00000003/sig0000027d ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000042d ( + .I0(\blk00000003/sig0000024d ), + .I1(\blk00000003/sig0000057d ), + .O(\blk00000003/sig00000276 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000042c ( + .I0(coef_we), + .I1(\blk00000003/sig00000224 ), + .I2(\blk00000003/sig0000022c ), + .O(\blk00000003/sig00000268 ) + ); + LUT4 #( + .INIT ( 16'hDAAA )) + \blk00000003/blk0000042b ( + .I0(\blk00000003/sig00000267 ), + .I1(\blk00000003/sig00000224 ), + .I2(\blk00000003/sig0000022c ), + .I3(coef_we), + .O(\blk00000003/sig00000265 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000042a ( + .I0(\blk00000003/sig00000263 ), + .I1(\blk00000003/sig000001c4 ), + .O(\blk00000003/sig00000261 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000429 ( + .I0(\blk00000003/sig00000258 ), + .I1(coef_we), + .O(\blk00000003/sig00000256 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000428 ( + .I0(coef_ld), + .I1(\blk00000003/sig0000024d ), + .O(\blk00000003/sig00000243 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000427 ( + .I0(coef_we), + .I1(\blk00000003/sig0000022c ), + .O(\blk00000003/sig00000225 ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk00000426 ( + .I0(\blk00000003/sig00000238 ), + .I1(coef_we), + .I2(coef_ld), + .O(\blk00000003/sig0000024b ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk00000425 ( + .I0(\blk00000003/sig00000254 ), + .I1(\blk00000003/sig00000255 ), + .I2(\blk00000003/sig00000258 ), + .O(\blk00000003/sig0000022e ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000424 ( + .I0(coef_ld), + .I1(\blk00000003/sig0000024d ), + .I2(\blk00000003/sig00000236 ), + .O(\blk00000003/sig00000222 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000423 ( + .I0(coef_we), + .I1(\blk00000003/sig00000238 ), + .I2(\blk00000003/sig00000236 ), + .O(\blk00000003/sig0000021f ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk00000422 ( + .I0(\blk00000003/sig00000238 ), + .I1(coef_we), + .I2(\blk00000003/sig0000022c ), + .I3(\blk00000003/sig00000224 ), + .I4(coef_ld), + .O(\blk00000003/sig00000237 ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk00000421 ( + .I0(\blk00000003/sig00000236 ), + .I1(\blk00000003/sig00000238 ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig00000235 ) + ); + LUT3 #( + .INIT ( 8'h80 )) + \blk00000003/blk00000420 ( + .I0(nd), + .I1(\blk00000003/sig000002a2 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000001e7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000041f ( + .I0(\blk00000003/sig000000be ), + .I1(\blk00000003/sig000001df ), + .O(\blk00000003/sig000001e5 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk0000041e ( + .I0(\blk00000003/sig000000be ), + .I1(\blk00000003/sig000004fd ), + .I2(\blk00000003/sig0000057c ), + .O(\blk00000003/sig000000bf ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk0000041d ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig000004fd ), + .O(\blk00000003/sig000001e0 ) + ); + LUT2 #( + .INIT ( 4'hD )) + \blk00000003/blk0000041c ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .O(\blk00000003/sig000001cb ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000041b ( + .I0(\blk00000003/sig0000029f ), + .I1(\blk00000003/sig000002a0 ), + .O(\blk00000003/sig000001c8 ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk0000041a ( + .I0(\blk00000003/sig0000025f ), + .I1(\blk00000003/sig00000260 ), + .I2(\blk00000003/sig00000263 ), + .O(\blk00000003/sig000001c5 ) + ); + LUT5 #( + .INIT ( 32'h00008000 )) + \blk00000003/blk00000419 ( + .I0(\blk00000003/sig00000573 ), + .I1(\blk00000003/sig00000574 ), + .I2(\blk00000003/sig00000575 ), + .I3(\blk00000003/sig00000576 ), + .I4(\blk00000003/sig00000577 ), + .O(\blk00000003/sig000000c1 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000418 ( + .I0(\blk00000003/sig000001d8 ), + .I1(\blk00000003/sig000001c4 ), + .I2(\blk00000003/sig000001e6 ), + .O(\blk00000003/sig000001d7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000417 ( + .I0(\blk00000003/sig000002b7 ), + .I1(\blk00000003/sig000001e4 ), + .O(\blk00000003/sig000001dd ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000416 ( + .I0(ce), + .I1(\blk00000003/sig00000579 ), + .I2(\blk00000003/sig000000b4 ), + .O(\blk00000003/sig000000b3 ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000415 ( + .I0(ce), + .I1(\blk00000003/sig00000579 ), + .I2(\blk00000003/sig000000b2 ), + .O(\blk00000003/sig000000b1 ) + ); + LUT4 #( + .INIT ( 16'h8F88 )) + \blk00000003/blk00000414 ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .I2(\blk00000003/sig000001da ), + .I3(\blk00000003/sig000001c7 ), + .O(\blk00000003/sig000001d9 ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk00000413 ( + .I0(\blk00000003/sig000001c4 ), + .I1(\blk00000003/sig000001e6 ), + .I2(\blk00000003/sig000001d6 ), + .I3(\blk00000003/sig000001d8 ), + .I4(\blk00000003/sig000001d4 ), + .O(\blk00000003/sig000001d5 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk00000412 ( + .I0(\blk00000003/sig000001d6 ), + .I1(\blk00000003/sig0000057b ), + .I2(\blk00000003/sig000001d8 ), + .I3(\blk00000003/sig000001e6 ), + .O(\blk00000003/sig000001d1 ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk00000411 ( + .I0(\blk00000003/sig000001e6 ), + .I1(\blk00000003/sig000001d6 ), + .I2(\blk00000003/sig000001d8 ), + .I3(\blk00000003/sig000001d4 ), + .O(\blk00000003/sig000001d3 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk00000410 ( + .I0(\blk00000003/sig000002b6 ), + .I1(\blk00000003/sig000002b7 ), + .I2(\blk00000003/sig000001e4 ), + .O(\blk00000003/sig000001db ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk0000040f ( + .I0(ce), + .I1(\blk00000003/sig00000579 ), + .I2(\blk00000003/sig0000057a ), + .I3(\blk00000003/sig000000b0 ), + .O(\blk00000003/sig000000af ) + ); + MUXCY \blk00000003/blk0000040e ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig00000578 ), + .O(\blk00000003/sig00000570 ) + ); + MUXCY_L \blk00000003/blk0000040d ( + .CI(\blk00000003/sig00000570 ), + .DI(\blk00000003/sig00000577 ), + .S(\blk00000003/sig00000571 ), + .LO(\blk00000003/sig0000056d ) + ); + MUXCY_L \blk00000003/blk0000040c ( + .CI(\blk00000003/sig0000056d ), + .DI(\blk00000003/sig00000576 ), + .S(\blk00000003/sig0000056e ), + .LO(\blk00000003/sig0000056a ) + ); + MUXCY_L \blk00000003/blk0000040b ( + .CI(\blk00000003/sig0000056a ), + .DI(\blk00000003/sig00000575 ), + .S(\blk00000003/sig0000056b ), + .LO(\blk00000003/sig00000567 ) + ); + MUXCY_L \blk00000003/blk0000040a ( + .CI(\blk00000003/sig00000567 ), + .DI(\blk00000003/sig00000574 ), + .S(\blk00000003/sig00000568 ), + .LO(\blk00000003/sig00000564 ) + ); + MUXCY_D \blk00000003/blk00000409 ( + .CI(\blk00000003/sig00000564 ), + .DI(\blk00000003/sig00000573 ), + .S(\blk00000003/sig00000565 ), + .O(\NLW_blk00000003/blk00000409_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000409_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000408 ( + .CI(\blk00000003/sig00000570 ), + .LI(\blk00000003/sig00000571 ), + .O(\blk00000003/sig00000572 ) + ); + XORCY \blk00000003/blk00000407 ( + .CI(\blk00000003/sig0000056d ), + .LI(\blk00000003/sig0000056e ), + .O(\blk00000003/sig0000056f ) + ); + XORCY \blk00000003/blk00000406 ( + .CI(\blk00000003/sig0000056a ), + .LI(\blk00000003/sig0000056b ), + .O(\blk00000003/sig0000056c ) + ); + XORCY \blk00000003/blk00000405 ( + .CI(\blk00000003/sig00000567 ), + .LI(\blk00000003/sig00000568 ), + .O(\blk00000003/sig00000569 ) + ); + XORCY \blk00000003/blk00000404 ( + .CI(\blk00000003/sig00000564 ), + .LI(\blk00000003/sig00000565 ), + .O(\blk00000003/sig00000566 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000403 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000563 ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000402 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000562 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[47]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000401 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000561 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000400 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000560 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000559 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000558 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000557 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000556 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000555 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000554 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000553 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000552 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000551 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000550 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000549 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000548 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000547 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000546 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000545 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000544 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000543 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000542 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000541 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000540 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003db ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000539 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000538 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000537 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000536 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000535 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000534 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000533 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000532 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[47]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000531 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000530 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000529 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000528 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000527 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000526 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000525 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000524 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000523 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000522 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000521 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000520 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000519 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000518 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000517 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000516 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000515 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000514 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000513 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000512 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000511 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000510 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000509 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000508 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000507 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000506 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000505 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000504 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000503 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000502 ), + .Q(\blk00000003/sig000001df ) + ); + MUXCY_L \blk00000003/blk000003a1 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000501 ), + .S(\blk00000003/sig000004ef ), + .LO(\blk00000003/sig000004fa ) + ); + MUXCY_L \blk00000003/blk000003a0 ( + .CI(\blk00000003/sig000004fa ), + .DI(\blk00000003/sig00000500 ), + .S(\blk00000003/sig000004fb ), + .LO(\blk00000003/sig000004f7 ) + ); + MUXCY_L \blk00000003/blk0000039f ( + .CI(\blk00000003/sig000004f7 ), + .DI(\blk00000003/sig000004ff ), + .S(\blk00000003/sig000004f8 ), + .LO(\blk00000003/sig000004f4 ) + ); + MUXCY_L \blk00000003/blk0000039e ( + .CI(\blk00000003/sig000004f4 ), + .DI(\blk00000003/sig000004fe ), + .S(\blk00000003/sig000004f5 ), + .LO(\blk00000003/sig000004f1 ) + ); + MUXCY_D \blk00000003/blk0000039d ( + .CI(\blk00000003/sig000004f1 ), + .DI(\blk00000003/sig000004fd ), + .S(\blk00000003/sig000004f2 ), + .O(\NLW_blk00000003/blk0000039d_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000039d_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000039c ( + .CI(\blk00000003/sig000004fa ), + .LI(\blk00000003/sig000004fb ), + .O(\blk00000003/sig000004fc ) + ); + XORCY \blk00000003/blk0000039b ( + .CI(\blk00000003/sig000004f7 ), + .LI(\blk00000003/sig000004f8 ), + .O(\blk00000003/sig000004f9 ) + ); + XORCY \blk00000003/blk0000039a ( + .CI(\blk00000003/sig000004f4 ), + .LI(\blk00000003/sig000004f5 ), + .O(\blk00000003/sig000004f6 ) + ); + XORCY \blk00000003/blk00000399 ( + .CI(\blk00000003/sig000004f1 ), + .LI(\blk00000003/sig000004f2 ), + .O(\blk00000003/sig000004f3 ) + ); + XORCY \blk00000003/blk00000398 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000004ef ), + .O(\blk00000003/sig000004f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000370 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003dd ), + .R(sclr), + .Q(\blk00000003/sig00000450 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036f ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003dc ), + .R(sclr), + .Q(\blk00000003/sig0000044f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036e ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003db ), + .R(sclr), + .Q(\blk00000003/sig0000044e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003da ), + .R(sclr), + .Q(\blk00000003/sig0000044d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036c ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d9 ), + .R(sclr), + .Q(\blk00000003/sig0000044c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036b ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d8 ), + .R(sclr), + .Q(\blk00000003/sig0000044b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036a ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d7 ), + .R(sclr), + .Q(\blk00000003/sig0000044a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000369 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d6 ), + .R(sclr), + .Q(\blk00000003/sig00000449 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000368 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d5 ), + .R(sclr), + .Q(\blk00000003/sig00000448 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000367 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d4 ), + .R(sclr), + .Q(\blk00000003/sig00000447 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000366 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d3 ), + .R(sclr), + .Q(\blk00000003/sig00000446 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000365 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d2 ), + .R(sclr), + .Q(\blk00000003/sig00000445 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000364 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d1 ), + .R(sclr), + .Q(\blk00000003/sig00000444 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000363 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d0 ), + .R(sclr), + .Q(\blk00000003/sig00000443 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000362 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003cf ), + .R(sclr), + .Q(\blk00000003/sig00000442 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000361 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003ce ), + .R(sclr), + .Q(\blk00000003/sig00000441 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000360 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003cd ), + .R(sclr), + .Q(\blk00000003/sig00000440 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035f ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003cc ), + .R(sclr), + .Q(\blk00000003/sig0000043f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035e ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003cb ), + .R(sclr), + .Q(\blk00000003/sig0000043e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035d ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003ca ), + .R(sclr), + .Q(\blk00000003/sig0000043d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035c ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003c9 ), + .R(sclr), + .Q(\blk00000003/sig0000043c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035b ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003c8 ), + .R(sclr), + .Q(\blk00000003/sig0000043b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035a ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003c7 ), + .R(sclr), + .Q(\blk00000003/sig0000043a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000359 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003c6 ), + .R(sclr), + .Q(\blk00000003/sig00000439 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000358 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig0000040d ), + .R(sclr), + .Q(\blk00000003/sig00000468 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000357 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig0000040c ), + .R(sclr), + .Q(\blk00000003/sig00000467 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000356 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig0000040b ), + .R(sclr), + .Q(\blk00000003/sig00000466 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000355 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig0000040a ), + .R(sclr), + .Q(\blk00000003/sig00000465 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000354 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000409 ), + .R(sclr), + .Q(\blk00000003/sig00000464 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000353 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000408 ), + .R(sclr), + .Q(\blk00000003/sig00000463 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000352 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000407 ), + .R(sclr), + .Q(\blk00000003/sig00000462 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000406 ), + .R(sclr), + .Q(\blk00000003/sig00000461 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000350 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000405 ), + .R(sclr), + .Q(\blk00000003/sig00000460 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034f ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000404 ), + .R(sclr), + .Q(\blk00000003/sig0000045f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034e ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000403 ), + .R(sclr), + .Q(\blk00000003/sig0000045e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034d ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000402 ), + .R(sclr), + .Q(\blk00000003/sig0000045d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034c ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000401 ), + .R(sclr), + .Q(\blk00000003/sig0000045c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034b ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000400 ), + .R(sclr), + .Q(\blk00000003/sig0000045b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003ff ), + .R(sclr), + .Q(\blk00000003/sig0000045a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000349 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fe ), + .R(sclr), + .Q(\blk00000003/sig00000459 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fd ), + .R(sclr), + .Q(\blk00000003/sig00000458 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000347 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fc ), + .R(sclr), + .Q(\blk00000003/sig00000457 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000346 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fb ), + .R(sclr), + .Q(\blk00000003/sig00000456 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000345 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fa ), + .R(sclr), + .Q(\blk00000003/sig00000455 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000344 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003f9 ), + .R(sclr), + .Q(\blk00000003/sig00000454 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000343 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003f8 ), + .R(sclr), + .Q(\blk00000003/sig00000453 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000342 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003f7 ), + .R(sclr), + .Q(\blk00000003/sig00000452 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000341 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003f6 ), + .R(sclr), + .Q(\blk00000003/sig00000451 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000340 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f5 ), + .R(sclr), + .Q(\blk00000003/sig00000498 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033f ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f4 ), + .R(sclr), + .Q(\blk00000003/sig00000497 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033e ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f3 ), + .R(sclr), + .Q(\blk00000003/sig00000496 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033d ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f2 ), + .R(sclr), + .Q(\blk00000003/sig00000495 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033c ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f1 ), + .R(sclr), + .Q(\blk00000003/sig00000494 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033b ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f0 ), + .R(sclr), + .Q(\blk00000003/sig00000493 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033a ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ef ), + .R(sclr), + .Q(\blk00000003/sig00000492 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000339 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ee ), + .R(sclr), + .Q(\blk00000003/sig00000491 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000338 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ed ), + .R(sclr), + .Q(\blk00000003/sig00000490 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000337 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ec ), + .R(sclr), + .Q(\blk00000003/sig0000048f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000336 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003eb ), + .R(sclr), + .Q(\blk00000003/sig0000048e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000335 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ea ), + .R(sclr), + .Q(\blk00000003/sig0000048d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000334 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e9 ), + .R(sclr), + .Q(\blk00000003/sig0000048c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000333 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e8 ), + .R(sclr), + .Q(\blk00000003/sig0000048b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000332 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e7 ), + .R(sclr), + .Q(\blk00000003/sig0000048a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000331 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e6 ), + .R(sclr), + .Q(\blk00000003/sig00000489 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000330 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e5 ), + .R(sclr), + .Q(\blk00000003/sig00000488 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032f ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e4 ), + .R(sclr), + .Q(\blk00000003/sig00000487 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032e ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e3 ), + .R(sclr), + .Q(\blk00000003/sig00000486 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032d ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e2 ), + .R(sclr), + .Q(\blk00000003/sig00000485 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032c ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e1 ), + .R(sclr), + .Q(\blk00000003/sig00000484 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032b ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e0 ), + .R(sclr), + .Q(\blk00000003/sig00000483 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032a ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003df ), + .R(sclr), + .Q(\blk00000003/sig00000482 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000329 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003de ), + .R(sclr), + .Q(\blk00000003/sig00000481 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000328 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000425 ), + .R(sclr), + .Q(\blk00000003/sig000004c8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000424 ), + .R(sclr), + .Q(\blk00000003/sig000004c7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000326 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000423 ), + .R(sclr), + .Q(\blk00000003/sig000004c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000325 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000422 ), + .R(sclr), + .Q(\blk00000003/sig000004c5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000324 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000421 ), + .R(sclr), + .Q(\blk00000003/sig000004c4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000323 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000420 ), + .R(sclr), + .Q(\blk00000003/sig000004c3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000322 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041f ), + .R(sclr), + .Q(\blk00000003/sig000004c2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000321 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041e ), + .R(sclr), + .Q(\blk00000003/sig000004c1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000320 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041d ), + .R(sclr), + .Q(\blk00000003/sig000004c0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031f ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041c ), + .R(sclr), + .Q(\blk00000003/sig000004bf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041b ), + .R(sclr), + .Q(\blk00000003/sig000004be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031d ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041a ), + .R(sclr), + .Q(\blk00000003/sig000004bd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031c ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000419 ), + .R(sclr), + .Q(\blk00000003/sig000004bc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031b ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000418 ), + .R(sclr), + .Q(\blk00000003/sig000004bb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031a ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000417 ), + .R(sclr), + .Q(\blk00000003/sig000004ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000319 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000416 ), + .R(sclr), + .Q(\blk00000003/sig000004b9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000318 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000415 ), + .R(sclr), + .Q(\blk00000003/sig000004b8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000317 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000414 ), + .R(sclr), + .Q(\blk00000003/sig000004b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000316 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000413 ), + .R(sclr), + .Q(\blk00000003/sig000004b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000412 ), + .R(sclr), + .Q(\blk00000003/sig000004b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000314 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000411 ), + .R(sclr), + .Q(\blk00000003/sig000004b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000313 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000410 ), + .R(sclr), + .Q(\blk00000003/sig000004b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000312 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000040f ), + .R(sclr), + .Q(\blk00000003/sig000004b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000311 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000040e ), + .R(sclr), + .Q(\blk00000003/sig000004b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000118 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d1 ), + .R(sclr), + .Q(\blk00000003/sig00000438 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d0 ), + .R(sclr), + .Q(\blk00000003/sig00000437 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002cf ), + .R(sclr), + .Q(\blk00000003/sig00000436 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000115 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000434 ), + .R(sclr), + .Q(\blk00000003/sig00000435 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000114 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d3 ), + .R(sclr), + .Q(\blk00000003/sig00000433 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000113 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d7 ), + .R(sclr), + .Q(\blk00000003/sig00000432 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000112 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002da ), + .R(sclr), + .Q(\blk00000003/sig00000431 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000111 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002e1 ), + .R(sclr), + .Q(\blk00000003/sig00000430 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000110 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000042e ), + .R(sclr), + .Q(\blk00000003/sig0000042f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c6 ), + .R(sclr), + .Q(\blk00000003/sig0000042d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c5 ), + .R(sclr), + .Q(\blk00000003/sig0000042c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c4 ), + .R(sclr), + .Q(\blk00000003/sig0000042b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000234 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000042a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000275 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000429 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000271 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000428 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000109 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000427 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000108 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000426 ) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000107 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000107_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk00000107_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000107_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000107_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000107_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000107_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000107_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig000000ae , +\blk00000003/sig00000049 , \blk00000003/sig000000ae }), + .PCIN({\blk00000003/sig00000384 , \blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , \blk00000003/sig00000388 , +\blk00000003/sig00000389 , \blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , \blk00000003/sig0000038d , +\blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , \blk00000003/sig00000392 , +\blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 , \blk00000003/sig00000397 , +\blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , \blk00000003/sig0000039c , +\blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , \blk00000003/sig000003a1 , +\blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , \blk00000003/sig000003a6 , +\blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa , \blk00000003/sig000003ab , +\blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , \blk00000003/sig000003b0 , +\blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000107_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000107_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000107_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , +\blk00000003/sig000003b9 , \blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , +\blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , +\blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 }), + .BCOUT({\NLW_blk00000003/blk00000107_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000003f6 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , +\blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , +\blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 , +\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d }), + .P({\NLW_blk00000003/blk00000107_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000040e , \blk00000003/sig0000040e , \blk00000003/sig0000040e , \blk00000003/sig0000040e , \blk00000003/sig0000040e , +\blk00000003/sig0000040e , \blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , +\blk00000003/sig00000412 , \blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , +\blk00000003/sig00000417 , \blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , \blk00000003/sig0000041b , +\blk00000003/sig0000041c , \blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , \blk00000003/sig00000420 , +\blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , \blk00000003/sig00000425 }), + .PCOUT({\blk00000003/sig000000c2 , \blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , +\blk00000003/sig000000c7 , \blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , +\blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , +\blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , +\blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , +\blk00000003/sig000000db , \blk00000003/sig000000dc , \blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , +\blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , +\blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , +\blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , +\blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000106 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000106_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk00000106_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000106_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000106_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000106_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000106_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000106_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig000000ae , +\blk00000003/sig00000049 , \blk00000003/sig000000ae }), + .PCIN({\blk00000003/sig00000324 , \blk00000003/sig00000325 , \blk00000003/sig00000326 , \blk00000003/sig00000327 , \blk00000003/sig00000328 , +\blk00000003/sig00000329 , \blk00000003/sig0000032a , \blk00000003/sig0000032b , \blk00000003/sig0000032c , \blk00000003/sig0000032d , +\blk00000003/sig0000032e , \blk00000003/sig0000032f , \blk00000003/sig00000330 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , +\blk00000003/sig00000333 , \blk00000003/sig00000334 , \blk00000003/sig00000335 , \blk00000003/sig00000336 , \blk00000003/sig00000337 , +\blk00000003/sig00000338 , \blk00000003/sig00000339 , \blk00000003/sig0000033a , \blk00000003/sig0000033b , \blk00000003/sig0000033c , +\blk00000003/sig0000033d , \blk00000003/sig0000033e , \blk00000003/sig0000033f , \blk00000003/sig00000340 , \blk00000003/sig00000341 , +\blk00000003/sig00000342 , \blk00000003/sig00000343 , \blk00000003/sig00000344 , \blk00000003/sig00000345 , \blk00000003/sig00000346 , +\blk00000003/sig00000347 , \blk00000003/sig00000348 , \blk00000003/sig00000349 , \blk00000003/sig0000034a , \blk00000003/sig0000034b , +\blk00000003/sig0000034c , \blk00000003/sig0000034d , \blk00000003/sig0000034e , \blk00000003/sig0000034f , \blk00000003/sig00000350 , +\blk00000003/sig00000351 , \blk00000003/sig00000352 , \blk00000003/sig00000353 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000106_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000106_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000106_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , +\blk00000003/sig000003b9 , \blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , +\blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , +\blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 }), + .BCOUT({\NLW_blk00000003/blk00000106_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000003c6 , \blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , +\blk00000003/sig000003ca , \blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd , \blk00000003/sig000003ce , +\blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 , \blk00000003/sig000003d3 , +\blk00000003/sig000003d4 , \blk00000003/sig000003d5 , \blk00000003/sig000003d6 , \blk00000003/sig000003d7 , \blk00000003/sig000003d8 , +\blk00000003/sig000003d9 , \blk00000003/sig000003da , \blk00000003/sig000003db , \blk00000003/sig000003dc , \blk00000003/sig000003dd }), + .P({\NLW_blk00000003/blk00000106_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000003de , \blk00000003/sig000003de , \blk00000003/sig000003de , \blk00000003/sig000003de , \blk00000003/sig000003de , +\blk00000003/sig000003de , \blk00000003/sig000003de , \blk00000003/sig000003df , \blk00000003/sig000003e0 , \blk00000003/sig000003e1 , +\blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , \blk00000003/sig000003e5 , \blk00000003/sig000003e6 , +\blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , \blk00000003/sig000003ea , \blk00000003/sig000003eb , +\blk00000003/sig000003ec , \blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , \blk00000003/sig000003f0 , +\blk00000003/sig000003f1 , \blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , \blk00000003/sig000003f5 }), + .PCOUT({\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , +\blk00000003/sig00000156 , \blk00000003/sig00000157 , \blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , +\blk00000003/sig0000015b , \blk00000003/sig0000015c , \blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , +\blk00000003/sig00000160 , \blk00000003/sig00000161 , \blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , +\blk00000003/sig00000165 , \blk00000003/sig00000166 , \blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , +\blk00000003/sig0000016a , \blk00000003/sig0000016b , \blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , +\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000105 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000105_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk00000105_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000105_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000105_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000105_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000105_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000105_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig000000ae , +\blk00000003/sig00000049 , \blk00000003/sig000000ae }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000105_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000105_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000105_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002e2 , \blk00000003/sig000002e3 , \blk00000003/sig000002e4 , \blk00000003/sig000002e5 , \blk00000003/sig000002e6 , +\blk00000003/sig000002e7 , \blk00000003/sig000002e8 , \blk00000003/sig000002e9 , \blk00000003/sig000002ea , \blk00000003/sig000002eb , +\blk00000003/sig000002ec , \blk00000003/sig000002ed , \blk00000003/sig000002ee , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , +\blk00000003/sig000002f1 , \blk00000003/sig000002f2 , \blk00000003/sig000002f3 }), + .BCOUT({\NLW_blk00000003/blk00000105_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000354 , \blk00000003/sig00000354 , \blk00000003/sig00000355 , \blk00000003/sig00000356 , \blk00000003/sig00000357 , +\blk00000003/sig00000358 , \blk00000003/sig00000359 , \blk00000003/sig0000035a , \blk00000003/sig0000035b , \blk00000003/sig0000035c , +\blk00000003/sig0000035d , \blk00000003/sig0000035e , \blk00000003/sig0000035f , \blk00000003/sig00000360 , \blk00000003/sig00000361 , +\blk00000003/sig00000362 , \blk00000003/sig00000363 , \blk00000003/sig00000364 , \blk00000003/sig00000365 , \blk00000003/sig00000366 , +\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b }), + .P({\NLW_blk00000003/blk00000105_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000036c , \blk00000003/sig0000036c , \blk00000003/sig0000036c , \blk00000003/sig0000036c , \blk00000003/sig0000036c , +\blk00000003/sig0000036c , \blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , +\blk00000003/sig00000370 , \blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , +\blk00000003/sig00000375 , \blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 , \blk00000003/sig00000379 , +\blk00000003/sig0000037a , \blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , \blk00000003/sig0000037e , +\blk00000003/sig0000037f , \blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , \blk00000003/sig00000383 }), + .PCOUT({\blk00000003/sig00000384 , \blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , \blk00000003/sig00000388 , +\blk00000003/sig00000389 , \blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , \blk00000003/sig0000038d , +\blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , \blk00000003/sig00000392 , +\blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 , \blk00000003/sig00000397 , +\blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , \blk00000003/sig0000039c , +\blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , \blk00000003/sig000003a1 , +\blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , \blk00000003/sig000003a6 , +\blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa , \blk00000003/sig000003ab , +\blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , \blk00000003/sig000003b0 , +\blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000104 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000104_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk00000104_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000104_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000104_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000104_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000104_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000104_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig000000ae , +\blk00000003/sig00000049 , \blk00000003/sig000000ae }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000104_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000104_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000104_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002e2 , \blk00000003/sig000002e3 , \blk00000003/sig000002e4 , \blk00000003/sig000002e5 , \blk00000003/sig000002e6 , +\blk00000003/sig000002e7 , \blk00000003/sig000002e8 , \blk00000003/sig000002e9 , \blk00000003/sig000002ea , \blk00000003/sig000002eb , +\blk00000003/sig000002ec , \blk00000003/sig000002ed , \blk00000003/sig000002ee , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , +\blk00000003/sig000002f1 , \blk00000003/sig000002f2 , \blk00000003/sig000002f3 }), + .BCOUT({\NLW_blk00000003/blk00000104_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000002f4 , \blk00000003/sig000002f4 , \blk00000003/sig000002f5 , \blk00000003/sig000002f6 , \blk00000003/sig000002f7 , +\blk00000003/sig000002f8 , \blk00000003/sig000002f9 , \blk00000003/sig000002fa , \blk00000003/sig000002fb , \blk00000003/sig000002fc , +\blk00000003/sig000002fd , \blk00000003/sig000002fe , \blk00000003/sig000002ff , \blk00000003/sig00000300 , \blk00000003/sig00000301 , +\blk00000003/sig00000302 , \blk00000003/sig00000303 , \blk00000003/sig00000304 , \blk00000003/sig00000305 , \blk00000003/sig00000306 , +\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b }), + .P({\NLW_blk00000003/blk00000104_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000030c , \blk00000003/sig0000030c , \blk00000003/sig0000030c , \blk00000003/sig0000030c , \blk00000003/sig0000030c , +\blk00000003/sig0000030c , \blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , +\blk00000003/sig00000310 , \blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , +\blk00000003/sig00000315 , \blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 , \blk00000003/sig00000319 , +\blk00000003/sig0000031a , \blk00000003/sig0000031b , \blk00000003/sig0000031c , \blk00000003/sig0000031d , \blk00000003/sig0000031e , +\blk00000003/sig0000031f , \blk00000003/sig00000320 , \blk00000003/sig00000321 , \blk00000003/sig00000322 , \blk00000003/sig00000323 }), + .PCOUT({\blk00000003/sig00000324 , \blk00000003/sig00000325 , \blk00000003/sig00000326 , \blk00000003/sig00000327 , \blk00000003/sig00000328 , +\blk00000003/sig00000329 , \blk00000003/sig0000032a , \blk00000003/sig0000032b , \blk00000003/sig0000032c , \blk00000003/sig0000032d , +\blk00000003/sig0000032e , \blk00000003/sig0000032f , \blk00000003/sig00000330 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , +\blk00000003/sig00000333 , \blk00000003/sig00000334 , \blk00000003/sig00000335 , \blk00000003/sig00000336 , \blk00000003/sig00000337 , +\blk00000003/sig00000338 , \blk00000003/sig00000339 , \blk00000003/sig0000033a , \blk00000003/sig0000033b , \blk00000003/sig0000033c , +\blk00000003/sig0000033d , \blk00000003/sig0000033e , \blk00000003/sig0000033f , \blk00000003/sig00000340 , \blk00000003/sig00000341 , +\blk00000003/sig00000342 , \blk00000003/sig00000343 , \blk00000003/sig00000344 , \blk00000003/sig00000345 , \blk00000003/sig00000346 , +\blk00000003/sig00000347 , \blk00000003/sig00000348 , \blk00000003/sig00000349 , \blk00000003/sig0000034a , \blk00000003/sig0000034b , +\blk00000003/sig0000034c , \blk00000003/sig0000034d , \blk00000003/sig0000034e , \blk00000003/sig0000034f , \blk00000003/sig00000350 , +\blk00000003/sig00000351 , \blk00000003/sig00000352 , \blk00000003/sig00000353 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000103 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ce ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000102 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000101 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig000002d2 ) + ); + XORCY \blk00000003/blk00000100 ( + .CI(\blk00000003/sig000002d9 ), + .LI(\blk00000003/sig000002db ), + .O(\blk00000003/sig000002dd ) + ); + XORCY \blk00000003/blk000000ff ( + .CI(\blk00000003/sig000002d5 ), + .LI(\blk00000003/sig000002d8 ), + .O(\blk00000003/sig000002dc ) + ); + MUXCY_D \blk00000003/blk000000fe ( + .CI(\blk00000003/sig000002d9 ), + .DI(\blk00000003/sig000002da ), + .S(\blk00000003/sig000002db ), + .O(\NLW_blk00000003/blk000000fe_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000fe_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000fd ( + .CI(\blk00000003/sig000002d5 ), + .DI(\blk00000003/sig000002d7 ), + .S(\blk00000003/sig000002d8 ), + .LO(\blk00000003/sig000002d9 ) + ); + XORCY \blk00000003/blk000000fc ( + .CI(\blk00000003/sig000002d2 ), + .LI(\blk00000003/sig000002d4 ), + .O(\blk00000003/sig000002d6 ) + ); + MUXCY_L \blk00000003/blk000000fb ( + .CI(\blk00000003/sig000002d2 ), + .DI(\blk00000003/sig000002d3 ), + .S(\blk00000003/sig000002d4 ), + .LO(\blk00000003/sig000002d5 ) + ); + MUXCY_L \blk00000003/blk000000fa ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002d1 ), + .S(\blk00000003/sig000002c7 ), + .LO(\blk00000003/sig000002cc ) + ); + MUXCY_L \blk00000003/blk000000f9 ( + .CI(\blk00000003/sig000002cc ), + .DI(\blk00000003/sig000002d0 ), + .S(\blk00000003/sig000002cd ), + .LO(\blk00000003/sig000002c9 ) + ); + MUXCY_D \blk00000003/blk000000f8 ( + .CI(\blk00000003/sig000002c9 ), + .DI(\blk00000003/sig000002cf ), + .S(\blk00000003/sig000002ca ), + .O(\NLW_blk00000003/blk000000f8_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f8_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000f7 ( + .CI(\blk00000003/sig000002cc ), + .LI(\blk00000003/sig000002cd ), + .O(\blk00000003/sig000002ce ) + ); + XORCY \blk00000003/blk000000f6 ( + .CI(\blk00000003/sig000002c9 ), + .LI(\blk00000003/sig000002ca ), + .O(\blk00000003/sig000002cb ) + ); + XORCY \blk00000003/blk000000f5 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002c7 ), + .O(\blk00000003/sig000002c8 ) + ); + MUXCY_L \blk00000003/blk000000f4 ( + .CI(\blk00000003/sig000002ba ), + .DI(\blk00000003/sig000002c6 ), + .S(\blk00000003/sig000002bb ), + .LO(\blk00000003/sig000002c0 ) + ); + MUXCY_L \blk00000003/blk000000f3 ( + .CI(\blk00000003/sig000002c0 ), + .DI(\blk00000003/sig000002c5 ), + .S(\blk00000003/sig000002c1 ), + .LO(\blk00000003/sig000002bd ) + ); + MUXCY_D \blk00000003/blk000000f2 ( + .CI(\blk00000003/sig000002bd ), + .DI(\blk00000003/sig000002c4 ), + .S(\blk00000003/sig000002be ), + .O(\NLW_blk00000003/blk000000f2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f2_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000f1 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig000002c3 ), + .O(\blk00000003/sig000002ba ) + ); + XORCY \blk00000003/blk000000f0 ( + .CI(\blk00000003/sig000002c0 ), + .LI(\blk00000003/sig000002c1 ), + .O(\blk00000003/sig000002c2 ) + ); + XORCY \blk00000003/blk000000ef ( + .CI(\blk00000003/sig000002bd ), + .LI(\blk00000003/sig000002be ), + .O(\blk00000003/sig000002bf ) + ); + XORCY \blk00000003/blk000000ee ( + .CI(\blk00000003/sig000002ba ), + .LI(\blk00000003/sig000002bb ), + .O(\blk00000003/sig000002bc ) + ); + FDE \blk00000003/blk000000ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b8 ), + .Q(\blk00000003/sig000002b9 ) + ); + MUXCY_L \blk00000003/blk000000ec ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002b7 ), + .S(\blk00000003/sig000002b1 ), + .LO(\blk00000003/sig000002b3 ) + ); + MUXCY_D \blk00000003/blk000000eb ( + .CI(\blk00000003/sig000002b3 ), + .DI(\blk00000003/sig000002b6 ), + .S(\blk00000003/sig000002b4 ), + .O(\NLW_blk00000003/blk000000eb_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000eb_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000ea ( + .CI(\blk00000003/sig000002b3 ), + .LI(\blk00000003/sig000002b4 ), + .O(\blk00000003/sig000002b5 ) + ); + XORCY \blk00000003/blk000000e9 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002b1 ), + .O(\blk00000003/sig000002b2 ) + ); + MUXCY_L \blk00000003/blk000000e8 ( + .CI(\blk00000003/sig000002aa ), + .DI(\blk00000003/sig000001e9 ), + .S(\blk00000003/sig000002ab ), + .LO(\blk00000003/sig000002ad ) + ); + MUXCY_D \blk00000003/blk000000e7 ( + .CI(\blk00000003/sig000002ad ), + .DI(\blk00000003/sig000001e8 ), + .S(\blk00000003/sig000002ae ), + .O(\NLW_blk00000003/blk000000e7_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e7_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000e6 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig000002b0 ), + .O(\blk00000003/sig000002aa ) + ); + XORCY \blk00000003/blk000000e5 ( + .CI(\blk00000003/sig000002ad ), + .LI(\blk00000003/sig000002ae ), + .O(\blk00000003/sig000002af ) + ); + XORCY \blk00000003/blk000000e4 ( + .CI(\blk00000003/sig000002aa ), + .LI(\blk00000003/sig000002ab ), + .O(\blk00000003/sig000002ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a8 ), + .R(sclr), + .Q(\blk00000003/sig000002a9 ) + ); + MUXCY_D \blk00000003/blk000000e2 ( + .CI(\blk00000003/sig000002a5 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002a7 ), + .O(\NLW_blk00000003/blk000000e2_O_UNCONNECTED ), + .LO(\blk00000003/sig000002a8 ) + ); + MUXCY_D \blk00000003/blk000000e1 ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002a6 ), + .O(\blk00000003/sig000002a3 ), + .LO(\NLW_blk00000003/blk000000e1_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig000002a3 ), + .DI(\blk00000003/sig000002a2 ), + .S(\blk00000003/sig000002a4 ), + .O(\blk00000003/sig000002a5 ), + .LO(\blk00000003/sig000002a1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a1 ), + .R(sclr), + .Q(\blk00000003/sig000002a2 ) + ); + MUXCY_L \blk00000003/blk000000de ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002a0 ), + .S(\blk00000003/sig0000029a ), + .LO(\blk00000003/sig0000029c ) + ); + MUXCY_D \blk00000003/blk000000dd ( + .CI(\blk00000003/sig0000029c ), + .DI(\blk00000003/sig0000029f ), + .S(\blk00000003/sig0000029d ), + .O(\NLW_blk00000003/blk000000dd_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000dd_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000dc ( + .CI(\blk00000003/sig0000029c ), + .LI(\blk00000003/sig0000029d ), + .O(\blk00000003/sig0000029e ) + ); + XORCY \blk00000003/blk000000db ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig0000029a ), + .O(\blk00000003/sig0000029b ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000028b ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000221 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000028a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021e ) + ); + MUXCY_D \blk00000003/blk000000d8 ( + .CI(\blk00000003/sig0000021e ), + .DI(\blk00000003/sig00000298 ), + .S(\blk00000003/sig00000299 ), + .O(\blk00000003/sig00000295 ), + .LO(\NLW_blk00000003/blk000000d8_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d7 ( + .CI(\blk00000003/sig00000295 ), + .DI(\blk00000003/sig00000296 ), + .S(\blk00000003/sig00000297 ), + .O(\blk00000003/sig00000293 ), + .LO(\NLW_blk00000003/blk000000d7_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d6 ( + .CI(\blk00000003/sig00000293 ), + .DI(\blk00000003/sig00000289 ), + .S(\blk00000003/sig00000294 ), + .O(\blk00000003/sig00000290 ), + .LO(\NLW_blk00000003/blk000000d6_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d5 ( + .CI(\blk00000003/sig00000290 ), + .DI(\blk00000003/sig00000291 ), + .S(\blk00000003/sig00000292 ), + .O(\blk00000003/sig0000028e ), + .LO(\NLW_blk00000003/blk000000d5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d4 ( + .CI(\blk00000003/sig0000028e ), + .DI(\blk00000003/sig00000246 ), + .S(\blk00000003/sig0000028f ), + .O(\blk00000003/sig0000028c ), + .LO(\NLW_blk00000003/blk000000d4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d3 ( + .CI(\blk00000003/sig0000028c ), + .DI(\blk00000003/sig0000021b ), + .S(\blk00000003/sig0000028d ), + .O(\NLW_blk00000003/blk000000d3_O_UNCONNECTED ), + .LO(\blk00000003/sig0000028a ) + ); + XORCY \blk00000003/blk000000d2 ( + .CI(\blk00000003/sig0000028a ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig0000028b ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000279 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000289 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000278 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000001ce ) + ); + MUXCY_D \blk00000003/blk000000cf ( + .CI(\blk00000003/sig000001ce ), + .DI(\blk00000003/sig00000287 ), + .S(\blk00000003/sig00000288 ), + .O(\blk00000003/sig00000285 ), + .LO(\NLW_blk00000003/blk000000cf_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000ce ( + .CI(\blk00000003/sig00000285 ), + .DI(\blk00000003/sig000001cf ), + .S(\blk00000003/sig00000286 ), + .O(\blk00000003/sig00000283 ), + .LO(\NLW_blk00000003/blk000000ce_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cd ( + .CI(\blk00000003/sig00000283 ), + .DI(\blk00000003/sig000001ce ), + .S(\blk00000003/sig00000284 ), + .O(\blk00000003/sig00000280 ), + .LO(\NLW_blk00000003/blk000000cd_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cc ( + .CI(\blk00000003/sig00000280 ), + .DI(\blk00000003/sig00000281 ), + .S(\blk00000003/sig00000282 ), + .O(\blk00000003/sig0000027e ), + .LO(\NLW_blk00000003/blk000000cc_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cb ( + .CI(\blk00000003/sig0000027e ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig0000027f ), + .O(\blk00000003/sig0000027a ), + .LO(\NLW_blk00000003/blk000000cb_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000ca ( + .CI(\blk00000003/sig0000027c ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig0000027d ), + .O(\NLW_blk00000003/blk000000ca_O_UNCONNECTED ), + .LO(\blk00000003/sig00000278 ) + ); + MUXCY_D \blk00000003/blk000000c9 ( + .CI(\blk00000003/sig0000027a ), + .DI(\blk00000003/sig0000023b ), + .S(\blk00000003/sig0000027b ), + .O(\blk00000003/sig0000027c ), + .LO(\NLW_blk00000003/blk000000c9_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c8 ( + .CI(\blk00000003/sig00000278 ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig00000279 ) + ); + FDE \blk00000003/blk000000c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000276 ), + .Q(\blk00000003/sig00000277 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000275 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000269 ) + ); + XORCY \blk00000003/blk000000c4 ( + .CI(\blk00000003/sig00000270 ), + .LI(\blk00000003/sig00000272 ), + .O(\blk00000003/sig00000274 ) + ); + XORCY \blk00000003/blk000000c3 ( + .CI(\blk00000003/sig0000026c ), + .LI(\blk00000003/sig0000026f ), + .O(\blk00000003/sig00000273 ) + ); + MUXCY_D \blk00000003/blk000000c2 ( + .CI(\blk00000003/sig00000270 ), + .DI(\blk00000003/sig00000271 ), + .S(\blk00000003/sig00000272 ), + .O(\NLW_blk00000003/blk000000c2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c2_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000c1 ( + .CI(\blk00000003/sig0000026c ), + .DI(\blk00000003/sig0000026e ), + .S(\blk00000003/sig0000026f ), + .LO(\blk00000003/sig00000270 ) + ); + XORCY \blk00000003/blk000000c0 ( + .CI(\blk00000003/sig00000269 ), + .LI(\blk00000003/sig0000026b ), + .O(\blk00000003/sig0000026d ) + ); + MUXCY_L \blk00000003/blk000000bf ( + .CI(\blk00000003/sig00000269 ), + .DI(\blk00000003/sig0000026a ), + .S(\blk00000003/sig0000026b ), + .LO(\blk00000003/sig0000026c ) + ); + MUXCY \blk00000003/blk000000be ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig00000268 ), + .O(\blk00000003/sig00000264 ) + ); + MUXCY_D \blk00000003/blk000000bd ( + .CI(\blk00000003/sig00000264 ), + .DI(\blk00000003/sig00000267 ), + .S(\blk00000003/sig00000265 ), + .O(\NLW_blk00000003/blk000000bd_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000bd_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000bc ( + .CI(\blk00000003/sig00000264 ), + .LI(\blk00000003/sig00000265 ), + .O(\blk00000003/sig00000266 ) + ); + MUXCY_L \blk00000003/blk000000bb ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000263 ), + .S(\blk00000003/sig00000261 ), + .LO(\blk00000003/sig0000025c ) + ); + XORCY \blk00000003/blk000000ba ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000261 ), + .O(\blk00000003/sig00000262 ) + ); + MUXCY_L \blk00000003/blk000000b9 ( + .CI(\blk00000003/sig0000025c ), + .DI(\blk00000003/sig00000260 ), + .S(\blk00000003/sig0000025d ), + .LO(\blk00000003/sig00000259 ) + ); + MUXCY_D \blk00000003/blk000000b8 ( + .CI(\blk00000003/sig00000259 ), + .DI(\blk00000003/sig0000025f ), + .S(\blk00000003/sig0000025a ), + .O(\NLW_blk00000003/blk000000b8_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b8_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000b7 ( + .CI(\blk00000003/sig0000025c ), + .LI(\blk00000003/sig0000025d ), + .O(\blk00000003/sig0000025e ) + ); + XORCY \blk00000003/blk000000b6 ( + .CI(\blk00000003/sig00000259 ), + .LI(\blk00000003/sig0000025a ), + .O(\blk00000003/sig0000025b ) + ); + MUXCY_L \blk00000003/blk000000b5 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000258 ), + .S(\blk00000003/sig00000256 ), + .LO(\blk00000003/sig00000251 ) + ); + XORCY \blk00000003/blk000000b4 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000256 ), + .O(\blk00000003/sig00000257 ) + ); + MUXCY_L \blk00000003/blk000000b3 ( + .CI(\blk00000003/sig00000251 ), + .DI(\blk00000003/sig00000255 ), + .S(\blk00000003/sig00000252 ), + .LO(\blk00000003/sig0000024e ) + ); + MUXCY_D \blk00000003/blk000000b2 ( + .CI(\blk00000003/sig0000024e ), + .DI(\blk00000003/sig00000254 ), + .S(\blk00000003/sig0000024f ), + .O(\NLW_blk00000003/blk000000b2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000b1 ( + .CI(\blk00000003/sig00000251 ), + .LI(\blk00000003/sig00000252 ), + .O(\blk00000003/sig00000253 ) + ); + XORCY \blk00000003/blk000000b0 ( + .CI(\blk00000003/sig0000024e ), + .LI(\blk00000003/sig0000024f ), + .O(\blk00000003/sig00000250 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig0000024d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig0000024c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e2 ), + .Q(\blk00000003/sig00000240 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024b ), + .Q(\blk00000003/sig00000233 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000249 ), + .Q(\blk00000003/sig0000024a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000248 ), + .Q(\blk00000003/sig00000231 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000247 ), + .Q(\blk00000003/sig0000023e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000245 ), + .Q(\blk00000003/sig00000246 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000243 ), + .Q(\blk00000003/sig00000244 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000241 ), + .Q(\blk00000003/sig00000242 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000240 ), + .Q(\blk00000003/sig0000023c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023e ), + .Q(\blk00000003/sig0000023f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023c ), + .Q(\blk00000003/sig0000023d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021d ), + .Q(\blk00000003/sig0000023b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000236 ), + .Q(\blk00000003/sig0000023a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000230 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a0_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022d ), + .R(coef_ld), + .Q(\blk00000003/sig0000022c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022a ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk0000009e_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000226 ), + .R(coef_ld), + .Q(\blk00000003/sig00000224 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000239 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000237 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000238 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000235 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000236 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000099 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000233 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000234 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000098 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000231 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000232 ) + ); + MUXCY_D \blk00000003/blk00000097 ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000228 ), + .LO(\blk00000003/sig00000230 ) + ); + MUXCY_D \blk00000003/blk00000096 ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022e ), + .O(\blk00000003/sig0000022b ), + .LO(\NLW_blk00000003/blk00000096_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000095 ( + .CI(\blk00000003/sig0000022b ), + .DI(\blk00000003/sig0000022c ), + .S(coef_we), + .O(\NLW_blk00000003/blk00000095_O_UNCONNECTED ), + .LO(\blk00000003/sig0000022d ) + ); + MUXCY_D \blk00000003/blk00000094 ( + .CI(\blk00000003/sig00000228 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000229 ), + .O(\NLW_blk00000003/blk00000094_O_UNCONNECTED ), + .LO(\blk00000003/sig0000022a ) + ); + MUXCY_D \blk00000003/blk00000093 ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000227 ), + .O(\blk00000003/sig00000223 ), + .LO(\NLW_blk00000003/blk00000093_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000092 ( + .CI(\blk00000003/sig00000223 ), + .DI(\blk00000003/sig00000224 ), + .S(\blk00000003/sig00000225 ), + .O(\NLW_blk00000003/blk00000092_O_UNCONNECTED ), + .LO(\blk00000003/sig00000226 ) + ); + XORCY \blk00000003/blk00000091 ( + .CI(\blk00000003/sig0000021c ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig0000021a ) + ); + MUXCY_D \blk00000003/blk00000090 ( + .CI(\blk00000003/sig00000220 ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig00000222 ), + .O(\NLW_blk00000003/blk00000090_O_UNCONNECTED ), + .LO(\blk00000003/sig0000021c ) + ); + MUXCY_D \blk00000003/blk0000008f ( + .CI(\blk00000003/sig0000021d ), + .DI(\blk00000003/sig0000021e ), + .S(\blk00000003/sig0000021f ), + .O(\blk00000003/sig00000220 ), + .LO(\NLW_blk00000003/blk0000008f_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000008e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021d ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000008d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021a ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000029 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e7 ), + .R(sclr), + .Q(\blk00000003/sig000001e6 ) + ); + FDR #( + .INIT ( 1'b1 )) + \blk00000003/blk00000028 ( + .C(clk), + .D(\blk00000003/sig000000b6 ), + .R(sclr), + .Q(\blk00000003/sig000000b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e6 ), + .R(sclr), + .Q(\blk00000003/sig000001e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e5 ), + .R(\blk00000003/sig000001e0 ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e3 ), + .R(sclr), + .Q(\blk00000003/sig000001e4 ) + ); + FDRE \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e1 ), + .R(sclr), + .Q(\blk00000003/sig000001e2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001df ), + .R(\blk00000003/sig000001e0 ), + .Q(rdy) + ); + FDSE \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001dd ), + .S(sclr), + .Q(\blk00000003/sig000001de ) + ); + FDRE \blk00000003/blk00000021 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001db ), + .R(sclr), + .Q(\blk00000003/sig000001dc ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000020 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cc ), + .S(sclr), + .Q(NlwRenamedSig_OI_rfd) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ca ), + .R(sclr), + .Q(\blk00000003/sig000001da ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d9 ), + .R(sclr), + .Q(\blk00000003/sig000001c7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001c6 ), + .R(sclr), + .Q(\blk00000003/sig000001d8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d7 ), + .R(sclr), + .Q(\blk00000003/sig000001c4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d5 ), + .R(sclr), + .Q(\blk00000003/sig000001d6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d3 ), + .R(sclr), + .Q(\blk00000003/sig000001d4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000019 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d1 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000019_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000018 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d1 ), + .R(sclr), + .Q(\blk00000003/sig000001d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000017 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cf ), + .Q(\blk00000003/sig000001d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000016 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ce ), + .Q(\blk00000003/sig000001cf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000015 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c0 ), + .R(sclr), + .Q(\blk00000003/sig000000be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000014 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000bb ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000014_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000013 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000bc ), + .S(sclr), + .Q(\blk00000003/sig000001cd ) + ); + MUXCY \blk00000003/blk00000012 ( + .CI(\blk00000003/sig000001c9 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig000001cb ), + .O(\blk00000003/sig000001cc ) + ); + MUXCY_D \blk00000003/blk00000011 ( + .CI(\blk00000003/sig000001c7 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001c8 ), + .O(\blk00000003/sig000001c9 ), + .LO(\blk00000003/sig000001ca ) + ); + MUXCY_D \blk00000003/blk00000010 ( + .CI(\blk00000003/sig000001c4 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001c5 ), + .O(\NLW_blk00000003/blk00000010_O_UNCONNECTED ), + .LO(\blk00000003/sig000001c6 ) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk0000000f ( + .PATTERNBDETECT(\NLW_blk00000003/blk0000000f_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk0000000f_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk0000000f_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk0000000f_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk0000000f_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk0000000f_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk0000000f_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b0 , \blk00000003/sig00000049 , \blk00000003/sig000000b4 , +\blk00000003/sig000000b2 , \blk00000003/sig000000b4 }), + .PCIN({\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , +\blk00000003/sig00000156 , \blk00000003/sig00000157 , \blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , +\blk00000003/sig0000015b , \blk00000003/sig0000015c , \blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , +\blk00000003/sig00000160 , \blk00000003/sig00000161 , \blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , +\blk00000003/sig00000165 , \blk00000003/sig00000166 , \blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , +\blk00000003/sig0000016a , \blk00000003/sig0000016b , \blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , +\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk0000000f_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000f_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000f_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , +\blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , \blk00000003/sig000000fb , +\blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , +\blk00000003/sig00000101 , \blk00000003/sig00000102 , \blk00000003/sig00000103 }), + .BCOUT({\NLW_blk00000003/blk0000000f_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\blk00000003/sig0000017c , \blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , \blk00000003/sig00000180 , +\blk00000003/sig00000181 , \blk00000003/sig00000182 , \blk00000003/sig00000183 , \blk00000003/sig00000184 , \blk00000003/sig00000185 , +\blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , \blk00000003/sig0000018a , +\blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , \blk00000003/sig0000018f , +\blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , \blk00000003/sig00000194 , +\blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , \blk00000003/sig00000199 , +\blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , \blk00000003/sig0000019e , +\blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , \blk00000003/sig000001a3 , +\blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 , \blk00000003/sig000001a8 , +\blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab }), + .A({\blk00000003/sig000001ac , \blk00000003/sig000001ac , \blk00000003/sig000001ac , \blk00000003/sig000001ac , \blk00000003/sig000001ac , +\blk00000003/sig000001ac , \blk00000003/sig000001ac , \blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af , +\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 , \blk00000003/sig000001c2 , \blk00000003/sig000001c3 }), + .PCOUT({\NLW_blk00000003/blk0000000f_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk0000000e ( + .PATTERNBDETECT(\NLW_blk00000003/blk0000000e_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk0000000e_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk0000000e_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk0000000e_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk0000000e_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk0000000e_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk0000000e_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b0 , \blk00000003/sig00000049 , \blk00000003/sig000000b4 , +\blk00000003/sig000000b2 , \blk00000003/sig000000b4 }), + .PCIN({\blk00000003/sig000000c2 , \blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , +\blk00000003/sig000000c7 , \blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , +\blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , +\blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , +\blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , +\blk00000003/sig000000db , \blk00000003/sig000000dc , \blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , +\blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , +\blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , +\blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , +\blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk0000000e_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000e_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000e_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , +\blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , \blk00000003/sig000000fb , +\blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , +\blk00000003/sig00000101 , \blk00000003/sig00000102 , \blk00000003/sig00000103 }), + .BCOUT({\NLW_blk00000003/blk0000000e_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , \blk00000003/sig00000107 , \blk00000003/sig00000108 , +\blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b , \blk00000003/sig0000010c , \blk00000003/sig0000010d , +\blk00000003/sig0000010e , \blk00000003/sig0000010f , \blk00000003/sig00000110 , \blk00000003/sig00000111 , \blk00000003/sig00000112 , +\blk00000003/sig00000113 , \blk00000003/sig00000114 , \blk00000003/sig00000115 , \blk00000003/sig00000116 , \blk00000003/sig00000117 , +\blk00000003/sig00000118 , \blk00000003/sig00000119 , \blk00000003/sig0000011a , \blk00000003/sig0000011b , \blk00000003/sig0000011c , +\blk00000003/sig0000011d , \blk00000003/sig0000011e , \blk00000003/sig0000011f , \blk00000003/sig00000120 , \blk00000003/sig00000121 , +\blk00000003/sig00000122 , \blk00000003/sig00000123 , \blk00000003/sig00000124 , \blk00000003/sig00000125 , \blk00000003/sig00000126 , +\blk00000003/sig00000127 , \blk00000003/sig00000128 , \blk00000003/sig00000129 , \blk00000003/sig0000012a , \blk00000003/sig0000012b , +\blk00000003/sig0000012c , \blk00000003/sig0000012d , \blk00000003/sig0000012e , \blk00000003/sig0000012f , \blk00000003/sig00000130 , +\blk00000003/sig00000131 , \blk00000003/sig00000132 , \blk00000003/sig00000133 }), + .A({\blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , +\blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000135 , \blk00000003/sig00000136 , \blk00000003/sig00000137 , +\blk00000003/sig00000138 , \blk00000003/sig00000139 , \blk00000003/sig0000013a , \blk00000003/sig0000013b , \blk00000003/sig0000013c , +\blk00000003/sig0000013d , \blk00000003/sig0000013e , \blk00000003/sig0000013f , \blk00000003/sig00000140 , \blk00000003/sig00000141 , +\blk00000003/sig00000142 , \blk00000003/sig00000143 , \blk00000003/sig00000144 , \blk00000003/sig00000145 , \blk00000003/sig00000146 , +\blk00000003/sig00000147 , \blk00000003/sig00000148 , \blk00000003/sig00000149 , \blk00000003/sig0000014a , \blk00000003/sig0000014b }), + .PCOUT({\NLW_blk00000003/blk0000000e_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + MUXCY_D \blk00000003/blk0000000d ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000c1 ), + .O(\blk00000003/sig000000bd ), + .LO(\NLW_blk00000003/blk0000000d_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000000c ( + .CI(\blk00000003/sig000000bd ), + .DI(\blk00000003/sig000000be ), + .S(\blk00000003/sig000000bf ), + .O(\blk00000003/sig000000b5 ), + .LO(\blk00000003/sig000000c0 ) + ); + XORCY \blk00000003/blk0000000b ( + .CI(\blk00000003/sig000000bb ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig000000bc ) + ); + MUXCY_D \blk00000003/blk0000000a ( + .CI(\blk00000003/sig000000b8 ), + .DI(\blk00000003/sig000000b9 ), + .S(\blk00000003/sig000000ba ), + .O(\NLW_blk00000003/blk0000000a_O_UNCONNECTED ), + .LO(\blk00000003/sig000000bb ) + ); + MUXCY_D \blk00000003/blk00000009 ( + .CI(\blk00000003/sig000000b5 ), + .DI(\blk00000003/sig000000b6 ), + .S(\blk00000003/sig000000b7 ), + .O(\blk00000003/sig000000b8 ), + .LO(\NLW_blk00000003/blk00000009_LO_UNCONNECTED ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000008 ( + .C(clk), + .D(\blk00000003/sig000000b3 ), + .Q(\blk00000003/sig000000b4 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000007 ( + .C(clk), + .D(\blk00000003/sig000000b1 ), + .Q(\blk00000003/sig000000b2 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000006 ( + .C(clk), + .D(\blk00000003/sig000000af ), + .Q(\blk00000003/sig000000b0 ) + ); + VCC \blk00000003/blk00000005 ( + .P(\blk00000003/sig000000ae ) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000002a/blk0000008c ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk0000002a/sig000006fd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000008b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006fb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000008a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006fa ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000089 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006fc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000088 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000087 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000086 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000085 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000084 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000083 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000082 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000081 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000080 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ef ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ee ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ec ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006eb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ed ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000079 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000078 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000077 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ea ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000076 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000075 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000074 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000073 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000072 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000071 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000070 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006df ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006dd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006dc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006de ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006da ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000069 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000068 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006db ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000067 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000066 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000066_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000065 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000065_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000064 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000064_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000063 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000063_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000062 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000062_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000061 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000061_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000060 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000060_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000005f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000005f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000005e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000005e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ce ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000005d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000005d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006cd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000005c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000005c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006fc ), + .Q(\blk00000003/sig000001ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006fb ), + .Q(\blk00000003/sig000001eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006fa ), + .Q(\blk00000003/sig000001ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f9 ), + .Q(\blk00000003/sig000001ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f8 ), + .Q(\blk00000003/sig000001ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f7 ), + .Q(\blk00000003/sig000001ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f6 ), + .Q(\blk00000003/sig000001f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f5 ), + .Q(\blk00000003/sig000001f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f4 ), + .Q(\blk00000003/sig000001f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f3 ), + .Q(\blk00000003/sig000001f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f2 ), + .Q(\blk00000003/sig000001f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f1 ), + .Q(\blk00000003/sig000001f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f0 ), + .Q(\blk00000003/sig000001f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ef ), + .Q(\blk00000003/sig000001f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ee ), + .Q(\blk00000003/sig000001f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ed ), + .Q(\blk00000003/sig000001f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ec ), + .Q(\blk00000003/sig000001fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006eb ), + .Q(\blk00000003/sig000001fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ea ), + .Q(\blk00000003/sig000001fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e9 ), + .Q(\blk00000003/sig000001fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e8 ), + .Q(\blk00000003/sig000001fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e7 ), + .Q(\blk00000003/sig000001ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e6 ), + .Q(\blk00000003/sig00000200 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e5 ), + .Q(\blk00000003/sig00000201 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e4 ), + .Q(\blk00000003/sig00000202 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e3 ), + .Q(\blk00000003/sig00000203 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e2 ), + .Q(\blk00000003/sig00000204 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e1 ), + .Q(\blk00000003/sig00000205 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e0 ), + .Q(\blk00000003/sig00000206 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006df ), + .Q(\blk00000003/sig00000207 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006de ), + .Q(\blk00000003/sig00000208 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006dd ), + .Q(\blk00000003/sig00000209 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006dc ), + .Q(\blk00000003/sig0000020a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006db ), + .Q(\blk00000003/sig0000020b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006da ), + .Q(\blk00000003/sig0000020c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d9 ), + .Q(\blk00000003/sig0000020d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d8 ), + .Q(\blk00000003/sig0000020e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000036 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d7 ), + .Q(\blk00000003/sig0000020f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000035 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d6 ), + .Q(\blk00000003/sig00000210 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000034 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d5 ), + .Q(\blk00000003/sig00000211 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d4 ), + .Q(\blk00000003/sig00000212 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d3 ), + .Q(\blk00000003/sig00000213 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d2 ), + .Q(\blk00000003/sig00000214 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d1 ), + .Q(\blk00000003/sig00000215 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d0 ), + .Q(\blk00000003/sig00000216 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006cf ), + .Q(\blk00000003/sig00000217 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000002d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ce ), + .Q(\blk00000003/sig00000218 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000002c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006cd ), + .Q(\blk00000003/sig00000219 ) + ); + GND \blk00000003/blk0000002a/blk0000002b ( + .G(\blk00000003/blk0000002a/sig000006cc ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000119/blk0000014b ( + .I0(ce), + .I1(\blk00000003/sig00000435 ), + .O(\blk00000003/blk00000119/sig0000074d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000014a ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f5 ), + .Q(\blk00000003/blk00000119/sig0000074b ), + .Q15(\NLW_blk00000003/blk00000119/blk0000014a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000149 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f6 ), + .Q(\blk00000003/blk00000119/sig0000074a ), + .Q15(\NLW_blk00000003/blk00000119/blk00000149_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000148 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f4 ), + .Q(\blk00000003/blk00000119/sig0000074c ), + .Q15(\NLW_blk00000003/blk00000119/blk00000148_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000147 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f8 ), + .Q(\blk00000003/blk00000119/sig00000748 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000147_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000146 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f9 ), + .Q(\blk00000003/blk00000119/sig00000747 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000146_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000145 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f7 ), + .Q(\blk00000003/blk00000119/sig00000749 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000145_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000144 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fb ), + .Q(\blk00000003/blk00000119/sig00000745 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000144_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000143 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fc ), + .Q(\blk00000003/blk00000119/sig00000744 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000143_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000142 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fa ), + .Q(\blk00000003/blk00000119/sig00000746 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000142_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000141 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fe ), + .Q(\blk00000003/blk00000119/sig00000742 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000141_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000140 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002ff ), + .Q(\blk00000003/blk00000119/sig00000741 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000140_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013f ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fd ), + .Q(\blk00000003/blk00000119/sig00000743 ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013e ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000301 ), + .Q(\blk00000003/blk00000119/sig0000073f ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013d ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000302 ), + .Q(\blk00000003/blk00000119/sig0000073e ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013c ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000300 ), + .Q(\blk00000003/blk00000119/sig00000740 ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013b ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000304 ), + .Q(\blk00000003/blk00000119/sig0000073c ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013a ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000305 ), + .Q(\blk00000003/blk00000119/sig0000073b ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000139 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000303 ), + .Q(\blk00000003/blk00000119/sig0000073d ), + .Q15(\NLW_blk00000003/blk00000119/blk00000139_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000138 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000307 ), + .Q(\blk00000003/blk00000119/sig00000739 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000138_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000137 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000308 ), + .Q(\blk00000003/blk00000119/sig00000738 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000137_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000136 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000306 ), + .Q(\blk00000003/blk00000119/sig0000073a ), + .Q15(\NLW_blk00000003/blk00000119/blk00000136_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000135 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig0000030a ), + .Q(\blk00000003/blk00000119/sig00000736 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000135_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000134 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig0000030b ), + .Q(\blk00000003/blk00000119/sig00000735 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000134_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000133 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000309 ), + .Q(\blk00000003/blk00000119/sig00000737 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000133_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000132 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000074c ), + .Q(\blk00000003/sig000003c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000131 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000074b ), + .Q(\blk00000003/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000130 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000074a ), + .Q(\blk00000003/sig000003c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000749 ), + .Q(\blk00000003/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000748 ), + .Q(\blk00000003/sig000003ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000747 ), + .Q(\blk00000003/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000746 ), + .Q(\blk00000003/sig000003cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000745 ), + .Q(\blk00000003/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000744 ), + .Q(\blk00000003/sig000003ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000743 ), + .Q(\blk00000003/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000742 ), + .Q(\blk00000003/sig000003d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000741 ), + .Q(\blk00000003/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000740 ), + .Q(\blk00000003/sig000003d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073f ), + .Q(\blk00000003/sig000003d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073e ), + .Q(\blk00000003/sig000003d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073d ), + .Q(\blk00000003/sig000003d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073c ), + .Q(\blk00000003/sig000003d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000121 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073b ), + .Q(\blk00000003/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000120 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073a ), + .Q(\blk00000003/sig000003d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000739 ), + .Q(\blk00000003/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000738 ), + .Q(\blk00000003/sig000003da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000737 ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000736 ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000735 ), + .Q(\blk00000003/sig000003dd ) + ); + GND \blk00000003/blk00000119/blk0000011a ( + .G(\blk00000003/blk00000119/sig00000734 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000014c/blk0000017e ( + .I0(ce), + .I1(\blk00000003/sig0000042f ), + .O(\blk00000003/blk0000014c/sig0000079d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000017d ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043a ), + .Q(\blk00000003/blk0000014c/sig0000079b ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000017d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000017c ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043b ), + .Q(\blk00000003/blk0000014c/sig0000079a ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000017c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000017b ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000439 ), + .Q(\blk00000003/blk0000014c/sig0000079c ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000017b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000017a ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043d ), + .Q(\blk00000003/blk0000014c/sig00000798 ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000017a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000179 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043e ), + .Q(\blk00000003/blk0000014c/sig00000797 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000179_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000178 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043c ), + .Q(\blk00000003/blk0000014c/sig00000799 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000178_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000177 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000440 ), + .Q(\blk00000003/blk0000014c/sig00000795 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000177_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000176 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000441 ), + .Q(\blk00000003/blk0000014c/sig00000794 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000176_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000175 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043f ), + .Q(\blk00000003/blk0000014c/sig00000796 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000175_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000174 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000443 ), + .Q(\blk00000003/blk0000014c/sig00000792 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000173 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000444 ), + .Q(\blk00000003/blk0000014c/sig00000791 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000172 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000442 ), + .Q(\blk00000003/blk0000014c/sig00000793 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000172_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000171 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000446 ), + .Q(\blk00000003/blk0000014c/sig0000078f ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000171_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000170 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000447 ), + .Q(\blk00000003/blk0000014c/sig0000078e ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000170_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016f ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000445 ), + .Q(\blk00000003/blk0000014c/sig00000790 ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016e ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000449 ), + .Q(\blk00000003/blk0000014c/sig0000078c ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016d ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044a ), + .Q(\blk00000003/blk0000014c/sig0000078b ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016c ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000448 ), + .Q(\blk00000003/blk0000014c/sig0000078d ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016b ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044c ), + .Q(\blk00000003/blk0000014c/sig00000789 ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016a ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044d ), + .Q(\blk00000003/blk0000014c/sig00000788 ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000169 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044b ), + .Q(\blk00000003/blk0000014c/sig0000078a ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000169_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000168 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044f ), + .Q(\blk00000003/blk0000014c/sig00000786 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000168_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000167 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000450 ), + .Q(\blk00000003/blk0000014c/sig00000785 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000167_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000166 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044e ), + .Q(\blk00000003/blk0000014c/sig00000787 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000166_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000165 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000079c ), + .Q(\blk00000003/sig000003de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000164 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000079b ), + .Q(\blk00000003/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000079a ), + .Q(\blk00000003/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000799 ), + .Q(\blk00000003/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000161 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000798 ), + .Q(\blk00000003/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000160 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000797 ), + .Q(\blk00000003/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000796 ), + .Q(\blk00000003/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000795 ), + .Q(\blk00000003/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000794 ), + .Q(\blk00000003/sig000003e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000793 ), + .Q(\blk00000003/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000792 ), + .Q(\blk00000003/sig000003e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000791 ), + .Q(\blk00000003/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000159 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000790 ), + .Q(\blk00000003/sig000003ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000158 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078f ), + .Q(\blk00000003/sig000003eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000157 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078e ), + .Q(\blk00000003/sig000003ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000156 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078d ), + .Q(\blk00000003/sig000003ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000155 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078c ), + .Q(\blk00000003/sig000003ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000154 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078b ), + .Q(\blk00000003/sig000003ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000153 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078a ), + .Q(\blk00000003/sig000003f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000152 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000789 ), + .Q(\blk00000003/sig000003f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000151 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000788 ), + .Q(\blk00000003/sig000003f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000150 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000787 ), + .Q(\blk00000003/sig000003f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000014f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000786 ), + .Q(\blk00000003/sig000003f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000014e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000785 ), + .Q(\blk00000003/sig000003f5 ) + ); + GND \blk00000003/blk0000014c/blk0000014d ( + .G(\blk00000003/blk0000014c/sig00000784 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000017f/blk000001b1 ( + .I0(ce), + .I1(\blk00000003/sig00000435 ), + .O(\blk00000003/blk0000017f/sig000007ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001b0 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000355 ), + .Q(\blk00000003/blk0000017f/sig000007eb ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001af ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000356 ), + .Q(\blk00000003/blk0000017f/sig000007ea ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001ae ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000354 ), + .Q(\blk00000003/blk0000017f/sig000007ec ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001ad ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000358 ), + .Q(\blk00000003/blk0000017f/sig000007e8 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001ac ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000359 ), + .Q(\blk00000003/blk0000017f/sig000007e7 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001ab ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000357 ), + .Q(\blk00000003/blk0000017f/sig000007e9 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001aa ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035b ), + .Q(\blk00000003/blk0000017f/sig000007e5 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a9 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035c ), + .Q(\blk00000003/blk0000017f/sig000007e4 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a8 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035a ), + .Q(\blk00000003/blk0000017f/sig000007e6 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a7 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035e ), + .Q(\blk00000003/blk0000017f/sig000007e2 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a6 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035f ), + .Q(\blk00000003/blk0000017f/sig000007e1 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a5 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035d ), + .Q(\blk00000003/blk0000017f/sig000007e3 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a4 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000361 ), + .Q(\blk00000003/blk0000017f/sig000007df ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a3 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000362 ), + .Q(\blk00000003/blk0000017f/sig000007de ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a2 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000360 ), + .Q(\blk00000003/blk0000017f/sig000007e0 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a1 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000364 ), + .Q(\blk00000003/blk0000017f/sig000007dc ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a0 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000365 ), + .Q(\blk00000003/blk0000017f/sig000007db ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019f ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000363 ), + .Q(\blk00000003/blk0000017f/sig000007dd ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019e ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000367 ), + .Q(\blk00000003/blk0000017f/sig000007d9 ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019d ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000368 ), + .Q(\blk00000003/blk0000017f/sig000007d8 ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019c ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000366 ), + .Q(\blk00000003/blk0000017f/sig000007da ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019b ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000036a ), + .Q(\blk00000003/blk0000017f/sig000007d6 ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019a ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000036b ), + .Q(\blk00000003/blk0000017f/sig000007d5 ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk00000199 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000369 ), + .Q(\blk00000003/blk0000017f/sig000007d7 ), + .Q15(\NLW_blk00000003/blk0000017f/blk00000199_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000198 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007ec ), + .Q(\blk00000003/sig000003f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000197 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007eb ), + .Q(\blk00000003/sig000003f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000196 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007ea ), + .Q(\blk00000003/sig000003f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000195 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e9 ), + .Q(\blk00000003/sig000003f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000194 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e8 ), + .Q(\blk00000003/sig000003fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000193 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e7 ), + .Q(\blk00000003/sig000003fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000192 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e6 ), + .Q(\blk00000003/sig000003fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000191 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e5 ), + .Q(\blk00000003/sig000003fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000190 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e4 ), + .Q(\blk00000003/sig000003fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e3 ), + .Q(\blk00000003/sig000003ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e2 ), + .Q(\blk00000003/sig00000400 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e1 ), + .Q(\blk00000003/sig00000401 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e0 ), + .Q(\blk00000003/sig00000402 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007df ), + .Q(\blk00000003/sig00000403 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007de ), + .Q(\blk00000003/sig00000404 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000189 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007dd ), + .Q(\blk00000003/sig00000405 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000188 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007dc ), + .Q(\blk00000003/sig00000406 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000187 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007db ), + .Q(\blk00000003/sig00000407 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000186 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007da ), + .Q(\blk00000003/sig00000408 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000185 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d9 ), + .Q(\blk00000003/sig00000409 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000184 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d8 ), + .Q(\blk00000003/sig0000040a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000183 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d7 ), + .Q(\blk00000003/sig0000040b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000182 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d6 ), + .Q(\blk00000003/sig0000040c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000181 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d5 ), + .Q(\blk00000003/sig0000040d ) + ); + GND \blk00000003/blk0000017f/blk00000180 ( + .G(\blk00000003/blk0000017f/sig000007d4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001b2/blk000001e4 ( + .I0(ce), + .I1(\blk00000003/sig0000042f ), + .O(\blk00000003/blk000001b2/sig0000083d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001e3 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000452 ), + .Q(\blk00000003/blk000001b2/sig0000083b ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001e2 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000453 ), + .Q(\blk00000003/blk000001b2/sig0000083a ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001e1 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000451 ), + .Q(\blk00000003/blk000001b2/sig0000083c ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001e0 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000455 ), + .Q(\blk00000003/blk000001b2/sig00000838 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001df ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000456 ), + .Q(\blk00000003/blk000001b2/sig00000837 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001de ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000454 ), + .Q(\blk00000003/blk000001b2/sig00000839 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001dd ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000458 ), + .Q(\blk00000003/blk000001b2/sig00000835 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001dc ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000459 ), + .Q(\blk00000003/blk000001b2/sig00000834 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001db ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000457 ), + .Q(\blk00000003/blk000001b2/sig00000836 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001da ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045b ), + .Q(\blk00000003/blk000001b2/sig00000832 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d9 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045c ), + .Q(\blk00000003/blk000001b2/sig00000831 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d8 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045a ), + .Q(\blk00000003/blk000001b2/sig00000833 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d7 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045e ), + .Q(\blk00000003/blk000001b2/sig0000082f ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d6 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045f ), + .Q(\blk00000003/blk000001b2/sig0000082e ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d5 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045d ), + .Q(\blk00000003/blk000001b2/sig00000830 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d4 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000461 ), + .Q(\blk00000003/blk000001b2/sig0000082c ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d3 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000462 ), + .Q(\blk00000003/blk000001b2/sig0000082b ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d2 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000460 ), + .Q(\blk00000003/blk000001b2/sig0000082d ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d1 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000464 ), + .Q(\blk00000003/blk000001b2/sig00000829 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d0 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000465 ), + .Q(\blk00000003/blk000001b2/sig00000828 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001cf ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000463 ), + .Q(\blk00000003/blk000001b2/sig0000082a ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001ce ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000467 ), + .Q(\blk00000003/blk000001b2/sig00000826 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001cd ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000468 ), + .Q(\blk00000003/blk000001b2/sig00000825 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001cc ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000466 ), + .Q(\blk00000003/blk000001b2/sig00000827 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001cc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000083c ), + .Q(\blk00000003/sig0000040e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000083b ), + .Q(\blk00000003/sig0000040f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000083a ), + .Q(\blk00000003/sig00000410 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000839 ), + .Q(\blk00000003/sig00000411 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000838 ), + .Q(\blk00000003/sig00000412 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000837 ), + .Q(\blk00000003/sig00000413 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000836 ), + .Q(\blk00000003/sig00000414 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000835 ), + .Q(\blk00000003/sig00000415 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000834 ), + .Q(\blk00000003/sig00000416 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000833 ), + .Q(\blk00000003/sig00000417 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000832 ), + .Q(\blk00000003/sig00000418 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000831 ), + .Q(\blk00000003/sig00000419 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000830 ), + .Q(\blk00000003/sig0000041a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082f ), + .Q(\blk00000003/sig0000041b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082e ), + .Q(\blk00000003/sig0000041c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082d ), + .Q(\blk00000003/sig0000041d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082c ), + .Q(\blk00000003/sig0000041e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082b ), + .Q(\blk00000003/sig0000041f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082a ), + .Q(\blk00000003/sig00000420 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000829 ), + .Q(\blk00000003/sig00000421 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000828 ), + .Q(\blk00000003/sig00000422 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000827 ), + .Q(\blk00000003/sig00000423 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000826 ), + .Q(\blk00000003/sig00000424 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000825 ), + .Q(\blk00000003/sig00000425 ) + ); + GND \blk00000003/blk000001b2/blk000001b3 ( + .G(\blk00000003/blk000001b2/sig00000824 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001e5/blk00000217 ( + .I0(ce), + .I1(\blk00000003/sig00000434 ), + .O(\blk00000003/blk000001e5/sig0000088d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000216 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046a ), + .Q(\blk00000003/blk000001e5/sig0000088b ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000216_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000215 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046b ), + .Q(\blk00000003/blk000001e5/sig0000088a ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000215_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000214 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000469 ), + .Q(\blk00000003/blk000001e5/sig0000088c ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000214_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000213 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046d ), + .Q(\blk00000003/blk000001e5/sig00000888 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000213_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000212 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046e ), + .Q(\blk00000003/blk000001e5/sig00000887 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000212_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000211 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046c ), + .Q(\blk00000003/blk000001e5/sig00000889 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000211_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000210 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000470 ), + .Q(\blk00000003/blk000001e5/sig00000885 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000210_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020f ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000471 ), + .Q(\blk00000003/blk000001e5/sig00000884 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020e ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046f ), + .Q(\blk00000003/blk000001e5/sig00000886 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020d ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000473 ), + .Q(\blk00000003/blk000001e5/sig00000882 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020c ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000474 ), + .Q(\blk00000003/blk000001e5/sig00000881 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020b ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000472 ), + .Q(\blk00000003/blk000001e5/sig00000883 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020a ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000476 ), + .Q(\blk00000003/blk000001e5/sig0000087f ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000209 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000477 ), + .Q(\blk00000003/blk000001e5/sig0000087e ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000209_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000208 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000475 ), + .Q(\blk00000003/blk000001e5/sig00000880 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000208_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000207 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000479 ), + .Q(\blk00000003/blk000001e5/sig0000087c ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000207_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000206 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047a ), + .Q(\blk00000003/blk000001e5/sig0000087b ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000206_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000205 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000478 ), + .Q(\blk00000003/blk000001e5/sig0000087d ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000205_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000204 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047c ), + .Q(\blk00000003/blk000001e5/sig00000879 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000204_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000203 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047d ), + .Q(\blk00000003/blk000001e5/sig00000878 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000203_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000202 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047b ), + .Q(\blk00000003/blk000001e5/sig0000087a ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000202_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000201 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047f ), + .Q(\blk00000003/blk000001e5/sig00000876 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000201_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000200 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000480 ), + .Q(\blk00000003/blk000001e5/sig00000875 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000200_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk000001ff ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047e ), + .Q(\blk00000003/blk000001e5/sig00000877 ), + .Q15(\NLW_blk00000003/blk000001e5/blk000001ff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000088c ), + .Q(\blk00000003/sig000002f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000088b ), + .Q(\blk00000003/sig000002f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000088a ), + .Q(\blk00000003/sig000002f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000889 ), + .Q(\blk00000003/sig000002f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000888 ), + .Q(\blk00000003/sig000002f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000887 ), + .Q(\blk00000003/sig000002f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000886 ), + .Q(\blk00000003/sig000002fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000885 ), + .Q(\blk00000003/sig000002fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000884 ), + .Q(\blk00000003/sig000002fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000883 ), + .Q(\blk00000003/sig000002fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000882 ), + .Q(\blk00000003/sig000002fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000881 ), + .Q(\blk00000003/sig000002ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000880 ), + .Q(\blk00000003/sig00000300 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087f ), + .Q(\blk00000003/sig00000301 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087e ), + .Q(\blk00000003/sig00000302 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087d ), + .Q(\blk00000003/sig00000303 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087c ), + .Q(\blk00000003/sig00000304 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087b ), + .Q(\blk00000003/sig00000305 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087a ), + .Q(\blk00000003/sig00000306 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000879 ), + .Q(\blk00000003/sig00000307 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000878 ), + .Q(\blk00000003/sig00000308 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000877 ), + .Q(\blk00000003/sig00000309 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000876 ), + .Q(\blk00000003/sig0000030a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000875 ), + .Q(\blk00000003/sig0000030b ) + ); + GND \blk00000003/blk000001e5/blk000001e6 ( + .G(\blk00000003/blk000001e5/sig00000874 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000218/blk0000024a ( + .I0(ce), + .I1(\blk00000003/sig0000042e ), + .O(\blk00000003/blk00000218/sig000008dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000249 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000482 ), + .Q(\blk00000003/blk00000218/sig000008db ), + .Q15(\NLW_blk00000003/blk00000218/blk00000249_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000248 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000483 ), + .Q(\blk00000003/blk00000218/sig000008da ), + .Q15(\NLW_blk00000003/blk00000218/blk00000248_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000247 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000481 ), + .Q(\blk00000003/blk00000218/sig000008dc ), + .Q15(\NLW_blk00000003/blk00000218/blk00000247_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000246 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000485 ), + .Q(\blk00000003/blk00000218/sig000008d8 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000245 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000486 ), + .Q(\blk00000003/blk00000218/sig000008d7 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000244 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000484 ), + .Q(\blk00000003/blk00000218/sig000008d9 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000244_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000243 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000488 ), + .Q(\blk00000003/blk00000218/sig000008d5 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000243_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000242 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000489 ), + .Q(\blk00000003/blk00000218/sig000008d4 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000242_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000241 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000487 ), + .Q(\blk00000003/blk00000218/sig000008d6 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000241_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000240 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048b ), + .Q(\blk00000003/blk00000218/sig000008d2 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000240_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023f ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048c ), + .Q(\blk00000003/blk00000218/sig000008d1 ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023e ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048a ), + .Q(\blk00000003/blk00000218/sig000008d3 ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023d ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048e ), + .Q(\blk00000003/blk00000218/sig000008cf ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023c ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048f ), + .Q(\blk00000003/blk00000218/sig000008ce ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023b ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048d ), + .Q(\blk00000003/blk00000218/sig000008d0 ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023a ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000491 ), + .Q(\blk00000003/blk00000218/sig000008cc ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000239 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000492 ), + .Q(\blk00000003/blk00000218/sig000008cb ), + .Q15(\NLW_blk00000003/blk00000218/blk00000239_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000238 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000490 ), + .Q(\blk00000003/blk00000218/sig000008cd ), + .Q15(\NLW_blk00000003/blk00000218/blk00000238_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000237 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000494 ), + .Q(\blk00000003/blk00000218/sig000008c9 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000237_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000236 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000495 ), + .Q(\blk00000003/blk00000218/sig000008c8 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000236_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000235 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000493 ), + .Q(\blk00000003/blk00000218/sig000008ca ), + .Q15(\NLW_blk00000003/blk00000218/blk00000235_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000234 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000497 ), + .Q(\blk00000003/blk00000218/sig000008c6 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000234_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000233 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000498 ), + .Q(\blk00000003/blk00000218/sig000008c5 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000233_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000232 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000496 ), + .Q(\blk00000003/blk00000218/sig000008c7 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000232_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000231 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008dc ), + .Q(\blk00000003/sig0000030c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000230 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008db ), + .Q(\blk00000003/sig0000030d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008da ), + .Q(\blk00000003/sig0000030e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d9 ), + .Q(\blk00000003/sig0000030f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d8 ), + .Q(\blk00000003/sig00000310 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d7 ), + .Q(\blk00000003/sig00000311 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d6 ), + .Q(\blk00000003/sig00000312 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d5 ), + .Q(\blk00000003/sig00000313 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000229 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d4 ), + .Q(\blk00000003/sig00000314 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000228 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d3 ), + .Q(\blk00000003/sig00000315 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000227 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d2 ), + .Q(\blk00000003/sig00000316 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000226 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d1 ), + .Q(\blk00000003/sig00000317 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000225 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d0 ), + .Q(\blk00000003/sig00000318 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000224 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008cf ), + .Q(\blk00000003/sig00000319 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000223 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008ce ), + .Q(\blk00000003/sig0000031a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000222 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008cd ), + .Q(\blk00000003/sig0000031b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000221 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008cc ), + .Q(\blk00000003/sig0000031c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000220 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008cb ), + .Q(\blk00000003/sig0000031d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008ca ), + .Q(\blk00000003/sig0000031e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c9 ), + .Q(\blk00000003/sig0000031f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c8 ), + .Q(\blk00000003/sig00000320 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c7 ), + .Q(\blk00000003/sig00000321 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c6 ), + .Q(\blk00000003/sig00000322 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c5 ), + .Q(\blk00000003/sig00000323 ) + ); + GND \blk00000003/blk00000218/blk00000219 ( + .G(\blk00000003/blk00000218/sig000008c4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000024b/blk0000027d ( + .I0(ce), + .I1(\blk00000003/sig00000434 ), + .O(\blk00000003/blk0000024b/sig0000092d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000027c ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049a ), + .Q(\blk00000003/blk0000024b/sig0000092b ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000027c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000027b ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049b ), + .Q(\blk00000003/blk0000024b/sig0000092a ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000027b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000027a ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig00000499 ), + .Q(\blk00000003/blk0000024b/sig0000092c ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000027a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000279 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049d ), + .Q(\blk00000003/blk0000024b/sig00000928 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000279_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000278 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049e ), + .Q(\blk00000003/blk0000024b/sig00000927 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000278_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000277 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049c ), + .Q(\blk00000003/blk0000024b/sig00000929 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000277_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000276 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a0 ), + .Q(\blk00000003/blk0000024b/sig00000925 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000276_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000275 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a1 ), + .Q(\blk00000003/blk0000024b/sig00000924 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000275_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000274 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049f ), + .Q(\blk00000003/blk0000024b/sig00000926 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000274_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000273 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a3 ), + .Q(\blk00000003/blk0000024b/sig00000922 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000273_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000272 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a4 ), + .Q(\blk00000003/blk0000024b/sig00000921 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000272_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000271 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a2 ), + .Q(\blk00000003/blk0000024b/sig00000923 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000271_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000270 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a6 ), + .Q(\blk00000003/blk0000024b/sig0000091f ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000270_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026f ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a7 ), + .Q(\blk00000003/blk0000024b/sig0000091e ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026e ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a5 ), + .Q(\blk00000003/blk0000024b/sig00000920 ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026d ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a9 ), + .Q(\blk00000003/blk0000024b/sig0000091c ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026c ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004aa ), + .Q(\blk00000003/blk0000024b/sig0000091b ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026b ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a8 ), + .Q(\blk00000003/blk0000024b/sig0000091d ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026a ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004ac ), + .Q(\blk00000003/blk0000024b/sig00000919 ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000269 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004ad ), + .Q(\blk00000003/blk0000024b/sig00000918 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000269_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000268 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004ab ), + .Q(\blk00000003/blk0000024b/sig0000091a ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000268_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000267 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004af ), + .Q(\blk00000003/blk0000024b/sig00000916 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000267_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000266 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004b0 ), + .Q(\blk00000003/blk0000024b/sig00000915 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000266_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000265 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004ae ), + .Q(\blk00000003/blk0000024b/sig00000917 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000265_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000264 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000092c ), + .Q(\blk00000003/sig00000354 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000263 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000092b ), + .Q(\blk00000003/sig00000355 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000262 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000092a ), + .Q(\blk00000003/sig00000356 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000261 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000929 ), + .Q(\blk00000003/sig00000357 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000260 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000928 ), + .Q(\blk00000003/sig00000358 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000927 ), + .Q(\blk00000003/sig00000359 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000926 ), + .Q(\blk00000003/sig0000035a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000925 ), + .Q(\blk00000003/sig0000035b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000924 ), + .Q(\blk00000003/sig0000035c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000923 ), + .Q(\blk00000003/sig0000035d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000922 ), + .Q(\blk00000003/sig0000035e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000921 ), + .Q(\blk00000003/sig0000035f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000920 ), + .Q(\blk00000003/sig00000360 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091f ), + .Q(\blk00000003/sig00000361 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000256 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091e ), + .Q(\blk00000003/sig00000362 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000255 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091d ), + .Q(\blk00000003/sig00000363 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000254 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091c ), + .Q(\blk00000003/sig00000364 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000253 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091b ), + .Q(\blk00000003/sig00000365 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000252 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091a ), + .Q(\blk00000003/sig00000366 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000251 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000919 ), + .Q(\blk00000003/sig00000367 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000250 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000918 ), + .Q(\blk00000003/sig00000368 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000024f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000917 ), + .Q(\blk00000003/sig00000369 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000024e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000916 ), + .Q(\blk00000003/sig0000036a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000024d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000915 ), + .Q(\blk00000003/sig0000036b ) + ); + GND \blk00000003/blk0000024b/blk0000024c ( + .G(\blk00000003/blk0000024b/sig00000914 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000027e/blk000002b0 ( + .I0(ce), + .I1(\blk00000003/sig0000042e ), + .O(\blk00000003/blk0000027e/sig0000097d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002af ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b2 ), + .Q(\blk00000003/blk0000027e/sig0000097b ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002ae ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b3 ), + .Q(\blk00000003/blk0000027e/sig0000097a ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002ad ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b1 ), + .Q(\blk00000003/blk0000027e/sig0000097c ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002ac ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b5 ), + .Q(\blk00000003/blk0000027e/sig00000978 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002ab ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b6 ), + .Q(\blk00000003/blk0000027e/sig00000977 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002aa ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b4 ), + .Q(\blk00000003/blk0000027e/sig00000979 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a9 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b8 ), + .Q(\blk00000003/blk0000027e/sig00000975 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a8 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b9 ), + .Q(\blk00000003/blk0000027e/sig00000974 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a7 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b7 ), + .Q(\blk00000003/blk0000027e/sig00000976 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a6 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004bb ), + .Q(\blk00000003/blk0000027e/sig00000972 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a5 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004bc ), + .Q(\blk00000003/blk0000027e/sig00000971 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a4 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004ba ), + .Q(\blk00000003/blk0000027e/sig00000973 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a3 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004be ), + .Q(\blk00000003/blk0000027e/sig0000096f ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a2 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004bf ), + .Q(\blk00000003/blk0000027e/sig0000096e ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a1 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004bd ), + .Q(\blk00000003/blk0000027e/sig00000970 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a0 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c1 ), + .Q(\blk00000003/blk0000027e/sig0000096c ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029f ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c2 ), + .Q(\blk00000003/blk0000027e/sig0000096b ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029e ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c0 ), + .Q(\blk00000003/blk0000027e/sig0000096d ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029d ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c4 ), + .Q(\blk00000003/blk0000027e/sig00000969 ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029c ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c5 ), + .Q(\blk00000003/blk0000027e/sig00000968 ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029b ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c3 ), + .Q(\blk00000003/blk0000027e/sig0000096a ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029a ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c7 ), + .Q(\blk00000003/blk0000027e/sig00000966 ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk00000299 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c8 ), + .Q(\blk00000003/blk0000027e/sig00000965 ), + .Q15(\NLW_blk00000003/blk0000027e/blk00000299_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk00000298 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c6 ), + .Q(\blk00000003/blk0000027e/sig00000967 ), + .Q15(\NLW_blk00000003/blk0000027e/blk00000298_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000297 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000097c ), + .Q(\blk00000003/sig0000036c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000296 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000097b ), + .Q(\blk00000003/sig0000036d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000295 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000097a ), + .Q(\blk00000003/sig0000036e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000294 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000979 ), + .Q(\blk00000003/sig0000036f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000293 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000978 ), + .Q(\blk00000003/sig00000370 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000292 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000977 ), + .Q(\blk00000003/sig00000371 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000291 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000976 ), + .Q(\blk00000003/sig00000372 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000290 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000975 ), + .Q(\blk00000003/sig00000373 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000974 ), + .Q(\blk00000003/sig00000374 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000973 ), + .Q(\blk00000003/sig00000375 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000972 ), + .Q(\blk00000003/sig00000376 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000971 ), + .Q(\blk00000003/sig00000377 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000970 ), + .Q(\blk00000003/sig00000378 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096f ), + .Q(\blk00000003/sig00000379 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000289 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096e ), + .Q(\blk00000003/sig0000037a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000288 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096d ), + .Q(\blk00000003/sig0000037b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000287 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096c ), + .Q(\blk00000003/sig0000037c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000286 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096b ), + .Q(\blk00000003/sig0000037d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000285 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096a ), + .Q(\blk00000003/sig0000037e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000284 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000969 ), + .Q(\blk00000003/sig0000037f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000283 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000968 ), + .Q(\blk00000003/sig00000380 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000282 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000967 ), + .Q(\blk00000003/sig00000381 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000281 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000966 ), + .Q(\blk00000003/sig00000382 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000280 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000965 ), + .Q(\blk00000003/sig00000383 ) + ); + GND \blk00000003/blk0000027e/blk0000027f ( + .G(\blk00000003/blk0000027e/sig00000964 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002b1/blk000002e9 ( + .I0(ce), + .I1(\blk00000003/sig00000234 ), + .O(\blk00000003/blk000002b1/sig000009e4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e8 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004c9 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009d1 ), + .DPO(\blk00000003/blk000002b1/sig000009e3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e7 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004ca ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009d0 ), + .DPO(\blk00000003/blk000002b1/sig000009e2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e6 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004cb ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009cf ), + .DPO(\blk00000003/blk000002b1/sig000009e1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e5 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004cc ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009ce ), + .DPO(\blk00000003/blk000002b1/sig000009e0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e4 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004cd ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009cd ), + .DPO(\blk00000003/blk000002b1/sig000009df ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e3 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004ce ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009cc ), + .DPO(\blk00000003/blk000002b1/sig000009de ) + ); + RAM32X1D #( + .INIT ( 32'h00000095 )) + \blk00000003/blk000002b1/blk000002e2 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d0 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009ca ), + .DPO(\blk00000003/blk000002b1/sig000009dc ) + ); + RAM32X1D #( + .INIT ( 32'h000000E5 )) + \blk00000003/blk000002b1/blk000002e1 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d1 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c9 ), + .DPO(\blk00000003/blk000002b1/sig000009db ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e0 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004cf ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009cb ), + .DPO(\blk00000003/blk000002b1/sig000009dd ) + ); + RAM32X1D #( + .INIT ( 32'h000000BD )) + \blk00000003/blk000002b1/blk000002df ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d2 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c8 ), + .DPO(\blk00000003/blk000002b1/sig000009da ) + ); + RAM32X1D #( + .INIT ( 32'h000000F1 )) + \blk00000003/blk000002b1/blk000002de ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d3 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c7 ), + .DPO(\blk00000003/blk000002b1/sig000009d9 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000B )) + \blk00000003/blk000002b1/blk000002dd ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d4 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c6 ), + .DPO(\blk00000003/blk000002b1/sig000009d8 ) + ); + RAM32X1D #( + .INIT ( 32'h000000DC )) + \blk00000003/blk000002b1/blk000002dc ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d5 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c5 ), + .DPO(\blk00000003/blk000002b1/sig000009d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000057 )) + \blk00000003/blk000002b1/blk000002db ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d6 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c4 ), + .DPO(\blk00000003/blk000002b1/sig000009d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000037 )) + \blk00000003/blk000002b1/blk000002da ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d7 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c3 ), + .DPO(\blk00000003/blk000002b1/sig000009d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000072 )) + \blk00000003/blk000002b1/blk000002d9 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d9 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c1 ), + .DPO(\blk00000003/blk000002b1/sig000009d3 ) + ); + RAM32X1D #( + .INIT ( 32'h000000A7 )) + \blk00000003/blk000002b1/blk000002d8 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004da ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c0 ), + .DPO(\blk00000003/blk000002b1/sig000009d2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000047 )) + \blk00000003/blk000002b1/blk000002d7 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d8 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c2 ), + .DPO(\blk00000003/blk000002b1/sig000009d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009e3 ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009e2 ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009e1 ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009e0 ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009df ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009de ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009dd ), + .Q(\blk00000003/sig000002e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009dc ), + .Q(\blk00000003/sig000002e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009db ), + .Q(\blk00000003/sig000002ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009da ), + .Q(\blk00000003/sig000002eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d9 ), + .Q(\blk00000003/sig000002ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d8 ), + .Q(\blk00000003/sig000002ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d7 ), + .Q(\blk00000003/sig000002ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d6 ), + .Q(\blk00000003/sig000002ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d5 ), + .Q(\blk00000003/sig000002f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d4 ), + .Q(\blk00000003/sig000002f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d3 ), + .Q(\blk00000003/sig000002f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d2 ), + .Q(\blk00000003/sig000002f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d1 ), + .Q(\blk00000003/sig000004db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d0 ), + .Q(\blk00000003/sig000004dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009cf ), + .Q(\blk00000003/sig000004dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009ce ), + .Q(\blk00000003/sig000004de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009cd ), + .Q(\blk00000003/sig000004df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009cc ), + .Q(\blk00000003/sig000004e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009cb ), + .Q(\blk00000003/sig000004e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009ca ), + .Q(\blk00000003/sig000004e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c9 ), + .Q(\blk00000003/sig000004e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c8 ), + .Q(\blk00000003/sig000004e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c7 ), + .Q(\blk00000003/sig000004e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c6 ), + .Q(\blk00000003/sig000004e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c5 ), + .Q(\blk00000003/sig000004e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c4 ), + .Q(\blk00000003/sig000004e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c3 ), + .Q(\blk00000003/sig000004e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c2 ), + .Q(\blk00000003/sig000004ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c1 ), + .Q(\blk00000003/sig000004eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c0 ), + .Q(\blk00000003/sig000004ec ) + ); + GND \blk00000003/blk000002b1/blk000002b2 ( + .G(\blk00000003/blk000002b1/sig000009bf ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002ea/blk00000310 ( + .I0(ce), + .I1(\blk00000003/sig0000042a ), + .O(\blk00000003/blk000002ea/sig00000a27 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002ea/blk0000030f ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004db ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a26 ) + ); + RAM32X1D #( + .INIT ( 32'h000000D5 )) + \blk00000003/blk000002ea/blk0000030e ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004dc ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a25 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002ea/blk0000030d ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004dd ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a24 ) + ); + RAM32X1D #( + .INIT ( 32'h00000095 )) + \blk00000003/blk000002ea/blk0000030c ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004de ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a23 ) + ); + RAM32X1D #( + .INIT ( 32'h00000025 )) + \blk00000003/blk000002ea/blk0000030b ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004df ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a22 ) + ); + RAM32X1D #( + .INIT ( 32'h00000079 )) + \blk00000003/blk000002ea/blk0000030a ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e0 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a21 ) + ); + RAM32X1D #( + .INIT ( 32'h000000FB )) + \blk00000003/blk000002ea/blk00000309 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e2 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000309_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1f ) + ); + RAM32X1D #( + .INIT ( 32'h00000056 )) + \blk00000003/blk000002ea/blk00000308 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e3 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000308_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1e ) + ); + RAM32X1D #( + .INIT ( 32'h0000002E )) + \blk00000003/blk000002ea/blk00000307 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e1 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000307_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a20 ) + ); + RAM32X1D #( + .INIT ( 32'h00000015 )) + \blk00000003/blk000002ea/blk00000306 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e4 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000306_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1d ) + ); + RAM32X1D #( + .INIT ( 32'h000000B2 )) + \blk00000003/blk000002ea/blk00000305 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e5 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000305_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1c ) + ); + RAM32X1D #( + .INIT ( 32'h0000009F )) + \blk00000003/blk000002ea/blk00000304 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e6 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000304_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1b ) + ); + RAM32X1D #( + .INIT ( 32'h000000CE )) + \blk00000003/blk000002ea/blk00000303 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e7 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000303_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1a ) + ); + RAM32X1D #( + .INIT ( 32'h000000C4 )) + \blk00000003/blk000002ea/blk00000302 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e8 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000302_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a19 ) + ); + RAM32X1D #( + .INIT ( 32'h00000094 )) + \blk00000003/blk000002ea/blk00000301 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e9 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000301_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a18 ) + ); + RAM32X1D #( + .INIT ( 32'h00000024 )) + \blk00000003/blk000002ea/blk00000300 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004eb ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000300_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a16 ) + ); + RAM32X1D #( + .INIT ( 32'h00000047 )) + \blk00000003/blk000002ea/blk000002ff ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004ec ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk000002ff_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a15 ) + ); + RAM32X1D #( + .INIT ( 32'h000000E6 )) + \blk00000003/blk000002ea/blk000002fe ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004ea ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk000002fe_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a17 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a26 ), + .Q(\blk00000003/sig000003b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a25 ), + .Q(\blk00000003/sig000003b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a24 ), + .Q(\blk00000003/sig000003b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a23 ), + .Q(\blk00000003/sig000003b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a22 ), + .Q(\blk00000003/sig000003b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a21 ), + .Q(\blk00000003/sig000003b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a20 ), + .Q(\blk00000003/sig000003ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1f ), + .Q(\blk00000003/sig000003bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1e ), + .Q(\blk00000003/sig000003bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1d ), + .Q(\blk00000003/sig000003bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1c ), + .Q(\blk00000003/sig000003be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1b ), + .Q(\blk00000003/sig000003bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1a ), + .Q(\blk00000003/sig000003c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a19 ), + .Q(\blk00000003/sig000003c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a18 ), + .Q(\blk00000003/sig000003c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a17 ), + .Q(\blk00000003/sig000003c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a16 ), + .Q(\blk00000003/sig000003c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a15 ), + .Q(\blk00000003/sig000003c5 ) + ); + GND \blk00000003/blk000002ea/blk000002eb ( + .G(\blk00000003/blk000002ea/sig00000a14 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000371/blk00000397 ( + .I0(ce), + .I1(\blk00000003/sig00000232 ), + .O(\blk00000003/blk00000371/sig00000a64 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000371/blk00000396 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004c9 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000396_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a63 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000395 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004ca ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000395_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a62 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000394 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004cb ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000394_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a61 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000393 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004cc ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000393_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a60 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000392 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004cd ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000392_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5f ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000391 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004ce ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000391_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5e ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000390 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d0 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000390_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5c ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038f ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d1 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5b ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038e ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004cf ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5d ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038d ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d2 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5a ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038c ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d3 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a59 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038b ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d4 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a58 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038a ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d5 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a57 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000389 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d6 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000389_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a56 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000388 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d7 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000388_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a55 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000387 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d9 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000387_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a53 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000386 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004da ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000386_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a52 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000385 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d8 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000385_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a54 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000384 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a63 ), + .Q(\blk00000003/sig000000f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000383 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a62 ), + .Q(\blk00000003/sig000000f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000382 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a61 ), + .Q(\blk00000003/sig000000f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000381 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a60 ), + .Q(\blk00000003/sig000000f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000380 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5f ), + .Q(\blk00000003/sig000000f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5e ), + .Q(\blk00000003/sig000000f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5d ), + .Q(\blk00000003/sig000000f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5c ), + .Q(\blk00000003/sig000000f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5b ), + .Q(\blk00000003/sig000000fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5a ), + .Q(\blk00000003/sig000000fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a59 ), + .Q(\blk00000003/sig000000fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000379 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a58 ), + .Q(\blk00000003/sig000000fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000378 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a57 ), + .Q(\blk00000003/sig000000fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000377 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a56 ), + .Q(\blk00000003/sig000000ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000376 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a55 ), + .Q(\blk00000003/sig00000100 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000375 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a54 ), + .Q(\blk00000003/sig00000101 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000374 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a53 ), + .Q(\blk00000003/sig00000102 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000373 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a52 ), + .Q(\blk00000003/sig00000103 ) + ); + GND \blk00000003/blk00000371/blk00000372 ( + .G(\blk00000003/blk00000371/sig00000a51 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/common/Makefile.srcs b/fpga/usrp3/top/n3xx/dboards/common/Makefile.srcs new file mode 100644 index 000000000..2439e8b40 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/Makefile.srcs @@ -0,0 +1,18 @@ +# +# Copyright 2018 Ettus Research, a National Instruments Company +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +################################################## +# DB COMMON Sources +################################################## +DB_COMMON_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/common/, \ +PkgRegs.vhd \ +sync/CrossTrigger.vhd \ +sync/Pulser.vhd \ +sync/TdcTop.vhd \ +sync/TdcWrapper.vhd \ +sync/TdcCore.edf \ +sync/SyncRegsIfc.edf \ +)) diff --git a/fpga/usrp3/top/n3xx/dboards/common/PkgRegs.vhd b/fpga/usrp3/top/n3xx/dboards/common/PkgRegs.vhd new file mode 100644 index 000000000..783e86e9c --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/PkgRegs.vhd @@ -0,0 +1,314 @@ +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- This package contains functions for reading and writing N310 registers. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + + +package PkgRegs is + + + -- RegPort Type Definitions : --------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + constant kAddressWidth : integer := 16; + + subtype InterfaceData_t is std_logic_vector(31 downto 0); + type RegDataAry_t is array (natural range <>) of InterfaceData_t; + constant kRegPortDataZero : InterfaceData_t := (others => '0'); + + -- The type of the signal used to communicate from the Interface + -- component to the frameworks + type RegPortIn_t is record + Address : unsigned(kAddressWidth - 1 downto 0); + Data : InterfaceData_t; + Rd : boolean; -- Must be a one clock cycle pulse + Wt : boolean; -- Must be a one clock cycle pulse + end record; + + -- The type of the signal used to communicate to the Interface + -- component from the frameworks + -- Ready is just the Ready signal from the Handshake component. + -- Address in RegPortIn_t should be valid in the cycle where Data, DataValid, + -- or Ready are being sampled by the bus communication interface. + type RegPortOut_t is record + Data : InterfaceData_t; + DataValid : boolean; -- Must be a one clock cycle pulse + Ready : boolean; -- Must be valid one clock after Wt assertion + end record; + + -- Constants for the RegPort + constant kRegPortInZero : RegPortIn_t := ( + Address => to_unsigned(0,kAddressWidth), + Data => (others => '0'), + Rd => false, + Wt => false); + + constant kRegPortOutZero : RegPortOut_t := ( + Data => (others=>'0'), + DataValid => false, + Ready => true); + + + + -- Register Offset Types : ------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + -- Custom type for defining register spaces. Is it assumed that all defined register + -- addresses for each space are kOffset <= Address < kOffset+kWidth. Therefore when + -- Address equals kOffset+kWidth, we are not talking to this space but the space + -- above it. + type RegOffset_t is record + kOffset : integer; + kWidth : integer; + end record; + + constant kRegOffsetZero : RegOffset_t := (kOffset => 16#0#, kWidth => 16#04#); + + + + -- Access Functions : ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + -- Helper function to combine register ports on their way back upstream. + function "+" (L, R : RegPortOut_t) return RegPortOut_t; + + function Mask(RegPortIn : in RegPortIn_t; + kRegisterOffset : in RegOffset_t) return RegPortIn_t; + + -- Helper functions to determine when a register is targeted by the RegPort. There + -- are three groups: RegSelected, RegWrite, and RegRead. The latter two call + -- RegSelected to determine if a register is targeted and being read or written. + -- RegSelected is also overloaded to accommodate the RegOffset_t type. + -- function RegSelected (RegPortIn : RegPortIn_t; + -- RegisterOffset : RegOffset_t) return boolean; + function RegSelected (RegOffset : integer; + RegPortIn : RegPortIn_t) return boolean; + function RegWrite (Address : integer; + RegPortIn : RegPortIn_t) return boolean; + function RegRead (Address : integer; + RegPortIn : RegPortIn_t) return boolean; + + function OrArray(ArrayIn : RegDataAry_t) return std_logic_vector; + + + + + -- Flattening Functions : ------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + constant kFlatRegPortInSize : natural := kAddressWidth + + InterfaceData_t'length + + 2; + + subtype FlatRegPortIn_t is std_logic_vector(kFlatRegPortInSize-1 downto 0); + + constant kFlatRegPortOutSize : natural := InterfaceData_t'length + + 2; + + subtype FlatRegPortOut_t is std_logic_vector(kFlatRegPortOutSize-1 downto 0); + + function Flatten(Var : RegPortIn_t) return FlatRegPortIn_t; + function Unflatten(Var : FlatRegPortIn_t) return RegPortIn_t; + + function Flatten(Var : RegPortOut_t) return FlatRegPortOut_t; + function Unflatten(Var : FlatRegPortOut_t) return RegPortOut_t; + + + + +end PkgRegs; + + +package body PkgRegs is + + -- Combines RegPortOut_t types together + function "+" (L, R : RegPortOut_t) return RegPortOut_t + is + variable ReturnVal : RegPortOut_t; + begin + ReturnVal := kRegPortOutZero; + ReturnVal.Data := L.Data or R.Data; + ReturnVal.DataValid := L.DataValid or R.DataValid; + ReturnVal.Ready := L.Ready and R.Ready; + return ReturnVal; + end function; + + + -- This function lops off the portion of the register bus that is + -- decoded in the InAddrSpace function in order to reduce the number of bits + -- decoded by the register read logic. Also, the Rd and Wt strobes are gated + -- as well. + function Mask(RegPortIn : in RegPortIn_t; + kRegisterOffset : in RegOffset_t) return RegPortIn_t + is + variable RegPortInVar : RegPortIn_t; + variable InSpace : boolean := false; + begin + + InSpace := (RegPortIn.Address >= kRegisterOffset.kOffset) and + (RegPortIn.Address < kRegisterOffset.kOffset + kRegisterOffset.kWidth); + + -- Compare the most significant bits of the address bus downto the LSb + -- that we just calculated. + if InSpace then + -- If in address space then allow Rd and Wt to assert + RegPortInVar.Rd := RegPortIn.Rd; + RegPortInVar.Wt := RegPortIn.Wt; + else + RegPortInVar.Rd := kRegPortInZero.Rd; + RegPortInVar.Wt := kRegPortInZero.Wt; + end if; + + RegPortInVar.Data := RegPortIn.Data; + RegPortInVar.Address := RegPortIn.Address - kRegisterOffset.kOffset; + return RegPortInVar; + end function Mask; + + + -- Returns true when this chip is selected and the address matches the register. + -- Note that RegOffset is divided by 4 before being compared against the register + -- port Address value. + function RegSelected (RegOffset : integer; + RegPortIn : RegPortIn_t) return boolean is + begin + return RegPortIn.Address = to_unsigned(RegOffset, RegPortIn.Address'length); + end function RegSelected; + + -- Returns true when the register is being written. + function RegWrite (Address : integer; + RegPortIn : RegPortIn_t) return boolean is + begin + return RegSelected(Address, RegPortIn) and RegPortIn.Wt; + end function RegWrite; + + -- Returns true when the register is being read. + function RegRead (Address : integer; + RegPortIn : RegPortIn_t) return boolean is + begin + return RegSelected(Address, RegPortIn) and RegPortIn.Rd; + end function RegRead; + + -- Overloaded version of RegSelected for the RegOffset_t + -- NOTE!!! Offset <= Address < Offset+Width + -- Therefore, this function assumes that when Address = Offset+Width we are talking to + -- a different register group than the one given in RegisterOffset. + -- function RegSelected (RegPortIn : RegPortIn_t; + -- RegisterOffset : RegOffset_t) return boolean is + -- begin + -- return (RegPortIn.Address >= to_unsigned(RegisterOffset.kOffset, RegPortIn.Address'length)) and + -- (RegPortIn.Address < to_unsigned(RegisterOffset.kOffset + RegisterOffset.kWidth, RegPortIn.Address'length)); + -- end function RegSelected; + + function OrArray(ArrayIn : RegDataAry_t) return std_logic_vector + is + variable ReturnVar : std_logic_vector(ArrayIn(ArrayIn'right)'range); + begin + ReturnVar := (others => '0'); + for i in ArrayIn'range loop + ReturnVar := ReturnVar or ArrayIn(i); + end loop; + return ReturnVar; + end function OrArray; + + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + + + ----------------------------------------------------- + -- REG PORTS (FROM PkgCommunicationInterface) + -- + -- subtype InterfaceData_t is std_logic_vector(31 downto 0); + -- + -- constant kAddressWidth : positive := kAddressWidth - 2; + -- + -- type RegPortIn_t is record + -- Address : unsigned(kAddressWidth - 1 downto 0); + -- Data : InterfaceData_t; + -- Rd : boolean; -- Must be a one clock cycle pulse + -- Wt : boolean; -- Must be a one clock cycle pulse + -- end record; + + function Flatten(Var : RegPortIn_t) return FlatRegPortIn_t is + variable Index : natural; + variable RetVar : FlatRegPortIn_t; + begin + Index := 0; + RetVar(Index) := to_StdLogic(Var.Wt); Index := Index + 1; + RetVar(Index) := to_StdLogic(Var.Rd); Index := Index + 1; + RetVar(Index + Var.Data'length - 1 downto Index) := std_logic_vector(Var.Data); + Index := Index + Var.Data'length; + RetVar(Index + Var.Address'length - 1 downto Index) := std_logic_vector(Var.Address); + Index := Index + Var.Address'length; + + return RetVar; + end function Flatten; + + function Unflatten(Var : FlatRegPortIn_t) return RegPortIn_t is + variable Index : natural; + variable RetVal : RegPortIn_t; + begin + Index := 0; + RetVal.Wt := to_Boolean(Var(Index)); Index := Index + 1; + RetVal.Rd := to_Boolean(Var(Index)); Index := Index + 1; + RetVal.Data := InterfaceData_t(Var(Index + RetVal.Data'length - 1 downto Index)); + Index := Index + RetVal.Data'length; + RetVal.Address := unsigned(Var(Index + RetVal.Address'length - 1 downto Index)); + Index := Index + RetVal.Address'length; + + return RetVal; + end function Unflatten; + + -- type RegPortOut_t is record + -- Data : InterfaceData_t; + -- DataValid : boolean; -- Must be a one clock cycle pulse + -- Ready : boolean; -- Must be valid one clock after Wt assertion + -- end record; + + function Flatten(Var : RegPortOut_t) return FlatRegPortOut_t is + variable Index : natural; + variable RetVar : FlatRegPortOut_t; + begin + Index := 0; + RetVar(Index) := to_StdLogic(Var.Ready); Index := Index + 1; + RetVar(Index) := to_StdLogic(Var.DataValid); Index := Index + 1; + RetVar(Index + Var.Data'length - 1 downto Index) := std_logic_vector(Var.Data); + Index := Index + Var.Data'length; + + return RetVar; + end function Flatten; + + function Unflatten(Var : FlatRegPortOut_t) return RegPortOut_t is + variable Index : natural; + variable RetVal : RegPortOut_t; + begin + Index := 0; + RetVal.Ready := to_Boolean(Var(Index)); Index := Index + 1; + RetVal.DataValid := to_Boolean(Var(Index)); Index := Index + 1; + RetVal.Data := InterfaceData_t(Var(Index + RetVal.Data'length - 1 downto Index)); + Index := Index + RetVal.Data'length; + + return RetVal; + end function Unflatten; + + + +end PkgRegs; diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/CrossTrigger.vhd b/fpga/usrp3/top/n3xx/dboards/common/sync/CrossTrigger.vhd new file mode 100644 index 000000000..70a873501 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/CrossTrigger.vhd @@ -0,0 +1,414 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- +-- Purpose: +-- +-- Uses the RP and SP edges to cross a trigger from the RefClk domain to +-- the SampleClk domain. The RP FE captures the input trigger and sends it to +-- the SampleClk domain. There, it is double-synchronized but only allowed to pass +-- when the SP RE occurs. The trigger (now in the SampleClk domain) is then passed +-- through an elastic buffer before being sent on it's merry way. +-- +-- Below is the latency through this module. If you assert rTriggerIn before or after +-- the rRP RE, then you need to add/subtract the distance to the rRP RE. +-- +-- Deterministic latency through this module is (starting at the rRP RE): +-- Measured difference between rRP and sSP rising edges (using a TDC, positive value +-- if rRP rises before sSP). +-- + One period of sSP +-- + Two periods of SampleClk (Double Sync) +-- + (sElasticBufferPtr value + 1) * SampleClk Period +-- + One period of SampleClk +-- +-- How much skew between RP and SP can we allow and still safely pass triggers? +-- Our "launch" edge is essentially the RP FE, and our "latch" edge is the SP RE. +-- Consider the no skew (RP and SP edges align) case first. Our setup and hold budget +-- is balanced at T/2. Based on this, it seems we can tolerate almost T/2 skew in either +-- direction (ignoring a few Reference and Sample Clock cycles here and there). +-- My recommendation is to keep the skew to a minimum, like less than T/4. +-- In the context of the FTDC project for N310, this should be a no-brainer since +-- the SP pulses are started only a few RefClk cycles after RP. The skew is +-- easily verified by taking a FTDC measurement. If the skew is less than T/4, you can +-- sleep easy. If not, then I recommend doing a comprehensive analysis of how much +-- settling time you have between the trigger being launched from the RefClk domain +-- and latched in the SampleClk domain. +-- +-- vreview_group Tdc +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library unisim; + use unisim.vcomponents.all; + + +entity CrossTrigger is + port ( + aReset : in boolean; + + RefClk : in std_logic; + -- For convenience while writing this, I have only considered the N3x0 case where + -- rRP is slightly ahead of sSP in phase. + rRP : in boolean; + -- De-asserts the clock cycle after rTriggerIn asserts. Re-asserts after the + -- second falling edge of rRP, indicating new triggers can be accepted. + rReadyForInput : out boolean; + -- Only one pulse will be output for each rising edge of rTriggerIn. rTriggerIn is + -- ignored when rReadyForInput is de-asserted. All levels are ignored when Enable + -- is de-asserted. + rEnableTrigger : in boolean; + rTriggerIn : in boolean; + + SampleClk : in std_logic; + sSP : in boolean; + -- An elastic buffer just before the output is used to compensate for skew + -- in sSP pulses across boards. Default should be in the middle of the 4 bit + -- range at 7. + sElasticBufferPtr : in unsigned(3 downto 0); + -- Single-cycle pulse output. + sTriggerOut : out boolean + ); +end CrossTrigger; + + +architecture rtl of CrossTrigger is + + --vhook_sigstart + --vhook_sigend + + signal rRpFE, + rRpDly, + rTriggerToSClk, + rTriggerCaptured, + sSpRE, + sSpDly : boolean; + + signal sTriggerBuffer : unsigned(2**sElasticBufferPtr'length-1 downto 0); + signal sTriggerInSClk, sTriggerInSClk_ms : boolean; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + attribute async_reg : string; + attribute async_reg of sTriggerInSClk : signal is "TRUE"; + attribute async_reg of sTriggerInSClk_ms : signal is "TRUE"; + +begin + + -- Reference Clock Domain Trigger Capture : ------------------------------------------- + -- The trigger input is captured whenever it is high. The captured value is reset + -- by the falling edge of rRP. + -- ------------------------------------------------------------------------------------ + + rRpFE <= rRpDly and not rRP; + + CaptureTrigger : process(aReset, RefClk) + begin + if aReset then + rTriggerCaptured <= false; + rRpDly <= false; + elsif rising_edge(RefClk) then + rRpDly <= rRP; + if not rEnableTrigger then + rTriggerCaptured <= false; + elsif rTriggerIn then + -- Capture trigger whenever the input is asserted (so this will work with single + -- cycle and multi-cycle pulses). + rTriggerCaptured <= true; + elsif rRpFE then + -- Reset the captured trigger one cycle after the rRP FE. + rTriggerCaptured <= false; + end if; + end if; + end process; + + + -- Send Trigger To Sample Clock Domain : ---------------------------------------------- + -- Send the captured trigger on the falling edge of rRP. + -- ------------------------------------------------------------------------------------ + SendTrigger : process(aReset, RefClk) + begin + if aReset then + rTriggerToSClk <= false; + elsif rising_edge(RefClk) then + if not rEnableTrigger then + rTriggerToSClk <= false; + elsif rRpFE then + rTriggerToSClk <= rTriggerCaptured; + end if; + end if; + end process; + + rReadyForInput <= not (rTriggerToSClk or rTriggerCaptured); + + -- Capture Trigger in Sample Clock Domain : ------------------------------------------- + -- On the rising edge of sSP, capture the trigger. To keep things free of + -- metastability, we double-sync the trigger into the SampleClk domain first. + -- ------------------------------------------------------------------------------------ + + ReceiveAndProcessTrigger : process(aReset, SampleClk) + begin + if aReset then + sSpDly <= false; + sTriggerBuffer <= (others => '0'); + sTriggerOut <= false; + sTriggerInSClk_ms <= false; + sTriggerInSClk <= false; + elsif rising_edge(SampleClk) then + -- Edge detector delays. + sSpDly <= sSP; + + -- Double-synchronizer for trigger. + sTriggerInSClk_ms <= rTriggerToSClk; + sTriggerInSClk <= sTriggerInSClk_ms; + + -- Delay chain for the elastic buffer. Move to the left people! Note that this + -- operation incurs at least one cycle of delay. Also note the trigger input is + -- gated with the SP RE. + sTriggerBuffer <= sTriggerBuffer(sTriggerBuffer'high-1 downto 0) & + to_stdlogic(sTriggerInSClk and sSpRE); + + -- Based on the buffer pointer value select and flop the output one more time. + sTriggerOut <= to_boolean(sTriggerBuffer(to_integer(sElasticBufferPtr))); + end if; + end process; + + -- Rising edge detectors. + sSpRE <= sSP and not sSpDly; + + +end rtl; + + + + + +-------------------------------------------------------------------------------- +-- Testbench for CrossTrigger +-- +-- Meh coverage on the triggers so far... but this tests general operation +-- and latency. +-------------------------------------------------------------------------------- + +--synopsys translate_off +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity tb_CrossTrigger is end tb_CrossTrigger; + +architecture test of tb_CrossTrigger is + + -- Sets up a 1.25 MHz period. + constant kClksPerPulseMaxBits: integer := 10; + constant kRpPeriodInRClks : integer := 8; + constant kRpHighTimeInRClks : integer := 4; + constant kSpPeriodInRClks : integer := 100; + constant kSpHighTimeInRClks : integer := 50; + + --vhook_sigstart + signal aReset: boolean; + signal RefClk: std_logic := '0'; + signal rEnablePulser: boolean; + signal rEnableTrigger: boolean; + signal rReadyForInput: boolean; + signal rRP: boolean; + signal rTriggerIn: boolean; + signal SampleClk: std_logic := '0'; + signal sElasticBufferPtr: unsigned(3 downto 0); + signal sEnablePulser: boolean; + signal sSP: boolean; + signal sTriggerOut: boolean; + --vhook_sigend + + signal StopSim : boolean; + -- shared variable Rand : Random_t; + constant kSPer : time := 8.000 ns; -- 125.00 MHz + constant kRPer : time := 100.000 ns; -- 10.00 MHz + + signal rRfiExpected: boolean:= true; + signal sTriggerOutExpected: boolean:= false; + + procedure ClkWait( + signal Clk : in std_logic; + X : positive := 1) is + begin + for i in 1 to X loop + wait until rising_edge(Clk); + end loop; + end procedure ClkWait; + +begin + + SampleClk <= not SampleClk after kSPer/2 when not StopSim else '0'; + RefClk <= not RefClk after kRPer/2 when not StopSim else '0'; + + --vhook_e Pulser RpPulser + --vhook_a Clk RefClk + --vhook_a cLoadLimits true + --vhook_a cPeriod to_unsigned(kRpPeriodInRClks,kClksPerPulseMaxBits) + --vhook_a cHighTime to_unsigned(kRpHighTimeInRClks,kClksPerPulseMaxBits) + --vhook_a cEnablePulse rEnablePulser + --vhook_a cPulse rRP + RpPulser: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => RefClk, --in std_logic + cLoadLimits => true, --in boolean + cPeriod => to_unsigned(kRpPeriodInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => to_unsigned(kRpHighTimeInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => rEnablePulser, --in boolean + cPulse => rRP); --out boolean + + --vhook_e Pulser SpPulser + --vhook_a Clk SampleClk + --vhook_a cLoadLimits true + --vhook_a cPeriod to_unsigned(kSpPeriodInRClks,kClksPerPulseMaxBits) + --vhook_a cHighTime to_unsigned(kSpHighTimeInRClks,kClksPerPulseMaxBits) + --vhook_a cEnablePulse sEnablePulser + --vhook_a cPulse sSP + SpPulser: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => SampleClk, --in std_logic + cLoadLimits => true, --in boolean + cPeriod => to_unsigned(kSpPeriodInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => to_unsigned(kSpHighTimeInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => sEnablePulser, --in boolean + cPulse => sSP); --out boolean + + + main: process + procedure SendTrigger is + begin + assert rReadyForInput + report "RFI isn't high, so we can't issue a trigger" severity error; + + -- Give it some action. We need to ideally test this for every phase offset of + -- rTriggerIn with respect to the rising edge of rRP, but let's get to that later. + -- For now, wait until a rising edge on rRP and then wait for most of the period + -- to issue the trigger. + wait until rRP and not rRP'delayed; + wait for (kRpPeriodInRClks-3)*kRPer; + rTriggerIn <= true; + ClkWait(RefClk); + rTriggerIn <= false; + rRfiExpected <= false; + + -- At this point, we wait until a sSP RE, plus two SampleClks, plus sElasticBufferPtr + -- plus 1 worth of SampleClks, plus one more SampleClk, and then the trigger + -- should appear. + wait until not rRP and rRP'delayed; + wait until sSP and not sSP'delayed; + ClkWait(SampleClk,1); + ClkWait(SampleClk, to_integer(sElasticBufferPtr)+1); + sTriggerOutExpected <= true; + ClkWait(SampleClk,1); + sTriggerOutExpected <= false; + wait until not rRP and rRP'delayed; + ClkWait(RefClk,1); + rRfiExpected <= true; + end procedure SendTrigger; + + begin + rEnablePulser <= false; + sEnablePulser <= false; + rEnableTrigger <= true; + sElasticBufferPtr <= to_unsigned(7, sElasticBufferPtr'length); + + aReset <= true, false after 10 ns; + ClkWait(RefClk,5); + + -- Start up the pulsers and ensure nothing comes out of the trigger for a while. + rEnablePulser <= true; + ClkWait(RefClk, 3); + ClkWait(SampleClk, 2); + sEnablePulser <= true; + + ClkWait(RefClk, kRpPeriodInRClks*5); + assert (not sTriggerOut) and sTriggerOut'stable(kRpPeriodInRClks*5*kRPer) + report "Rogue activity on sTriggerOut before rTriggerIn asserted!" severity error; + assert (rReadyForInput) and rReadyForInput'stable(kRpPeriodInRClks*5*kRPer) + report "Ready for Input was not high before trigger!" severity error; + + + SendTrigger; + + ClkWait(RefClk, kRpPeriodInRClks*5); + + SendTrigger; + + ClkWait(RefClk, kRpPeriodInRClks*5); + + -- Turn off the trigger enable and send a trigger. + rEnableTrigger <= false; + ClkWait(RefClk); + rTriggerIn <= true; + ClkWait(RefClk); + rTriggerIn <= false; + + -- And nothing should happen. + ClkWait(RefClk, kRpPeriodInRClks*5); + assert (not sTriggerOut) and sTriggerOut'stable(kRpPeriodInRClks*5*kRPer) + report "Rogue activity on sTriggerOut before rTriggerIn asserted!" severity error; + + + ClkWait(RefClk, kRpPeriodInRClks*5); + StopSim <= true; + wait; + end process; + + + CheckRfi : process(RefClk) + begin + if falling_edge(RefClk) then + assert rReadyForInput = rRfiExpected + report "RFI didn't match expected" severity error; + end if; + end process; + + CheckTrigOut : process(SampleClk) + begin + if falling_edge(SampleClk) then + assert sTriggerOut = sTriggerOutExpected + report "Trigger Out didn't match expected" severity error; + end if; + end process; + + + --vhook_e CrossTrigger dutx + dutx: entity work.CrossTrigger (rtl) + port map ( + aReset => aReset, --in boolean + RefClk => RefClk, --in std_logic + rRP => rRP, --in boolean + rReadyForInput => rReadyForInput, --out boolean + rEnableTrigger => rEnableTrigger, --in boolean + rTriggerIn => rTriggerIn, --in boolean + SampleClk => SampleClk, --in std_logic + sSP => sSP, --in boolean + sElasticBufferPtr => sElasticBufferPtr, --in unsigned(3:0) + sTriggerOut => sTriggerOut); --out boolean + + +end test; +--synopsys translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/Pulser.vhd b/fpga/usrp3/top/n3xx/dboards/common/sync/Pulser.vhd new file mode 100644 index 000000000..c6cb30f24 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/Pulser.vhd @@ -0,0 +1,362 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- +-- Purpose: +-- +-- The purpose of this module is to create a psuedo-clock "pulse" on the output +-- cPulse whenever cEnablePulse is asserted. +-- +-- The output period and high time are determined by the inputs cPeriod and +-- cHighTime, where cPeriod must be greater than cHighTime+2. When these values +-- are valid at the inputs, pulse cLoadLimits to load them into the pulser routine. +-- It is not recommended to leave cEnablePulse asserted when loading new limits. +-- +-- Dynamic period and duty cycle setup: +-- 1) Disable the pulser by de-asserting cEnablePulse. +-- 2) Load new period and duty cycle by modifying cPeriod and cHighTime. Pulse +-- cLoadLimits for at least one Clk cycle. +-- 3) Enable the pulser by asserting cEnablePulse. +-- 4) Repeat 1-3 as necessary. +-- +-- Static period and duty cycle setup: +-- 1) Tie cLoadLimits to asserted. +-- 2) Tie cPeriod and cHighTime to static values. +-- 3) Enable and disable the pulser by asserting and de-asserting cEnablePulser at will. +-- This input can also be tied asserted in this case. +-- +-- vreview_group Tdc +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +entity Pulser is + generic ( + -- The pulse counter is kClksPerPulseMaxBits wide. + -- Why 16? Then both cPeriod and cHighTime fit nicely into one 32 bit register! + -- Minimum of 3 to make our default values for cHighTime work out. + kClksPerPulseMaxBits : integer range 3 to 32 := 16 + ); + port ( + aReset : in boolean; + Clk : in std_logic; + + -- Pulse cLoadLimits when cPeriod and cHighTime are valid. Is it not recommended to + -- load new limits when the output is enabled. + -- Alternatively, cLoadLimits can be tied high if cPeriod and cHighTime are also + -- tied to static values. + cLoadLimits : in boolean; + cPeriod : in unsigned(kClksPerPulseMaxBits - 1 downto 0); + cHighTime : in unsigned(kClksPerPulseMaxBits - 1 downto 0); + + -- When cEnablePulse is de-asserted, cPulse idles low on the following cycle. + -- When asserted, cPulse will then assert within a few cycles. + -- This input can be tied high, if desired, and the pulses will start several + -- clock cycles after aReset de-assertion. + cEnablePulse : in boolean; + + -- When cEnablePulse is asserted, cPulse will produce a rising edge every + -- cPeriod of the Clk input and a falling edge cHighTime cycles after + -- the rising edge. + cPulse : out boolean + ); +end Pulser; + + +architecture rtl of Pulser is + + signal cCounter, + cPeriodStored, + cHighTimeStored : unsigned(cPeriod'range); + + signal cSafeToStart_ms, cSafeToStart, cSafeToStartDly : boolean; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of cSafeToStart_ms : signal is "true"; + attribute ASYNC_REG of cSafeToStart : signal is "true"; + +begin + + --synthesis translate_off + CheckInputRanges : process(Clk) + begin + if falling_edge(Clk) then + -- +2 since we have the output high offset from the zero of the counter + assert (cPeriodStored > cHighTimeStored + 2) + report "cPeriod is not greater than cHighTime + 2" severity error; + -- Ensure the high time is greater than 1... + assert (cHighTimeStored > 1) + report "cHighTime is not greater than 1" severity error; + end if; + end process; + --synthesis translate_on + + + -- ------------------------------------------------------------------------------------ + -- !!! SAFE COUNTER STARTUP !!! + -- This counter starts safely, meaning it cannot start counting immediately after + -- aReset de-assertion, because the counter cannot start until cSafeToStart asserts, + -- which cannot happen until 1-2 clock cycles after aReset de-assertion. + -- ------------------------------------------------------------------------------------ + CountFreqRefPeriod: process(aReset, Clk) + begin + if aReset then + cCounter <= (others => '0'); + cSafeToStart_ms <= false; + cSafeToStart <= false; + cSafeToStartDly <= false; + cPulse <= false; + cPeriodStored <= (others => '1'); + -- This is a rather arbitrary start value, but we are guaranteed that it is + -- less than the reset value of cPeriodStored as well as greater than 2, + -- so it works well enough in case the module isn't set up correctly. + cHighTimeStored <= to_unsigned(kClksPerPulseMaxBits+2,cHighTimeStored'length); + elsif rising_edge(Clk) then + -- Create a safe counter startup signal that asserts shortly after + -- aReset de-assertion. + cSafeToStart_ms <= true; + cSafeToStart <= cSafeToStart_ms; + -- In the case where cLoadLimits and cEnablePulse are tied high, we need to give + -- them one cycle to load before starting the counter, so we delay cSafeToStart + -- by one for the counter. + cSafeToStartDly <= cSafeToStart; + + if cEnablePulse and cSafeToStartDly then + -- Simple counter increment until ceiling reached, then roll over. + if cCounter >= cPeriodStored - 1 then + cCounter <= (others => '0'); + else + cCounter <= cCounter + 1; + end if; + + -- Pulse the output when counter is between 1 and cHighTimeStored. + if cCounter = 1 then + cPulse <= true; + elsif cCounter >= cHighTimeStored+1 then + cPulse <= false; + end if; + + else + cPulse <= false; + cCounter <= (others => '0'); + end if; + + if cLoadLimits and cSafeToStart then + cPeriodStored <= cPeriod; + cHighTimeStored <= cHighTime; + end if; + end if; + end process; + +end rtl; + + +-------------------------------------------------------------------------------- +-- Testbench for Pulser +-------------------------------------------------------------------------------- + +--synopsys translate_off +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +entity tb_Pulser is end tb_Pulser; + +architecture test of tb_Pulser is + + constant kClksPerPulseMaxBits : integer := 16; + + --vhook_sigstart + signal aReset: boolean; + signal cEnablePulse: boolean; + signal cHighTime: unsigned(kClksPerPulseMaxBits-1 downto 0); + signal Clk: std_logic := '0'; + signal cLoadLimits: boolean; + signal cPeriod: unsigned(kClksPerPulseMaxBits-1 downto 0); + signal cPulse: boolean; + signal cPulseDut2: boolean; + --vhook_sigend + + signal StopSim : boolean; + constant kPer : time := 10 ns; + + signal CheckPulse : boolean := false; + signal cPulseSl : std_logic := '0'; + signal cPulseDut2Sl : std_logic := '0'; + + procedure ClkWait(X : positive := 1) is + begin + for i in 1 to X loop + wait until rising_edge(Clk); + end loop; + end procedure ClkWait; + +begin + + Clk <= not Clk after kPer/2 when not StopSim else '0'; + + main: process + begin + cEnablePulse <= false; + aReset <= true, false after 10 ns; + ClkWait(5); + + -- Ensure the pulse is quiet for a while. + ClkWait(100); + assert cPulse'stable(kPer*100) and not cPulse + report "pulse not stable at false at startup" + severity error; + + + -- Set up, then enable the pulse; expect it to go high after a few cycles. + cPeriod <= to_unsigned(250,cPeriod'length); + cHighTime <= to_unsigned(100,cPeriod'length); + cLoadLimits <= true; + ClkWait; + cLoadLimits <= false; + cEnablePulse <= true; + ClkWait(2); -- pulse rises here + wait until falling_edge(Clk); + assert cPulse report "cPulse not high two cycles after enabling" severity error; + -- After another clock cycle the checker below should be primed, so we can enable it. + ClkWait; + CheckPulse <= true; + ClkWait(to_integer(cHighTime)-1); + wait until falling_edge(Clk); + assert not cPulse report "Pulse not low after high requirement" severity error; + + -- Check the pulse high and low for a few cycles (duplicated below, but this also + -- checks that it actually is toggling). + for i in 0 to 100 loop + ClkWait(to_integer(cPeriod) - to_integer(cHighTime)); + wait until falling_edge(Clk); + assert cPulse report "Pulse not high when expected" severity error; + ClkWait(to_integer(cHighTime)); + wait until falling_edge(Clk); + assert not cPulse report "Pulse not low after high requirement" severity error; + end loop; + + -- Disable pulse, and check that it goes away for a long time + cEnablePulse <= false; + CheckPulse <= false; + -- 2 is about the max time for it to go away. + ClkWait(2); + ClkWait(2**kClksPerPulseMaxBits); + assert (not cPulse) and cPulse'stable(2**kClksPerPulseMaxBits*kPer) + report "disable didn't work" severity error; + + + -- Re-do all the initial tests with different periods and such. + + -- Enable the pulse, expect it to go high after a few cycles + cPeriod <= to_unsigned(10,cPeriod'length); + cHighTime <= to_unsigned(5,cPeriod'length); + cLoadLimits <= true; + ClkWait; + cLoadLimits <= false; + cEnablePulse <= true; + ClkWait(2); -- pulse rises here + wait until falling_edge(Clk); + assert cPulse report "cPulse not high two cycles after enabling" severity error; + -- After another clock cycle the checker below should be primed, so we can enable it. + ClkWait; + CheckPulse <= true; + ClkWait(to_integer(cHighTime)-1); + wait until falling_edge(Clk); + assert not cPulse report "Pulse not low after high requirement" severity error; + + -- Check the pulse high and low for a few cycles (duplicated below, but this also + -- checks that it actually is toggling). + for i in 0 to 100 loop + ClkWait(to_integer(cPeriod) - to_integer(cHighTime)); + wait until falling_edge(Clk); + assert cPulse report "Pulse not high when expected" severity error; + ClkWait(to_integer(cHighTime)); + wait until falling_edge(Clk); + assert not cPulse report "Pulse not low after high requirement" severity error; + end loop; + + ClkWait(100); + + + StopSim <= true; + wait; + end process; + + cPulseSl <= '1' when cPulse else '0'; + + -- Test the period and duty cycle of the pulse. + CheckPulseSpecs : process(cPulseSl) + variable LastRise : time := 0 ns; + begin + if falling_edge(cPulseSl) then + assert (not CheckPulse) or (now - LastRise = kPer*to_integer(cHighTime)) + report "High cycles requirement not met" severity error; + elsif rising_edge(cPulseSl) then + assert (not CheckPulse) or (now - LastRise = kPer*to_integer(cPeriod)) + report "Period requirement not met" & LF & + "Act: " & time'image(now-LastRise) & LF & + "Req: " & time'image(kPer*to_integer(cPeriod)) + severity error; + LastRise := now; + end if; + end process; + + --vhook_e Pulser dutx + dutx: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => Clk, --in std_logic + cLoadLimits => cLoadLimits, --in boolean + cPeriod => cPeriod, --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => cHighTime, --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => cEnablePulse, --in boolean + cPulse => cPulse); --out boolean + + + --vhook_e Pulser dut2 + --vhook_a cLoadLimits true + --vhook_a cPeriod to_unsigned(5,kClksPerPulseMaxBits) + --vhook_a cHighTime to_unsigned(2,kClksPerPulseMaxBits) + --vhook_a cEnablePulse true + --vhook_a cPulse cPulseDut2 + dut2: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => Clk, --in std_logic + cLoadLimits => true, --in boolean + cPeriod => to_unsigned(5,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => to_unsigned(2,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => true, --in boolean + cPulse => cPulseDut2); --out boolean + + cPulseDut2Sl <= '1' when cPulseDut2 else '0'; + + CheckDut2 : process (cPulseDut2Sl) + variable LastRise : time := 0 ns; + begin + if falling_edge(cPulseDut2Sl) then + assert (not CheckPulse) or (now - LastRise = kPer*2) + report "DUT 2 High cycles requirement not met" severity error; + elsif rising_edge(cPulseDut2Sl) then + assert (not CheckPulse) or (now - LastRise = kPer*5) + report "DUT 2 Period requirement not met" & LF & + "Act: " & time'image(now-LastRise) & LF & + "Req: " & time'image(kPer*5) + severity error; + LastRise := now; + end if; + end process; + + +end test; +--synopsys translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/SyncRegsIfc.edf b/fpga/usrp3/top/n3xx/dboards/common/sync/SyncRegsIfc.edf new file mode 100644 index 000000000..a3886f6d4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/SyncRegsIfc.edf @@ -0,0 +1,23420 @@ +(edif SyncRegsIfc + (edifversion 2 0 0) + (edifLevel 0) + (keywordmap (keywordlevel 0)) +(status + (written + (timeStamp 2018 03 16 14 23 36) + (program "Vivado" (version "2017.4")) + (comment "Built on 'Fri Dec 15 20:55:39 MST 2017'") + (comment "Built by 'xbuild'") + ) +) + (Library hdi_primitives + (edifLevel 0) + (technology (numberDefinition )) + (cell LUT3 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + ) + ) + ) + (cell LUT2 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + (cell FDCE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port CLR (direction INPUT)) + (port D (direction INPUT)) + ) + ) + ) + (cell GND (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port G (direction OUTPUT)) + ) + ) + ) + (cell LUT4 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + ) + ) + ) + (cell LUT1 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + ) + ) + ) + (cell VCC (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port P (direction OUTPUT)) + ) + ) + ) + (cell LUT6 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + (port I5 (direction INPUT)) + ) + ) + ) + (cell LUT5 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + ) + ) + ) + (cell FDPE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port PRE (direction INPUT)) + ) + ) + ) + (cell INV (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + ) + (Library work + (edifLevel 0) + (technology (numberDefinition )) + (cell SyncRegsIfc (celltype GENERIC) + (view SyncRegsIfc (viewtype NETLIST) + (interface + (port BusClk (direction INPUT)) + (port MeasClk (direction INPUT)) + (port RefClk (direction INPUT)) + (port SampleClk (direction INPUT)) + (port aBusReset (direction INPUT)) + (port aTdcReset (direction OUTPUT)) + (port bBusReset (direction INPUT)) + (port mOffsetsDone (direction INPUT)) + (port mOffsetsValid (direction INPUT)) + (port rEnablePpsCrossing (direction OUTPUT)) + (port rEnableTdc (direction OUTPUT)) + (port rLoadRePulseCounts (direction OUTPUT)) + (port rLoadRpCounts (direction OUTPUT)) + (port rLoadRptCounts (direction OUTPUT)) + (port rPpsPulseCaptured (direction INPUT)) + (port rReRunEnable (direction OUTPUT)) + (port rResetTdc (direction OUTPUT)) + (port rResetTdcDone (direction INPUT)) + (port sLoadSpCounts (direction OUTPUT)) + (port sLoadSptCounts (direction OUTPUT)) + (port (array (rename bRegPortInFlat "bRegPortInFlat[49:0]") 50) (direction INPUT)) + (port (array (rename bRegPortOutFlat "bRegPortOutFlat[33:0]") 34) (direction OUTPUT)) + (port (array (rename mRpOffset "mRpOffset[39:0]") 40) (direction INPUT)) + (port (array (rename mSpOffset "mSpOffset[39:0]") 40) (direction INPUT)) + (port (array (rename rPulserEnableDelayVal "rPulserEnableDelayVal[3:0]") 4) (direction OUTPUT)) + (port (array (rename rRePulseHighTimeInRClks "rRePulseHighTimeInRClks[23:0]") 24) (direction OUTPUT)) + (port (array (rename rRePulsePeriodInRClks "rRePulsePeriodInRClks[23:0]") 24) (direction OUTPUT)) + (port (array (rename rRpHighTimeInRClks "rRpHighTimeInRClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename rRpPeriodInRClks "rRpPeriodInRClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename rRptHighTimeInRClks "rRptHighTimeInRClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename rRptPeriodInRClks "rRptPeriodInRClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename sPpsClkCrossDelayVal "sPpsClkCrossDelayVal[3:0]") 4) (direction OUTPUT)) + (port (array (rename sSpHighTimeInSClks "sSpHighTimeInSClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename sSpPeriodInSClks "sSpPeriodInSClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename sSptHighTimeInSClks "sSptHighTimeInSClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename sSptPeriodInSClks "sSptPeriodInSClks[15:0]") 16) (direction OUTPUT)) + ) + (contents + (instance (rename BlkIn_iDlyPush_i_1 "BlkIn.iDlyPush_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h80")) + (property SOFT_HLUTNM (string "soft_lutpair22")) + ) + (instance (rename BlkIn_iDlyPush_i_1__0 "BlkIn.iDlyPush_i_1__0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h20")) + (property SOFT_HLUTNM (string "soft_lutpair23")) + ) + (instance (rename BlkIn_iDlyPush_i_1__1 "BlkIn.iDlyPush_i_1__1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h20")) + (property SOFT_HLUTNM (string "soft_lutpair24")) + ) + (instance (rename BlkIn_iDlyPush_i_1__2 "BlkIn.iDlyPush_i_1__2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair24")) + ) + (instance (rename BlkIn_iDlyPush_i_1__3 "BlkIn.iDlyPush_i_1__3") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h80")) + (property SOFT_HLUTNM (string "soft_lutpair25")) + ) + (instance (rename BlkIn_iDlyPush_i_1__4 "BlkIn.iDlyPush_i_1__4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h20")) + (property SOFT_HLUTNM (string "soft_lutpair26")) + ) + (instance (rename BlkOut_oDataValid_i_1 "BlkOut.oDataValid_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename BlkOut_oDataValid_i_1__0 "BlkOut.oDataValid_i_1__0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename BlkOut_oDataValid_i_1__1 "BlkOut.oDataValid_i_1__1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename BlkOut_oDataValid_i_1__2 "BlkOut.oDataValid_i_1__2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename BlkOut_oDataValid_i_1__3 "BlkOut.oDataValid_i_1__3") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "EnableTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "EnableTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "EnableTdcDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance (rename Gen0_FDCEx_i_1 "Gen0.FDCEx_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h4000")) + ) + (instance (rename Gen0_FDCEx_i_1__0 "Gen0.FDCEx_i_1__0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0400")) + ) + (instance (rename Gen0_FDCEx_i_1__1 "Gen0.FDCEx_i_1__1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0400")) + ) + (instance (rename Gen0_FDCEx_i_1__10 "Gen0.FDCEx_i_1__10") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename Gen0_FDCEx_i_1__11 "Gen0.FDCEx_i_1__11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename Gen0_FDCEx_i_1__2 "Gen0.FDCEx_i_1__2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0100")) + ) + (instance (rename Gen0_FDCEx_i_1__3 "Gen0.FDCEx_i_1__3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h4000")) + ) + (instance (rename Gen0_FDCEx_i_1__4 "Gen0.FDCEx_i_1__4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0400")) + ) + (instance (rename Gen0_FDCEx_i_1__5 "Gen0.FDCEx_i_1__5") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename Gen0_FDCEx_i_1__6 "Gen0.FDCEx_i_1__6") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename Gen0_FDCEx_i_1__7 "Gen0.FDCEx_i_1__7") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename Gen0_FDCEx_i_1__8 "Gen0.FDCEx_i_1__8") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename Gen0_FDCEx_i_1__9 "Gen0.FDCEx_i_1__9") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename Gen0_FDCEx_i_2 "Gen0.FDCEx_i_2") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__0 "Gen0.FDCEx_i_2__0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__1 "Gen0.FDCEx_i_2__1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__2 "Gen0.FDCEx_i_2__2") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__3 "Gen0.FDCEx_i_2__3") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__4 "Gen0.FDCEx_i_2__4") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__5 "Gen0.FDCEx_i_2__5") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__6 "Gen0.FDCEx_i_2__6") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__7 "Gen0.FDCEx_i_2__7") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_3 "Gen0.FDCEx_i_3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0400")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance (rename Gen0_FDCEx_i_3__0 "Gen0.FDCEx_i_3__0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0008")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance (rename Gen0_FDCEx_i_3__1 "Gen0.FDCEx_i_3__1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0002")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg "IncomingOffsetHs/HBx/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[32]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[33]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[34]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[35]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[36]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[37]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[38]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[39]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[40]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[41]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[42]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[43]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[44]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[45]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[46]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[47]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[48]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[49]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[50]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[51]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[52]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[53]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[54]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[55]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[56]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[57]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[58]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[59]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[60]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[61]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[62]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[63]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[64]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[65]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[66]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[67]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[68]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[69]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[70]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[71]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[72]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[73]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[74]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[75]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[76]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[77]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[78]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[79]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx 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(property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[34].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[35].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename 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IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[42].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[43].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename 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IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[50].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[51].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[52].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[53].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx 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(property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[59].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[60].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[61].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[62].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[63].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[64].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[65].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[66].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[67].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[68].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[69].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[70].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[71].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_72__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[72].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_73__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[73].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_74__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[74].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_75__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[75].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[76].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[77].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[78].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[79].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_oDataValid_reg "IncomingOffsetHs/HBx/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg "IncomingOffsetHs/HBx/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[0].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[0].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[10].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[10].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[11].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[11].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[12].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[12].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[13].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[13].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[14].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[14].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[15].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[15].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[16].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[16].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[17].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[17].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[18].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[18].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[19].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[19].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[1].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[1].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[20].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[20].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[21].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[21].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[22].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[22].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[23].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[23].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[24].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[24].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[25].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[25].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[26].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[26].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[27].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[27].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[28].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[28].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[29].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[29].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[2].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[2].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[30].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[30].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[31].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[31].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[32].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[32].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[33].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[33].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[34].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[34].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[35].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[35].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[36].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[36].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[37].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[37].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[38].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[38].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[39].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[39].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[3].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[3].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[40].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[40].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[41].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[41].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[42].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[42].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[43].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[43].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[44].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[44].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[45].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[45].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[46].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[46].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[47].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[47].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[48].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[48].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[49].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[49].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[4].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[4].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[50].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[50].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[51].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[51].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[52].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[52].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[53].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[53].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[54].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[54].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[55].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[55].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[56].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[56].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[57].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[57].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[58].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[58].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[59].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[59].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[5].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[5].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[60].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[60].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[61].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[61].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[62].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[62].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[63].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[63].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[64].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[64].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[65].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[65].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[66].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[66].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[67].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[67].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[68].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[68].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[69].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[69].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[6].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[6].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[70].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[70].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[71].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[71].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[72].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[72].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[73].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[73].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[74].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[74].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[75].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[75].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[76].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[76].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[77].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[77].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[78].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[78].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[79].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[79].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[7].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[7].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[8].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[8].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[9].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[9].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsValidDs/DoubleSyncSlAsyncInx/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsValidDs/DoubleSyncSlAsyncInx/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "PpsCapturedDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "PpsCapturedDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "PpsCapturedDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "PpsCrossEnDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "PpsCrossEnDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCrossEnDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "PpsCrossEnDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg "PpsDelayValCrossingHs/HBx/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_oDataValid_reg "PpsDelayValCrossingHs/HBx/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg "PpsDelayValCrossingHs/HBx/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg "PulserEnableDelayValCrossingHs/HBx/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg "PulserEnableDelayValCrossingHs/HBx/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg "PulserEnableDelayValCrossingHs/HBx/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkIn_iDlyPush_reg "RePulse1CntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_0_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_10_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_11_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_12_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_13_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_14_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_15_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_16_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_17_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_18_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_19_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_1_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_20_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_21_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_22_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_23_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_24_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_25_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_26_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_27_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_28_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_29_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_2_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_30_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_31_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_3_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_4_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_5_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_6_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_7_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_8_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_9_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx "RePulse1CntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "RePulse1CntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_oPushToggle2_reg "RePulse1CntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "RePulse1CntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkIn_iDlyPush_reg "RePulse2CntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_0_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_10_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_11_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_12_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_13_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_14_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_15_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_16_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_17_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_18_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_19_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_1_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_20_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_21_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_22_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_23_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_24_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_25_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_26_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_27_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_28_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_29_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_2_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_30_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_31_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_3_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_4_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_5_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_6_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_7_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_8_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_9_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx "RePulse2CntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_oDataValid_reg "RePulse2CntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "RePulse2CntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_oPushToggle2_reg "RePulse2CntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "RePulse2CntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[0].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[0].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[10].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[10].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[11].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[11].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[12].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[12].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[13].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[13].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[14].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[14].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[15].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[15].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[16].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[16].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[17].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[17].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[18].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[18].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[19].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[19].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[1].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[1].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[20].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[20].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[21].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[21].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[22].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[22].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[23].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[23].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[24].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[24].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[25].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[25].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[26].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[26].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[27].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[27].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[28].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[28].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[29].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[29].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[2].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[2].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[30].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[30].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[31].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[31].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[3].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[3].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[4].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[4].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[5].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[5].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[6].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[6].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[7].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[7].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[8].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[8].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[9].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[9].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[0].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[0].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[10].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[10].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[11].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[11].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[12].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[12].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[13].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[13].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[14].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[14].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[15].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[15].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[16].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[16].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[17].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[17].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[18].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[18].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[19].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[19].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[1].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[1].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[20].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[20].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[21].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[21].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[22].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[22].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[23].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[23].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[24].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[24].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[25].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[25].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[26].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[26].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[27].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[27].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[28].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[28].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[29].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[29].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[2].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[2].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[30].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[30].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[31].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[31].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[3].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[3].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[4].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[4].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[5].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[5].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[6].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[6].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[7].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[7].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[8].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[8].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[9].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[9].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "ReRunEnableDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "ReRunEnableDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ReRunEnableDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "ReRunEnableDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "ResetDoneDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "ResetDoneDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetDoneDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "ResetDoneDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "ResetTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "ResetTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "ResetTdcDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkIn_iDlyPush_reg "RpCntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_0_ "RpCntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_10_ "RpCntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_11_ "RpCntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_12_ "RpCntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_13_ "RpCntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_14_ "RpCntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_15_ "RpCntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_16_ "RpCntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_17_ "RpCntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_18_ "RpCntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_19_ "RpCntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_1_ "RpCntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_20_ "RpCntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_21_ "RpCntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_22_ "RpCntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_23_ "RpCntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_24_ "RpCntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_25_ "RpCntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_26_ "RpCntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_27_ "RpCntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_28_ "RpCntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_29_ "RpCntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_2_ "RpCntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_30_ "RpCntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_31_ "RpCntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_3_ "RpCntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_4_ "RpCntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_5_ "RpCntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_6_ "RpCntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_7_ "RpCntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_8_ "RpCntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_9_ "RpCntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx "RpCntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[30].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_oDataValid_reg "RpCntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "RpCntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_oPushToggle2_reg "RpCntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "RpCntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[0].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[0].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[10].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[10].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[11].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[11].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[12].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[12].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[13].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[13].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[14].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[14].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[15].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[15].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[16].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[16].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[17].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[17].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[18].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[18].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[19].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[19].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[1].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[1].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[20].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[20].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[21].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[21].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[22].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[22].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[23].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[23].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[24].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[24].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[25].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[25].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[26].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[26].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[27].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[27].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[28].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[28].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[29].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[29].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[2].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[2].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[30].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[30].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[31].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[31].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[3].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[3].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[4].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[4].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[5].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[5].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[6].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[6].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[7].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[7].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[8].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[8].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[9].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[9].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkIn_iDlyPush_reg "RptCntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_0_ "RptCntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_10_ "RptCntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_11_ "RptCntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_12_ "RptCntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_13_ "RptCntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_14_ "RptCntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_15_ "RptCntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_16_ "RptCntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_17_ "RptCntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_18_ "RptCntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_19_ "RptCntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_1_ "RptCntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_20_ "RptCntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_21_ "RptCntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_22_ "RptCntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_23_ "RptCntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_24_ "RptCntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_25_ "RptCntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_26_ "RptCntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_27_ "RptCntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_28_ "RptCntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_29_ "RptCntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_2_ "RptCntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_30_ "RptCntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_31_ "RptCntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_3_ "RptCntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_4_ "RptCntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_5_ "RptCntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_6_ "RptCntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_7_ "RptCntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_8_ "RptCntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_9_ "RptCntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx "RptCntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[30].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_oDataValid_reg "RptCntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "RptCntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_oPushToggle2_reg "RptCntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "RptCntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[0].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[0].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[10].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[10].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[11].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[11].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[12].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[12].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[13].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[13].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[14].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[14].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[15].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[15].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[16].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[16].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[17].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[17].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[18].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[18].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[19].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[19].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[1].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[1].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[20].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[20].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[21].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[21].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[22].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[22].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[23].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[23].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[24].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[24].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[25].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[25].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[26].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[26].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[27].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[27].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[28].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[28].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[29].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[29].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[2].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[2].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[30].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[30].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[31].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[31].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[3].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[3].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[4].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[4].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[5].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[5].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[6].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[6].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[7].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[7].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[8].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[8].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[9].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[9].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkIn_iDlyPush_reg "SpCntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_0_ "SpCntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_10_ "SpCntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_11_ "SpCntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_12_ "SpCntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_13_ "SpCntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_14_ "SpCntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_15_ "SpCntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_16_ "SpCntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_17_ "SpCntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_18_ "SpCntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_19_ "SpCntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_1_ "SpCntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_20_ "SpCntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_21_ "SpCntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_22_ "SpCntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_23_ "SpCntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_24_ "SpCntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_25_ "SpCntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_26_ "SpCntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_27_ "SpCntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_28_ "SpCntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_29_ "SpCntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_2_ "SpCntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_30_ "SpCntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_31_ "SpCntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_3_ "SpCntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_4_ "SpCntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_5_ "SpCntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_6_ "SpCntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_7_ "SpCntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_8_ "SpCntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_9_ "SpCntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx "SpCntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[30].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_oDataValid_reg "SpCntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "SpCntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_oPushToggle2_reg "SpCntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "SpCntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[0].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[0].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[10].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[10].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[11].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[11].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[12].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[12].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[13].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[13].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[14].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[14].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[15].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[15].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[16].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[16].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[17].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[17].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[18].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[18].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[19].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[19].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[1].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[1].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[20].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[20].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[21].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[21].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[22].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[22].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[23].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[23].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[24].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[24].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[25].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[25].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[26].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[26].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[27].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[27].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[28].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[28].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[29].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[29].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[2].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[2].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[30].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[30].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[31].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[31].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[3].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[3].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[4].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[4].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[5].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[5].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[6].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[6].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[7].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[7].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[8].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[8].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[9].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[9].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkIn_iDlyPush_reg "SptCntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_0_ "SptCntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_10_ "SptCntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_11_ "SptCntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_12_ "SptCntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_13_ "SptCntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_14_ "SptCntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_15_ "SptCntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_16_ "SptCntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_17_ "SptCntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_18_ "SptCntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_19_ "SptCntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_1_ "SptCntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_20_ "SptCntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_21_ "SptCntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_22_ "SptCntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_23_ "SptCntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_24_ "SptCntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_25_ "SptCntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_26_ "SptCntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_27_ "SptCntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_28_ "SptCntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_29_ "SptCntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_2_ "SptCntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_30_ "SptCntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_31_ "SptCntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_3_ "SptCntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_4_ "SptCntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_5_ "SptCntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_6_ "SptCntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_7_ "SptCntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_8_ "SptCntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_9_ "SptCntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx "SptCntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[30].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_oDataValid_reg "SptCntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "SptCntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_oPushToggle2_reg "SptCntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "SptCntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[0].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[0].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[10].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[10].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[11].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[11].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[12].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[12].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[13].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[13].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[14].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[14].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[15].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[15].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[16].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[16].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[17].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[17].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[18].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[18].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[19].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[19].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[1].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[1].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[20].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[20].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[21].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[21].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[22].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[22].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[23].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[23].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[24].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[24].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[25].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[25].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[26].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[26].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[27].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[27].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[28].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[28].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[29].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[29].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[2].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[2].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[30].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[30].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[31].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[31].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[3].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[3].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[4].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[4].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[5].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[5].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[6].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[6].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[7].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[7].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[8].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[8].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[9].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[9].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance aTdcResetLcl_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0200000000000000")) + ) + (instance aTdcResetLcl_i_3 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00001000")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance aTdcResetLcl_i_4 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0001")) + ) + (instance aTdcResetLcl_i_5 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0001")) + ) + (instance aTdcResetLcl_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep__0 (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep__1 (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep__2 (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep__3 (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_rep_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_rep_i_1__0 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_rep_i_1__1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_rep_i_1__2 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_rep_i_1__3 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance bClearTdcRegs_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00000080")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance bClearTdcRegs_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000080")) + ) + (instance bClearTdcRegs_i_3 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair22")) + ) + (instance bClearTdcRegs_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bEnableTdc_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h1101111111000000")) + ) + (instance bEnableTdc_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bOffsetUpdated_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h05030500")) + ) + (instance bOffsetUpdated_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPpsClkCrossDelayVal_0__i_1 "bPpsClkCrossDelayVal[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename bPpsClkCrossDelayVal_1__i_1 "bPpsClkCrossDelayVal[1]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance (rename bPpsClkCrossDelayVal_2__i_1 "bPpsClkCrossDelayVal[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance (rename bPpsClkCrossDelayVal_3__i_1 "bPpsClkCrossDelayVal[3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFF8")) + ) + (instance (rename bPpsClkCrossDelayVal_3__i_2 "bPpsClkCrossDelayVal[3]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance (rename bPpsClkCrossDelayVal_3__i_3 "bPpsClkCrossDelayVal[3]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000100")) + ) + (instance (rename bPpsClkCrossDelayVal_reg_0_ "bPpsClkCrossDelayVal_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPpsClkCrossDelayVal_reg_1_ "bPpsClkCrossDelayVal_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPpsClkCrossDelayVal_reg_2_ "bPpsClkCrossDelayVal_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPpsClkCrossDelayVal_reg_3_ "bPpsClkCrossDelayVal_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bPpsClkCrossEn_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h1101111111000000")) + ) + (instance bPpsClkCrossEn_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPulserEnableDelayVal_0__i_1 "bPulserEnableDelayVal[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFE")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename bPulserEnableDelayVal_1__i_1 "bPulserEnableDelayVal[1]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair29")) + ) + (instance (rename bPulserEnableDelayVal_2__i_1 "bPulserEnableDelayVal[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance (rename bPulserEnableDelayVal_3__i_1 "bPulserEnableDelayVal[3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFF8")) + ) + (instance (rename bPulserEnableDelayVal_3__i_2 "bPulserEnableDelayVal[3]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (instance (rename bPulserEnableDelayVal_reg_0_ "bPulserEnableDelayVal_reg[0]") (viewref netlist (cellref FDPE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename bPulserEnableDelayVal_reg_1_ "bPulserEnableDelayVal_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPulserEnableDelayVal_reg_2_ "bPulserEnableDelayVal_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPulserEnableDelayVal_reg_3_ "bPulserEnableDelayVal_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bPushPpsDelayVal_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0080000000000000")) + ) + (instance bPushPpsDelayVal_i_2 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h01")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance bPushPpsDelayVal_i_3 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair27")) + ) + (instance bPushPpsDelayVal_i_4 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + (property SOFT_HLUTNM (string "soft_lutpair25")) + ) + (instance bPushPpsDelayVal_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bPushPulserEnableDelayVal_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0080000000000000")) + ) + (instance bPushPulserEnableDelayVal_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bReRunEnable_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h1101111111000000")) + ) + (instance bReRunEnable_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_1 "bRegPortOutLcl[Data][0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_2 "bRegPortOutLcl[Data][0]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_3 "bRegPortOutLcl[Data][0]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_4 "bRegPortOutLcl[Data][0]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_5 "bRegPortOutLcl[Data][0]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hAAAAFAAAAAAAEEAA")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_6 "bRegPortOutLcl[Data][0]_i_6") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_7 "bRegPortOutLcl[Data][0]_i_7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000002000")) + ) + (instance (rename bRegPortOutLcl_Data__10__i_1 "bRegPortOutLcl[Data][10]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename bRegPortOutLcl_Data__10__i_2 "bRegPortOutLcl[Data][10]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__10__i_3 "bRegPortOutLcl[Data][10]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h88F8888888888888")) + ) + (instance (rename bRegPortOutLcl_Data__10__i_4 "bRegPortOutLcl[Data][10]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__11__i_1 "bRegPortOutLcl[Data][11]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__11__i_2 "bRegPortOutLcl[Data][11]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__11__i_3 "bRegPortOutLcl[Data][11]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__11__i_4 "bRegPortOutLcl[Data][11]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__12__i_1 "bRegPortOutLcl[Data][12]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__12__i_2 "bRegPortOutLcl[Data][12]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__12__i_3 "bRegPortOutLcl[Data][12]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__12__i_4 "bRegPortOutLcl[Data][12]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__13__i_1 "bRegPortOutLcl[Data][13]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFBAA")) + ) + (instance (rename bRegPortOutLcl_Data__13__i_2 "bRegPortOutLcl[Data][13]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__13__i_3 "bRegPortOutLcl[Data][13]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__13__i_4 "bRegPortOutLcl[Data][13]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__14__i_1 "bRegPortOutLcl[Data][14]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__14__i_2 "bRegPortOutLcl[Data][14]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__14__i_3 "bRegPortOutLcl[Data][14]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__14__i_4 "bRegPortOutLcl[Data][14]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__15__i_1 "bRegPortOutLcl[Data][15]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFE")) + ) + (instance (rename bRegPortOutLcl_Data__15__i_2 "bRegPortOutLcl[Data][15]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__15__i_3 "bRegPortOutLcl[Data][15]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__15__i_4 "bRegPortOutLcl[Data][15]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_1 "bRegPortOutLcl[Data][16]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFEEE")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_2 "bRegPortOutLcl[Data][16]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_3 "bRegPortOutLcl[Data][16]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF002000200020")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_4 "bRegPortOutLcl[Data][16]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF080008000000000")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_5 "bRegPortOutLcl[Data][16]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__17__i_1 "bRegPortOutLcl[Data][17]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__17__i_2 "bRegPortOutLcl[Data][17]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__17__i_3 "bRegPortOutLcl[Data][17]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__17__i_4 "bRegPortOutLcl[Data][17]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__18__i_1 "bRegPortOutLcl[Data][18]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__18__i_2 "bRegPortOutLcl[Data][18]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__18__i_3 "bRegPortOutLcl[Data][18]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__18__i_4 "bRegPortOutLcl[Data][18]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__19__i_1 "bRegPortOutLcl[Data][19]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFEAA")) + ) + (instance (rename bRegPortOutLcl_Data__19__i_2 "bRegPortOutLcl[Data][19]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__19__i_3 "bRegPortOutLcl[Data][19]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__19__i_4 "bRegPortOutLcl[Data][19]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_1 "bRegPortOutLcl[Data][1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_2 "bRegPortOutLcl[Data][1]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF88F888F888F8")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_3 "bRegPortOutLcl[Data][1]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_4 "bRegPortOutLcl[Data][1]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_5 "bRegPortOutLcl[Data][1]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__20__i_1 "bRegPortOutLcl[Data][20]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__20__i_2 "bRegPortOutLcl[Data][20]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__20__i_3 "bRegPortOutLcl[Data][20]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__20__i_4 "bRegPortOutLcl[Data][20]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__21__i_1 "bRegPortOutLcl[Data][21]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__21__i_2 "bRegPortOutLcl[Data][21]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__21__i_3 "bRegPortOutLcl[Data][21]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__21__i_4 "bRegPortOutLcl[Data][21]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__22__i_1 "bRegPortOutLcl[Data][22]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__22__i_2 "bRegPortOutLcl[Data][22]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__22__i_3 "bRegPortOutLcl[Data][22]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__22__i_4 "bRegPortOutLcl[Data][22]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__23__i_1 "bRegPortOutLcl[Data][23]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFE")) + ) + (instance (rename bRegPortOutLcl_Data__23__i_2 "bRegPortOutLcl[Data][23]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__23__i_3 "bRegPortOutLcl[Data][23]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__23__i_4 "bRegPortOutLcl[Data][23]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__24__i_1 "bRegPortOutLcl[Data][24]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFEAA")) + ) + (instance (rename bRegPortOutLcl_Data__24__i_2 "bRegPortOutLcl[Data][24]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__24__i_3 "bRegPortOutLcl[Data][24]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__24__i_4 "bRegPortOutLcl[Data][24]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_1 "bRegPortOutLcl[Data][25]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFEAA")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_2 "bRegPortOutLcl[Data][25]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_3 "bRegPortOutLcl[Data][25]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000100000000000")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_4 "bRegPortOutLcl[Data][25]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_5 "bRegPortOutLcl[Data][25]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_1 "bRegPortOutLcl[Data][26]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_2 "bRegPortOutLcl[Data][26]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_3 "bRegPortOutLcl[Data][26]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0020000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_4 "bRegPortOutLcl[Data][26]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_5 "bRegPortOutLcl[Data][26]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_1 "bRegPortOutLcl[Data][27]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_2 "bRegPortOutLcl[Data][27]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_3 "bRegPortOutLcl[Data][27]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000200000")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_4 "bRegPortOutLcl[Data][27]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000120000000000")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_5 "bRegPortOutLcl[Data][27]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_6 "bRegPortOutLcl[Data][27]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_7 "bRegPortOutLcl[Data][27]_i_7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0040000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_1 "bRegPortOutLcl[Data][28]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_10 "bRegPortOutLcl[Data][28]_i_10") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_2 "bRegPortOutLcl[Data][28]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_3 "bRegPortOutLcl[Data][28]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h88F8888888888888")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_4 "bRegPortOutLcl[Data][28]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0004000C00000000")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_5 "bRegPortOutLcl[Data][28]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0800000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_6 "bRegPortOutLcl[Data][28]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_7 "bRegPortOutLcl[Data][28]_i_7") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0040")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_8 "bRegPortOutLcl[Data][28]_i_8") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000008000")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_9 "bRegPortOutLcl[Data][28]_i_9") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance (rename bRegPortOutLcl_Data__29__i_1 "bRegPortOutLcl[Data][29]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__29__i_2 "bRegPortOutLcl[Data][29]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__29__i_3 "bRegPortOutLcl[Data][29]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__29__i_4 "bRegPortOutLcl[Data][29]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_1 "bRegPortOutLcl[Data][2]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_2 "bRegPortOutLcl[Data][2]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_3 "bRegPortOutLcl[Data][2]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_4 "bRegPortOutLcl[Data][2]_i_4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hF8")) + (property SOFT_HLUTNM (string "soft_lutpair21")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_5 "bRegPortOutLcl[Data][2]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_1 "bRegPortOutLcl[Data][30]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_2 "bRegPortOutLcl[Data][30]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_3 "bRegPortOutLcl[Data][30]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_4 "bRegPortOutLcl[Data][30]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000002000000000")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_5 "bRegPortOutLcl[Data][30]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_6 "bRegPortOutLcl[Data][30]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000004000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_1 "bRegPortOutLcl[Data][31]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFE")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_10 "bRegPortOutLcl[Data][31]_i_10") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000020000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_11 "bRegPortOutLcl[Data][31]_i_11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0800000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_12 "bRegPortOutLcl[Data][31]_i_12") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h8")) + (property SOFT_HLUTNM (string "soft_lutpair23")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_2 "bRegPortOutLcl[Data][31]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_3 "bRegPortOutLcl[Data][31]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_4 "bRegPortOutLcl[Data][31]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_5 "bRegPortOutLcl[Data][31]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0010000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_6 "bRegPortOutLcl[Data][31]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000800000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_7 "bRegPortOutLcl[Data][31]_i_7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000200000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_8 "bRegPortOutLcl[Data][31]_i_8") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000200000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_9 "bRegPortOutLcl[Data][31]_i_9") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000020000000000")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_1 "bRegPortOutLcl[Data][3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_2 "bRegPortOutLcl[Data][3]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_3 "bRegPortOutLcl[Data][3]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_4 "bRegPortOutLcl[Data][3]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_5 "bRegPortOutLcl[Data][3]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_1 "bRegPortOutLcl[Data][4]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_2 "bRegPortOutLcl[Data][4]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_3 "bRegPortOutLcl[Data][4]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_4 "bRegPortOutLcl[Data][4]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_5 "bRegPortOutLcl[Data][4]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0001000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_6 "bRegPortOutLcl[Data][4]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h000000C00000E000")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_7 "bRegPortOutLcl[Data][4]_i_7") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_1 "bRegPortOutLcl[Data][5]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_2 "bRegPortOutLcl[Data][5]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF88F888F888F8")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_3 "bRegPortOutLcl[Data][5]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_4 "bRegPortOutLcl[Data][5]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_5 "bRegPortOutLcl[Data][5]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_1 "bRegPortOutLcl[Data][6]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_2 "bRegPortOutLcl[Data][6]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_3 "bRegPortOutLcl[Data][6]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_4 "bRegPortOutLcl[Data][6]_i_4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hF8")) + (property SOFT_HLUTNM (string "soft_lutpair21")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_5 "bRegPortOutLcl[Data][6]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_1 "bRegPortOutLcl[Data][7]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_2 "bRegPortOutLcl[Data][7]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_3 "bRegPortOutLcl[Data][7]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_4 "bRegPortOutLcl[Data][7]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_5 "bRegPortOutLcl[Data][7]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_6 "bRegPortOutLcl[Data][7]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000008000")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_1 "bRegPortOutLcl[Data][8]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_2 "bRegPortOutLcl[Data][8]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_3 "bRegPortOutLcl[Data][8]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_4 "bRegPortOutLcl[Data][8]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_5 "bRegPortOutLcl[Data][8]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_6 "bRegPortOutLcl[Data][8]_i_6") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h8000")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_1 "bRegPortOutLcl[Data][9]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_2 "bRegPortOutLcl[Data][9]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_3 "bRegPortOutLcl[Data][9]_i_3") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF88F8")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_4 "bRegPortOutLcl[Data][9]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h88F8888888888888")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_5 "bRegPortOutLcl[Data][9]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_reg_Data__0_ "bRegPortOutLcl_reg[Data][0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__10_ "bRegPortOutLcl_reg[Data][10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__11_ "bRegPortOutLcl_reg[Data][11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__12_ "bRegPortOutLcl_reg[Data][12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__13_ "bRegPortOutLcl_reg[Data][13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__14_ "bRegPortOutLcl_reg[Data][14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__15_ "bRegPortOutLcl_reg[Data][15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__16_ "bRegPortOutLcl_reg[Data][16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__17_ "bRegPortOutLcl_reg[Data][17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__18_ "bRegPortOutLcl_reg[Data][18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__19_ "bRegPortOutLcl_reg[Data][19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__1_ "bRegPortOutLcl_reg[Data][1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__20_ "bRegPortOutLcl_reg[Data][20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__21_ "bRegPortOutLcl_reg[Data][21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__22_ "bRegPortOutLcl_reg[Data][22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__23_ "bRegPortOutLcl_reg[Data][23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__24_ "bRegPortOutLcl_reg[Data][24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__25_ "bRegPortOutLcl_reg[Data][25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__26_ "bRegPortOutLcl_reg[Data][26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__27_ "bRegPortOutLcl_reg[Data][27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__28_ "bRegPortOutLcl_reg[Data][28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__29_ "bRegPortOutLcl_reg[Data][29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__2_ "bRegPortOutLcl_reg[Data][2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__30_ "bRegPortOutLcl_reg[Data][30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__31_ "bRegPortOutLcl_reg[Data][31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__3_ "bRegPortOutLcl_reg[Data][3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__4_ "bRegPortOutLcl_reg[Data][4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__5_ "bRegPortOutLcl_reg[Data][5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__6_ "bRegPortOutLcl_reg[Data][6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__7_ "bRegPortOutLcl_reg[Data][7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__8_ "bRegPortOutLcl_reg[Data][8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__9_ "bRegPortOutLcl_reg[Data][9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bResetTdc_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFEFFFFFFFEEEEEE")) + ) + (instance bResetTdc_reg (viewref netlist (cellref FDPE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename bRpOffsetStored_0__i_1 "bRpOffsetStored[0]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair49")) + ) + (instance (rename bRpOffsetStored_10__i_1 "bRpOffsetStored[10]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair44")) + ) + (instance (rename bRpOffsetStored_11__i_1 "bRpOffsetStored[11]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair43")) + ) + (instance (rename bRpOffsetStored_12__i_1 "bRpOffsetStored[12]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair43")) + ) + (instance (rename bRpOffsetStored_13__i_1 "bRpOffsetStored[13]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair42")) + ) + (instance (rename bRpOffsetStored_14__i_1 "bRpOffsetStored[14]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair42")) + ) + (instance (rename bRpOffsetStored_15__i_1 "bRpOffsetStored[15]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair41")) + ) + (instance (rename bRpOffsetStored_16__i_1 "bRpOffsetStored[16]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair41")) + ) + (instance (rename bRpOffsetStored_17__i_1 "bRpOffsetStored[17]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair40")) + ) + (instance (rename bRpOffsetStored_18__i_1 "bRpOffsetStored[18]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair40")) + ) + (instance (rename bRpOffsetStored_19__i_1 "bRpOffsetStored[19]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair39")) + ) + (instance (rename bRpOffsetStored_1__i_1 "bRpOffsetStored[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair48")) + ) + (instance (rename bRpOffsetStored_20__i_1 "bRpOffsetStored[20]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair39")) + ) + (instance (rename bRpOffsetStored_21__i_1 "bRpOffsetStored[21]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair38")) + ) + (instance (rename bRpOffsetStored_22__i_1 "bRpOffsetStored[22]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair38")) + ) + (instance (rename bRpOffsetStored_23__i_1 "bRpOffsetStored[23]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair37")) + ) + (instance (rename bRpOffsetStored_24__i_1 "bRpOffsetStored[24]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair37")) + ) + (instance (rename bRpOffsetStored_25__i_1 "bRpOffsetStored[25]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair36")) + ) + (instance (rename bRpOffsetStored_26__i_1 "bRpOffsetStored[26]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair36")) + ) + (instance (rename bRpOffsetStored_27__i_1 "bRpOffsetStored[27]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair35")) + ) + (instance (rename bRpOffsetStored_28__i_1 "bRpOffsetStored[28]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair35")) + ) + (instance (rename bRpOffsetStored_29__i_1 "bRpOffsetStored[29]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair34")) + ) + (instance (rename bRpOffsetStored_2__i_1 "bRpOffsetStored[2]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair48")) + ) + (instance (rename bRpOffsetStored_30__i_1 "bRpOffsetStored[30]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair34")) + ) + (instance (rename bRpOffsetStored_31__i_1 "bRpOffsetStored[31]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair33")) + ) + (instance (rename bRpOffsetStored_32__i_1 "bRpOffsetStored[32]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair33")) + ) + (instance (rename bRpOffsetStored_33__i_1 "bRpOffsetStored[33]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair32")) + ) + (instance (rename bRpOffsetStored_34__i_1 "bRpOffsetStored[34]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair32")) + ) + (instance (rename bRpOffsetStored_35__i_1 "bRpOffsetStored[35]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair31")) + ) + (instance (rename bRpOffsetStored_36__i_1 "bRpOffsetStored[36]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair31")) + ) + (instance (rename bRpOffsetStored_37__i_1 "bRpOffsetStored[37]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair30")) + ) + (instance (rename bRpOffsetStored_38__i_1 "bRpOffsetStored[38]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair30")) + ) + (instance (rename bRpOffsetStored_39__i_1 "bRpOffsetStored[39]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF8000")) + ) + (instance (rename bRpOffsetStored_39__i_2 "bRpOffsetStored[39]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair29")) + ) + (instance (rename bRpOffsetStored_39__i_3 "bRpOffsetStored[39]_i_3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0008")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance (rename bRpOffsetStored_39__i_4 "bRpOffsetStored[39]_i_4") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00000004")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance (rename bRpOffsetStored_3__i_1 "bRpOffsetStored[3]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair47")) + ) + (instance (rename bRpOffsetStored_4__i_1 "bRpOffsetStored[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair47")) + ) + (instance (rename bRpOffsetStored_5__i_1 "bRpOffsetStored[5]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair46")) + ) + (instance (rename bRpOffsetStored_6__i_1 "bRpOffsetStored[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair46")) + ) + (instance (rename bRpOffsetStored_7__i_1 "bRpOffsetStored[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair45")) + ) + (instance (rename bRpOffsetStored_8__i_1 "bRpOffsetStored[8]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair45")) + ) + (instance (rename bRpOffsetStored_9__i_1 "bRpOffsetStored[9]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair44")) + ) + (instance (rename bRpOffsetStored_reg_0_ "bRpOffsetStored_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_10_ "bRpOffsetStored_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_11_ "bRpOffsetStored_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_12_ "bRpOffsetStored_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_13_ "bRpOffsetStored_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_14_ "bRpOffsetStored_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_15_ "bRpOffsetStored_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_16_ "bRpOffsetStored_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_17_ "bRpOffsetStored_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_18_ "bRpOffsetStored_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_19_ "bRpOffsetStored_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_1_ "bRpOffsetStored_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_20_ "bRpOffsetStored_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_21_ "bRpOffsetStored_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_22_ "bRpOffsetStored_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_23_ "bRpOffsetStored_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_24_ "bRpOffsetStored_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_25_ "bRpOffsetStored_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_26_ "bRpOffsetStored_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_27_ "bRpOffsetStored_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_28_ "bRpOffsetStored_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_29_ "bRpOffsetStored_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_2_ "bRpOffsetStored_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_30_ "bRpOffsetStored_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_31_ "bRpOffsetStored_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_32_ "bRpOffsetStored_reg[32]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_33_ "bRpOffsetStored_reg[33]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_34_ "bRpOffsetStored_reg[34]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_35_ "bRpOffsetStored_reg[35]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_36_ "bRpOffsetStored_reg[36]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_37_ "bRpOffsetStored_reg[37]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_38_ "bRpOffsetStored_reg[38]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_39_ "bRpOffsetStored_reg[39]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_3_ "bRpOffsetStored_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_4_ "bRpOffsetStored_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_5_ "bRpOffsetStored_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_6_ "bRpOffsetStored_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_7_ "bRpOffsetStored_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_8_ "bRpOffsetStored_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_9_ "bRpOffsetStored_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_0__i_1 "bScratch[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair28")) + ) + (instance (rename bScratch_10__i_1 "bScratch[10]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance (rename bScratch_11__i_1 "bScratch[11]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename bScratch_12__i_1 "bScratch[12]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename bScratch_13__i_1 "bScratch[13]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename bScratch_14__i_1 "bScratch[14]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename bScratch_15__i_1 "bScratch[15]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance (rename bScratch_1__i_1 "bScratch[1]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (instance (rename bScratch_20__i_1 "bScratch[20]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename bScratch_21__i_1 "bScratch[21]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair20")) + ) + (instance (rename bScratch_22__i_1 "bScratch[22]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance (rename bScratch_23__i_1 "bScratch[23]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair20")) + ) + (instance (rename bScratch_24__i_1 "bScratch[24]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair28")) + ) + (instance (rename bScratch_28__i_1 "bScratch[28]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance (rename bScratch_29__i_1 "bScratch[29]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance (rename bScratch_2__i_1 "bScratch[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance (rename bScratch_30__i_1 "bScratch[30]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance (rename bScratch_31__i_1 "bScratch[31]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFF00800000")) + ) + (instance (rename bScratch_31__i_2 "bScratch[31]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename bScratch_31__i_3 "bScratch[31]_i_3") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h40")) + (property SOFT_HLUTNM (string "soft_lutpair27")) + ) + (instance (rename bScratch_31__i_4 "bScratch[31]_i_4") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair26")) + ) + (instance (rename bScratch_31__i_5 "bScratch[31]_i_5") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hE")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance (rename bScratch_3__i_1 "bScratch[3]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance (rename bScratch_4__i_1 "bScratch[4]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename bScratch_5__i_1 "bScratch[5]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance (rename bScratch_6__i_1 "bScratch[6]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename bScratch_7__i_1 "bScratch[7]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance (rename bScratch_8__i_1 "bScratch[8]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance (rename bScratch_9__i_1 "bScratch[9]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance (rename bScratch_reg_0_ "bScratch_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_10_ "bScratch_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_11_ "bScratch_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_12_ "bScratch_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_13_ "bScratch_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_14_ "bScratch_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_15_ "bScratch_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_16_ "bScratch_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_17_ "bScratch_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_18_ "bScratch_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_19_ "bScratch_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_1_ "bScratch_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_20_ "bScratch_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_21_ "bScratch_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_22_ "bScratch_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_23_ "bScratch_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_24_ "bScratch_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_25_ "bScratch_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_26_ "bScratch_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_27_ "bScratch_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_28_ "bScratch_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_29_ "bScratch_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_2_ "bScratch_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_30_ "bScratch_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_31_ "bScratch_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_3_ "bScratch_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_4_ "bScratch_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_5_ "bScratch_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_6_ "bScratch_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_7_ "bScratch_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_8_ "bScratch_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_9_ "bScratch_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_0__i_1 "bSpOffsetStored[0]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename bSpOffsetStored_10__i_1 "bSpOffsetStored[10]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair60")) + ) + (instance (rename bSpOffsetStored_11__i_1 "bSpOffsetStored[11]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair59")) + ) + (instance (rename bSpOffsetStored_12__i_1 "bSpOffsetStored[12]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair59")) + ) + (instance (rename bSpOffsetStored_13__i_1 "bSpOffsetStored[13]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair58")) + ) + (instance (rename bSpOffsetStored_14__i_1 "bSpOffsetStored[14]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair58")) + ) + (instance (rename bSpOffsetStored_15__i_1 "bSpOffsetStored[15]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair57")) + ) + (instance (rename bSpOffsetStored_16__i_1 "bSpOffsetStored[16]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair57")) + ) + (instance (rename bSpOffsetStored_17__i_1 "bSpOffsetStored[17]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair56")) + ) + (instance (rename bSpOffsetStored_18__i_1 "bSpOffsetStored[18]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair56")) + ) + (instance (rename bSpOffsetStored_19__i_1 "bSpOffsetStored[19]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair55")) + ) + (instance (rename bSpOffsetStored_1__i_1 "bSpOffsetStored[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair64")) + ) + (instance (rename bSpOffsetStored_20__i_1 "bSpOffsetStored[20]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair55")) + ) + (instance (rename bSpOffsetStored_21__i_1 "bSpOffsetStored[21]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair54")) + ) + (instance (rename bSpOffsetStored_22__i_1 "bSpOffsetStored[22]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair54")) + ) + (instance (rename bSpOffsetStored_23__i_1 "bSpOffsetStored[23]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair53")) + ) + (instance (rename bSpOffsetStored_24__i_1 "bSpOffsetStored[24]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair53")) + ) + (instance (rename bSpOffsetStored_25__i_1 "bSpOffsetStored[25]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair52")) + ) + (instance (rename bSpOffsetStored_26__i_1 "bSpOffsetStored[26]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair52")) + ) + (instance (rename bSpOffsetStored_27__i_1 "bSpOffsetStored[27]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair51")) + ) + (instance (rename bSpOffsetStored_28__i_1 "bSpOffsetStored[28]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair51")) + ) + (instance (rename bSpOffsetStored_29__i_1 "bSpOffsetStored[29]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair50")) + ) + (instance (rename bSpOffsetStored_2__i_1 "bSpOffsetStored[2]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair64")) + ) + (instance (rename bSpOffsetStored_30__i_1 "bSpOffsetStored[30]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair50")) + ) + (instance (rename bSpOffsetStored_31__i_1 "bSpOffsetStored[31]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair49")) + ) + (instance (rename bSpOffsetStored_3__i_1 "bSpOffsetStored[3]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair63")) + ) + (instance (rename bSpOffsetStored_4__i_1 "bSpOffsetStored[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair63")) + ) + (instance (rename bSpOffsetStored_5__i_1 "bSpOffsetStored[5]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair62")) + ) + (instance (rename bSpOffsetStored_6__i_1 "bSpOffsetStored[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair62")) + ) + (instance (rename bSpOffsetStored_7__i_1 "bSpOffsetStored[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair61")) + ) + (instance (rename bSpOffsetStored_8__i_1 "bSpOffsetStored[8]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair61")) + ) + (instance (rename bSpOffsetStored_9__i_1 "bSpOffsetStored[9]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair60")) + ) + (instance (rename bSpOffsetStored_reg_0_ "bSpOffsetStored_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_10_ "bSpOffsetStored_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_11_ "bSpOffsetStored_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_12_ "bSpOffsetStored_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_13_ "bSpOffsetStored_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_14_ "bSpOffsetStored_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_15_ "bSpOffsetStored_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_16_ "bSpOffsetStored_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_17_ "bSpOffsetStored_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_18_ "bSpOffsetStored_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_19_ "bSpOffsetStored_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_1_ "bSpOffsetStored_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_20_ "bSpOffsetStored_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_21_ "bSpOffsetStored_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_22_ "bSpOffsetStored_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_23_ "bSpOffsetStored_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_24_ "bSpOffsetStored_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_25_ "bSpOffsetStored_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_26_ "bSpOffsetStored_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_27_ "bSpOffsetStored_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_28_ "bSpOffsetStored_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_29_ "bSpOffsetStored_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_2_ "bSpOffsetStored_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_30_ "bSpOffsetStored_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_31_ "bSpOffsetStored_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_3_ "bSpOffsetStored_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_4_ "bSpOffsetStored_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_5_ "bSpOffsetStored_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_6_ "bSpOffsetStored_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_7_ "bSpOffsetStored_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_8_ "bSpOffsetStored_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_9_ "bSpOffsetStored_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rPulserEnableDelayVal_reg_0_ "rPulserEnableDelayVal_reg[0]") (viewref netlist (cellref FDPE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename rPulserEnableDelayVal_reg_1_ "rPulserEnableDelayVal_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rPulserEnableDelayVal_reg_2_ "rPulserEnableDelayVal_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rPulserEnableDelayVal_reg_3_ "rPulserEnableDelayVal_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename sPpsClkCrossDelayVal_reg_0_ "sPpsClkCrossDelayVal_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename sPpsClkCrossDelayVal_reg_1_ "sPpsClkCrossDelayVal_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename sPpsClkCrossDelayVal_reg_2_ "sPpsClkCrossDelayVal_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename sPpsClkCrossDelayVal_reg_3_ "sPpsClkCrossDelayVal_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const0_ "") (joined + (portref CLR (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref ResetDoneDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref G (instanceref GND)) + (portref (member bRegPortOutFlat 32)) + (portref (member rRePulseHighTimeInRClks 0)) + (portref (member rRpHighTimeInRClks 0)) + (portref (member rRptHighTimeInRClks 0)) + (portref (member sSpHighTimeInSClks 0)) + (portref (member sSptHighTimeInSClks 0)) + ) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_oDataValid_reg)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref 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RpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref C (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkIn_iDlyPush_reg)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref C (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkIn_iDlyPush_reg)) + (portref C (instanceref SpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref C (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref C (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref C 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SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref aTdcResetLcl_reg)) + (portref C (instanceref aTdcResetLcl_reg_rep)) + (portref C (instanceref aTdcResetLcl_reg_rep__0)) + (portref C (instanceref aTdcResetLcl_reg_rep__1)) + (portref C (instanceref aTdcResetLcl_reg_rep__2)) + (portref C (instanceref aTdcResetLcl_reg_rep__3)) + (portref C (instanceref bClearTdcRegs_reg)) + (portref C (instanceref bEnableTdc_reg)) + (portref C (instanceref bOffsetUpdated_reg)) + (portref C (instanceref bPpsClkCrossDelayVal_reg_0_)) + (portref C (instanceref bPpsClkCrossDelayVal_reg_1_)) + (portref C (instanceref bPpsClkCrossDelayVal_reg_2_)) + (portref C (instanceref bPpsClkCrossDelayVal_reg_3_)) + (portref C (instanceref bPpsClkCrossEn_reg)) + (portref C (instanceref bPulserEnableDelayVal_reg_0_)) + (portref C (instanceref bPulserEnableDelayVal_reg_1_)) + (portref C (instanceref bPulserEnableDelayVal_reg_2_)) + (portref C (instanceref bPulserEnableDelayVal_reg_3_)) + (portref C (instanceref bPushPpsDelayVal_reg)) + (portref C (instanceref bPushPulserEnableDelayVal_reg)) + (portref C (instanceref bReRunEnable_reg)) + (portref C (instanceref bRegPortOutLcl_reg_Data__0_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__10_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__11_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__12_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__13_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__14_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__15_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__16_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__17_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__18_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__19_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__1_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__20_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__21_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__22_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__23_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__24_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__25_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__26_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__27_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__28_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__29_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__2_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__30_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__31_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__3_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__4_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__5_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__6_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__7_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__8_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__9_)) + (portref C (instanceref bResetTdc_reg)) + (portref C (instanceref bRpOffsetStored_reg_0_)) + (portref C (instanceref bRpOffsetStored_reg_10_)) + (portref C (instanceref bRpOffsetStored_reg_11_)) + (portref C (instanceref bRpOffsetStored_reg_12_)) + (portref C (instanceref bRpOffsetStored_reg_13_)) + (portref C (instanceref bRpOffsetStored_reg_14_)) + (portref C (instanceref bRpOffsetStored_reg_15_)) + (portref C (instanceref bRpOffsetStored_reg_16_)) + (portref C (instanceref bRpOffsetStored_reg_17_)) + (portref C (instanceref bRpOffsetStored_reg_18_)) + (portref C (instanceref bRpOffsetStored_reg_19_)) + (portref C (instanceref bRpOffsetStored_reg_1_)) + (portref C (instanceref bRpOffsetStored_reg_20_)) + (portref C (instanceref bRpOffsetStored_reg_21_)) + (portref C (instanceref bRpOffsetStored_reg_22_)) + (portref C (instanceref bRpOffsetStored_reg_23_)) + (portref C (instanceref bRpOffsetStored_reg_24_)) + (portref C (instanceref bRpOffsetStored_reg_25_)) + (portref C (instanceref bRpOffsetStored_reg_26_)) + (portref C (instanceref bRpOffsetStored_reg_27_)) + (portref C (instanceref bRpOffsetStored_reg_28_)) + (portref C (instanceref bRpOffsetStored_reg_29_)) + (portref C (instanceref bRpOffsetStored_reg_2_)) + (portref C (instanceref bRpOffsetStored_reg_30_)) + (portref C (instanceref bRpOffsetStored_reg_31_)) + (portref C (instanceref bRpOffsetStored_reg_32_)) + (portref C (instanceref bRpOffsetStored_reg_33_)) + (portref C (instanceref bRpOffsetStored_reg_34_)) + (portref C (instanceref bRpOffsetStored_reg_35_)) + (portref C (instanceref bRpOffsetStored_reg_36_)) + (portref C (instanceref bRpOffsetStored_reg_37_)) + (portref C (instanceref bRpOffsetStored_reg_38_)) + (portref C (instanceref bRpOffsetStored_reg_39_)) + (portref C (instanceref bRpOffsetStored_reg_3_)) + (portref C (instanceref bRpOffsetStored_reg_4_)) + (portref C (instanceref bRpOffsetStored_reg_5_)) + (portref C (instanceref bRpOffsetStored_reg_6_)) + (portref C (instanceref bRpOffsetStored_reg_7_)) + (portref C (instanceref bRpOffsetStored_reg_8_)) + (portref C (instanceref bRpOffsetStored_reg_9_)) + (portref C (instanceref bScratch_reg_0_)) + (portref C (instanceref bScratch_reg_10_)) + (portref C (instanceref bScratch_reg_11_)) + (portref C (instanceref bScratch_reg_12_)) + (portref C (instanceref bScratch_reg_13_)) + (portref C (instanceref bScratch_reg_14_)) + (portref C (instanceref bScratch_reg_15_)) + (portref C (instanceref bScratch_reg_16_)) + (portref C (instanceref bScratch_reg_17_)) + (portref C (instanceref bScratch_reg_18_)) + (portref C (instanceref bScratch_reg_19_)) + (portref C (instanceref bScratch_reg_1_)) + (portref C (instanceref bScratch_reg_20_)) + (portref C (instanceref bScratch_reg_21_)) + (portref C (instanceref bScratch_reg_22_)) + (portref C (instanceref bScratch_reg_23_)) + (portref C (instanceref bScratch_reg_24_)) + (portref C (instanceref bScratch_reg_25_)) + (portref C (instanceref bScratch_reg_26_)) + (portref C (instanceref bScratch_reg_27_)) + (portref C (instanceref bScratch_reg_28_)) + (portref C (instanceref bScratch_reg_29_)) + (portref C (instanceref bScratch_reg_2_)) + (portref C (instanceref bScratch_reg_30_)) + (portref C (instanceref bScratch_reg_31_)) + (portref C (instanceref bScratch_reg_3_)) + (portref C (instanceref bScratch_reg_4_)) + (portref C (instanceref bScratch_reg_5_)) + (portref C (instanceref bScratch_reg_6_)) + (portref C (instanceref bScratch_reg_7_)) + (portref C (instanceref bScratch_reg_8_)) + (portref C (instanceref bScratch_reg_9_)) + (portref C (instanceref bSpOffsetStored_reg_0_)) + (portref C (instanceref bSpOffsetStored_reg_10_)) + (portref C (instanceref bSpOffsetStored_reg_11_)) + (portref C (instanceref bSpOffsetStored_reg_12_)) + (portref C (instanceref bSpOffsetStored_reg_13_)) + (portref C (instanceref bSpOffsetStored_reg_14_)) + (portref C (instanceref bSpOffsetStored_reg_15_)) + (portref C (instanceref bSpOffsetStored_reg_16_)) + (portref C (instanceref bSpOffsetStored_reg_17_)) + (portref C (instanceref bSpOffsetStored_reg_18_)) + (portref C (instanceref bSpOffsetStored_reg_19_)) + (portref C (instanceref bSpOffsetStored_reg_1_)) + (portref C (instanceref bSpOffsetStored_reg_20_)) + (portref C (instanceref bSpOffsetStored_reg_21_)) + (portref C (instanceref bSpOffsetStored_reg_22_)) + (portref C (instanceref bSpOffsetStored_reg_23_)) + (portref C (instanceref bSpOffsetStored_reg_24_)) + (portref C (instanceref bSpOffsetStored_reg_25_)) + (portref C (instanceref bSpOffsetStored_reg_26_)) + (portref C (instanceref bSpOffsetStored_reg_27_)) + (portref C (instanceref bSpOffsetStored_reg_28_)) + (portref C (instanceref bSpOffsetStored_reg_29_)) + (portref C (instanceref bSpOffsetStored_reg_2_)) + (portref C (instanceref bSpOffsetStored_reg_30_)) + (portref C (instanceref bSpOffsetStored_reg_31_)) + (portref C (instanceref bSpOffsetStored_reg_3_)) + (portref C (instanceref bSpOffsetStored_reg_4_)) + (portref C (instanceref bSpOffsetStored_reg_5_)) + (portref C (instanceref bSpOffsetStored_reg_6_)) + (portref C (instanceref bSpOffsetStored_reg_7_)) + (portref C (instanceref bSpOffsetStored_reg_8_)) + (portref C (instanceref bSpOffsetStored_reg_9_)) + (portref BusClk) + ) + ) + (net (rename EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "EnableTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename EnableTdcDs_DoubleSyncBasex_iDlySig "EnableTdcDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename Gen0_FDCEx_i_1__10_n_0 "Gen0.FDCEx_i_1__10_n_0") (joined + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__10)) + ) + ) + (net (rename Gen0_FDCEx_i_1__11_n_0 "Gen0.FDCEx_i_1__11_n_0") (joined + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__11)) + ) + ) + (net (rename Gen0_FDCEx_i_1__9_n_0 "Gen0.FDCEx_i_1__9_n_0") (joined + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__9)) + ) + ) + (net (rename Gen0_FDCEx_i_3__0_n_0 "Gen0.FDCEx_i_3__0_n_0") (joined + (portref I0 (instanceref BlkIn_iDlyPush_i_1__1)) + (portref I0 (instanceref BlkIn_iDlyPush_i_1__2)) + (portref I3 (instanceref Gen0_FDCEx_i_1__1)) + (portref I3 (instanceref Gen0_FDCEx_i_1__2)) + (portref O (instanceref Gen0_FDCEx_i_3__0)) + ) + ) + (net (rename Gen0_FDCEx_i_3__1_n_0 "Gen0.FDCEx_i_3__1_n_0") (joined + (portref I0 (instanceref BlkIn_iDlyPush_i_1__3)) + (portref I0 (instanceref BlkIn_iDlyPush_i_1__4)) + (portref I3 (instanceref Gen0_FDCEx_i_1__3)) + (portref I3 (instanceref Gen0_FDCEx_i_1__4)) + (portref O (instanceref Gen0_FDCEx_i_3__1)) + ) + ) + (net (rename Gen0_FDCEx_i_3_n_0 "Gen0.FDCEx_i_3_n_0") (joined + (portref I0 (instanceref BlkIn_iDlyPush_i_1)) + (portref I0 (instanceref BlkIn_iDlyPush_i_1__0)) + (portref I3 (instanceref Gen0_FDCEx_i_1)) + (portref I3 (instanceref Gen0_FDCEx_i_1__0)) + (portref O (instanceref Gen0_FDCEx_i_3)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__0_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[0]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__10_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[10]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__11_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[11]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__12_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[12]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__13_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[13]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__14_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[14]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__15_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[15]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__16_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[16]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__17_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[17]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__18_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[18]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__19_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[19]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__1_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[1]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__20_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[20]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__21_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[21]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__22_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[22]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__23_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[23]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__24_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[24]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__25_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[25]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__26_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[26]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__27_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[27]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__28_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[28]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__29_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[29]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__2_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[2]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__30_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[30]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__31_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[31]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_31__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__32_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[32]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_32__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__33_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[33]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_33__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__34_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[34]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__35_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[35]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__36_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[36]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_36__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__37_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[37]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_37__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__38_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[38]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_38__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__39_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[39]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_39__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__3_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[3]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__40_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[40]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_40__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__41_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[41]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_41__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__42_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[42]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__43_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[43]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__44_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[44]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_44__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__45_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[45]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_45__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__46_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[46]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_46__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__47_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[47]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_47__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__48_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[48]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_48__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__49_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[49]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_49__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__4_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[4]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__50_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[50]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__51_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[51]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__52_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[52]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__53_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[53]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__54_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[54]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__55_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[55]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_55__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__56_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[56]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_56__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__57_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[57]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_57__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__58_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[58]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_58__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__59_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[59]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__5_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[5]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__60_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[60]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__61_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[61]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__62_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[62]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__63_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[63]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__64_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[64]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__65_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[65]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__66_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[66]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__67_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[67]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__68_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[68]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__69_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[69]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__6_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[6]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__70_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[70]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__71_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[71]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__72_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[72]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_72__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__73_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[73]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_73__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__74_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[74]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_74__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__75_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[75]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_75__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__76_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[76]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__77_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[77]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__78_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[78]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__79_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[79]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__7_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[7]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__8_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[8]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__9_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[9]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg_n_0 "IncomingOffsetHs/HBx/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__7)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename IncomingOffsetHs_HBx_iDlyPush "IncomingOffsetHs/HBx/iDlyPush") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__11)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename IncomingOffsetHs_HBx_iPushToggle "IncomingOffsetHs/HBx/iPushToggle") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__1)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename IncomingOffsetHs_HBx_iPushToggleNx "IncomingOffsetHs/HBx/iPushToggleNx") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__1)) + ) + ) + (net (rename IncomingOffsetHs_HBx_oPushToggle0_ms "IncomingOffsetHs/HBx/oPushToggle0_ms") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename IncomingOffsetHs_HBx_oPushToggle1 "IncomingOffsetHs/HBx/oPushToggle1") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__7)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename IncomingOffsetHs_HBx_oPushToggleChanged "IncomingOffsetHs/HBx/oPushToggleChanged") (joined + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_31__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_32__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_33__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_36__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_37__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_38__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_39__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_40__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_41__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_44__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_45__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_46__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_47__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_48__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_49__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_55__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_56__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_57__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_58__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_72__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_73__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_74__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_75__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_oDataValid_reg)) + (portref O (instanceref Gen0_FDCEx_i_1__7)) + ) + ) + (net MeasClk (joined + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref MeasClk) + ) + ) + (net (rename OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[0].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[10].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[11].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[12].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[13].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[14].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[15].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[16].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[17].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[18].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[19].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[1].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined 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OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[69].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[6].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[70].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[71].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[72].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[73].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[74].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[75].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[76].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[77].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[78].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[79].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[7].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[8].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[9].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_ms "OffsetsValidDs/DoubleSyncSlAsyncInx/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "PpsCapturedDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename PpsCapturedDs_DoubleSyncBasex_iDlySig "PpsCapturedDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "PpsCrossEnDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename PpsCrossEnDs_DoubleSyncBasex_iDlySig "PpsCrossEnDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref PpsCrossEnDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__0_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[0]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__1_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[1]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__2_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[2]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__3_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[3]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_iDlyPush "PpsDelayValCrossingHs/HBx/iDlyPush") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__9)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_iPushToggle "PpsDelayValCrossingHs/HBx/iPushToggle") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_iPushToggleNx "PpsDelayValCrossingHs/HBx/iPushToggleNx") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_oPushToggle0_ms "PpsDelayValCrossingHs/HBx/oPushToggle0_ms") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_oPushToggle1 "PpsDelayValCrossingHs/HBx/oPushToggle1") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__5)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_oPushToggleChanged "PpsDelayValCrossingHs/HBx/oPushToggleChanged") (joined + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref O (instanceref Gen0_FDCEx_i_1__5)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__0_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[0]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__1_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[1]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__2_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[2]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__3_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[3]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg_n_0 "PulserEnableDelayValCrossingHs/HBx/BlkOut.oDataValid_reg_n_0") (joined + (portref CE (instanceref rPulserEnableDelayVal_reg_0_)) + (portref CE (instanceref rPulserEnableDelayVal_reg_1_)) + (portref CE (instanceref rPulserEnableDelayVal_reg_2_)) + (portref CE (instanceref rPulserEnableDelayVal_reg_3_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg_n_0 "PulserEnableDelayValCrossingHs/HBx/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__6)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_iDlyPush "PulserEnableDelayValCrossingHs/HBx/iDlyPush") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__10)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_iPushToggle "PulserEnableDelayValCrossingHs/HBx/iPushToggle") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__0)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_iPushToggleNx "PulserEnableDelayValCrossingHs/HBx/iPushToggleNx") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__0)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_oPushToggle0_ms "PulserEnableDelayValCrossingHs/HBx/oPushToggle0_ms") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_oPushToggle1 "PulserEnableDelayValCrossingHs/HBx/oPushToggle1") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__6)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_oPushToggleChanged "PulserEnableDelayValCrossingHs/HBx/oPushToggleChanged") (joined + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref O (instanceref Gen0_FDCEx_i_1__6)) + ) + ) + (net (rename RePulse1CntHs_BlkIn_iDlyPush_reg_n_0 "RePulse1CntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__2)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename RePulse1CntHs_BlkOut_oPushToggle2_reg_n_0 "RePulse1CntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__8)) + (portref Q (instanceref RePulse1CntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename RePulse1CntHs_iPushPulse "RePulse1CntHs/iPushPulse") (joined + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__2)) + ) + ) + (net (rename RePulse1CntHs_iPushToggle "RePulse1CntHs/iPushToggle") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__4)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename RePulse1CntHs_iPushToggleNx "RePulse1CntHs/iPushToggleNx") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__4)) + ) + ) + (net (rename RePulse1CntHs_oPushToggle0_ms "RePulse1CntHs/oPushToggle0_ms") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulse1CntHs_oPushToggle1 "RePulse1CntHs/oPushToggle1") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__8)) + (portref Q (instanceref RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename RePulse1CntHs_oPushToggleChanged "RePulse1CntHs/oPushToggleChanged") (joined + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__8)) + ) + ) + (net (rename RePulse2CntHs_BlkIn_iDlyPush_reg_n_0 "RePulse2CntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__1)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename RePulse2CntHs_BlkOut_oPushToggle2_reg_n_0 "RePulse2CntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1__1)) + (portref Q (instanceref RePulse2CntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename RePulse2CntHs_iPushPulse "RePulse2CntHs/iPushPulse") (joined + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__1)) + ) + ) + (net (rename RePulse2CntHs_iPushToggle "RePulse2CntHs/iPushToggle") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__5)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename RePulse2CntHs_iPushToggleNx "RePulse2CntHs/iPushToggleNx") (joined + (portref D (instanceref RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__5)) + ) + ) + (net (rename RePulse2CntHs_oPushToggle0_ms "RePulse2CntHs/oPushToggle0_ms") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulse2CntHs_oPushToggle1 "RePulse2CntHs/oPushToggle1") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1__1)) + (portref Q (instanceref RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename RePulse2CntHs_oPushToggleChanged "RePulse2CntHs/oPushToggleChanged") (joined + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulse2CntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1__1)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[0].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[10].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[11].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[12].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[13].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[14].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[15].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[16].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[17].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[18].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[19].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[1].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[20].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[21].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[22].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[23].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[24].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[25].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[26].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[27].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[28].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[29].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[2].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[30].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[31].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[3].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[4].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[5].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[6].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[7].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[8].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[9].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[0].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[10].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[11].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[12].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[13].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[14].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[15].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[16].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[17].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[18].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[19].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[1].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[20].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[21].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[22].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[23].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[24].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[25].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[26].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[27].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[28].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[29].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[2].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[30].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[31].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[3].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[4].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[5].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[6].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[7].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[8].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[9].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "ReRunEnableDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename ReRunEnableDs_DoubleSyncBasex_iDlySig "ReRunEnableDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref ReRunEnableDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net RefClk (joined + (portref C (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref C (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref ResetDoneDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref C (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref rPulserEnableDelayVal_reg_0_)) + (portref C (instanceref rPulserEnableDelayVal_reg_1_)) + (portref C (instanceref rPulserEnableDelayVal_reg_2_)) + (portref C (instanceref rPulserEnableDelayVal_reg_3_)) + (portref RefClk) + ) + ) + (net RegWrite53_out (joined + (portref D (instanceref SptCntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1)) + ) + ) + (net RegWrite54_out (joined + (portref D (instanceref RptCntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__0)) + ) + ) + (net RegWrite55_out (joined + (portref D (instanceref RePulse2CntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__1)) + ) + ) + (net RegWrite56_out (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__2)) + ) + ) + (net RegWrite57_out (joined + (portref D (instanceref SpCntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__3)) + ) + ) + (net RegWrite58_out (joined + (portref D (instanceref RpCntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__4)) + ) + ) + (net (rename ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "ResetDoneDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename ResetDoneDs_DoubleSyncBasex_iDlySig "ResetDoneDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref ResetDoneDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "ResetTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename ResetTdcDs_DoubleSyncBasex_iDlySig "ResetTdcDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref ResetTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename RpCntHs_BlkOut_oPushToggle2_reg_n_0 "RpCntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1)) + (portref Q (instanceref RpCntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename RpCntHs_iPushPulse "RpCntHs/iPushPulse") (joined + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__4)) + ) + ) + (net (rename RpCntHs_iPushToggle "RpCntHs/iPushToggle") (joined + (portref D (instanceref RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__2)) + (portref Q (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename RpCntHs_iPushToggleNx "RpCntHs/iPushToggleNx") (joined + (portref D (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__2)) + ) + ) + (net (rename RpCntHs_oPushToggle0_ms "RpCntHs/oPushToggle0_ms") (joined + (portref D (instanceref RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntHs_oPushToggle1 "RpCntHs/oPushToggle1") (joined + (portref D (instanceref RpCntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1)) + (portref Q (instanceref RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename RpCntHs_oPushToggleChanged "RpCntHs/oPushToggleChanged") (joined + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1)) + ) + ) + (net (rename RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[0].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[10].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[11].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[12].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[13].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[14].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[15].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[16].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[17].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[18].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[19].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[1].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[20].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[21].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[22].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[23].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[24].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[25].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[26].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[27].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[28].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[29].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[2].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[30].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[31].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[3].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[4].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[5].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[6].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[7].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[8].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[9].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntHs_BlkIn_iDlyPush_reg_n_0 "RptCntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__0)) + (portref Q (instanceref RptCntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename RptCntHs_BlkOut_oPushToggle2_reg_n_0 "RptCntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1__2)) + (portref Q (instanceref RptCntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename RptCntHs_iPushPulse "RptCntHs/iPushPulse") (joined + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__0)) + ) + ) + (net (rename RptCntHs_iPushToggle "RptCntHs/iPushToggle") (joined + (portref D (instanceref RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__6)) + (portref Q (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename RptCntHs_iPushToggleNx "RptCntHs/iPushToggleNx") (joined + (portref D (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__6)) + ) + ) + (net (rename RptCntHs_oPushToggle0_ms "RptCntHs/oPushToggle0_ms") (joined + (portref D (instanceref RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntHs_oPushToggle1 "RptCntHs/oPushToggle1") (joined + (portref D (instanceref RptCntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1__2)) + (portref Q (instanceref RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename RptCntHs_oPushToggleChanged "RptCntHs/oPushToggleChanged") (joined + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1__2)) + ) + ) + (net (rename RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[0].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[10].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[11].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[12].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[13].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[14].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[15].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[16].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[17].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[18].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[19].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[1].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[20].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[21].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[22].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[23].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[24].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[25].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[26].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[27].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[28].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[29].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[2].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[30].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[31].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[3].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[4].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[5].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[6].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[7].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[8].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[9].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net SampleClk (joined + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref sPpsClkCrossDelayVal_reg_0_)) + (portref C (instanceref sPpsClkCrossDelayVal_reg_1_)) + (portref C (instanceref sPpsClkCrossDelayVal_reg_2_)) + (portref C (instanceref sPpsClkCrossDelayVal_reg_3_)) + (portref SampleClk) + ) + ) + (net (rename SpCntHs_BlkIn_iDlyPush_reg_n_0 "SpCntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__3)) + (portref Q (instanceref SpCntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename SpCntHs_BlkOut_oPushToggle2_reg_n_0 "SpCntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1__0)) + (portref Q (instanceref SpCntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename SpCntHs_iPushPulse "SpCntHs/iPushPulse") (joined + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__3)) + ) + ) + (net (rename SpCntHs_iPushToggle "SpCntHs/iPushToggle") (joined + (portref D (instanceref SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__3)) + (portref Q (instanceref SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename SpCntHs_iPushToggleNx "SpCntHs/iPushToggleNx") (joined + (portref D (instanceref SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__3)) + ) + ) + (net (rename SpCntHs_oPushToggle0_ms "SpCntHs/oPushToggle0_ms") (joined + (portref D (instanceref SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntHs_oPushToggle1 "SpCntHs/oPushToggle1") (joined + (portref D (instanceref SpCntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1__0)) + (portref Q (instanceref SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename SpCntHs_oPushToggleChanged "SpCntHs/oPushToggleChanged") (joined + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1__0)) + ) + ) + (net (rename SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[0].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[10].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[11].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[12].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[13].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[14].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[15].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[16].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[17].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[18].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[19].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[1].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[20].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[21].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[22].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[23].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[24].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[25].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[26].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[27].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[28].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[29].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[2].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[30].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[31].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[3].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[4].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[5].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[6].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[7].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[8].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[9].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntHs_BlkIn_iDlyPush_reg_n_0 "SptCntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1)) + (portref Q (instanceref SptCntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename SptCntHs_BlkOut_oPushToggle2_reg_n_0 "SptCntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1__3)) + (portref Q (instanceref SptCntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename SptCntHs_iPushPulse "SptCntHs/iPushPulse") (joined + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1)) + ) + ) + (net (rename SptCntHs_iPushToggle "SptCntHs/iPushToggle") (joined + (portref D (instanceref SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__7)) + (portref Q (instanceref SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename SptCntHs_iPushToggleNx "SptCntHs/iPushToggleNx") (joined + (portref D (instanceref SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__7)) + ) + ) + (net (rename SptCntHs_oPushToggle0_ms "SptCntHs/oPushToggle0_ms") (joined + (portref D (instanceref SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntHs_oPushToggle1 "SptCntHs/oPushToggle1") (joined + (portref D (instanceref SptCntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1__3)) + (portref Q (instanceref SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename SptCntHs_oPushToggleChanged "SptCntHs/oPushToggleChanged") (joined + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1__3)) + ) + ) + (net (rename SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[0].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[10].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[11].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[12].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[13].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[14].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[15].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[16].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[17].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[18].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[19].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[1].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[20].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[21].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[22].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[23].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[24].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[25].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[26].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[27].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[28].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[29].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[2].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[30].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[31].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[3].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[4].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[5].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[6].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[7].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[8].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[9].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net aBusReset (joined + (portref CLR (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCrossEnDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CLR (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref ReRunEnableDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref ResetTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref aTdcResetLcl_reg)) + (portref CLR (instanceref aTdcResetLcl_reg_rep)) + (portref CLR (instanceref aTdcResetLcl_reg_rep__0)) + (portref CLR (instanceref aTdcResetLcl_reg_rep__1)) + (portref CLR (instanceref aTdcResetLcl_reg_rep__2)) + (portref CLR (instanceref aTdcResetLcl_reg_rep__3)) + (portref CLR (instanceref bClearTdcRegs_reg)) + (portref CLR (instanceref bEnableTdc_reg)) + (portref CLR (instanceref bOffsetUpdated_reg)) + (portref CLR (instanceref bPpsClkCrossDelayVal_reg_0_)) + (portref CLR (instanceref bPpsClkCrossDelayVal_reg_1_)) + (portref CLR (instanceref bPpsClkCrossDelayVal_reg_2_)) + (portref CLR (instanceref bPpsClkCrossDelayVal_reg_3_)) + (portref CLR (instanceref bPpsClkCrossEn_reg)) + (portref CLR (instanceref bPulserEnableDelayVal_reg_1_)) + (portref CLR (instanceref bPulserEnableDelayVal_reg_2_)) + (portref CLR (instanceref bPulserEnableDelayVal_reg_3_)) + (portref CLR (instanceref bPushPpsDelayVal_reg)) + (portref CLR (instanceref bPushPulserEnableDelayVal_reg)) + (portref CLR (instanceref bReRunEnable_reg)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__0_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__10_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__11_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__12_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__13_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__14_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__15_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__16_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__17_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__18_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__19_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__1_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__20_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__21_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__22_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__23_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__24_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__25_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__26_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__27_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__28_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__29_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__2_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__30_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__31_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__3_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__4_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__5_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__6_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__7_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__8_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__9_)) + (portref CLR (instanceref bRpOffsetStored_reg_0_)) + (portref CLR (instanceref bRpOffsetStored_reg_10_)) + (portref CLR (instanceref bRpOffsetStored_reg_11_)) + (portref CLR (instanceref bRpOffsetStored_reg_12_)) + (portref CLR (instanceref bRpOffsetStored_reg_13_)) + (portref CLR (instanceref bRpOffsetStored_reg_14_)) + (portref CLR (instanceref bRpOffsetStored_reg_15_)) + (portref CLR (instanceref bRpOffsetStored_reg_16_)) + (portref CLR (instanceref bRpOffsetStored_reg_17_)) + (portref CLR (instanceref bRpOffsetStored_reg_18_)) + (portref CLR (instanceref bRpOffsetStored_reg_19_)) + (portref CLR (instanceref bRpOffsetStored_reg_1_)) + (portref CLR (instanceref bRpOffsetStored_reg_20_)) + (portref CLR (instanceref bRpOffsetStored_reg_21_)) + (portref CLR (instanceref bRpOffsetStored_reg_22_)) + (portref CLR (instanceref bRpOffsetStored_reg_23_)) + (portref CLR (instanceref bRpOffsetStored_reg_24_)) + (portref CLR (instanceref bRpOffsetStored_reg_25_)) + (portref CLR (instanceref bRpOffsetStored_reg_26_)) + (portref CLR (instanceref bRpOffsetStored_reg_27_)) + (portref CLR (instanceref bRpOffsetStored_reg_28_)) + (portref CLR (instanceref bRpOffsetStored_reg_29_)) + (portref CLR (instanceref bRpOffsetStored_reg_2_)) + (portref CLR (instanceref bRpOffsetStored_reg_30_)) + (portref CLR (instanceref bRpOffsetStored_reg_31_)) + (portref CLR (instanceref bRpOffsetStored_reg_32_)) + (portref CLR (instanceref bRpOffsetStored_reg_33_)) + (portref CLR (instanceref bRpOffsetStored_reg_34_)) + (portref CLR (instanceref bRpOffsetStored_reg_35_)) + (portref CLR (instanceref bRpOffsetStored_reg_36_)) + (portref CLR (instanceref bRpOffsetStored_reg_37_)) + (portref CLR (instanceref bRpOffsetStored_reg_38_)) + (portref CLR (instanceref bRpOffsetStored_reg_39_)) + (portref CLR (instanceref bRpOffsetStored_reg_3_)) + (portref CLR (instanceref bRpOffsetStored_reg_4_)) + (portref CLR (instanceref bRpOffsetStored_reg_5_)) + (portref CLR (instanceref bRpOffsetStored_reg_6_)) + (portref CLR (instanceref bRpOffsetStored_reg_7_)) + (portref CLR (instanceref bRpOffsetStored_reg_8_)) + (portref CLR (instanceref bRpOffsetStored_reg_9_)) + (portref CLR (instanceref bScratch_reg_0_)) + (portref CLR (instanceref bScratch_reg_10_)) + (portref CLR (instanceref bScratch_reg_11_)) + (portref CLR (instanceref bScratch_reg_12_)) + (portref CLR (instanceref bScratch_reg_13_)) + (portref CLR (instanceref bScratch_reg_14_)) + (portref CLR (instanceref bScratch_reg_15_)) + (portref CLR (instanceref bScratch_reg_16_)) + (portref CLR (instanceref bScratch_reg_17_)) + (portref CLR (instanceref bScratch_reg_18_)) + (portref CLR (instanceref bScratch_reg_19_)) + (portref CLR (instanceref bScratch_reg_1_)) + (portref CLR (instanceref bScratch_reg_20_)) + (portref CLR (instanceref bScratch_reg_21_)) + (portref CLR (instanceref bScratch_reg_22_)) + (portref CLR (instanceref bScratch_reg_23_)) + (portref CLR (instanceref bScratch_reg_24_)) + (portref CLR (instanceref bScratch_reg_25_)) + (portref CLR (instanceref bScratch_reg_26_)) + (portref CLR (instanceref bScratch_reg_27_)) + (portref CLR (instanceref bScratch_reg_28_)) + (portref CLR (instanceref bScratch_reg_29_)) + (portref CLR (instanceref bScratch_reg_2_)) + (portref CLR (instanceref bScratch_reg_30_)) + (portref CLR (instanceref bScratch_reg_31_)) + (portref CLR (instanceref bScratch_reg_3_)) + (portref CLR (instanceref bScratch_reg_4_)) + (portref CLR (instanceref bScratch_reg_5_)) + (portref CLR (instanceref bScratch_reg_6_)) + (portref CLR (instanceref bScratch_reg_7_)) + (portref CLR (instanceref bScratch_reg_8_)) + (portref CLR (instanceref bScratch_reg_9_)) + (portref CLR (instanceref bSpOffsetStored_reg_0_)) + (portref CLR (instanceref bSpOffsetStored_reg_10_)) + (portref CLR (instanceref bSpOffsetStored_reg_11_)) + (portref CLR (instanceref bSpOffsetStored_reg_12_)) + (portref CLR (instanceref bSpOffsetStored_reg_13_)) + (portref CLR (instanceref bSpOffsetStored_reg_14_)) + (portref CLR (instanceref bSpOffsetStored_reg_15_)) + (portref CLR (instanceref bSpOffsetStored_reg_16_)) + (portref CLR (instanceref bSpOffsetStored_reg_17_)) + (portref CLR (instanceref bSpOffsetStored_reg_18_)) + (portref CLR (instanceref bSpOffsetStored_reg_19_)) + (portref CLR (instanceref bSpOffsetStored_reg_1_)) + (portref CLR (instanceref bSpOffsetStored_reg_20_)) + (portref CLR (instanceref bSpOffsetStored_reg_21_)) + (portref CLR (instanceref bSpOffsetStored_reg_22_)) + (portref CLR (instanceref bSpOffsetStored_reg_23_)) + (portref CLR (instanceref bSpOffsetStored_reg_24_)) + (portref CLR (instanceref bSpOffsetStored_reg_25_)) + (portref CLR (instanceref bSpOffsetStored_reg_26_)) + (portref CLR (instanceref bSpOffsetStored_reg_27_)) + (portref CLR (instanceref bSpOffsetStored_reg_28_)) + (portref CLR (instanceref bSpOffsetStored_reg_29_)) + (portref CLR (instanceref bSpOffsetStored_reg_2_)) + (portref CLR (instanceref bSpOffsetStored_reg_30_)) + (portref CLR (instanceref bSpOffsetStored_reg_31_)) + (portref CLR (instanceref bSpOffsetStored_reg_3_)) + (portref CLR (instanceref bSpOffsetStored_reg_4_)) + (portref CLR (instanceref bSpOffsetStored_reg_5_)) + (portref CLR (instanceref bSpOffsetStored_reg_6_)) + (portref CLR (instanceref bSpOffsetStored_reg_7_)) + (portref CLR (instanceref bSpOffsetStored_reg_8_)) + (portref CLR (instanceref bSpOffsetStored_reg_9_)) + (portref CLR (instanceref rPulserEnableDelayVal_reg_1_)) + (portref CLR (instanceref rPulserEnableDelayVal_reg_2_)) + (portref CLR (instanceref rPulserEnableDelayVal_reg_3_)) + (portref CLR (instanceref sPpsClkCrossDelayVal_reg_0_)) + (portref CLR (instanceref sPpsClkCrossDelayVal_reg_1_)) + (portref CLR (instanceref sPpsClkCrossDelayVal_reg_2_)) + (portref CLR (instanceref sPpsClkCrossDelayVal_reg_3_)) + (portref PRE (instanceref bPulserEnableDelayVal_reg_0_)) + (portref PRE (instanceref bResetTdc_reg)) + (portref PRE (instanceref rPulserEnableDelayVal_reg_0_)) + (portref aBusReset) + ) + ) + (net aTdcReset (joined + (portref CLR (instanceref RptCntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I3 (instanceref aTdcResetLcl_i_1)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1__0)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1__1)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1__2)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1__3)) + (portref Q (instanceref aTdcResetLcl_reg)) + (portref aTdcReset) + ) + ) + (net aTdcResetLcl_i_1_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg)) + (portref O (instanceref aTdcResetLcl_i_1)) + ) + ) + (net aTdcResetLcl_i_2_n_0 (joined + (portref I1 (instanceref aTdcResetLcl_i_1)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1__0)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1__1)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1__2)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1__3)) + (portref O (instanceref aTdcResetLcl_i_2)) + ) + ) + (net aTdcResetLcl_i_3_n_0 (joined + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_7)) + (portref I1 (instanceref bRegPortOutLcl_Data__28__i_5)) + (portref I1 (instanceref bRegPortOutLcl_Data__28__i_7)) + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_11)) + (portref I2 (instanceref aTdcResetLcl_i_1)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1__0)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1__1)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1__2)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1__3)) + (portref I2 (instanceref bRegPortOutLcl_Data__0__i_7)) + (portref I2 (instanceref bRegPortOutLcl_Data__25__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_6)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_7)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_8)) + (portref I2 (instanceref bRegPortOutLcl_Data__7__i_6)) + (portref I2 (instanceref bRegPortOutLcl_Data__8__i_6)) + (portref I5 (instanceref bPushPpsDelayVal_i_1)) + (portref I5 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref O (instanceref aTdcResetLcl_i_3)) + ) + ) + (net aTdcResetLcl_i_4_n_0 (joined + (portref I1 (instanceref bRpOffsetStored_39__i_3)) + (portref I2 (instanceref aTdcResetLcl_i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__28__i_8)) + (portref I2 (instanceref bRegPortOutLcl_Data__30__i_6)) + (portref O (instanceref aTdcResetLcl_i_4)) + ) + ) + (net aTdcResetLcl_i_5_n_0 (joined + (portref I0 (instanceref bRpOffsetStored_39__i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__30__i_6)) + (portref I3 (instanceref aTdcResetLcl_i_3)) + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_8)) + (portref O (instanceref aTdcResetLcl_i_5)) + ) + ) + (net aTdcResetLcl_reg_rep__0_n_0 (joined + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_31__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_32__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_33__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_36__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_37__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_38__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_39__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_40__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_41__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_44__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_45__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_46__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_47__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_48__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_49__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_55__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_56__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_57__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_58__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_72__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_73__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_74__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_75__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_oDataValid_reg)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep__0)) + ) + ) + (net aTdcResetLcl_reg_rep__1_n_0 (joined + (portref CLR (instanceref RpCntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep__1)) + ) + ) + (net aTdcResetLcl_reg_rep__2_n_0 (joined + (portref CLR (instanceref RePulse1CntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep__2)) + ) + ) + (net aTdcResetLcl_reg_rep__3_n_0 (joined + (portref CLR (instanceref SptCntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep__3)) + ) + ) + (net aTdcResetLcl_reg_rep_n_0 (joined + (portref CLR (instanceref SpCntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep)) + ) + ) + (net aTdcResetLcl_rep_i_1__0_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep__0)) + (portref O (instanceref aTdcResetLcl_rep_i_1__0)) + ) + ) + (net aTdcResetLcl_rep_i_1__1_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep__1)) + (portref O (instanceref aTdcResetLcl_rep_i_1__1)) + ) + ) + (net aTdcResetLcl_rep_i_1__2_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep__2)) + (portref O (instanceref aTdcResetLcl_rep_i_1__2)) + ) + ) + (net aTdcResetLcl_rep_i_1__3_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep__3)) + (portref O (instanceref aTdcResetLcl_rep_i_1__3)) + ) + ) + (net aTdcResetLcl_rep_i_1_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep)) + (portref O (instanceref aTdcResetLcl_rep_i_1)) + ) + ) + (net bBusReset (joined + (portref I0 (instanceref bOffsetUpdated_i_1)) + (portref I0 (instanceref bPulserEnableDelayVal_0__i_1)) + (portref I0 (instanceref bRegPortOutLcl_Data__30__i_6)) + (portref I1 (instanceref bEnableTdc_i_1)) + (portref I1 (instanceref bPpsClkCrossDelayVal_0__i_1)) + (portref I1 (instanceref bPpsClkCrossDelayVal_1__i_1)) + (portref I1 (instanceref bPpsClkCrossDelayVal_2__i_1)) + (portref I1 (instanceref bPpsClkCrossDelayVal_3__i_2)) + (portref I1 (instanceref bPpsClkCrossEn_i_1)) + (portref I1 (instanceref bPulserEnableDelayVal_1__i_1)) + (portref I1 (instanceref bPulserEnableDelayVal_2__i_1)) + (portref I1 (instanceref bPulserEnableDelayVal_3__i_2)) + (portref I1 (instanceref bReRunEnable_i_1)) + (portref I1 (instanceref bResetTdc_i_1)) + (portref I1 (instanceref bRpOffsetStored_0__i_1)) + (portref I1 (instanceref bRpOffsetStored_10__i_1)) + (portref I1 (instanceref bRpOffsetStored_11__i_1)) + (portref I1 (instanceref bRpOffsetStored_12__i_1)) + (portref I1 (instanceref bRpOffsetStored_13__i_1)) + (portref I1 (instanceref bRpOffsetStored_14__i_1)) + (portref I1 (instanceref bRpOffsetStored_15__i_1)) + (portref I1 (instanceref bRpOffsetStored_16__i_1)) + (portref I1 (instanceref bRpOffsetStored_17__i_1)) + (portref I1 (instanceref bRpOffsetStored_18__i_1)) + (portref I1 (instanceref bRpOffsetStored_19__i_1)) + (portref I1 (instanceref bRpOffsetStored_1__i_1)) + (portref I1 (instanceref bRpOffsetStored_20__i_1)) + (portref I1 (instanceref bRpOffsetStored_21__i_1)) + (portref I1 (instanceref bRpOffsetStored_22__i_1)) + (portref I1 (instanceref bRpOffsetStored_23__i_1)) + (portref I1 (instanceref bRpOffsetStored_24__i_1)) + (portref I1 (instanceref bRpOffsetStored_25__i_1)) + (portref I1 (instanceref bRpOffsetStored_26__i_1)) + (portref I1 (instanceref bRpOffsetStored_27__i_1)) + (portref I1 (instanceref bRpOffsetStored_28__i_1)) + (portref I1 (instanceref bRpOffsetStored_29__i_1)) + (portref I1 (instanceref bRpOffsetStored_2__i_1)) + (portref I1 (instanceref bRpOffsetStored_30__i_1)) + (portref I1 (instanceref bRpOffsetStored_31__i_1)) + (portref I1 (instanceref bRpOffsetStored_32__i_1)) + (portref I1 (instanceref bRpOffsetStored_33__i_1)) + (portref I1 (instanceref bRpOffsetStored_34__i_1)) + (portref I1 (instanceref bRpOffsetStored_35__i_1)) + (portref I1 (instanceref bRpOffsetStored_36__i_1)) + (portref I1 (instanceref bRpOffsetStored_37__i_1)) + (portref I1 (instanceref bRpOffsetStored_38__i_1)) + (portref I1 (instanceref bRpOffsetStored_39__i_2)) + (portref I1 (instanceref bRpOffsetStored_3__i_1)) + (portref I1 (instanceref bRpOffsetStored_4__i_1)) + (portref I1 (instanceref bRpOffsetStored_5__i_1)) + (portref I1 (instanceref bRpOffsetStored_6__i_1)) + (portref I1 (instanceref bRpOffsetStored_7__i_1)) + (portref I1 (instanceref bRpOffsetStored_8__i_1)) + (portref I1 (instanceref bRpOffsetStored_9__i_1)) + (portref I1 (instanceref bScratch_0__i_1)) + (portref I1 (instanceref bScratch_10__i_1)) + (portref I1 (instanceref bScratch_11__i_1)) + (portref I1 (instanceref bScratch_12__i_1)) + (portref I1 (instanceref bScratch_13__i_1)) + (portref I1 (instanceref bScratch_14__i_1)) + (portref I1 (instanceref bScratch_15__i_1)) + (portref I1 (instanceref bScratch_1__i_1)) + (portref I1 (instanceref bScratch_20__i_1)) + (portref I1 (instanceref bScratch_21__i_1)) + (portref I1 (instanceref bScratch_22__i_1)) + (portref I1 (instanceref bScratch_23__i_1)) + (portref I1 (instanceref bScratch_24__i_1)) + (portref I1 (instanceref bScratch_28__i_1)) + (portref I1 (instanceref bScratch_29__i_1)) + (portref I1 (instanceref bScratch_2__i_1)) + (portref I1 (instanceref bScratch_30__i_1)) + (portref I1 (instanceref bScratch_31__i_2)) + (portref I1 (instanceref bScratch_31__i_5)) + (portref I1 (instanceref bScratch_3__i_1)) + (portref I1 (instanceref bScratch_4__i_1)) + (portref I1 (instanceref bScratch_5__i_1)) + (portref I1 (instanceref bScratch_6__i_1)) + (portref I1 (instanceref bScratch_7__i_1)) + (portref I1 (instanceref bScratch_8__i_1)) + (portref I1 (instanceref bScratch_9__i_1)) + (portref I1 (instanceref bSpOffsetStored_0__i_1)) + (portref I1 (instanceref bSpOffsetStored_10__i_1)) + (portref I1 (instanceref bSpOffsetStored_11__i_1)) + (portref I1 (instanceref bSpOffsetStored_12__i_1)) + (portref I1 (instanceref bSpOffsetStored_13__i_1)) + (portref I1 (instanceref bSpOffsetStored_14__i_1)) + (portref I1 (instanceref bSpOffsetStored_15__i_1)) + (portref I1 (instanceref bSpOffsetStored_16__i_1)) + (portref I1 (instanceref bSpOffsetStored_17__i_1)) + (portref I1 (instanceref bSpOffsetStored_18__i_1)) + (portref I1 (instanceref bSpOffsetStored_19__i_1)) + (portref I1 (instanceref bSpOffsetStored_1__i_1)) + (portref I1 (instanceref bSpOffsetStored_20__i_1)) + (portref I1 (instanceref bSpOffsetStored_21__i_1)) + (portref I1 (instanceref bSpOffsetStored_22__i_1)) + (portref I1 (instanceref bSpOffsetStored_23__i_1)) + (portref I1 (instanceref bSpOffsetStored_24__i_1)) + (portref I1 (instanceref bSpOffsetStored_25__i_1)) + (portref I1 (instanceref bSpOffsetStored_26__i_1)) + (portref I1 (instanceref bSpOffsetStored_27__i_1)) + (portref I1 (instanceref bSpOffsetStored_28__i_1)) + (portref I1 (instanceref bSpOffsetStored_29__i_1)) + (portref I1 (instanceref bSpOffsetStored_2__i_1)) + (portref I1 (instanceref bSpOffsetStored_30__i_1)) + (portref I1 (instanceref bSpOffsetStored_31__i_1)) + (portref I1 (instanceref bSpOffsetStored_3__i_1)) + (portref I1 (instanceref bSpOffsetStored_4__i_1)) + (portref I1 (instanceref bSpOffsetStored_5__i_1)) + (portref I1 (instanceref bSpOffsetStored_6__i_1)) + (portref I1 (instanceref bSpOffsetStored_7__i_1)) + (portref I1 (instanceref bSpOffsetStored_8__i_1)) + (portref I1 (instanceref bSpOffsetStored_9__i_1)) + (portref I2 (instanceref bPpsClkCrossDelayVal_3__i_1)) + (portref I2 (instanceref bPulserEnableDelayVal_3__i_1)) + (portref I3 (instanceref bClearTdcRegs_i_1)) + (portref I4 (instanceref aTdcResetLcl_i_3)) + (portref I4 (instanceref bRegPortOutLcl_Data__28__i_8)) + (portref I4 (instanceref bRpOffsetStored_39__i_1)) + (portref bBusReset) + ) + ) + (net bClearTdcRegs (joined + (portref D (instanceref bScratch_reg_0_)) + (portref O (instanceref bScratch_0__i_1)) + ) + ) + (net bClearTdcRegs_i_1_n_0 (joined + (portref D (instanceref bClearTdcRegs_reg)) + (portref O (instanceref bClearTdcRegs_i_1)) + ) + ) + (net bClearTdcRegs_i_2_n_0 (joined + (portref I2 (instanceref bClearTdcRegs_i_1)) + (portref O (instanceref bClearTdcRegs_i_2)) + ) + ) + (net bClearTdcRegs_i_3_n_0 (joined + (portref I0 (instanceref bClearTdcRegs_i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_7)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_9)) + (portref O (instanceref bClearTdcRegs_i_3)) + ) + ) + (net bClearTdcRegs_reg_n_0 (joined + (portref I0 (instanceref bEnableTdc_i_1)) + (portref I0 (instanceref bPpsClkCrossEn_i_1)) + (portref I0 (instanceref bReRunEnable_i_1)) + (portref I0 (instanceref bResetTdc_i_1)) + (portref I0 (instanceref bScratch_31__i_5)) + (portref I1 (instanceref bPulserEnableDelayVal_0__i_1)) + (portref I2 (instanceref aTdcResetLcl_i_2)) + (portref I2 (instanceref bPpsClkCrossDelayVal_0__i_1)) + (portref I2 (instanceref bPpsClkCrossDelayVal_1__i_1)) + (portref I2 (instanceref bPpsClkCrossDelayVal_2__i_1)) + (portref I2 (instanceref bPpsClkCrossDelayVal_3__i_2)) + (portref I2 (instanceref bPulserEnableDelayVal_1__i_1)) + (portref I2 (instanceref bPulserEnableDelayVal_2__i_1)) + (portref I2 (instanceref bPulserEnableDelayVal_3__i_2)) + (portref I2 (instanceref bScratch_0__i_1)) + (portref I2 (instanceref bScratch_10__i_1)) + (portref I2 (instanceref bScratch_11__i_1)) + (portref I2 (instanceref bScratch_12__i_1)) + (portref I2 (instanceref bScratch_13__i_1)) + (portref I2 (instanceref bScratch_14__i_1)) + (portref I2 (instanceref bScratch_15__i_1)) + (portref I2 (instanceref bScratch_1__i_1)) + (portref I2 (instanceref bScratch_20__i_1)) + (portref I2 (instanceref bScratch_21__i_1)) + (portref I2 (instanceref bScratch_22__i_1)) + (portref I2 (instanceref bScratch_23__i_1)) + (portref I2 (instanceref bScratch_24__i_1)) + (portref I2 (instanceref bScratch_28__i_1)) + (portref I2 (instanceref bScratch_29__i_1)) + (portref I2 (instanceref bScratch_2__i_1)) + (portref I2 (instanceref bScratch_30__i_1)) + (portref I2 (instanceref bScratch_31__i_2)) + (portref I2 (instanceref bScratch_3__i_1)) + (portref I2 (instanceref bScratch_4__i_1)) + (portref I2 (instanceref bScratch_5__i_1)) + (portref I2 (instanceref bScratch_6__i_1)) + (portref I2 (instanceref bScratch_7__i_1)) + (portref I2 (instanceref bScratch_8__i_1)) + (portref I2 (instanceref bScratch_9__i_1)) + (portref I3 (instanceref bPpsClkCrossDelayVal_3__i_1)) + (portref I3 (instanceref bPulserEnableDelayVal_3__i_1)) + (portref I3 (instanceref bPushPpsDelayVal_i_1)) + (portref I3 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref I4 (instanceref bClearTdcRegs_i_1)) + (portref Q (instanceref bClearTdcRegs_reg)) + ) + ) + (net bEnableTdc (joined + (portref D (instanceref bScratch_reg_4_)) + (portref O (instanceref bScratch_4__i_1)) + ) + ) + (net bEnableTdc_i_1_n_0 (joined + (portref D (instanceref bEnableTdc_reg)) + (portref O (instanceref bEnableTdc_i_1)) + ) + ) + (net bEnableTdc_reg_n_0 (joined + (portref D (instanceref EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref I3 (instanceref bRegPortOutLcl_Data__5__i_2)) + (portref I5 (instanceref bEnableTdc_i_1)) + (portref I5 (instanceref bRegPortOutLcl_Data__4__i_5)) + (portref Q (instanceref bEnableTdc_reg)) + ) + ) + (net bOffsetUpdated_i_1_n_0 (joined + (portref D (instanceref bOffsetUpdated_reg)) + (portref O (instanceref bOffsetUpdated_i_1)) + ) + ) + (net bOffsetUpdated_reg_n_0 (joined + (portref I1 (instanceref bRegPortOutLcl_Data__8__i_2)) + (portref I4 (instanceref bOffsetUpdated_i_1)) + (portref Q (instanceref bOffsetUpdated_reg)) + ) + ) + (net bOffsetsValid (joined + (portref D (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_oDataValid_reg)) + ) + ) + (net bOffsetsValidSyncReset (joined + (portref I3 (instanceref bOffsetUpdated_i_1)) + (portref Q (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_0_ "bOffsets[0]") (joined + (portref D (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_10_ "bOffsets[10]") (joined + (portref D (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_11_ "bOffsets[11]") (joined + (portref D (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_12_ "bOffsets[12]") (joined + (portref D (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_13_ "bOffsets[13]") (joined + (portref D (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_14_ "bOffsets[14]") (joined + (portref D (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_15_ "bOffsets[15]") (joined + (portref D (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_16_ "bOffsets[16]") (joined + (portref D (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_17_ "bOffsets[17]") (joined + (portref D (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_18_ "bOffsets[18]") (joined + (portref D (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_19_ "bOffsets[19]") (joined + (portref D (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_1_ "bOffsets[1]") (joined + (portref D (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_20_ "bOffsets[20]") (joined + (portref D (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_21_ "bOffsets[21]") (joined + (portref D (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_22_ "bOffsets[22]") (joined + (portref D (instanceref OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_23_ "bOffsets[23]") (joined + (portref D (instanceref OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_24_ "bOffsets[24]") (joined + (portref D (instanceref OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_25_ "bOffsets[25]") (joined + (portref D (instanceref OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_26_ "bOffsets[26]") (joined + (portref D (instanceref OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_27_ "bOffsets[27]") (joined + (portref D (instanceref OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_28_ "bOffsets[28]") (joined + (portref D (instanceref OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_29_ "bOffsets[29]") (joined + (portref D (instanceref OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_2_ "bOffsets[2]") (joined + (portref D (instanceref OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_30_ "bOffsets[30]") (joined + (portref D (instanceref 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(portref D (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_35_ "bOffsets[35]") (joined + (portref D (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_36_ "bOffsets[36]") (joined + (portref D (instanceref OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_36__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_37_ "bOffsets[37]") (joined + (portref D (instanceref OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_37__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_38_ "bOffsets[38]") (joined + (portref D (instanceref OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_38__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_39_ "bOffsets[39]") (joined + (portref D (instanceref OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_39__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_3_ "bOffsets[3]") (joined + (portref D (instanceref OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_40_ "bOffsets[40]") (joined + (portref D (instanceref OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_40__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_41_ "bOffsets[41]") (joined + (portref D (instanceref OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_41__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_42_ "bOffsets[42]") (joined + (portref D (instanceref OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_43_ "bOffsets[43]") (joined + (portref D (instanceref OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_44_ "bOffsets[44]") (joined + (portref D (instanceref OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_44__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_45_ "bOffsets[45]") (joined + (portref D (instanceref OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_45__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_46_ "bOffsets[46]") (joined + (portref D (instanceref OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_46__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_47_ "bOffsets[47]") (joined + (portref D (instanceref OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_47__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_48_ "bOffsets[48]") (joined + (portref D (instanceref OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_48__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_49_ "bOffsets[49]") (joined + (portref D (instanceref OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_49__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_4_ "bOffsets[4]") (joined + (portref D (instanceref OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_50_ "bOffsets[50]") (joined + (portref D (instanceref OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_51_ "bOffsets[51]") (joined + (portref D (instanceref OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_52_ "bOffsets[52]") (joined + (portref D (instanceref OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_53_ "bOffsets[53]") (joined + (portref D (instanceref OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_54_ "bOffsets[54]") (joined + (portref D (instanceref OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_55_ "bOffsets[55]") (joined + (portref D (instanceref OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_55__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_56_ "bOffsets[56]") (joined + (portref D (instanceref OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_56__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_57_ "bOffsets[57]") (joined + (portref D (instanceref OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_57__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_58_ "bOffsets[58]") (joined + (portref D (instanceref OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_58__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_59_ "bOffsets[59]") (joined + (portref D (instanceref OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_5_ "bOffsets[5]") (joined + (portref D (instanceref OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_60_ "bOffsets[60]") (joined + (portref D (instanceref OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_61_ "bOffsets[61]") (joined + (portref D (instanceref OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_62_ "bOffsets[62]") (joined + (portref D (instanceref OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_63_ "bOffsets[63]") (joined + (portref D (instanceref OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_64_ "bOffsets[64]") (joined + (portref D (instanceref OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_65_ "bOffsets[65]") (joined + (portref D (instanceref OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_66_ "bOffsets[66]") (joined + (portref D (instanceref OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_67_ "bOffsets[67]") (joined + (portref D (instanceref OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_68_ "bOffsets[68]") (joined + (portref D (instanceref OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_69_ "bOffsets[69]") (joined + (portref D (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_6_ "bOffsets[6]") (joined + (portref D (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_70_ "bOffsets[70]") (joined + (portref D (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_71_ "bOffsets[71]") (joined + (portref D (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_72_ "bOffsets[72]") (joined + (portref D (instanceref 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(portref D (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_77_ "bOffsets[77]") (joined + (portref D (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_78_ "bOffsets[78]") (joined + (portref D (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_79_ "bOffsets[79]") (joined + (portref D (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_7_ "bOffsets[7]") (joined + (portref D (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_8_ "bOffsets[8]") (joined + (portref D (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_9_ "bOffsets[9]") (joined + (portref D (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bPpsClkCrossDelayVal_1__i_1_n_0 "bPpsClkCrossDelayVal[1]_i_1_n_0") (joined + (portref D (instanceref bPpsClkCrossDelayVal_reg_1_)) + (portref D (instanceref bScratch_reg_17_)) + (portref O (instanceref bPpsClkCrossDelayVal_1__i_1)) + ) + ) + (net (rename bPpsClkCrossDelayVal_2__i_1_n_0 "bPpsClkCrossDelayVal[2]_i_1_n_0") (joined + (portref D (instanceref bPpsClkCrossDelayVal_reg_2_)) + (portref D (instanceref bScratch_reg_18_)) + (portref O (instanceref bPpsClkCrossDelayVal_2__i_1)) + ) + ) + (net (rename bPpsClkCrossDelayVal_3__i_1_n_0 "bPpsClkCrossDelayVal[3]_i_1_n_0") (joined + (portref CE (instanceref bPpsClkCrossDelayVal_reg_0_)) + (portref CE (instanceref bPpsClkCrossDelayVal_reg_1_)) + (portref CE (instanceref bPpsClkCrossDelayVal_reg_2_)) + (portref CE (instanceref bPpsClkCrossDelayVal_reg_3_)) + (portref O (instanceref bPpsClkCrossDelayVal_3__i_1)) + ) + ) + (net (rename bPpsClkCrossDelayVal_3__i_3_n_0 "bPpsClkCrossDelayVal[3]_i_3_n_0") (joined + (portref I1 (instanceref bPpsClkCrossDelayVal_3__i_1)) + (portref I1 (instanceref bPulserEnableDelayVal_3__i_1)) + (portref I4 (instanceref bEnableTdc_i_1)) + (portref I4 (instanceref bPpsClkCrossEn_i_1)) + (portref I4 (instanceref bReRunEnable_i_1)) + (portref I4 (instanceref bResetTdc_i_1)) + (portref O (instanceref bPpsClkCrossDelayVal_3__i_3)) + ) + ) + (net (rename bPpsClkCrossDelayVal_reg_n_0__0_ "bPpsClkCrossDelayVal_reg_n_0_[0]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref I2 (instanceref bRegPortOutLcl_Data__16__i_1)) + (portref Q (instanceref bPpsClkCrossDelayVal_reg_0_)) + ) + ) + (net (rename bPpsClkCrossDelayVal_reg_n_0__1_ "bPpsClkCrossDelayVal_reg_n_0_[1]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref I1 (instanceref bRegPortOutLcl_Data__17__i_3)) + (portref Q (instanceref bPpsClkCrossDelayVal_reg_1_)) + ) + ) + (net (rename bPpsClkCrossDelayVal_reg_n_0__2_ "bPpsClkCrossDelayVal_reg_n_0_[2]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref I1 (instanceref bRegPortOutLcl_Data__18__i_3)) + (portref Q (instanceref bPpsClkCrossDelayVal_reg_2_)) + ) + ) + (net (rename bPpsClkCrossDelayVal_reg_n_0__3_ "bPpsClkCrossDelayVal_reg_n_0_[3]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref I1 (instanceref bRegPortOutLcl_Data__19__i_1)) + (portref Q (instanceref bPpsClkCrossDelayVal_reg_3_)) + ) + ) + (net bPpsClkCrossEn (joined + (portref D (instanceref bScratch_reg_12_)) + (portref O (instanceref bScratch_12__i_1)) + ) + ) + (net bPpsClkCrossEn_i_1_n_0 (joined + (portref D (instanceref bPpsClkCrossEn_reg)) + (portref O (instanceref bPpsClkCrossEn_i_1)) + ) + ) + (net bPpsClkCrossEn_reg_n_0 (joined + (portref D (instanceref PpsCrossEnDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref I1 (instanceref bRegPortOutLcl_Data__12__i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__13__i_1)) + (portref I5 (instanceref bPpsClkCrossEn_i_1)) + (portref Q (instanceref bPpsClkCrossEn_reg)) + ) + ) + (net bPpsPulseCaptured (joined + (portref I0 (instanceref bRegPortOutLcl_Data__4__i_6)) + (portref Q (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bPulserEnableDelayVal_0__i_1_n_0 "bPulserEnableDelayVal[0]_i_1_n_0") (joined + (portref D (instanceref bPulserEnableDelayVal_reg_0_)) + (portref O (instanceref bPulserEnableDelayVal_0__i_1)) + ) + ) + (net (rename bPulserEnableDelayVal_2__i_1_n_0 "bPulserEnableDelayVal[2]_i_1_n_0") (joined + (portref D (instanceref bPulserEnableDelayVal_reg_2_)) + (portref D (instanceref bScratch_reg_26_)) + (portref O (instanceref bPulserEnableDelayVal_2__i_1)) + ) + ) + (net (rename bPulserEnableDelayVal_3__i_1_n_0 "bPulserEnableDelayVal[3]_i_1_n_0") (joined + (portref CE (instanceref bPulserEnableDelayVal_reg_0_)) + (portref CE (instanceref bPulserEnableDelayVal_reg_1_)) + (portref CE (instanceref bPulserEnableDelayVal_reg_2_)) + (portref CE (instanceref bPulserEnableDelayVal_reg_3_)) + (portref O (instanceref bPulserEnableDelayVal_3__i_1)) + ) + ) + (net (rename bPulserEnableDelayVal_3__i_2_n_0 "bPulserEnableDelayVal[3]_i_2_n_0") (joined + (portref D (instanceref bPulserEnableDelayVal_reg_3_)) + (portref D (instanceref bScratch_reg_27_)) + (portref O (instanceref bPulserEnableDelayVal_3__i_2)) + ) + ) + (net (rename bPulserEnableDelayVal_reg_n_0__0_ "bPulserEnableDelayVal_reg_n_0_[0]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref I1 (instanceref bRegPortOutLcl_Data__24__i_1)) + (portref Q (instanceref bPulserEnableDelayVal_reg_0_)) + ) + ) + (net (rename bPulserEnableDelayVal_reg_n_0__1_ "bPulserEnableDelayVal_reg_n_0_[1]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref I1 (instanceref bRegPortOutLcl_Data__25__i_1)) + (portref Q (instanceref bPulserEnableDelayVal_reg_1_)) + ) + ) + (net (rename bPulserEnableDelayVal_reg_n_0__2_ "bPulserEnableDelayVal_reg_n_0_[2]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref I1 (instanceref bRegPortOutLcl_Data__26__i_4)) + (portref Q (instanceref bPulserEnableDelayVal_reg_2_)) + ) + ) + (net (rename bPulserEnableDelayVal_reg_n_0__3_ "bPulserEnableDelayVal_reg_n_0_[3]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_5)) + (portref Q (instanceref bPulserEnableDelayVal_reg_3_)) + ) + ) + (net bPushPpsDelayVal (joined + (portref D (instanceref bPushPpsDelayVal_reg)) + (portref O (instanceref bPushPpsDelayVal_i_1)) + ) + ) + (net bPushPpsDelayVal_i_2_n_0 (joined + (portref I0 (instanceref bPushPpsDelayVal_i_1)) + (portref I0 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_6)) + (portref I0 (instanceref bRegPortOutLcl_Data__7__i_6)) + (portref I5 (instanceref aTdcResetLcl_i_2)) + (portref O (instanceref bPushPpsDelayVal_i_2)) + ) + ) + (net bPushPpsDelayVal_i_3_n_0 (joined + (portref I1 (instanceref bPushPpsDelayVal_i_1)) + (portref I1 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref O (instanceref bPushPpsDelayVal_i_3)) + ) + ) + (net bPushPpsDelayVal_i_4_n_0 (joined + (portref I0 (instanceref bRegPortOutLcl_Data__30__i_4)) + (portref I4 (instanceref bPushPpsDelayVal_i_1)) + (portref I4 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref I5 (instanceref bRegPortOutLcl_Data__25__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__27__i_7)) + (portref I5 (instanceref bRegPortOutLcl_Data__31__i_11)) + (portref O (instanceref bPushPpsDelayVal_i_4)) + ) + ) + (net bPushPpsDelayVal_reg_n_0 (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__9)) + (portref Q (instanceref bPushPpsDelayVal_reg)) + ) + ) + (net bPushPulserEnableDelayVal (joined + (portref D (instanceref bPushPulserEnableDelayVal_reg)) + (portref O (instanceref bPushPulserEnableDelayVal_i_1)) + ) + ) + (net bPushPulserEnableDelayVal_reg_n_0 (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__10)) + (portref Q (instanceref bPushPulserEnableDelayVal_reg)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_0_ "bRePulsePeriod1CtrlReadbackSyncReset[0]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__0__i_3)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_10_ "bRePulsePeriod1CtrlReadbackSyncReset[10]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_11_ "bRePulsePeriod1CtrlReadbackSyncReset[11]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__11__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_12_ "bRePulsePeriod1CtrlReadbackSyncReset[12]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__12__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_13_ "bRePulsePeriod1CtrlReadbackSyncReset[13]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__13__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_14_ "bRePulsePeriod1CtrlReadbackSyncReset[14]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__14__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_15_ "bRePulsePeriod1CtrlReadbackSyncReset[15]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__15__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_16_ "bRePulsePeriod1CtrlReadbackSyncReset[16]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_17_ "bRePulsePeriod1CtrlReadbackSyncReset[17]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__17__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_18_ "bRePulsePeriod1CtrlReadbackSyncReset[18]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__18__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_19_ "bRePulsePeriod1CtrlReadbackSyncReset[19]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__19__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_1_ "bRePulsePeriod1CtrlReadbackSyncReset[1]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_20_ "bRePulsePeriod1CtrlReadbackSyncReset[20]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__20__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_21_ "bRePulsePeriod1CtrlReadbackSyncReset[21]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__21__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_22_ "bRePulsePeriod1CtrlReadbackSyncReset[22]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__22__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_23_ "bRePulsePeriod1CtrlReadbackSyncReset[23]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__23__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_24_ "bRePulsePeriod1CtrlReadbackSyncReset[24]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__24__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_25_ "bRePulsePeriod1CtrlReadbackSyncReset[25]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__25__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_26_ "bRePulsePeriod1CtrlReadbackSyncReset[26]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__26__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_27_ "bRePulsePeriod1CtrlReadbackSyncReset[27]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__27__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_28_ "bRePulsePeriod1CtrlReadbackSyncReset[28]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_29_ "bRePulsePeriod1CtrlReadbackSyncReset[29]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__29__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_2_ "bRePulsePeriod1CtrlReadbackSyncReset[2]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_30_ "bRePulsePeriod1CtrlReadbackSyncReset[30]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__30__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_31_ "bRePulsePeriod1CtrlReadbackSyncReset[31]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_3_ "bRePulsePeriod1CtrlReadbackSyncReset[3]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_4_ "bRePulsePeriod1CtrlReadbackSyncReset[4]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_5_ "bRePulsePeriod1CtrlReadbackSyncReset[5]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_6_ "bRePulsePeriod1CtrlReadbackSyncReset[6]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__6__i_3)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_7_ "bRePulsePeriod1CtrlReadbackSyncReset[7]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__7__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_8_ "bRePulsePeriod1CtrlReadbackSyncReset[8]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__8__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_9_ "bRePulsePeriod1CtrlReadbackSyncReset[9]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__9__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_0_ "bRePulsePeriod1CtrlReadback[0]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_10_ "bRePulsePeriod1CtrlReadback[10]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_11_ "bRePulsePeriod1CtrlReadback[11]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_12_ "bRePulsePeriod1CtrlReadback[12]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_13_ "bRePulsePeriod1CtrlReadback[13]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_14_ "bRePulsePeriod1CtrlReadback[14]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_15_ "bRePulsePeriod1CtrlReadback[15]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_16_ "bRePulsePeriod1CtrlReadback[16]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_17_ "bRePulsePeriod1CtrlReadback[17]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_18_ "bRePulsePeriod1CtrlReadback[18]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_19_ "bRePulsePeriod1CtrlReadback[19]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_1_ "bRePulsePeriod1CtrlReadback[1]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_20_ "bRePulsePeriod1CtrlReadback[20]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_21_ "bRePulsePeriod1CtrlReadback[21]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_22_ "bRePulsePeriod1CtrlReadback[22]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_23_ "bRePulsePeriod1CtrlReadback[23]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_24_ "bRePulsePeriod1CtrlReadback[24]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_25_ "bRePulsePeriod1CtrlReadback[25]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_26_ "bRePulsePeriod1CtrlReadback[26]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_27_ "bRePulsePeriod1CtrlReadback[27]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_28_ "bRePulsePeriod1CtrlReadback[28]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_29_ "bRePulsePeriod1CtrlReadback[29]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_2_ "bRePulsePeriod1CtrlReadback[2]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_30_ "bRePulsePeriod1CtrlReadback[30]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_31_ "bRePulsePeriod1CtrlReadback[31]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_3_ "bRePulsePeriod1CtrlReadback[3]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_4_ "bRePulsePeriod1CtrlReadback[4]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_5_ "bRePulsePeriod1CtrlReadback[5]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_6_ "bRePulsePeriod1CtrlReadback[6]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_7_ "bRePulsePeriod1CtrlReadback[7]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_8_ "bRePulsePeriod1CtrlReadback[8]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_9_ "bRePulsePeriod1CtrlReadback[9]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_0_ "bRePulsePeriod2CtrlReadbackSyncReset[0]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__0__i_3)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_10_ "bRePulsePeriod2CtrlReadbackSyncReset[10]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__10__i_1)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_11_ "bRePulsePeriod2CtrlReadbackSyncReset[11]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__11__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_12_ "bRePulsePeriod2CtrlReadbackSyncReset[12]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__12__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_13_ "bRePulsePeriod2CtrlReadbackSyncReset[13]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__13__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_14_ "bRePulsePeriod2CtrlReadbackSyncReset[14]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__14__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_15_ "bRePulsePeriod2CtrlReadbackSyncReset[15]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__15__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_16_ "bRePulsePeriod2CtrlReadbackSyncReset[16]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__16__i_3)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_17_ "bRePulsePeriod2CtrlReadbackSyncReset[17]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__17__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_18_ "bRePulsePeriod2CtrlReadbackSyncReset[18]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__18__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_19_ "bRePulsePeriod2CtrlReadbackSyncReset[19]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__19__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_1_ "bRePulsePeriod2CtrlReadbackSyncReset[1]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__1__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_20_ "bRePulsePeriod2CtrlReadbackSyncReset[20]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__20__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_21_ "bRePulsePeriod2CtrlReadbackSyncReset[21]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__21__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_22_ "bRePulsePeriod2CtrlReadbackSyncReset[22]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__22__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_23_ "bRePulsePeriod2CtrlReadbackSyncReset[23]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__23__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_24_ "bRePulsePeriod2CtrlReadbackSyncReset[24]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__24__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_25_ "bRePulsePeriod2CtrlReadbackSyncReset[25]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__25__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_26_ "bRePulsePeriod2CtrlReadbackSyncReset[26]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__26__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_27_ "bRePulsePeriod2CtrlReadbackSyncReset[27]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__27__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_28_ "bRePulsePeriod2CtrlReadbackSyncReset[28]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_1)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_29_ "bRePulsePeriod2CtrlReadbackSyncReset[29]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__29__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_2_ "bRePulsePeriod2CtrlReadbackSyncReset[2]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__2__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_30_ "bRePulsePeriod2CtrlReadbackSyncReset[30]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__30__i_5)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_31_ "bRePulsePeriod2CtrlReadbackSyncReset[31]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__31__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_3_ "bRePulsePeriod2CtrlReadbackSyncReset[3]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__3__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_4_ "bRePulsePeriod2CtrlReadbackSyncReset[4]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__4__i_7)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_5_ "bRePulsePeriod2CtrlReadbackSyncReset[5]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__5__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_6_ "bRePulsePeriod2CtrlReadbackSyncReset[6]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__6__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_7_ "bRePulsePeriod2CtrlReadbackSyncReset[7]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__7__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_8_ "bRePulsePeriod2CtrlReadbackSyncReset[8]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__8__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_9_ "bRePulsePeriod2CtrlReadbackSyncReset[9]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__9__i_3)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_0_ "bRePulsePeriod2CtrlReadback[0]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_10_ "bRePulsePeriod2CtrlReadback[10]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_11_ "bRePulsePeriod2CtrlReadback[11]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_12_ "bRePulsePeriod2CtrlReadback[12]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_13_ "bRePulsePeriod2CtrlReadback[13]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_14_ "bRePulsePeriod2CtrlReadback[14]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_15_ "bRePulsePeriod2CtrlReadback[15]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_16_ "bRePulsePeriod2CtrlReadback[16]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_17_ "bRePulsePeriod2CtrlReadback[17]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_18_ "bRePulsePeriod2CtrlReadback[18]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_19_ "bRePulsePeriod2CtrlReadback[19]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_1_ "bRePulsePeriod2CtrlReadback[1]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_20_ "bRePulsePeriod2CtrlReadback[20]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_21_ "bRePulsePeriod2CtrlReadback[21]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_22_ "bRePulsePeriod2CtrlReadback[22]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_23_ "bRePulsePeriod2CtrlReadback[23]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_24_ "bRePulsePeriod2CtrlReadback[24]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_25_ "bRePulsePeriod2CtrlReadback[25]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_26_ "bRePulsePeriod2CtrlReadback[26]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_27_ "bRePulsePeriod2CtrlReadback[27]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_28_ "bRePulsePeriod2CtrlReadback[28]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_29_ "bRePulsePeriod2CtrlReadback[29]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_2_ "bRePulsePeriod2CtrlReadback[2]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_30_ "bRePulsePeriod2CtrlReadback[30]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_31_ "bRePulsePeriod2CtrlReadback[31]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_3_ "bRePulsePeriod2CtrlReadback[3]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_4_ "bRePulsePeriod2CtrlReadback[4]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_5_ "bRePulsePeriod2CtrlReadback[5]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_6_ "bRePulsePeriod2CtrlReadback[6]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_7_ "bRePulsePeriod2CtrlReadback[7]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_8_ "bRePulsePeriod2CtrlReadback[8]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_9_ "bRePulsePeriod2CtrlReadback[9]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net bReRunEnable (joined + (portref D (instanceref bScratch_reg_8_)) + (portref O (instanceref bScratch_8__i_1)) + ) + ) + (net bReRunEnable_i_1_n_0 (joined + (portref D (instanceref bReRunEnable_reg)) + (portref O (instanceref bReRunEnable_i_1)) + ) + ) + (net bReRunEnable_reg_n_0 (joined + (portref D (instanceref ReRunEnableDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref I1 (instanceref bRegPortOutLcl_Data__8__i_3)) + (portref I3 (instanceref bRegPortOutLcl_Data__9__i_3)) + (portref I5 (instanceref bReRunEnable_i_1)) + (portref Q (instanceref bReRunEnable_reg)) + ) + ) + (net (rename bRegPortInFlat_0_ "bRegPortInFlat[0]") (joined + (portref I0 (instanceref bPushPpsDelayVal_i_3)) + (portref I1 (instanceref bClearTdcRegs_i_2)) + (portref I1 (instanceref bScratch_31__i_3)) + (portref I4 (instanceref aTdcResetLcl_i_2)) + (portref (member bRegPortInFlat 49)) + ) + ) + (net (rename bRegPortInFlat_10_ "bRegPortInFlat[10]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref I0 (instanceref bScratch_8__i_1)) + (portref I3 (instanceref bReRunEnable_i_1)) + (portref (member bRegPortInFlat 39)) + ) + ) + (net (rename bRegPortInFlat_11_ "bRegPortInFlat[11]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref I0 (instanceref bScratch_9__i_1)) + (portref I2 (instanceref bReRunEnable_i_1)) + (portref (member bRegPortInFlat 38)) + ) + ) + (net (rename bRegPortInFlat_12_ "bRegPortInFlat[12]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref I0 (instanceref bScratch_10__i_1)) + (portref (member bRegPortInFlat 37)) + ) + ) + (net (rename bRegPortInFlat_13_ "bRegPortInFlat[13]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref I0 (instanceref bScratch_11__i_1)) + (portref (member bRegPortInFlat 36)) + ) + ) + (net (rename bRegPortInFlat_14_ "bRegPortInFlat[14]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref I0 (instanceref bScratch_12__i_1)) + (portref I3 (instanceref bPpsClkCrossEn_i_1)) + (portref (member bRegPortInFlat 35)) + ) + ) + (net (rename bRegPortInFlat_15_ "bRegPortInFlat[15]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref I0 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bRegPortOutLcl_Data__28__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__28__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__28__i_4_n_0 "bRegPortOutLcl[Data][28]_i_4_n_0") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__10__i_1)) + (portref I2 (instanceref bRegPortOutLcl_Data__28__i_1)) + (portref I4 (instanceref bRegPortOutLcl_Data__9__i_3)) + (portref O (instanceref bRegPortOutLcl_Data__28__i_4)) + ) + ) + (net (rename bRegPortOutLcl_Data__28__i_5_n_0 "bRegPortOutLcl[Data][28]_i_5_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__1__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__5__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__9__i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__2__i_4)) + (portref I1 (instanceref bRegPortOutLcl_Data__6__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__11__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__13__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__14__i_4)) + (portref I2 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"bRegPortOutLcl[Data][29]_i_1_n_0") (joined + (portref D (instanceref bRegPortOutLcl_reg_Data__29_)) + (portref O (instanceref bRegPortOutLcl_Data__29__i_1)) + ) + ) + (net (rename bRegPortOutLcl_Data__29__i_2_n_0 "bRegPortOutLcl[Data][29]_i_2_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__29__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__29__i_2)) + ) + ) + (net (rename bRegPortOutLcl_Data__29__i_3_n_0 "bRegPortOutLcl[Data][29]_i_3_n_0") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__29__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__29__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__29__i_4_n_0 "bRegPortOutLcl[Data][29]_i_4_n_0") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__29__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__29__i_4)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_1_n_0 "bRegPortOutLcl[Data][2]_i_1_n_0") (joined + (portref D (instanceref bRegPortOutLcl_reg_Data__2_)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_1)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_2_n_0 "bRegPortOutLcl[Data][2]_i_2_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_2)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_3_n_0 "bRegPortOutLcl[Data][2]_i_3_n_0") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_4_n_0 "bRegPortOutLcl[Data][2]_i_4_n_0") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_4)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_5_n_0 "bRegPortOutLcl[Data][2]_i_5_n_0") (joined + (portref I5 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_5)) + ) + ) + (net (rename bRegPortOutLcl_Data__30__i_1_n_0 "bRegPortOutLcl[Data][30]_i_1_n_0") (joined + (portref D (instanceref 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(instanceref bRegPortOutLcl_Data__30__i_6)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_10_n_0 "bRegPortOutLcl[Data][31]_i_10_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__0__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__12__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__17__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__18__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__26__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__27__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref I2 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref I2 (instanceref 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bRegPortOutLcl_Data__31__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_4_n_0 "bRegPortOutLcl[Data][31]_i_4_n_0") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_4)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_5_n_0 "bRegPortOutLcl[Data][31]_i_5_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__11__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__13__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__14__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__15__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__19__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__1__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__20__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__21__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__22__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__23__i_2)) + (portref I0 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bRegPortOutLcl_Data__26__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__27__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__8__i_3)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_5)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_6_n_0 "bRegPortOutLcl[Data][31]_i_6_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__0__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__11__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__12__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__13__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__14__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__15__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__17__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__18__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__19__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__20__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__21__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__22__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__23__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__24__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__25__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__26__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__27__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__29__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__30__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__8__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__1__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__2__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__3__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__4__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__5__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__6__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__7__i_3)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_6)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_7_n_0 "bRegPortOutLcl[Data][31]_i_7_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref I2 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__1__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__2__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__3__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__4__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__5__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__6__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__7__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__8__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__11__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__13__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__14__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__15__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__19__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__20__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__21__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__22__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__23__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__24__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__25__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__29__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__30__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__31__i_2)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_7)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_8_n_0 "bRegPortOutLcl[Data][31]_i_8_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__11__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__13__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__14__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__15__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__19__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__20__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__21__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__22__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__23__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__24__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__25__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__29__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__30__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref I5 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__1__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__2__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__3__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__4__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__5__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__6__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__7__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__8__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_8)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_9_n_0 "bRegPortOutLcl[Data][31]_i_9_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref I0 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__6__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__7__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__8__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__9__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__11__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__13__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__14__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__15__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__19__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__20__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__21__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__22__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__23__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__24__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__25__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__29__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__30__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_9)) + ) + ) + (net (rename bRegPortOutLcl_Data__3__i_1_n_0 "bRegPortOutLcl[Data][3]_i_1_n_0") (joined + (portref D (instanceref bRegPortOutLcl_reg_Data__3_)) + (portref O (instanceref bRegPortOutLcl_Data__3__i_1)) + ) + ) + (net (rename bRegPortOutLcl_Data__3__i_2_n_0 "bRegPortOutLcl[Data][3]_i_2_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__3__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__3__i_2)) + ) + ) + (net (rename bRegPortOutLcl_Data__3__i_3_n_0 "bRegPortOutLcl[Data][3]_i_3_n_0") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__3__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__3__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__3__i_4_n_0 "bRegPortOutLcl[Data][3]_i_4_n_0") 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(instanceref bRpOffsetStored_28__i_1)) + ) + ) + (net (rename bRpOffsetStored_29_ "bRpOffsetStored[29]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__29__i_2)) + (portref Q (instanceref bRpOffsetStored_reg_29_)) + ) + ) + (net (rename bRpOffsetStored_29__i_1_n_0 "bRpOffsetStored[29]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_29_)) + (portref O (instanceref bRpOffsetStored_29__i_1)) + ) + ) + (net (rename bRpOffsetStored_2_ "bRpOffsetStored[2]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__2__i_5)) + (portref Q (instanceref bRpOffsetStored_reg_2_)) + ) + ) + (net (rename bRpOffsetStored_2__i_1_n_0 "bRpOffsetStored[2]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_2_)) + (portref O (instanceref bRpOffsetStored_2__i_1)) + ) + ) + (net (rename bRpOffsetStored_30_ "bRpOffsetStored[30]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__30__i_2)) + (portref Q (instanceref bRpOffsetStored_reg_30_)) + ) + ) + (net (rename bRpOffsetStored_30__i_1_n_0 "bRpOffsetStored[30]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_30_)) + (portref O (instanceref bRpOffsetStored_30__i_1)) + ) + ) + (net (rename bRpOffsetStored_31_ "bRpOffsetStored[31]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_2)) + (portref Q (instanceref bRpOffsetStored_reg_31_)) + ) + ) + (net (rename bRpOffsetStored_31__i_1_n_0 "bRpOffsetStored[31]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_31_)) + (portref O (instanceref bRpOffsetStored_31__i_1)) + ) + ) + (net (rename bRpOffsetStored_32_ "bRpOffsetStored[32]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__0__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_32_)) + ) + ) + (net (rename bRpOffsetStored_32__i_1_n_0 "bRpOffsetStored[32]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_32_)) + (portref O (instanceref bRpOffsetStored_32__i_1)) + ) + ) + (net (rename bRpOffsetStored_33_ "bRpOffsetStored[33]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__1__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_33_)) + ) + ) + (net (rename bRpOffsetStored_33__i_1_n_0 "bRpOffsetStored[33]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_33_)) + (portref O (instanceref bRpOffsetStored_33__i_1)) + ) + ) + (net (rename bRpOffsetStored_34_ "bRpOffsetStored[34]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__2__i_5)) + (portref Q (instanceref bRpOffsetStored_reg_34_)) + ) + ) + (net (rename bRpOffsetStored_34__i_1_n_0 "bRpOffsetStored[34]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_34_)) + (portref O (instanceref bRpOffsetStored_34__i_1)) + ) + ) + (net (rename bRpOffsetStored_35_ "bRpOffsetStored[35]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__3__i_3)) + (portref Q (instanceref bRpOffsetStored_reg_35_)) + ) + ) + (net (rename bRpOffsetStored_35__i_1_n_0 "bRpOffsetStored[35]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_35_)) + (portref O (instanceref bRpOffsetStored_35__i_1)) + ) + ) + (net (rename bRpOffsetStored_36_ "bRpOffsetStored[36]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__4__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_36_)) + ) + ) + (net (rename bRpOffsetStored_36__i_1_n_0 "bRpOffsetStored[36]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_36_)) + (portref O (instanceref bRpOffsetStored_36__i_1)) + ) + ) + (net (rename bRpOffsetStored_37_ "bRpOffsetStored[37]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__5__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_37_)) + ) + ) + (net (rename bRpOffsetStored_37__i_1_n_0 "bRpOffsetStored[37]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_37_)) + (portref O (instanceref bRpOffsetStored_37__i_1)) + ) + ) + (net (rename bRpOffsetStored_38_ "bRpOffsetStored[38]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__6__i_5)) + (portref Q (instanceref bRpOffsetStored_reg_38_)) + ) + ) + (net (rename bRpOffsetStored_38__i_1_n_0 "bRpOffsetStored[38]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_38_)) + (portref O (instanceref bRpOffsetStored_38__i_1)) + ) + ) + (net (rename bRpOffsetStored_39_ "bRpOffsetStored[39]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__7__i_3)) + (portref Q (instanceref bRpOffsetStored_reg_39_)) + ) + ) + (net (rename bRpOffsetStored_39__i_2_n_0 "bRpOffsetStored[39]_i_2_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_39_)) + (portref O (instanceref bRpOffsetStored_39__i_2)) + ) + ) + (net (rename bRpOffsetStored_39__i_3_n_0 "bRpOffsetStored[39]_i_3_n_0") (joined + (portref I0 (instanceref bRpOffsetStored_39__i_1)) + (portref I1 (instanceref bClearTdcRegs_i_1)) + (portref I2 (instanceref bScratch_31__i_3)) + (portref O (instanceref bRpOffsetStored_39__i_3)) + ) + ) + (net (rename bRpOffsetStored_39__i_4_n_0 "bRpOffsetStored[39]_i_4_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__8__i_6)) + (portref I3 (instanceref bRpOffsetStored_39__i_1)) + (portref O (instanceref bRpOffsetStored_39__i_4)) + ) + ) + (net (rename bRpOffsetStored_3_ "bRpOffsetStored[3]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__3__i_3)) + (portref Q (instanceref bRpOffsetStored_reg_3_)) + ) + ) + (net (rename bRpOffsetStored_3__i_1_n_0 "bRpOffsetStored[3]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_3_)) + (portref O (instanceref bRpOffsetStored_3__i_1)) + ) + ) + (net (rename bRpOffsetStored_4_ "bRpOffsetStored[4]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__4__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_4_)) + ) + ) + (net (rename bRpOffsetStored_4__i_1_n_0 "bRpOffsetStored[4]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_4_)) + (portref O (instanceref bRpOffsetStored_4__i_1)) + ) + ) + (net (rename bRpOffsetStored_5_ "bRpOffsetStored[5]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__5__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_5_)) + ) + ) + (net (rename bRpOffsetStored_5__i_1_n_0 "bRpOffsetStored[5]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_5_)) + (portref O (instanceref bRpOffsetStored_5__i_1)) + ) + ) + (net (rename bRpOffsetStored_6_ "bRpOffsetStored[6]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__6__i_5)) + (portref Q (instanceref bRpOffsetStored_reg_6_)) + ) + ) + (net (rename bRpOffsetStored_6__i_1_n_0 "bRpOffsetStored[6]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_6_)) + (portref O (instanceref bRpOffsetStored_6__i_1)) + ) + ) + (net (rename bRpOffsetStored_7_ "bRpOffsetStored[7]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__7__i_3)) + (portref Q (instanceref bRpOffsetStored_reg_7_)) + ) + ) + (net (rename bRpOffsetStored_7__i_1_n_0 "bRpOffsetStored[7]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_7_)) + (portref O (instanceref bRpOffsetStored_7__i_1)) + ) + ) + (net (rename bRpOffsetStored_8_ "bRpOffsetStored[8]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__8__i_3)) + (portref Q (instanceref bRpOffsetStored_reg_8_)) + ) + ) + (net (rename bRpOffsetStored_8__i_1_n_0 "bRpOffsetStored[8]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_8_)) + (portref O (instanceref bRpOffsetStored_8__i_1)) + ) + ) + (net (rename bRpOffsetStored_9_ "bRpOffsetStored[9]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__9__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_9_)) + ) + ) + (net (rename bRpOffsetStored_9__i_1_n_0 "bRpOffsetStored[9]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_9_)) + (portref O (instanceref bRpOffsetStored_9__i_1)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_0_ "bRpPeriodCtrlReadbackSyncReset[0]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_10_ "bRpPeriodCtrlReadbackSyncReset[10]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_11_ "bRpPeriodCtrlReadbackSyncReset[11]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__11__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_12_ "bRpPeriodCtrlReadbackSyncReset[12]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref Q (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_13_ "bRpPeriodCtrlReadbackSyncReset[13]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__13__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_14_ "bRpPeriodCtrlReadbackSyncReset[14]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__14__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_15_ "bRpPeriodCtrlReadbackSyncReset[15]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__15__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_16_ "bRpPeriodCtrlReadbackSyncReset[16]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref Q (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_17_ "bRpPeriodCtrlReadbackSyncReset[17]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref Q (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_18_ "bRpPeriodCtrlReadbackSyncReset[18]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref Q (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_19_ "bRpPeriodCtrlReadbackSyncReset[19]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__19__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_1_ "bRpPeriodCtrlReadbackSyncReset[1]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__1__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_20_ "bRpPeriodCtrlReadbackSyncReset[20]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__20__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_21_ "bRpPeriodCtrlReadbackSyncReset[21]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__21__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_22_ "bRpPeriodCtrlReadbackSyncReset[22]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__22__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_23_ "bRpPeriodCtrlReadbackSyncReset[23]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__23__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_24_ "bRpPeriodCtrlReadbackSyncReset[24]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__24__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_25_ "bRpPeriodCtrlReadbackSyncReset[25]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__25__i_4)) + (portref Q (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_26_ "bRpPeriodCtrlReadbackSyncReset[26]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref Q (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_27_ "bRpPeriodCtrlReadbackSyncReset[27]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref Q (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_28_ "bRpPeriodCtrlReadbackSyncReset[28]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_29_ "bRpPeriodCtrlReadbackSyncReset[29]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__29__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_2_ "bRpPeriodCtrlReadbackSyncReset[2]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__2__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_30_ "bRpPeriodCtrlReadbackSyncReset[30]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__30__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_31_ "bRpPeriodCtrlReadbackSyncReset[31]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_3_ "bRpPeriodCtrlReadbackSyncReset[3]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__3__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_4_ "bRpPeriodCtrlReadbackSyncReset[4]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__4__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_5_ "bRpPeriodCtrlReadbackSyncReset[5]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__5__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_6_ "bRpPeriodCtrlReadbackSyncReset[6]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__6__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_7_ "bRpPeriodCtrlReadbackSyncReset[7]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__7__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_8_ "bRpPeriodCtrlReadbackSyncReset[8]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__8__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_9_ "bRpPeriodCtrlReadbackSyncReset[9]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref Q (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadback_0_ "bRpPeriodCtrlReadback[0]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_10_ "bRpPeriodCtrlReadback[10]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_11_ "bRpPeriodCtrlReadback[11]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_12_ "bRpPeriodCtrlReadback[12]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_13_ "bRpPeriodCtrlReadback[13]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_14_ "bRpPeriodCtrlReadback[14]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_15_ "bRpPeriodCtrlReadback[15]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_16_ "bRpPeriodCtrlReadback[16]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_17_ "bRpPeriodCtrlReadback[17]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_18_ "bRpPeriodCtrlReadback[18]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_19_ "bRpPeriodCtrlReadback[19]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_1_ "bRpPeriodCtrlReadback[1]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_20_ "bRpPeriodCtrlReadback[20]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_21_ "bRpPeriodCtrlReadback[21]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_22_ "bRpPeriodCtrlReadback[22]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_23_ "bRpPeriodCtrlReadback[23]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_24_ "bRpPeriodCtrlReadback[24]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_25_ "bRpPeriodCtrlReadback[25]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_26_ "bRpPeriodCtrlReadback[26]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_27_ "bRpPeriodCtrlReadback[27]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_28_ "bRpPeriodCtrlReadback[28]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_29_ "bRpPeriodCtrlReadback[29]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_2_ "bRpPeriodCtrlReadback[2]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_30_ "bRpPeriodCtrlReadback[30]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_31_ "bRpPeriodCtrlReadback[31]") (joined + (portref D (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_3_ "bRpPeriodCtrlReadback[3]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_4_ "bRpPeriodCtrlReadback[4]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_5_ "bRpPeriodCtrlReadback[5]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_6_ "bRpPeriodCtrlReadback[6]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_7_ "bRpPeriodCtrlReadback[7]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_8_ "bRpPeriodCtrlReadback[8]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_9_ "bRpPeriodCtrlReadback[9]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_0_ "bRptPeriodCtrlReadbackSyncReset[0]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref Q (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_10_ "bRptPeriodCtrlReadbackSyncReset[10]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_11_ "bRptPeriodCtrlReadbackSyncReset[11]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__11__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_12_ "bRptPeriodCtrlReadbackSyncReset[12]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_13_ "bRptPeriodCtrlReadbackSyncReset[13]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__13__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_14_ "bRptPeriodCtrlReadbackSyncReset[14]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__14__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_15_ "bRptPeriodCtrlReadbackSyncReset[15]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__15__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_16_ "bRptPeriodCtrlReadbackSyncReset[16]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref Q (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_17_ "bRptPeriodCtrlReadbackSyncReset[17]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_18_ "bRptPeriodCtrlReadbackSyncReset[18]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_19_ "bRptPeriodCtrlReadbackSyncReset[19]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__19__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_1_ "bRptPeriodCtrlReadbackSyncReset[1]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_20_ "bRptPeriodCtrlReadbackSyncReset[20]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__20__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_21_ "bRptPeriodCtrlReadbackSyncReset[21]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__21__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_22_ "bRptPeriodCtrlReadbackSyncReset[22]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__22__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_23_ "bRptPeriodCtrlReadbackSyncReset[23]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__23__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_24_ "bRptPeriodCtrlReadbackSyncReset[24]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__24__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_25_ "bRptPeriodCtrlReadbackSyncReset[25]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__25__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_26_ "bRptPeriodCtrlReadbackSyncReset[26]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_27_ "bRptPeriodCtrlReadbackSyncReset[27]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref Q (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_28_ "bRptPeriodCtrlReadbackSyncReset[28]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref Q (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_29_ "bRptPeriodCtrlReadbackSyncReset[29]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__29__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_2_ "bRptPeriodCtrlReadbackSyncReset[2]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_30_ "bRptPeriodCtrlReadbackSyncReset[30]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__30__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_31_ "bRptPeriodCtrlReadbackSyncReset[31]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__31__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_3_ "bRptPeriodCtrlReadbackSyncReset[3]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_4_ "bRptPeriodCtrlReadbackSyncReset[4]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_5_ "bRptPeriodCtrlReadbackSyncReset[5]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_6_ "bRptPeriodCtrlReadbackSyncReset[6]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__6__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_7_ "bRptPeriodCtrlReadbackSyncReset[7]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__7__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_8_ "bRptPeriodCtrlReadbackSyncReset[8]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__8__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_9_ "bRptPeriodCtrlReadbackSyncReset[9]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__9__i_2)) + (portref Q (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadback_0_ "bRptPeriodCtrlReadback[0]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_10_ "bRptPeriodCtrlReadback[10]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_11_ "bRptPeriodCtrlReadback[11]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_12_ "bRptPeriodCtrlReadback[12]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_13_ "bRptPeriodCtrlReadback[13]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_14_ "bRptPeriodCtrlReadback[14]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_15_ "bRptPeriodCtrlReadback[15]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_16_ "bRptPeriodCtrlReadback[16]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_17_ "bRptPeriodCtrlReadback[17]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_18_ "bRptPeriodCtrlReadback[18]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_19_ "bRptPeriodCtrlReadback[19]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_1_ "bRptPeriodCtrlReadback[1]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_20_ "bRptPeriodCtrlReadback[20]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_21_ "bRptPeriodCtrlReadback[21]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_22_ "bRptPeriodCtrlReadback[22]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_23_ "bRptPeriodCtrlReadback[23]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_24_ "bRptPeriodCtrlReadback[24]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_25_ "bRptPeriodCtrlReadback[25]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_26_ "bRptPeriodCtrlReadback[26]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_27_ "bRptPeriodCtrlReadback[27]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_28_ "bRptPeriodCtrlReadback[28]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_29_ "bRptPeriodCtrlReadback[29]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_2_ "bRptPeriodCtrlReadback[2]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_30_ "bRptPeriodCtrlReadback[30]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_31_ "bRptPeriodCtrlReadback[31]") (joined + (portref D (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_3_ "bRptPeriodCtrlReadback[3]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_4_ "bRptPeriodCtrlReadback[4]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_5_ "bRptPeriodCtrlReadback[5]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_6_ "bRptPeriodCtrlReadback[6]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_7_ "bRptPeriodCtrlReadback[7]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_8_ "bRptPeriodCtrlReadback[8]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_9_ "bRptPeriodCtrlReadback[9]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename bScratch_0_ "bScratch[0]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__0__i_6)) + (portref Q (instanceref bScratch_reg_0_)) + ) + ) + (net (rename bScratch_10_ "bScratch[10]") (joined + (portref I5 (instanceref bRegPortOutLcl_Data__10__i_3)) + (portref Q (instanceref bScratch_reg_10_)) + ) + ) + (net (rename bScratch_11_ "bScratch[11]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__11__i_4)) + (portref Q (instanceref bScratch_reg_11_)) + ) + ) + (net (rename bScratch_12_ "bScratch[12]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__12__i_1)) + (portref Q (instanceref bScratch_reg_12_)) + ) + ) + (net (rename bScratch_13_ "bScratch[13]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__13__i_2)) + (portref Q (instanceref bScratch_reg_13_)) + ) + ) + (net (rename bScratch_14_ "bScratch[14]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__14__i_4)) + (portref Q (instanceref bScratch_reg_14_)) + ) + ) + (net (rename bScratch_15_ "bScratch[15]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__15__i_4)) + (portref Q (instanceref bScratch_reg_15_)) + ) + ) + (net (rename bScratch_16_ "bScratch[16]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__16__i_4)) + (portref Q (instanceref bScratch_reg_16_)) + ) + ) + (net (rename bScratch_17_ "bScratch[17]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__17__i_1)) + (portref Q (instanceref bScratch_reg_17_)) + ) + ) + (net (rename bScratch_18_ "bScratch[18]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__18__i_1)) + (portref Q (instanceref bScratch_reg_18_)) + ) + ) + (net (rename bScratch_19_ "bScratch[19]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__19__i_2)) + (portref Q (instanceref bScratch_reg_19_)) + ) + ) + (net (rename bScratch_1_ "bScratch[1]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__1__i_2)) + (portref Q (instanceref bScratch_reg_1_)) + ) + ) + (net (rename bScratch_20_ "bScratch[20]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__20__i_4)) + (portref Q (instanceref bScratch_reg_20_)) + ) + ) + (net (rename bScratch_21_ "bScratch[21]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__21__i_4)) + (portref Q (instanceref bScratch_reg_21_)) + ) + ) + (net (rename bScratch_22_ "bScratch[22]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__22__i_4)) + (portref Q (instanceref bScratch_reg_22_)) + ) + ) + (net (rename bScratch_23_ "bScratch[23]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__23__i_4)) + (portref Q (instanceref bScratch_reg_23_)) + ) + ) + (net (rename bScratch_24_ "bScratch[24]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__24__i_2)) + (portref Q (instanceref bScratch_reg_24_)) + ) + ) + (net (rename bScratch_25_ "bScratch[25]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__25__i_2)) + (portref Q (instanceref bScratch_reg_25_)) + ) + ) + (net (rename bScratch_26_ "bScratch[26]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__26__i_1)) + (portref Q (instanceref bScratch_reg_26_)) + ) + ) + (net (rename bScratch_27_ "bScratch[27]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_1)) + (portref Q (instanceref bScratch_reg_27_)) + ) + ) + (net (rename bScratch_28_ "bScratch[28]") (joined + (portref I5 (instanceref bRegPortOutLcl_Data__28__i_3)) + (portref Q (instanceref bScratch_reg_28_)) + ) + ) + (net (rename bScratch_29_ "bScratch[29]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__29__i_4)) + (portref Q (instanceref bScratch_reg_29_)) + ) + ) + (net (rename bScratch_2_ "bScratch[2]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref Q (instanceref bScratch_reg_2_)) + ) + ) + (net (rename bScratch_30_ "bScratch[30]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__30__i_5)) + (portref Q (instanceref bScratch_reg_30_)) + ) + ) + (net (rename bScratch_31_ "bScratch[31]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_4)) + (portref Q (instanceref bScratch_reg_31_)) + ) + ) + (net (rename bScratch_31__i_1_n_0 "bScratch[31]_i_1_n_0") (joined + (portref CE (instanceref bScratch_reg_0_)) + (portref CE (instanceref bScratch_reg_10_)) + (portref CE (instanceref bScratch_reg_11_)) + (portref CE (instanceref bScratch_reg_12_)) + (portref CE (instanceref bScratch_reg_13_)) + (portref CE (instanceref bScratch_reg_14_)) + (portref CE (instanceref bScratch_reg_15_)) + (portref CE (instanceref bScratch_reg_16_)) + (portref CE (instanceref bScratch_reg_17_)) + (portref CE (instanceref bScratch_reg_18_)) + (portref CE (instanceref bScratch_reg_19_)) + (portref CE (instanceref bScratch_reg_1_)) + (portref CE (instanceref bScratch_reg_20_)) + (portref CE (instanceref bScratch_reg_21_)) + (portref CE (instanceref bScratch_reg_22_)) + (portref CE (instanceref bScratch_reg_23_)) + (portref CE (instanceref bScratch_reg_24_)) + (portref CE (instanceref bScratch_reg_25_)) + (portref CE (instanceref bScratch_reg_26_)) + (portref CE (instanceref bScratch_reg_27_)) + (portref CE (instanceref bScratch_reg_28_)) + (portref CE (instanceref bScratch_reg_29_)) + (portref CE (instanceref bScratch_reg_2_)) + (portref CE (instanceref bScratch_reg_30_)) + (portref CE (instanceref bScratch_reg_31_)) + (portref CE (instanceref bScratch_reg_3_)) + (portref CE (instanceref bScratch_reg_4_)) + (portref CE (instanceref bScratch_reg_5_)) + (portref CE (instanceref bScratch_reg_6_)) + (portref CE (instanceref bScratch_reg_7_)) + (portref CE (instanceref bScratch_reg_8_)) + (portref CE (instanceref bScratch_reg_9_)) + (portref O (instanceref bScratch_31__i_1)) + ) + ) + (net (rename bScratch_31__i_3_n_0 "bScratch[31]_i_3_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_3__0)) + (portref I0 (instanceref Gen0_FDCEx_i_3__1)) + (portref I0 (instanceref bScratch_31__i_1)) + (portref I3 (instanceref Gen0_FDCEx_i_3)) + (portref I3 (instanceref bPpsClkCrossDelayVal_3__i_3)) + (portref O (instanceref bScratch_31__i_3)) + ) + ) + (net (rename bScratch_31__i_4_n_0 "bScratch[31]_i_4_n_0") (joined + (portref I2 (instanceref bScratch_31__i_1)) + (portref I5 (instanceref bRegPortOutLcl_Data__16__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__26__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__28__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__31__i_5)) + (portref O (instanceref bScratch_31__i_4)) + ) + ) + (net (rename bScratch_31__i_5_n_0 "bScratch[31]_i_5_n_0") (joined + (portref I5 (instanceref bScratch_31__i_1)) + (portref O (instanceref bScratch_31__i_5)) + ) + ) + (net (rename bScratch_3_ "bScratch[3]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__3__i_4)) + (portref Q (instanceref bScratch_reg_3_)) + ) + ) + (net (rename bScratch_4_ "bScratch[4]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__4__i_7)) + (portref Q (instanceref bScratch_reg_4_)) + ) + ) + (net (rename bScratch_5_ "bScratch[5]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__5__i_2)) + (portref Q (instanceref bScratch_reg_5_)) + ) + ) + (net (rename bScratch_6_ "bScratch[6]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__6__i_1)) + (portref Q (instanceref bScratch_reg_6_)) + ) + ) + (net (rename bScratch_7_ "bScratch[7]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__7__i_4)) + (portref Q (instanceref bScratch_reg_7_)) + ) + ) + (net (rename bScratch_8_ "bScratch[8]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__8__i_4)) + (portref Q (instanceref bScratch_reg_8_)) + ) + ) + (net (rename bScratch_9_ "bScratch[9]") (joined + (portref I5 (instanceref bRegPortOutLcl_Data__9__i_4)) + (portref Q (instanceref bScratch_reg_9_)) + ) + ) + (net bSpOffsetStored (joined + (portref CE (instanceref bRpOffsetStored_reg_0_)) + (portref CE (instanceref bRpOffsetStored_reg_10_)) + (portref CE (instanceref bRpOffsetStored_reg_11_)) + (portref CE (instanceref bRpOffsetStored_reg_12_)) + (portref CE (instanceref bRpOffsetStored_reg_13_)) + (portref CE (instanceref bRpOffsetStored_reg_14_)) + (portref CE (instanceref bRpOffsetStored_reg_15_)) + (portref CE (instanceref bRpOffsetStored_reg_16_)) + (portref CE (instanceref bRpOffsetStored_reg_17_)) + (portref CE (instanceref bRpOffsetStored_reg_18_)) + (portref CE (instanceref bRpOffsetStored_reg_19_)) + (portref CE (instanceref bRpOffsetStored_reg_1_)) + (portref CE (instanceref bRpOffsetStored_reg_20_)) + (portref CE (instanceref bRpOffsetStored_reg_21_)) + (portref CE (instanceref bRpOffsetStored_reg_22_)) + (portref CE (instanceref bRpOffsetStored_reg_23_)) + (portref CE (instanceref bRpOffsetStored_reg_24_)) + (portref CE (instanceref bRpOffsetStored_reg_25_)) + (portref CE (instanceref bRpOffsetStored_reg_26_)) + (portref CE (instanceref bRpOffsetStored_reg_27_)) + (portref CE (instanceref bRpOffsetStored_reg_28_)) + (portref CE (instanceref bRpOffsetStored_reg_29_)) + (portref CE (instanceref bRpOffsetStored_reg_2_)) + (portref CE (instanceref bRpOffsetStored_reg_30_)) + (portref CE (instanceref bRpOffsetStored_reg_31_)) + (portref CE (instanceref bRpOffsetStored_reg_32_)) + (portref CE (instanceref bRpOffsetStored_reg_33_)) + (portref CE (instanceref bRpOffsetStored_reg_34_)) + (portref CE (instanceref bRpOffsetStored_reg_35_)) + (portref CE (instanceref bRpOffsetStored_reg_36_)) + (portref CE (instanceref bRpOffsetStored_reg_37_)) + (portref CE (instanceref bRpOffsetStored_reg_38_)) + (portref CE (instanceref bRpOffsetStored_reg_39_)) + (portref CE (instanceref bRpOffsetStored_reg_3_)) + (portref CE (instanceref bRpOffsetStored_reg_4_)) + (portref CE (instanceref bRpOffsetStored_reg_5_)) + (portref CE (instanceref bRpOffsetStored_reg_6_)) + (portref CE (instanceref bRpOffsetStored_reg_7_)) + (portref CE (instanceref bRpOffsetStored_reg_8_)) + (portref CE (instanceref bRpOffsetStored_reg_9_)) + (portref CE (instanceref bSpOffsetStored_reg_0_)) + (portref CE (instanceref bSpOffsetStored_reg_10_)) + (portref CE (instanceref bSpOffsetStored_reg_11_)) + (portref CE (instanceref bSpOffsetStored_reg_12_)) + (portref CE (instanceref bSpOffsetStored_reg_13_)) + (portref CE (instanceref bSpOffsetStored_reg_14_)) + (portref CE (instanceref bSpOffsetStored_reg_15_)) + (portref CE (instanceref bSpOffsetStored_reg_16_)) + (portref CE (instanceref bSpOffsetStored_reg_17_)) + (portref CE (instanceref bSpOffsetStored_reg_18_)) + (portref CE (instanceref bSpOffsetStored_reg_19_)) + (portref CE (instanceref bSpOffsetStored_reg_1_)) + (portref CE (instanceref bSpOffsetStored_reg_20_)) + (portref CE (instanceref bSpOffsetStored_reg_21_)) + (portref CE (instanceref bSpOffsetStored_reg_22_)) + (portref CE (instanceref bSpOffsetStored_reg_23_)) + (portref CE (instanceref bSpOffsetStored_reg_24_)) + (portref CE (instanceref bSpOffsetStored_reg_25_)) + (portref CE (instanceref bSpOffsetStored_reg_26_)) + (portref CE (instanceref bSpOffsetStored_reg_27_)) + (portref CE (instanceref bSpOffsetStored_reg_28_)) + (portref CE (instanceref bSpOffsetStored_reg_29_)) + (portref CE (instanceref bSpOffsetStored_reg_2_)) + (portref CE (instanceref bSpOffsetStored_reg_30_)) + (portref CE (instanceref bSpOffsetStored_reg_31_)) + (portref CE (instanceref bSpOffsetStored_reg_3_)) + (portref CE (instanceref bSpOffsetStored_reg_4_)) + (portref CE (instanceref bSpOffsetStored_reg_5_)) + (portref CE (instanceref bSpOffsetStored_reg_6_)) + (portref CE (instanceref bSpOffsetStored_reg_7_)) + (portref CE (instanceref bSpOffsetStored_reg_8_)) + (portref CE (instanceref bSpOffsetStored_reg_9_)) + (portref I1 (instanceref bOffsetUpdated_i_1)) + (portref O (instanceref bRpOffsetStored_39__i_1)) + ) + ) + (net (rename bSpOffsetStored_0__i_1_n_0 "bSpOffsetStored[0]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_0_)) + (portref O (instanceref bSpOffsetStored_0__i_1)) + ) + ) + (net (rename bSpOffsetStored_10__i_1_n_0 "bSpOffsetStored[10]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_10_)) + (portref O (instanceref bSpOffsetStored_10__i_1)) + ) + ) + (net (rename bSpOffsetStored_11__i_1_n_0 "bSpOffsetStored[11]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_11_)) + (portref O (instanceref bSpOffsetStored_11__i_1)) + ) + ) + (net (rename bSpOffsetStored_12__i_1_n_0 "bSpOffsetStored[12]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_12_)) + (portref O (instanceref bSpOffsetStored_12__i_1)) + ) + ) + (net (rename bSpOffsetStored_13__i_1_n_0 "bSpOffsetStored[13]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_13_)) + (portref O (instanceref bSpOffsetStored_13__i_1)) + ) + ) + (net (rename bSpOffsetStored_14__i_1_n_0 "bSpOffsetStored[14]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_14_)) + (portref O (instanceref bSpOffsetStored_14__i_1)) + ) + ) + (net (rename bSpOffsetStored_15__i_1_n_0 "bSpOffsetStored[15]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_15_)) + (portref O (instanceref bSpOffsetStored_15__i_1)) + ) + ) + (net (rename bSpOffsetStored_16__i_1_n_0 "bSpOffsetStored[16]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_16_)) + (portref O (instanceref bSpOffsetStored_16__i_1)) + ) + ) + (net (rename bSpOffsetStored_17__i_1_n_0 "bSpOffsetStored[17]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_17_)) + (portref O (instanceref bSpOffsetStored_17__i_1)) + ) + ) + (net (rename bSpOffsetStored_18__i_1_n_0 "bSpOffsetStored[18]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_18_)) + (portref O (instanceref bSpOffsetStored_18__i_1)) + ) + ) + (net (rename bSpOffsetStored_19__i_1_n_0 "bSpOffsetStored[19]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_19_)) + (portref O (instanceref bSpOffsetStored_19__i_1)) + ) + ) + (net (rename bSpOffsetStored_1__i_1_n_0 "bSpOffsetStored[1]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_1_)) + (portref O (instanceref bSpOffsetStored_1__i_1)) + ) + ) + (net (rename bSpOffsetStored_20__i_1_n_0 "bSpOffsetStored[20]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_20_)) + (portref O (instanceref bSpOffsetStored_20__i_1)) + ) + ) + (net (rename bSpOffsetStored_21__i_1_n_0 "bSpOffsetStored[21]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_21_)) + (portref O (instanceref bSpOffsetStored_21__i_1)) + ) + ) + (net (rename bSpOffsetStored_22__i_1_n_0 "bSpOffsetStored[22]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_22_)) + (portref O (instanceref bSpOffsetStored_22__i_1)) + ) + ) + (net (rename bSpOffsetStored_23__i_1_n_0 "bSpOffsetStored[23]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_23_)) + (portref O (instanceref bSpOffsetStored_23__i_1)) + ) + ) + (net (rename bSpOffsetStored_24__i_1_n_0 "bSpOffsetStored[24]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_24_)) + (portref O (instanceref bSpOffsetStored_24__i_1)) + ) + ) + (net (rename bSpOffsetStored_25__i_1_n_0 "bSpOffsetStored[25]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_25_)) + (portref O (instanceref bSpOffsetStored_25__i_1)) + ) + ) + (net (rename bSpOffsetStored_26__i_1_n_0 "bSpOffsetStored[26]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_26_)) + (portref O (instanceref bSpOffsetStored_26__i_1)) + ) + ) + (net (rename bSpOffsetStored_27__i_1_n_0 "bSpOffsetStored[27]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_27_)) + (portref O (instanceref bSpOffsetStored_27__i_1)) + ) + ) + (net (rename bSpOffsetStored_28__i_1_n_0 "bSpOffsetStored[28]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_28_)) + (portref O (instanceref bSpOffsetStored_28__i_1)) + ) + ) + (net (rename bSpOffsetStored_29__i_1_n_0 "bSpOffsetStored[29]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_29_)) + (portref O (instanceref bSpOffsetStored_29__i_1)) + ) + ) + (net (rename bSpOffsetStored_2__i_1_n_0 "bSpOffsetStored[2]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_2_)) + (portref O (instanceref bSpOffsetStored_2__i_1)) + ) + ) + (net (rename bSpOffsetStored_30__i_1_n_0 "bSpOffsetStored[30]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_30_)) + (portref O (instanceref bSpOffsetStored_30__i_1)) + ) + ) + (net (rename bSpOffsetStored_31__i_1_n_0 "bSpOffsetStored[31]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_31_)) + (portref O (instanceref bSpOffsetStored_31__i_1)) + ) + ) + (net (rename bSpOffsetStored_3__i_1_n_0 "bSpOffsetStored[3]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_3_)) + (portref O (instanceref bSpOffsetStored_3__i_1)) + ) + ) + (net (rename bSpOffsetStored_4__i_1_n_0 "bSpOffsetStored[4]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_4_)) + (portref O (instanceref bSpOffsetStored_4__i_1)) + ) + ) + (net (rename bSpOffsetStored_5__i_1_n_0 "bSpOffsetStored[5]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_5_)) + (portref O (instanceref bSpOffsetStored_5__i_1)) + ) + ) + (net (rename bSpOffsetStored_6__i_1_n_0 "bSpOffsetStored[6]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_6_)) + (portref O (instanceref bSpOffsetStored_6__i_1)) + ) + ) + (net (rename bSpOffsetStored_7__i_1_n_0 "bSpOffsetStored[7]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_7_)) + (portref O (instanceref bSpOffsetStored_7__i_1)) + ) + ) + (net (rename bSpOffsetStored_8__i_1_n_0 "bSpOffsetStored[8]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_8_)) + (portref O (instanceref bSpOffsetStored_8__i_1)) + ) + ) + (net (rename bSpOffsetStored_9__i_1_n_0 "bSpOffsetStored[9]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_9_)) + (portref O (instanceref bSpOffsetStored_9__i_1)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__0_ "bSpOffsetStored_reg_n_0_[0]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__0__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_0_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__10_ "bSpOffsetStored_reg_n_0_[10]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_10_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__11_ "bSpOffsetStored_reg_n_0_[11]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__11__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_11_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__12_ "bSpOffsetStored_reg_n_0_[12]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__12__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_12_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__13_ "bSpOffsetStored_reg_n_0_[13]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__13__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_13_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__14_ "bSpOffsetStored_reg_n_0_[14]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__14__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_14_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__15_ "bSpOffsetStored_reg_n_0_[15]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__15__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_15_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__16_ "bSpOffsetStored_reg_n_0_[16]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_16_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__17_ "bSpOffsetStored_reg_n_0_[17]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__17__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_17_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__18_ "bSpOffsetStored_reg_n_0_[18]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__18__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_18_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__19_ "bSpOffsetStored_reg_n_0_[19]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__19__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_19_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__1_ "bSpOffsetStored_reg_n_0_[1]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__1__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_1_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__20_ "bSpOffsetStored_reg_n_0_[20]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__20__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_20_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__21_ "bSpOffsetStored_reg_n_0_[21]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__21__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_21_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__22_ "bSpOffsetStored_reg_n_0_[22]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__22__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_22_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__23_ "bSpOffsetStored_reg_n_0_[23]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__23__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_23_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__24_ "bSpOffsetStored_reg_n_0_[24]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__24__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_24_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__25_ "bSpOffsetStored_reg_n_0_[25]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__25__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_25_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__26_ "bSpOffsetStored_reg_n_0_[26]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__26__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_26_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__27_ "bSpOffsetStored_reg_n_0_[27]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__27__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_27_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__28_ "bSpOffsetStored_reg_n_0_[28]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_28_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__29_ "bSpOffsetStored_reg_n_0_[29]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__29__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_29_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__2_ "bSpOffsetStored_reg_n_0_[2]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__2__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_2_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__30_ "bSpOffsetStored_reg_n_0_[30]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__30__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_30_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__31_ "bSpOffsetStored_reg_n_0_[31]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__31__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_31_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__3_ "bSpOffsetStored_reg_n_0_[3]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__3__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_3_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__4_ "bSpOffsetStored_reg_n_0_[4]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__4__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_4_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__5_ "bSpOffsetStored_reg_n_0_[5]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__5__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_5_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__6_ "bSpOffsetStored_reg_n_0_[6]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__6__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_6_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__7_ "bSpOffsetStored_reg_n_0_[7]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__7__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_7_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__8_ "bSpOffsetStored_reg_n_0_[8]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__8__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_8_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__9_ "bSpOffsetStored_reg_n_0_[9]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_9_)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_0_ "bSpPeriodCtrlReadbackSyncReset[0]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_10_ "bSpPeriodCtrlReadbackSyncReset[10]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_11_ "bSpPeriodCtrlReadbackSyncReset[11]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__11__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_12_ "bSpPeriodCtrlReadbackSyncReset[12]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_13_ "bSpPeriodCtrlReadbackSyncReset[13]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__13__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_14_ "bSpPeriodCtrlReadbackSyncReset[14]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__14__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_15_ "bSpPeriodCtrlReadbackSyncReset[15]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__15__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_16_ "bSpPeriodCtrlReadbackSyncReset[16]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref Q (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_17_ "bSpPeriodCtrlReadbackSyncReset[17]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_18_ "bSpPeriodCtrlReadbackSyncReset[18]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_19_ "bSpPeriodCtrlReadbackSyncReset[19]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__19__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_1_ "bSpPeriodCtrlReadbackSyncReset[1]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__1__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_20_ "bSpPeriodCtrlReadbackSyncReset[20]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__20__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_21_ "bSpPeriodCtrlReadbackSyncReset[21]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__21__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_22_ "bSpPeriodCtrlReadbackSyncReset[22]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__22__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_23_ "bSpPeriodCtrlReadbackSyncReset[23]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__23__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_24_ "bSpPeriodCtrlReadbackSyncReset[24]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__24__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_25_ "bSpPeriodCtrlReadbackSyncReset[25]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__25__i_5)) + (portref Q (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_26_ "bSpPeriodCtrlReadbackSyncReset[26]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref Q (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_27_ "bSpPeriodCtrlReadbackSyncReset[27]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref Q (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_28_ "bSpPeriodCtrlReadbackSyncReset[28]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_29_ "bSpPeriodCtrlReadbackSyncReset[29]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__29__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_2_ "bSpPeriodCtrlReadbackSyncReset[2]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__2__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_30_ "bSpPeriodCtrlReadbackSyncReset[30]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__30__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_31_ "bSpPeriodCtrlReadbackSyncReset[31]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_3_ "bSpPeriodCtrlReadbackSyncReset[3]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__3__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_4_ "bSpPeriodCtrlReadbackSyncReset[4]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__4__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_5_ "bSpPeriodCtrlReadbackSyncReset[5]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__5__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_6_ "bSpPeriodCtrlReadbackSyncReset[6]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__6__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_7_ "bSpPeriodCtrlReadbackSyncReset[7]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__7__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_8_ "bSpPeriodCtrlReadbackSyncReset[8]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__8__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_9_ "bSpPeriodCtrlReadbackSyncReset[9]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref Q (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadback_0_ "bSpPeriodCtrlReadback[0]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_10_ "bSpPeriodCtrlReadback[10]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_11_ "bSpPeriodCtrlReadback[11]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_12_ "bSpPeriodCtrlReadback[12]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_13_ "bSpPeriodCtrlReadback[13]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_14_ "bSpPeriodCtrlReadback[14]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_15_ "bSpPeriodCtrlReadback[15]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_16_ "bSpPeriodCtrlReadback[16]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_17_ "bSpPeriodCtrlReadback[17]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_18_ "bSpPeriodCtrlReadback[18]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_19_ "bSpPeriodCtrlReadback[19]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_1_ "bSpPeriodCtrlReadback[1]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_20_ "bSpPeriodCtrlReadback[20]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_21_ "bSpPeriodCtrlReadback[21]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_22_ "bSpPeriodCtrlReadback[22]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_23_ "bSpPeriodCtrlReadback[23]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_24_ "bSpPeriodCtrlReadback[24]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_25_ "bSpPeriodCtrlReadback[25]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_26_ "bSpPeriodCtrlReadback[26]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_27_ "bSpPeriodCtrlReadback[27]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_28_ "bSpPeriodCtrlReadback[28]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_29_ "bSpPeriodCtrlReadback[29]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_2_ "bSpPeriodCtrlReadback[2]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_30_ "bSpPeriodCtrlReadback[30]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_31_ "bSpPeriodCtrlReadback[31]") (joined + (portref D (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_3_ "bSpPeriodCtrlReadback[3]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_4_ "bSpPeriodCtrlReadback[4]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_5_ "bSpPeriodCtrlReadback[5]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_6_ "bSpPeriodCtrlReadback[6]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_7_ "bSpPeriodCtrlReadback[7]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_8_ "bSpPeriodCtrlReadback[8]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_9_ "bSpPeriodCtrlReadback[9]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_0_ "bSptPeriodCtrlReadbackSyncReset[0]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__0__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_10_ "bSptPeriodCtrlReadbackSyncReset[10]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref Q (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_11_ "bSptPeriodCtrlReadbackSyncReset[11]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__11__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_12_ "bSptPeriodCtrlReadbackSyncReset[12]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__12__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_13_ "bSptPeriodCtrlReadbackSyncReset[13]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__13__i_4)) + (portref Q (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_14_ "bSptPeriodCtrlReadbackSyncReset[14]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__14__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_15_ "bSptPeriodCtrlReadbackSyncReset[15]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__15__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_16_ "bSptPeriodCtrlReadbackSyncReset[16]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_17_ "bSptPeriodCtrlReadbackSyncReset[17]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__17__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_18_ "bSptPeriodCtrlReadbackSyncReset[18]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__18__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_19_ "bSptPeriodCtrlReadbackSyncReset[19]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__19__i_4)) + (portref Q (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_1_ "bSptPeriodCtrlReadbackSyncReset[1]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_20_ "bSptPeriodCtrlReadbackSyncReset[20]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__20__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_21_ "bSptPeriodCtrlReadbackSyncReset[21]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__21__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_22_ "bSptPeriodCtrlReadbackSyncReset[22]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__22__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_23_ "bSptPeriodCtrlReadbackSyncReset[23]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__23__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_24_ "bSptPeriodCtrlReadbackSyncReset[24]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__24__i_4)) + (portref Q (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_25_ "bSptPeriodCtrlReadbackSyncReset[25]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__25__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_26_ "bSptPeriodCtrlReadbackSyncReset[26]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__26__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_27_ "bSptPeriodCtrlReadbackSyncReset[27]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_28_ "bSptPeriodCtrlReadbackSyncReset[28]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref Q (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_29_ "bSptPeriodCtrlReadbackSyncReset[29]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__29__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_2_ "bSptPeriodCtrlReadbackSyncReset[2]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_30_ "bSptPeriodCtrlReadbackSyncReset[30]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__30__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_31_ "bSptPeriodCtrlReadbackSyncReset[31]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_3_ "bSptPeriodCtrlReadbackSyncReset[3]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_4_ "bSptPeriodCtrlReadbackSyncReset[4]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_5_ "bSptPeriodCtrlReadbackSyncReset[5]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_6_ "bSptPeriodCtrlReadbackSyncReset[6]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__6__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_7_ "bSptPeriodCtrlReadbackSyncReset[7]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__7__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_8_ "bSptPeriodCtrlReadbackSyncReset[8]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__8__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_9_ "bSptPeriodCtrlReadbackSyncReset[9]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__9__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadback_0_ "bSptPeriodCtrlReadback[0]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_10_ "bSptPeriodCtrlReadback[10]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_11_ "bSptPeriodCtrlReadback[11]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_12_ "bSptPeriodCtrlReadback[12]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_13_ "bSptPeriodCtrlReadback[13]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_14_ "bSptPeriodCtrlReadback[14]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_15_ "bSptPeriodCtrlReadback[15]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_16_ "bSptPeriodCtrlReadback[16]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_17_ "bSptPeriodCtrlReadback[17]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_18_ "bSptPeriodCtrlReadback[18]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_19_ "bSptPeriodCtrlReadback[19]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_1_ "bSptPeriodCtrlReadback[1]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_20_ "bSptPeriodCtrlReadback[20]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_21_ "bSptPeriodCtrlReadback[21]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_22_ "bSptPeriodCtrlReadback[22]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_23_ "bSptPeriodCtrlReadback[23]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_24_ "bSptPeriodCtrlReadback[24]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_25_ "bSptPeriodCtrlReadback[25]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_26_ "bSptPeriodCtrlReadback[26]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_27_ "bSptPeriodCtrlReadback[27]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_28_ "bSptPeriodCtrlReadback[28]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_29_ "bSptPeriodCtrlReadback[29]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_2_ "bSptPeriodCtrlReadback[2]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_30_ "bSptPeriodCtrlReadback[30]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_31_ "bSptPeriodCtrlReadback[31]") (joined + (portref D (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_3_ "bSptPeriodCtrlReadback[3]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_4_ "bSptPeriodCtrlReadback[4]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_5_ "bSptPeriodCtrlReadback[5]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_6_ "bSptPeriodCtrlReadback[6]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_7_ "bSptPeriodCtrlReadback[7]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_8_ "bSptPeriodCtrlReadback[8]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_9_ "bSptPeriodCtrlReadback[9]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net iDlyPush (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__4)) + (portref Q (instanceref RpCntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net mOffsetsValid (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__11)) + (portref mOffsetsValid) + ) + ) + (net (rename mRpOffset_0_ "mRpOffset[0]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + (portref (member mRpOffset 39)) + ) + ) + (net (rename mRpOffset_10_ "mRpOffset[10]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + (portref (member mRpOffset 29)) + ) + ) + (net (rename mRpOffset_11_ "mRpOffset[11]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + (portref (member mRpOffset 28)) + ) + ) + (net (rename mRpOffset_12_ "mRpOffset[12]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + (portref (member mRpOffset 27)) + ) + ) + (net (rename mRpOffset_13_ "mRpOffset[13]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + (portref (member mRpOffset 26)) + ) + ) + (net (rename mRpOffset_14_ "mRpOffset[14]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + (portref (member mRpOffset 25)) + ) + ) + (net (rename mRpOffset_15_ "mRpOffset[15]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + (portref (member mRpOffset 24)) + ) + ) + (net (rename mRpOffset_16_ "mRpOffset[16]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + (portref (member mRpOffset 23)) + ) + ) + (net (rename mRpOffset_17_ "mRpOffset[17]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + (portref (member mRpOffset 22)) + ) + ) + (net (rename mRpOffset_18_ "mRpOffset[18]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + (portref (member mRpOffset 21)) + ) + ) + (net (rename mRpOffset_19_ "mRpOffset[19]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + (portref (member mRpOffset 20)) + ) + ) + (net (rename mRpOffset_1_ "mRpOffset[1]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + (portref (member mRpOffset 38)) + ) + ) + (net (rename mRpOffset_20_ "mRpOffset[20]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + (portref (member mRpOffset 19)) + ) + ) + (net (rename mRpOffset_21_ "mRpOffset[21]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + (portref (member mRpOffset 18)) + ) + ) + (net (rename mRpOffset_22_ "mRpOffset[22]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + (portref (member mRpOffset 17)) + ) + ) + (net (rename mRpOffset_23_ "mRpOffset[23]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + (portref (member mRpOffset 16)) + ) + ) + (net (rename mRpOffset_24_ "mRpOffset[24]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + (portref (member mRpOffset 15)) + ) + ) + (net (rename mRpOffset_25_ "mRpOffset[25]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + (portref (member mRpOffset 14)) + ) + ) + (net (rename mRpOffset_26_ "mRpOffset[26]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + (portref (member mRpOffset 13)) + ) + ) + (net (rename mRpOffset_27_ "mRpOffset[27]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + (portref (member mRpOffset 12)) + ) + ) + (net (rename mRpOffset_28_ "mRpOffset[28]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + (portref (member mRpOffset 11)) + ) + ) + (net (rename mRpOffset_29_ "mRpOffset[29]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + (portref (member mRpOffset 10)) + ) + ) + (net (rename mRpOffset_2_ "mRpOffset[2]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + (portref (member mRpOffset 37)) + ) + ) + (net (rename mRpOffset_30_ "mRpOffset[30]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + (portref (member mRpOffset 9)) + ) + ) + (net (rename mRpOffset_31_ "mRpOffset[31]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + (portref (member mRpOffset 8)) + ) + ) + (net (rename mRpOffset_32_ "mRpOffset[32]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + (portref (member mRpOffset 7)) + ) + ) + (net (rename mRpOffset_33_ "mRpOffset[33]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + (portref (member mRpOffset 6)) + ) + ) + (net (rename mRpOffset_34_ "mRpOffset[34]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + (portref (member mRpOffset 5)) + ) + ) + (net (rename mRpOffset_35_ "mRpOffset[35]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + (portref (member mRpOffset 4)) + ) + ) + (net (rename mRpOffset_36_ "mRpOffset[36]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + (portref (member mRpOffset 3)) + ) + ) + (net (rename mRpOffset_37_ "mRpOffset[37]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + (portref (member mRpOffset 2)) + ) + ) + (net (rename mRpOffset_38_ "mRpOffset[38]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + (portref (member mRpOffset 1)) + ) + ) + (net (rename mRpOffset_39_ "mRpOffset[39]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + (portref (member mRpOffset 0)) + ) + ) + (net (rename mRpOffset_3_ "mRpOffset[3]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + (portref (member mRpOffset 36)) + ) + ) + (net (rename mRpOffset_4_ "mRpOffset[4]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + (portref (member mRpOffset 35)) + ) + ) + (net (rename mRpOffset_5_ "mRpOffset[5]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + (portref (member mRpOffset 34)) + ) + ) + (net (rename mRpOffset_6_ "mRpOffset[6]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + (portref (member mRpOffset 33)) + ) + ) + (net (rename mRpOffset_7_ "mRpOffset[7]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + (portref (member mRpOffset 32)) + ) + ) + (net (rename mRpOffset_8_ "mRpOffset[8]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + (portref (member mRpOffset 31)) + ) + ) + (net (rename mRpOffset_9_ "mRpOffset[9]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + (portref (member mRpOffset 30)) + ) + ) + (net (rename mSpOffset_0_ "mSpOffset[0]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref (member mSpOffset 39)) + ) + ) + (net (rename mSpOffset_10_ "mSpOffset[10]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + (portref (member mSpOffset 29)) + ) + ) + (net (rename mSpOffset_11_ "mSpOffset[11]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + (portref (member mSpOffset 28)) + ) + ) + (net (rename mSpOffset_12_ "mSpOffset[12]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + (portref (member mSpOffset 27)) + ) + ) + (net (rename mSpOffset_13_ "mSpOffset[13]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + (portref (member mSpOffset 26)) + ) + ) + (net (rename mSpOffset_14_ "mSpOffset[14]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + (portref (member mSpOffset 25)) + ) + ) + (net (rename mSpOffset_15_ "mSpOffset[15]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + (portref (member mSpOffset 24)) + ) + ) + (net (rename mSpOffset_16_ "mSpOffset[16]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + (portref (member mSpOffset 23)) + ) + ) + (net (rename mSpOffset_17_ "mSpOffset[17]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + (portref (member mSpOffset 22)) + ) + ) + (net (rename mSpOffset_18_ "mSpOffset[18]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + (portref (member mSpOffset 21)) + ) + ) + (net (rename mSpOffset_19_ "mSpOffset[19]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + (portref (member mSpOffset 20)) + ) + ) + (net (rename mSpOffset_1_ "mSpOffset[1]") (joined + (portref D (instanceref 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OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_49_out (joined + (portref I0 (instanceref bRpOffsetStored_9__i_1)) + (portref Q (instanceref OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_4_out (joined + (portref I0 (instanceref bSpOffsetStored_4__i_1)) + (portref Q (instanceref OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_50_out (joined + (portref I0 (instanceref bRpOffsetStored_10__i_1)) + (portref Q (instanceref OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_51_out (joined + (portref I0 (instanceref bRpOffsetStored_11__i_1)) + (portref Q (instanceref OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_52_out (joined + (portref I0 (instanceref bRpOffsetStored_12__i_1)) + (portref Q (instanceref OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_53_out (joined + (portref I0 (instanceref bRpOffsetStored_13__i_1)) + (portref Q (instanceref OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_54_out (joined + (portref I0 (instanceref bRpOffsetStored_14__i_1)) + (portref Q (instanceref OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_55_out (joined + (portref I0 (instanceref bRpOffsetStored_15__i_1)) + (portref Q (instanceref OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_56_out (joined + (portref I0 (instanceref bRpOffsetStored_16__i_1)) + (portref Q (instanceref OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_57_out (joined + (portref I0 (instanceref bRpOffsetStored_17__i_1)) + (portref Q (instanceref OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_58_out (joined + (portref I0 (instanceref bRpOffsetStored_18__i_1)) + (portref Q (instanceref OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_59_out (joined + (portref I0 (instanceref bRpOffsetStored_19__i_1)) + (portref Q (instanceref OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_5_out (joined + (portref I0 (instanceref bSpOffsetStored_5__i_1)) + (portref Q (instanceref OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_60_out (joined + (portref I0 (instanceref bRpOffsetStored_20__i_1)) + (portref Q (instanceref OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_61_out (joined + (portref I0 (instanceref bRpOffsetStored_21__i_1)) + (portref Q (instanceref OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_62_out (joined + (portref I0 (instanceref bRpOffsetStored_22__i_1)) + (portref Q (instanceref OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_63_out (joined + (portref I0 (instanceref bRpOffsetStored_23__i_1)) + (portref Q (instanceref OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_64_out (joined + (portref I0 (instanceref bRpOffsetStored_24__i_1)) + (portref Q (instanceref OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_65_out (joined + (portref I0 (instanceref bRpOffsetStored_25__i_1)) + (portref Q (instanceref OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_66_out (joined + (portref I0 (instanceref bRpOffsetStored_26__i_1)) + (portref Q (instanceref OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_67_out (joined + (portref I0 (instanceref bRpOffsetStored_27__i_1)) + (portref Q (instanceref OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_68_out (joined + (portref I0 (instanceref bRpOffsetStored_28__i_1)) + (portref Q (instanceref OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_69_out (joined + (portref I0 (instanceref bRpOffsetStored_29__i_1)) + (portref Q (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_6_out (joined + (portref I0 (instanceref bSpOffsetStored_6__i_1)) + (portref Q (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_70_out (joined + (portref I0 (instanceref bRpOffsetStored_30__i_1)) + (portref Q (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_71_out (joined + (portref I0 (instanceref bRpOffsetStored_31__i_1)) + (portref Q (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_72_out (joined + (portref I0 (instanceref bRpOffsetStored_32__i_1)) + (portref Q (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_73_out (joined + (portref I0 (instanceref bRpOffsetStored_33__i_1)) + (portref Q (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_74_out (joined + (portref I0 (instanceref bRpOffsetStored_34__i_1)) + (portref Q (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_75_out (joined + (portref I0 (instanceref bRpOffsetStored_35__i_1)) + (portref Q (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_76_out (joined + (portref I0 (instanceref bRpOffsetStored_36__i_1)) + (portref Q (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_77_out (joined + (portref I0 (instanceref bRpOffsetStored_37__i_1)) + (portref Q (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_78_out (joined + (portref I0 (instanceref bRpOffsetStored_38__i_1)) + (portref Q (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_79_out (joined + (portref I0 (instanceref bRpOffsetStored_39__i_2)) + (portref Q (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_7_out (joined + (portref I0 (instanceref bSpOffsetStored_7__i_1)) + (portref Q (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_8_out (joined + (portref I0 (instanceref bSpOffsetStored_8__i_1)) + (portref Q (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_9_out (joined + (portref I0 (instanceref bSpOffsetStored_9__i_1)) + (portref Q (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net rEnablePpsCrossing (joined + (portref Q (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref rEnablePpsCrossing) + ) + ) + (net rEnableTdc (joined + (portref Q (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref rEnableTdc) + ) + ) + (net rLoadRePulseCounts (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_oDataValid_reg)) + (portref rLoadRePulseCounts) + ) + ) + (net rLoadRpCounts (joined + (portref Q (instanceref RpCntHs_BlkOut_oDataValid_reg)) + (portref rLoadRpCounts) + ) + ) + (net rLoadRptCounts (joined + (portref Q (instanceref RptCntHs_BlkOut_oDataValid_reg)) + (portref rLoadRptCounts) + ) + ) + (net rPpsPulseCaptured (joined + (portref D (instanceref PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref rPpsPulseCaptured) + ) + ) + (net (rename rPulserEnableDelayValTemp_0_ "rPulserEnableDelayValTemp[0]") (joined + (portref D (instanceref rPulserEnableDelayVal_reg_0_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename rPulserEnableDelayValTemp_1_ "rPulserEnableDelayValTemp[1]") (joined + (portref D (instanceref rPulserEnableDelayVal_reg_1_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename rPulserEnableDelayValTemp_2_ "rPulserEnableDelayValTemp[2]") (joined + (portref D (instanceref rPulserEnableDelayVal_reg_2_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename rPulserEnableDelayValTemp_3_ "rPulserEnableDelayValTemp[3]") (joined + (portref D (instanceref rPulserEnableDelayVal_reg_3_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename rPulserEnableDelayVal_0_ "rPulserEnableDelayVal[0]") (joined + (portref Q (instanceref rPulserEnableDelayVal_reg_0_)) + (portref (member rPulserEnableDelayVal 3)) + ) + ) + (net (rename rPulserEnableDelayVal_1_ "rPulserEnableDelayVal[1]") (joined + (portref Q (instanceref rPulserEnableDelayVal_reg_1_)) + (portref (member rPulserEnableDelayVal 2)) + ) + ) + (net (rename rPulserEnableDelayVal_2_ "rPulserEnableDelayVal[2]") (joined + (portref Q (instanceref rPulserEnableDelayVal_reg_2_)) + (portref (member rPulserEnableDelayVal 1)) + ) + ) + (net (rename rPulserEnableDelayVal_3_ "rPulserEnableDelayVal[3]") (joined + (portref Q (instanceref rPulserEnableDelayVal_reg_3_)) + (portref (member rPulserEnableDelayVal 0)) + ) + ) + (net (rename rRePulseHighTimeInRClks_0_ "rRePulseHighTimeInRClks[0]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 23)) + ) + ) + (net (rename rRePulseHighTimeInRClks_10_ "rRePulseHighTimeInRClks[10]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 13)) + ) + ) + (net (rename rRePulseHighTimeInRClks_11_ "rRePulseHighTimeInRClks[11]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 12)) + ) + ) + (net (rename rRePulseHighTimeInRClks_12_ "rRePulseHighTimeInRClks[12]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 11)) + ) + ) + (net (rename rRePulseHighTimeInRClks_13_ "rRePulseHighTimeInRClks[13]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 10)) + ) + ) + (net (rename rRePulseHighTimeInRClks_14_ "rRePulseHighTimeInRClks[14]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 9)) + ) + ) + (net (rename rRePulseHighTimeInRClks_15_ "rRePulseHighTimeInRClks[15]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 8)) + ) + ) + (net (rename rRePulseHighTimeInRClks_16_ "rRePulseHighTimeInRClks[16]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 7)) + ) + ) + (net (rename rRePulseHighTimeInRClks_17_ "rRePulseHighTimeInRClks[17]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 6)) + ) + ) + (net (rename rRePulseHighTimeInRClks_18_ "rRePulseHighTimeInRClks[18]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 5)) + ) + ) + (net (rename rRePulseHighTimeInRClks_19_ "rRePulseHighTimeInRClks[19]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 4)) + ) + ) + (net (rename rRePulseHighTimeInRClks_1_ "rRePulseHighTimeInRClks[1]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 22)) + ) + ) + (net (rename rRePulseHighTimeInRClks_20_ "rRePulseHighTimeInRClks[20]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 3)) + ) + ) + (net (rename rRePulseHighTimeInRClks_21_ "rRePulseHighTimeInRClks[21]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 2)) + ) + ) + (net (rename rRePulseHighTimeInRClks_22_ "rRePulseHighTimeInRClks[22]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 1)) + ) + ) + (net (rename rRePulseHighTimeInRClks_2_ "rRePulseHighTimeInRClks[2]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 21)) + ) + ) + (net (rename rRePulseHighTimeInRClks_3_ "rRePulseHighTimeInRClks[3]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 20)) + ) + ) + (net (rename rRePulseHighTimeInRClks_4_ "rRePulseHighTimeInRClks[4]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 19)) + ) + ) + (net (rename rRePulseHighTimeInRClks_5_ "rRePulseHighTimeInRClks[5]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 18)) + ) + ) + (net (rename rRePulseHighTimeInRClks_6_ "rRePulseHighTimeInRClks[6]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 17)) + ) + ) + (net (rename rRePulseHighTimeInRClks_7_ "rRePulseHighTimeInRClks[7]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 16)) + ) + ) + (net (rename rRePulseHighTimeInRClks_8_ "rRePulseHighTimeInRClks[8]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 15)) + ) + ) + (net (rename rRePulseHighTimeInRClks_9_ "rRePulseHighTimeInRClks[9]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 14)) + ) + ) + (net (rename rRePulsePeriodInRClks_0_ "rRePulsePeriodInRClks[0]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 23)) + ) + ) + (net (rename rRePulsePeriodInRClks_10_ "rRePulsePeriodInRClks[10]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 13)) + ) + ) + (net (rename rRePulsePeriodInRClks_11_ "rRePulsePeriodInRClks[11]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 12)) + ) + ) + (net (rename rRePulsePeriodInRClks_12_ "rRePulsePeriodInRClks[12]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 11)) + ) + ) + (net (rename rRePulsePeriodInRClks_13_ "rRePulsePeriodInRClks[13]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 10)) + ) + ) + (net (rename rRePulsePeriodInRClks_14_ "rRePulsePeriodInRClks[14]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 9)) + ) + ) + (net (rename rRePulsePeriodInRClks_15_ "rRePulsePeriodInRClks[15]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 8)) + ) + ) + (net (rename rRePulsePeriodInRClks_16_ "rRePulsePeriodInRClks[16]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 7)) + ) + ) + (net (rename rRePulsePeriodInRClks_17_ "rRePulsePeriodInRClks[17]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 6)) + ) + ) + (net (rename rRePulsePeriodInRClks_18_ "rRePulsePeriodInRClks[18]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 5)) + ) + ) + (net (rename rRePulsePeriodInRClks_19_ "rRePulsePeriodInRClks[19]") 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(portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 0)) + ) + ) + (net (rename sSptPeriodInSClks_1_ "sSptPeriodInSClks[1]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 14)) + ) + ) + (net (rename sSptPeriodInSClks_2_ "sSptPeriodInSClks[2]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 13)) + ) + ) + (net (rename sSptPeriodInSClks_3_ "sSptPeriodInSClks[3]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 12)) + ) + ) + (net (rename sSptPeriodInSClks_4_ "sSptPeriodInSClks[4]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 11)) + ) + ) + (net (rename sSptPeriodInSClks_5_ "sSptPeriodInSClks[5]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 10)) + ) + ) + (net (rename sSptPeriodInSClks_6_ "sSptPeriodInSClks[6]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 9)) + ) + ) + (net (rename sSptPeriodInSClks_7_ "sSptPeriodInSClks[7]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 8)) + ) + ) + (net (rename sSptPeriodInSClks_8_ "sSptPeriodInSClks[8]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 7)) + ) + ) + (net (rename sSptPeriodInSClks_9_ "sSptPeriodInSClks[9]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 6)) + ) + ) + ) + ) + ) + ) +(comment "Reference To The Cell Of Highest Level") + + (design SyncRegsIfc + (cellref SyncRegsIfc (libraryref work)) + (property part (string "xc7z100ffg900-2")) + ) +) diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/TdcCore.edf b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcCore.edf new file mode 100644 index 000000000..9679f2c63 Binary files /dev/null and b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcCore.edf differ diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/TdcTop.vhd b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcTop.vhd new file mode 100644 index 000000000..6535bbd04 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcTop.vhd @@ -0,0 +1,1147 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- +-- Purpose: +-- +-- This top level module orchestrates both of the TDC Cores for the RP and SP. It +-- handles PPS capture, resets, re-run logic, and PPS crossing logic. The guts of the TDC +-- are all located in the Cores. +-- +-- This file (and the Cores) follows exactly the "TDC Detail" diagram from this document: +-- //MI/RF/HW/USRP/N310/HWCode/Common/Synchronization/design/Diagrams.vsdx +-- +-- +-- +-- To control this module: +-- 0) Default values expected to be driven on the control inputs: +-- aReset <= true +-- rResetTdc <= true +-- rEnableTdc <= false +-- rReRunEnable <= false +-- rEnablePpsCrossing <= false +-- sPpsClkCrossDelayVal <= don't care +-- Prior to starting the core, the Sync Pulse counters must be loaded. Apply the +-- correct count values to rRpPeriodInRClks, etc, and then pulse the load bit for +-- each RP and SP. It is critical that this step is performed before de-asserting +-- reset. +-- +-- 1) De-assert the global reset, aReset, as well as the synchronous reset, rResetTdc, +-- after all clocks are active and stable. Wait until rResetTdcDone is de-asserted. +-- If it doesn't de-assert, then one of your clocks isn't running. +-- +-- 2) At any point after rResetTdcDone de-asserts it is safe to assert rEnableTdc. +-- The rPpsPulse input is now actively listening for PPS activity and the TDC +-- will begin on the first PPS pulse received. After a PPS is received, the +-- rPpsPulseCaptured bit will assert and will remain asserted until aReset or +-- rResetTdc is asserted. +-- +-- 3) When the TDC measurement completes, mRpOffsetDone and mSpOffsetDone will assert +-- (not necessarily at the same time). The results of the measurements will be valid +-- on mRpOffset and mSpOffset. +-- +-- 4) To cross the PPS trigger into the SampleClk domain, first write the correct delay +-- value to sPpsClkCrossDelayVal. Then (or at the same time), enable the crossing +-- logic by asserting rEnablePpsCrossing. All subsequent PPS pulses will be crossed +-- deterministically. Although not the typical use case, sPpsClkCrossDelayVal can +-- be adjusted on the fly without producing output glitches, although output pulses +-- may be skipped. +-- +-- 5) To run the measurement again, assert the rReRunEnable input and capture the new +-- offsets whenever mRpOffsetValid or mSpOffsetValid asserts. +-- +-- +-- +-- Sync Pulse = RP and SP, which are the repeated pulses that are some integer +-- divisor of the Reference and Sample clocks. RP = Reference Pulse in the +-- RefClk domain. SP = Repeated TClk pulse in the SampleClk domain. +-- +-- +-- Clock period relationship requirements to meet system concerns: +-- 1) MeasClkPeriod < 2*RefClkPeriod +-- 2) MeasClkPeriod < 4*SampleClkPeriod +-- +-- +-- vreview_group Tdc +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +entity TdcTop is + generic ( + -- Determines the maximum number of bits required to create the restart + -- pulser. This value is based off of the RefClk and RePulse rates. + kRClksPerRePulsePeriodBitsMax : integer range 3 to 32 := 24; + -- Determines the maximum number of bits required to create the Gated and Freerunning + -- sync pulsers. This value is based off of the RefClk and SyncPulse rates. + kRClksPerRpPeriodBitsMax : integer range 3 to 16 := 16; + -- This value is based off of the SampleClk and SyncPulse rates. + kSClksPerSpPeriodBitsMax : integer range 3 to 16 := 16; + -- Number of MeasClk periods required to count one period of RP or SP (in bits). + kPulsePeriodCntSize : integer := 13; + -- Number of FreqRef periods to be measured (in bits). + kFreqRefPeriodsToCheckSize: integer := 17; + -- Number of Sync Pulse Periods to be timestamped (in bits). + kSyncPeriodsToStampSize : integer := 10 + ); + port ( + + -- Clocks and Resets : -------------------------------------------------------------- + -- Asynchronous global reset. + aReset : in boolean; + -- Reference Clock + RefClk : in std_logic; + -- Sample Clock + SampleClk : in std_logic; + -- Measurement Clock must run at a very specific frequency, determined by the + -- SampleClk, RefClk, and Sync Pulse rates... oh and a lot of math/luck. + MeasClk : in std_logic; + + + -- Controls and Status : ------------------------------------------------------------ + -- Soft reset for the module. Wait until rResetTdcDone asserts before de-asserting + -- the reset. + rResetTdc : in boolean; + rResetTdcDone : out boolean; + -- Once enabled, the TDC waits for the next PPS pulse to begin measurements. Leave + -- this signal asserted for the measurement duration (there is no need to de-assert + -- it unless you want to capture a different PPS edge). + rEnableTdc : in boolean; + -- Assert this bit to allow the TDC to perform repeated measurements. + rReRunEnable : in boolean; + + -- Only required to pulse 1 RefClk cycle. + rPpsPulse : in boolean; + -- Debug, held asserted when pulse is captured. + rPpsPulseCaptured : out boolean; + + -- Programmable value for delaying the RP and SP pulsers from when the Restart + -- Pulser begins. + rPulserEnableDelayVal : in unsigned(3 downto 0); + + + -- Crossing PPS into Sample Clock : ------------------------------------------------- + -- Enable crossing rPpsPulse into SampleClk domain. This should remain de-asserted + -- until the TDC measurements are complete and sPpsClkCrossDelayVal is written. + rEnablePpsCrossing : in boolean; + -- Programmable delay value for crossing clock domains. This is used to compensate + -- for differences in sSP pulses across modules. This value is typically set once + -- after running initial synchronization. + sPpsClkCrossDelayVal : in unsigned(3 downto 0); + -- PPS pulse output on the SampleClk domain. + sPpsPulse : out boolean; + + + -- FTDC Measurement Results : ------------------------------------------------------- + -- Final FTDC measurements in MeasClk ticks. Done will assert when *Offset + -- becomes valid and will remain asserted until aReset or rResetTdc asserts. + -- FXP<+40,13> where kPulsePeriodCntSize is the number of integer bits. + mRpOffset : out unsigned(kPulsePeriodCntSize+ + kSyncPeriodsToStampSize+ + kFreqRefPeriodsToCheckSize-1 downto 0); + mSpOffset : out unsigned(kPulsePeriodCntSize+ + kSyncPeriodsToStampSize+ + kFreqRefPeriodsToCheckSize-1 downto 0); + mOffsetsDone : out boolean; + mOffsetsValid : out boolean; + + + -- Setup for Pulsers : -------------------------------------------------------------- + -- Only load these counts when rResetTdc is asserted and rEnableTdc is de-asserted!!! + -- If both of the above conditions are met, load the counts by pulsing Load + -- when the counts are valid. It is not necessary to keep the count values valid + -- after pulsing Load. + rLoadRePulseCounts : in boolean; -- RePulse + rRePulsePeriodInRClks : in unsigned(kRClksPerRePulsePeriodBitsMax - 1 downto 0); + rRePulseHighTimeInRClks : in unsigned(kRClksPerRePulsePeriodBitsMax - 1 downto 0); + rLoadRpCounts : in boolean; -- RP + rRpPeriodInRClks : in unsigned(kRClksPerRpPeriodBitsMax - 1 downto 0); + rRpHighTimeInRClks : in unsigned(kRClksPerRpPeriodBitsMax - 1 downto 0); + rLoadRptCounts : in boolean; -- RP-transfer + rRptPeriodInRClks : in unsigned(kRClksPerRpPeriodBitsMax - 1 downto 0); + rRptHighTimeInRClks : in unsigned(kRClksPerRpPeriodBitsMax - 1 downto 0); + sLoadSpCounts : in boolean; -- SP + sSpPeriodInSClks : in unsigned(kSClksPerSpPeriodBitsMax - 1 downto 0); + sSpHighTimeInSClks : in unsigned(kSClksPerSpPeriodBitsMax - 1 downto 0); + sLoadSptCounts : in boolean; -- SP-transfer + sSptPeriodInSClks : in unsigned(kSClksPerSpPeriodBitsMax - 1 downto 0); + sSptHighTimeInSClks : in unsigned(kSClksPerSpPeriodBitsMax - 1 downto 0); + + + -- Sync Pulse Outputs : ------------------------------------------------------------- + -- The repeating pulses can be useful for many things, including passing triggers. + -- The rising edges will always have a fixed (but unknown) phase relationship to one + -- another. This fixed phase relationship is valid across daughterboards and all + -- modules using the same Reference Clock and Sample Clock rates and sources. + rRpTransfer : out boolean; + sSpTransfer : out boolean; + + -- Pin bouncers out and in. Must go to unused and unconnected pins on the FPGA! + rGatedPulseToPin : inout std_logic; + sGatedPulseToPin : inout std_logic + ); +end TdcTop; + + +architecture struct of TdcTop is + + component TdcCore + generic ( + kSourceClksPerPulseMaxBits : integer range 3 to 16 := 16; + kPulsePeriodCntSize : integer := 13; + kFreqRefPeriodsToCheckSize : integer := 17; + kSyncPeriodsToStampSize : integer := 10); + port ( + aReset : in boolean; + MeasClk : in std_logic; + mResetPeriodMeas : in boolean; + mPeriodMeasDone : out boolean; + mResetTdcMeas : in boolean; + mRunTdcMeas : in boolean; + mGatedPulse : out boolean; + mAvgOffset : out unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + mAvgOffsetDone : out boolean; + mAvgOffsetValid : out boolean; + SourceClk : in std_logic; + sResetTdc : in boolean; + sSyncPulseLoadCnt : in boolean; + sSyncPulsePeriod : in unsigned(kSourceClksPerPulseMaxBits-1 downto 0); + sSyncPulseHighTime : in unsigned(kSourceClksPerPulseMaxBits-1 downto 0); + sSyncPulseEnable : in boolean; + sGatedPulse : out boolean; + sGatedPulseToPin : inout std_logic); + end component; + + --vhook_sigstart + signal mRP: boolean; + signal mRpOffsetDoneLcl: boolean; + signal mRpOffsetValidLcl: boolean; + signal mRunTdc: boolean; + signal mSP: boolean; + signal mSpOffsetDoneLcl: boolean; + signal mSpOffsetValidLcl: boolean; + signal rCrossTrigRFI: boolean; + signal rGatedCptrPulseIn: boolean; + signal rRePulse: boolean; + signal rRePulseEnable: boolean; + signal rRpEnable: boolean; + signal rRptPulse: boolean; + signal sSpEnable: boolean; + signal sSptPulse: boolean; + --vhook_sigend + + signal sSpEnable_ms : boolean; + + -- Delay chain for enables. + constant kDelaySizeForRpEnable : integer := 15; + constant kAddtlDelayForSpEnable : integer := 3; + signal rSyncPulseEnableDly : + std_logic_vector(kDelaySizeForRpEnable+ + kAddtlDelayForSpEnable-1 downto 0) := (others => '0'); + -- Adding kAddtlDelayForSpEnable stages, so this vector needs to handle one extra + -- bit of range (hence no -1 downto 0). + signal rSyncPulseEnableDlyVal : unsigned(rPulserEnableDelayVal'length downto 0); + + signal rResetTdcFlop_ms, rResetTdcFlop, + rResetTdcDone_ms, + rSpEnable, + mRunTdcEnable_ms, mRunTdcEnable, + mRunTdcEnableDly, mRunTdcEnableRe, + mResetTdc_ms, mResetTdc, + sResetTdc_ms, sResetTdc, + mRpValidStored, mSpValidStored, + mOffsetsValidLcl, + rPpsPulseDly, rPpsPulseRe, + mReRunEnable_ms, mReRunEnable : boolean; + + signal rPpsCaptured : std_logic; + + type EnableFsmState_t is (Disabled, WaitForRunComplete, ReRuns); + signal mEnableState : EnableFsmState_t; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of sSpEnable_ms : signal is "true"; + attribute ASYNC_REG of sSpEnable : signal is "true"; + attribute ASYNC_REG of rResetTdcFlop_ms : signal is "true"; + attribute ASYNC_REG of rResetTdcFlop : signal is "true"; + attribute ASYNC_REG of rResetTdcDone_ms : signal is "true"; + attribute ASYNC_REG of rResetTdcDone : signal is "true"; + attribute ASYNC_REG of mRunTdcEnable_ms : signal is "true"; + attribute ASYNC_REG of mRunTdcEnable : signal is "true"; + attribute ASYNC_REG of mResetTdc_ms : signal is "true"; + attribute ASYNC_REG of mResetTdc : signal is "true"; + attribute ASYNC_REG of sResetTdc_ms : signal is "true"; + attribute ASYNC_REG of sResetTdc : signal is "true"; + attribute ASYNC_REG of mReRunEnable_ms : signal is "true"; + attribute ASYNC_REG of mReRunEnable : signal is "true"; + +begin + + + -- Generate Resets : ------------------------------------------------------------------ + -- Double-sync the reset to the MeasClk domain and then back to the RefClk domain to + -- prove it made it all the way into the TDC. Also move it into the SampleClk domain. + -- ------------------------------------------------------------------------------------ + GenResets : process(aReset, RefClk) + begin + if aReset then + rResetTdcFlop_ms <= true; + rResetTdcFlop <= true; + rResetTdcDone_ms <= true; + rResetTdcDone <= true; + elsif rising_edge(RefClk) then + -- Run this through a double-sync in case the user defaults it to false, which + -- could cause rResetTdcFlop_ms to go meta-stable. + rResetTdcFlop_ms <= rResetTdc; + rResetTdcFlop <= rResetTdcFlop_ms; + -- Second double-sync to move the reset from the MeasClk domain back to RefClk. + rResetTdcDone_ms <= mResetTdc; + rResetTdcDone <= rResetTdcDone_ms; + end if; + end process; + + GenResetsMeasClk : process(aReset, MeasClk) + begin + if aReset then + mResetTdc_ms <= true; + mResetTdc <= true; + elsif rising_edge(MeasClk) then + -- Move the reset from the RefClk to the MeasClk domain. + mResetTdc_ms <= rResetTdcFlop; + mResetTdc <= mResetTdc_ms; + end if; + end process; + + GenResetsSampleClk : process(aReset, SampleClk) + begin + if aReset then + sResetTdc_ms <= true; + sResetTdc <= true; + elsif rising_edge(SampleClk) then + -- Move the reset from the RefClk to the SampleClk domain. + sResetTdc_ms <= rResetTdcFlop; + sResetTdc <= sResetTdc_ms; + end if; + end process; + + + -- Generate Enables for TDCs : -------------------------------------------------------- + -- When the TDC is enabled by asserting rEnableTdc, we start "listening" for a PPS + -- rising edge to occur. We capture the first edge we see and then keep the all the + -- enables asserted until the TDC is disabled. + -- ------------------------------------------------------------------------------------ + rPpsPulseRe <= rPpsPulse and not rPpsPulseDly; + + EnableTdc : process(aReset, RefClk) + begin + if aReset then + rPpsPulseDly <= false; + rPpsCaptured <= '0'; + rSyncPulseEnableDly <= (others => '0'); + elsif rising_edge(RefClk) then + -- RE detector for PPS to ONLY trigger on the edge and not accidentally half + -- way through the high time. + rPpsPulseDly <= rPpsPulse; + -- When the TDC is enabled we capture the first PPS. This starts the Sync Pulses + -- (RP / SP) as well as enables the TDC measurement for capturing edges. Note + -- that this is independent from any synchronous reset such that we can control + -- the PPS capture and the edge capture independently. + if rEnableTdc then + if rPpsPulseRe then + rPpsCaptured <= '1'; + end if; + else + rPpsCaptured <= '0'; + rSyncPulseEnableDly <= (others => '0'); + end if; + + -- Delay chain for the enable bits. Shift left low to high. + rSyncPulseEnableDly <= + rSyncPulseEnableDly(rSyncPulseEnableDly'high-1 downto 0) & rPpsCaptured; + end if; + end process; + + rSyncPulseEnableDlyVal <= resize(rPulserEnableDelayVal, rSyncPulseEnableDlyVal'length); + + -- Enables for the RePulse/RP/SP. The RePulse enable must be asserted two cycles + -- before the other enables to allow the TDC to start running before the RP/SP begin. + rRePulseEnable <= rPpsCaptured = '1'; -- no delay + rRpEnable <= rSyncPulseEnableDly(to_integer(rSyncPulseEnableDlyVal)) = '1'; + rSpEnable <= rSyncPulseEnableDly(to_integer(rSyncPulseEnableDlyVal)+kAddtlDelayForSpEnable-1) = '1'; + + -- Local to output. + rPpsPulseCaptured <= rPpsCaptured = '1'; + + -- Sync rSpEnable to the SampleClk now... based on the "TDC 2.0" diagram. + SyncEnableToSampleClk : process(aReset, SampleClk) + begin + if aReset then + sSpEnable_ms <= false; + sSpEnable <= false; + elsif rising_edge(SampleClk) then + sSpEnable_ms <= rSpEnable; + sSpEnable <= sSpEnable_ms; + end if; + end process; + + --vhook_e Pulser ReRunPulser + --vhook_a kClksPerPulseMaxBits kRClksPerRePulsePeriodBitsMax + --vhook_a Clk RefClk + --vhook_a cLoadLimits rLoadRePulseCounts + --vhook_a cPeriod rRePulsePeriodInRClks + --vhook_a cHighTime rRePulseHighTimeInRClks + --vhook_a cEnablePulse rRePulseEnable + --vhook_a cPulse rRePulse + ReRunPulser: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kRClksPerRePulsePeriodBitsMax) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => RefClk, --in std_logic + cLoadLimits => rLoadRePulseCounts, --in boolean + cPeriod => rRePulsePeriodInRClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => rRePulseHighTimeInRClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => rRePulseEnable, --in boolean + cPulse => rRePulse); --out boolean + + mRunTdcEnableRe <= mRunTdcEnable and not mRunTdcEnableDly; + + -- FSM to generate the master Run signal, as well as the repeat run. + SyncEnableToMeasClk : process(aReset, MeasClk) + begin + if aReset then + mRunTdcEnable_ms <= false; + mRunTdcEnable <= false; + mReRunEnable_ms <= false; + mReRunEnable <= false; + mRunTdcEnableDly <= false; + mRunTdc <= false; + mEnableState <= Disabled; + elsif rising_edge(MeasClk) then + -- rRePulse is many, many MeasClk cycles high/low, so this is safe to double-sync. + mRunTdcEnable_ms <= rRePulse; + mRunTdcEnable <= mRunTdcEnable_ms; + mReRunEnable_ms <= rReRunEnable; + mReRunEnable <= mReRunEnable_ms; + + mRunTdcEnableDly <= mRunTdcEnable; + + -- STATE MACHINE STARTUP !!! ------------------------------------------------------ + -- This state machine starts safely because it cannot change state until + -- mRunTdcEnable is asserted, which cannot happen until several cycles after + -- aReset de-assertion due to the double-synchronizer from the RefClk domain. + -- -------------------------------------------------------------------------------- + -- De-assert strobe. + mRunTdc <= false; + + case mEnableState is + -- Transition to WaitForRunComplete when the TDC is enabled. Pulse mRunTdc here, + -- and then wait for it to complete in WaitForRunComplete. + when Disabled => + if mRunTdcEnableRe then + mRunTdc <= true; + mEnableState <= WaitForRunComplete; + end if; + + -- The TDC measurement is complete when both offsets are valid. Go to the re-run + -- state regardless of whether re-runs are enabled. If they aren't we just sit + -- there and wait for more instructions... + when WaitForRunComplete => + if mOffsetsValidLcl then + mEnableState <= ReRuns; + end if; + + -- Only pulse mRunTdc again if re-runs are enabled and the rising edge of + -- the enable signal occurs. This guarantees our RP/SP have the correct phase + -- relationship every time the TDC is run. + when ReRuns => + if mReRunEnable and mRunTdcEnableRe then + mRunTdc <= true; + mEnableState <= WaitForRunComplete; + end if; + + when others => + mEnableState <= Disabled; + end case; + + -- Synchronous reset for FSM. + if mResetTdc then + mEnableState <= Disabled; + mRunTdc <= false; + end if; + + end if; + end process; + + + + -- Generate Output Valid Signals : ---------------------------------------------------- + -- Depending on how fast SW can read the measurements (and in what order they read) + -- the readings could be out of sync with one another. This section conditions the + -- output valid signals from each core and asserts a single output valid pulse after + -- BOTH valids have asserted. It is agnostic to the order in which the valids assert. + -- It creates a delay in the output valid assertion. Minimal delay is one MeasClk cycle + -- if the core valids assert together. Worst-case delay is two MeasClk cycles after + -- the latter of the two valids asserts. This is acceptable delay because the core + -- cannot be re-run until both valids have asserted (mOffsetsValidLcl is fed back into + -- the ReRun FSM above). + -- ------------------------------------------------------------------------------------ + ConditionDataValidProc : process(aReset, MeasClk) is + begin + if aReset then + mOffsetsValidLcl <= false; + mRpValidStored <= false; + mSpValidStored <= false; + elsif rising_edge(MeasClk) then + -- Reset the strobe signals. + mOffsetsValidLcl <= false; + + -- First, we're sensitive to the TDC sync reset signal. + if mResetTdc then + mOffsetsValidLcl <= false; + mRpValidStored <= false; + mSpValidStored <= false; + -- Case 1: Both Valid signals pulse at the same time. + -- Case 4: Both Valid signals have been stored independently. Yes, this incurs + -- a one-cycle delay in the output valid (from when the second one asserts) + -- but it makes for cleaner code and is safe because by design because the + -- valid signals cannot assert again for a longggg time. + elsif (mRpOffsetValidLcl and mSpOffsetValidLcl) or + (mRpValidStored and mSpValidStored) then + mOffsetsValidLcl <= true; + mRpValidStored <= false; + mSpValidStored <= false; + -- Case 2: RP Valid pulses alone. + elsif mRpOffsetValidLcl then + mRpValidStored <= true; + -- Case 3: SP Valid pulses alone. + elsif mSpOffsetValidLcl then + mSpValidStored <= true; + end if; + end if; + end process; + + -- Local to output. + mOffsetsValid <= mOffsetsValidLcl; + -- Only assert done with both cores are done. + mOffsetsDone <= mRpOffsetDoneLcl and mSpOffsetDoneLcl; + + + + -- Reference Clock TDC (RP) : --------------------------------------------------------- + -- mRP is only used for testbenching purposes, so ignore vhook warnings. + --vhook_nowarn mRP + -- ------------------------------------------------------------------------------------ + + --vhook TdcCore RpTdc + --vhook_g kSourceClksPerPulseMaxBits kRClksPerRpPeriodBitsMax + --vhook_a mResetPeriodMeas mResetTdc + --vhook_a mResetTdcMeas mResetTdc + --vhook_a mPeriodMeasDone open + --vhook_a mRunTdcMeas mRunTdc + --vhook_a mGatedPulse mRP + --vhook_a mAvgOffset mRpOffset + --vhook_a mAvgOffsetDone mRpOffsetDoneLcl + --vhook_a mAvgOffsetValid mRpOffsetValidLcl + --vhook_a SourceClk RefClk + --vhook_a sResetTdc rResetTdcFlop + --vhook_a sSyncPulseLoadCnt rLoadRpCounts + --vhook_a sSyncPulsePeriod rRpPeriodInRClks + --vhook_a sSyncPulseHighTime rRpHighTimeInRClks + --vhook_a sSyncPulseEnable rRpEnable + --vhook_a sGatedPulse open + --vhook_a {^sGated(.*)} rGated$1 + RpTdc: TdcCore + generic map ( + kSourceClksPerPulseMaxBits => kRClksPerRpPeriodBitsMax, --integer range 3:16 :=16 + kPulsePeriodCntSize => kPulsePeriodCntSize, --integer:=13 + kFreqRefPeriodsToCheckSize => kFreqRefPeriodsToCheckSize, --integer:=17 + kSyncPeriodsToStampSize => kSyncPeriodsToStampSize) --integer:=10 + port map ( + aReset => aReset, --in boolean + MeasClk => MeasClk, --in std_logic + mResetPeriodMeas => mResetTdc, --in boolean + mPeriodMeasDone => open, --out boolean + mResetTdcMeas => mResetTdc, --in boolean + mRunTdcMeas => mRunTdc, --in boolean + mGatedPulse => mRP, --out boolean + mAvgOffset => mRpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mAvgOffsetDone => mRpOffsetDoneLcl, --out boolean + mAvgOffsetValid => mRpOffsetValidLcl, --out boolean + SourceClk => RefClk, --in std_logic + sResetTdc => rResetTdcFlop, --in boolean + sSyncPulseLoadCnt => rLoadRpCounts, --in boolean + sSyncPulsePeriod => rRpPeriodInRClks, --in unsigned(kSourceClksPerPulseMaxBits-1:0) + sSyncPulseHighTime => rRpHighTimeInRClks, --in unsigned(kSourceClksPerPulseMaxBits-1:0) + sSyncPulseEnable => rRpEnable, --in boolean + sGatedPulse => open, --out boolean + sGatedPulseToPin => rGatedPulseToPin); --inout std_logic + + --vhook_e Pulser RpTransferPulse + --vhook_a kClksPerPulseMaxBits kRClksPerRpPeriodBitsMax + --vhook_a Clk RefClk + --vhook_a cLoadLimits rLoadRptCounts + --vhook_a cPeriod rRptPeriodInRClks + --vhook_a cHighTime rRptHighTimeInRClks + --vhook_a cEnablePulse rRpEnable + --vhook_a cPulse rRptPulse + RpTransferPulse: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kRClksPerRpPeriodBitsMax) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => RefClk, --in std_logic + cLoadLimits => rLoadRptCounts, --in boolean + cPeriod => rRptPeriodInRClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => rRptHighTimeInRClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => rRpEnable, --in boolean + cPulse => rRptPulse); --out boolean + + -- Local to output + rRpTransfer <= rRptPulse; + + + -- Sample Clock TDC (SP) : ------------------------------------------------------------ + -- mSP is only used for testbenching purposes, so ignore vhook warnings. + --vhook_nowarn mSP + -- ------------------------------------------------------------------------------------ + + --vhook TdcCore SpTdc + --vhook_g kSourceClksPerPulseMaxBits kSClksPerSpPeriodBitsMax + --vhook_a mResetPeriodMeas mResetTdc + --vhook_a mResetTdcMeas mResetTdc + --vhook_a mPeriodMeasDone open + --vhook_a mRunTdcMeas mRunTdc + --vhook_a mGatedPulse mSP + --vhook_a mAvgOffset mSpOffset + --vhook_a mAvgOffsetDone mSpOffsetDoneLcl + --vhook_a mAvgOffsetValid mSpOffsetValidLcl + --vhook_a SourceClk SampleClk + --vhook_a sResetTdc sResetTdc + --vhook_a sSyncPulseLoadCnt sLoadSpCounts + --vhook_a sSyncPulsePeriod sSpPeriodInSClks + --vhook_a sSyncPulseHighTime sSpHighTimeInSClks + --vhook_a sSyncPulseEnable sSpEnable + --vhook_a sGatedPulse open + --vhook_a {^sGated(.*)} sGated$1 + SpTdc: TdcCore + generic map ( + kSourceClksPerPulseMaxBits => kSClksPerSpPeriodBitsMax, --integer range 3:16 :=16 + kPulsePeriodCntSize => kPulsePeriodCntSize, --integer:=13 + kFreqRefPeriodsToCheckSize => kFreqRefPeriodsToCheckSize, --integer:=17 + kSyncPeriodsToStampSize => kSyncPeriodsToStampSize) --integer:=10 + port map ( + aReset => aReset, --in boolean + MeasClk => MeasClk, --in std_logic + mResetPeriodMeas => mResetTdc, --in boolean + mPeriodMeasDone => open, --out boolean + mResetTdcMeas => mResetTdc, --in boolean + mRunTdcMeas => mRunTdc, --in boolean + mGatedPulse => mSP, --out boolean + mAvgOffset => mSpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mAvgOffsetDone => mSpOffsetDoneLcl, --out boolean + mAvgOffsetValid => mSpOffsetValidLcl, --out boolean + SourceClk => SampleClk, --in std_logic + sResetTdc => sResetTdc, --in boolean + sSyncPulseLoadCnt => sLoadSpCounts, --in boolean + sSyncPulsePeriod => sSpPeriodInSClks, --in unsigned(kSourceClksPerPulseMaxBits-1:0) + sSyncPulseHighTime => sSpHighTimeInSClks, --in unsigned(kSourceClksPerPulseMaxBits-1:0) + sSyncPulseEnable => sSpEnable, --in boolean + sGatedPulse => open, --out boolean + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + --vhook_e Pulser SpTransferPulse + --vhook_a kClksPerPulseMaxBits kSClksPerSpPeriodBitsMax + --vhook_a Clk SampleClk + --vhook_a cLoadLimits sLoadSptCounts + --vhook_a cPeriod sSptPeriodInSClks + --vhook_a cHighTime sSptHighTimeInSClks + --vhook_a cEnablePulse sSpEnable + --vhook_a cPulse sSptPulse + SpTransferPulse: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kSClksPerSpPeriodBitsMax) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => SampleClk, --in std_logic + cLoadLimits => sLoadSptCounts, --in boolean + cPeriod => sSptPeriodInSClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => sSptHighTimeInSClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => sSpEnable, --in boolean + cPulse => sSptPulse); --out boolean + + -- Local to output + sSpTransfer <= sSptPulse; + + + -- Cross PPS to SampleClk : ---------------------------------------------------------- + -- Cross it safely and with deterministic delay. + -- ------------------------------------------------------------------------------------ + + -- Keep the module from over-pulsing itself by gating the input with the RFI signal, + -- although at 1 Hz, this module should never run into the RFI de-asserted case + -- by design. + rGatedCptrPulseIn <= rCrossTrigRFI and rPpsPulseRe; + + --vhook_e CrossTrigger CrossCptrPulse + --vhook_a rRP rRptPulse + --vhook_a rReadyForInput rCrossTrigRFI + --vhook_a rEnableTrigger rEnablePpsCrossing + --vhook_a rTriggerIn rGatedCptrPulseIn + --vhook_a sSP sSptPulse + --vhook_a sElasticBufferPtr sPpsClkCrossDelayVal + --vhook_a sTriggerOut sPpsPulse + CrossCptrPulse: entity work.CrossTrigger (rtl) + port map ( + aReset => aReset, --in boolean + RefClk => RefClk, --in std_logic + rRP => rRptPulse, --in boolean + rReadyForInput => rCrossTrigRFI, --out boolean + rEnableTrigger => rEnablePpsCrossing, --in boolean + rTriggerIn => rGatedCptrPulseIn, --in boolean + SampleClk => SampleClk, --in std_logic + sSP => sSptPulse, --in boolean + sElasticBufferPtr => sPpsClkCrossDelayVal, --in unsigned(3:0) + sTriggerOut => sPpsPulse); --out boolean + + +end struct; + + + + + + + +-------------------------------------------------------------------------------- +-- Testbench for TdcTop +-------------------------------------------------------------------------------- + +--synopsys translate_off +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +entity tb_TdcTop is end tb_TdcTop; + +architecture test of tb_TdcTop is + + -- Constants for the clock periods. + constant kSPer : time := 8.000 ns; -- 125.00 MHz + constant kMPer : time := 5.050 ns; -- 198.00 MHz + constant kRPer : time := 100.000 ns; -- 10.00 MHz + + constant kRClksPerRePulsePeriodBitsMax : integer := 24; + constant kRClksPerRpPeriodBitsMax : integer := 16; + constant kSClksPerSpPeriodBitsMax : integer := 16; + + -- Constants for the RP/SP pulses, based on the clock frequencies above. The periods + -- should all divide into one another without remainders, so this is safe to do... + -- High time is 50% duty cycle, or close to it if the period isn't a round number. + constant kRpPeriod : time := 1000 ns; + constant kRpPeriodInRClks : integer := kRpPeriod/kRPer; + constant kRpHighTimeInRClks : integer := integer(floor(real(kRpPeriodInRClks)/2.0)); + constant kRptPeriod : time := 25000 ns; + constant kRptPeriodInRClks : integer := kRptPeriod/kRPer; + constant kRptHighTimeInRClks : integer := integer(floor(real(kRptPeriodInRClks)/2.0)); + constant kSpPeriod : time := 800 ns; + constant kSpPeriodInSClks : integer := kSpPeriod/kSPer; + constant kSpHighTimeInSClks : integer := integer(floor(real(kSpPeriodInSClks)/2.0)); + constant kSptPeriod : time := 25000 ns; + constant kSptPeriodInSClks : integer := kSptPeriod/kSPer; + constant kSptHighTimeInSClks : integer := integer(floor(real(kSptPeriodInSClks)/2.0)); + constant kRePulsePeriod : time := 2.500 ms; + constant kRePulsePeriodInRClks : integer := kRePulsePeriod/kRPer; + constant kRePulseHighTimeInRClks : integer := integer(floor(real(kRePulsePeriodInRClks)/2.0)); + + -- This doesn't come out to a nice number (or shouldn't), but that's ok. Round up. + constant kMeasClksPerRp : integer := kRpPeriod/kMPer+1; + + -- Inputs to DUT + constant kPulsePeriodCntSize : integer := integer(ceil(log2(real(kMeasClksPerRp)))); + constant kFreqRefPeriodsToCheckSize: integer := 12; -- usually 17, but to save run time... + constant kSyncPeriodsToStampSize : integer := 10; + + constant kMeasurementTimeout : time := + kMPer*(kMeasClksPerRp*(2**kSyncPeriodsToStampSize) + + 40*(2**kSyncPeriodsToStampSize) + + kMeasClksPerRp*(2**kFreqRefPeriodsToCheckSize) + ); + + --vhook_sigstart + signal aReset: boolean; + signal MeasClk: std_logic := '0'; + signal mOffsetsDone: boolean; + signal mOffsetsValid: boolean; + signal mRpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + signal mSpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + signal RefClk: std_logic := '0'; + signal rEnablePpsCrossing: boolean; + signal rEnableTdc: boolean; + signal rGatedPulseToPin: std_logic; + signal rLoadRePulseCounts: boolean; + signal rLoadRpCounts: boolean; + signal rLoadRptCounts: boolean; + signal rPpsPulse: boolean; + signal rPpsPulseCaptured: boolean; + signal rPulserEnableDelayVal: unsigned(3 downto 0); + signal rReRunEnable: boolean; + signal rResetTdc: boolean; + signal rResetTdcDone: boolean; + signal rRpTransfer: boolean; + signal SampleClk: std_logic := '0'; + signal sGatedPulseToPin: std_logic; + signal sLoadSpCounts: boolean; + signal sLoadSptCounts: boolean; + signal sPpsClkCrossDelayVal: unsigned(3 downto 0); + signal sPpsPulse: boolean; + signal sSpTransfer: boolean; + --vhook_sigend + + signal StopSim : boolean; + signal EnableOutputChecks : boolean := true; + + signal ExpectedRpOutput, + ExpectedFinalMeas, + ExpectedSpOutput : real := 0.0; + + alias mRunTdc is <>; + alias mSP is <>; + alias mRP is <>; + + procedure ClkWait( + signal Clk : in std_logic; + X : positive := 1) is + begin + for i in 1 to X loop + wait until rising_edge(Clk); + end loop; + end procedure ClkWait; + + function OffsetToReal (Offset : unsigned) return real is + variable TempVar : real := 0.0; + begin + TempVar := + real(to_integer( + Offset(Offset'high downto kFreqRefPeriodsToCheckSize+kSyncPeriodsToStampSize))) + + real(to_integer( + Offset(kFreqRefPeriodsToCheckSize+kSyncPeriodsToStampSize-1 downto 0)))* + real(2.0**(-(kFreqRefPeriodsToCheckSize+kSyncPeriodsToStampSize))); + return TempVar; + end OffsetToReal; + +begin + + SampleClk <= not SampleClk after kSPer/2 when not StopSim else '0'; + RefClk <= not RefClk after kRPer/2 when not StopSim else '0'; + MeasClk <= not MeasClk after kMPer/2 when not StopSim else '0'; + + + main: process + begin + -- Defaults, per instructions in Purpose + sPpsClkCrossDelayVal <= to_unsigned(0, sPpsClkCrossDelayVal'length); + rPulserEnableDelayVal <= to_unsigned(1, rPulserEnableDelayVal'length); + rResetTdc <= true; + rEnableTdc <= false; + rReRunEnable <= false; + rEnablePpsCrossing <= false; + rPpsPulse <= false; + rLoadRePulseCounts <= false; + rLoadRpCounts <= false; + rLoadRptCounts <= false; + sLoadSpCounts <= false; + sLoadSptCounts <= false; + + aReset <= true, false after kRPer*4; + ClkWait(RefClk,10); + + -- Step 0 : ------------------------------------------------------------------------- + -- Prior to de-asserting reset, we need to load the counters, so pulse the loads. + ClkWait(RefClk); + rLoadRePulseCounts <= true; + rLoadRpCounts <= true; + rLoadRptCounts <= true; + ClkWait(RefClk); + rLoadRePulseCounts <= false; + rLoadRpCounts <= false; + rLoadRptCounts <= false; + ClkWait(SampleClk); + sLoadSpCounts <= true; + sLoadSptCounts <= true; + ClkWait(SampleClk); + sLoadSpCounts <= false; + sLoadSptCounts <= false; + + + -- Step 1 : ------------------------------------------------------------------------- + report "De-asserting Synchronous Reset..." severity note; + ClkWait(RefClk); + rResetTdc <= false; + wait until not rResetTdcDone for (kRPer*4)+(kMPer*2); + assert not rResetTdcDone + report "rRestTdcDone didn't de-assert in time" + severity error; + + + -- Step 2 : ------------------------------------------------------------------------- + report "Enabling TDC Measurement & Capturing PPS..." severity note; + rEnableTdc <= true; + ClkWait(RefClk,5); + + -- Trigger a PPS one-cycle pulse. + rPpsPulse <= true; + ClkWait(RefClk); + rPpsPulse <= false; + ClkWait(RefClk); + assert rPpsPulseCaptured report "PPS not captured" severity error; + + + -- Step 3 : ------------------------------------------------------------------------- + report "Waiting for Measurements to Complete..." severity note; + wait until mOffsetsDone for kMeasurementTimeout; + assert mOffsetsDone + report "Offset measurements not completed within timeout" + severity error; + + -- Offset values checked below in CheckOutput. + + report "Printing Results..." & LF & + "RP: " & real'image(OffsetToReal(mRpOffset)) & + " Expected: " & real'image(ExpectedRpOutput) & LF & + "SP: " & real'image(OffsetToReal(mSpOffset)) & + " Expected: " & real'image(ExpectedSpOutput) & LF & + "Meas: " & real'image((OffsetToReal(mSpOffset-mRpOffset)*real(kMPer/1 ns)+ + real(kRPer/1 ns)-real(kSPer/1 ns))/real(kSPer/1 ns)) & + " Expected: " & real'image(ExpectedFinalMeas) + severity note; + + + -- Step 4 : ------------------------------------------------------------------------- + -- Trigger another PPS one-cycle pulse to watch it all cross over correctly. + -- Issue the trigger around where a real PPS pulse will come (RE of RP). + -- First, set the programmable delay sPpsClkCrossDelayVal. + ClkWait(SampleClk); + sPpsClkCrossDelayVal <= to_unsigned(4, sPpsClkCrossDelayVal'length); + ClkWait(RefClk); + rEnablePpsCrossing <= true; + wait until rRpTransfer and not rRpTransfer'delayed; + rPpsPulse <= true; + ClkWait(RefClk); + rPpsPulse <= false; + ClkWait(RefClk); + + -- We expect the PPS output pulse to arrive after FE and RE of sSP have passed, + -- and then a few extra cycles of SampleClk delay on there as well. + wait until (not sSpTransfer) and ( sSpTransfer'delayed); -- FE + wait until ( sSpTransfer) and (not sSpTransfer'delayed); -- RE + ClkWait(SampleClk, 2 + to_integer(sPpsClkCrossDelayVal)); + -- Check on falling edge of clock. + wait until falling_edge(SampleClk); + assert sPpsPulse and not sPpsPulse'delayed(kSPer) report "sPpsPulse did not assert"; + wait until falling_edge(SampleClk); + assert not sPpsPulse report "sPpsPulse did not pulse correctly"; + + + -- Step 5 : ------------------------------------------------------------------------- + report "Repeating TDC Measurement..." severity note; + ClkWait(RefClk); + rReRunEnable <= true; + + -- Now wait for the measurement to complete. + wait until mOffsetsValid for kMeasurementTimeout; + assert mOffsetsValid + report "Offset measurements not re-completed within timeout" + severity error; + + -- Offset values checked below in CheckOutput. + + report "Printing Results..." & LF & + "RP: " & real'image(OffsetToReal(mRpOffset)) & + " Expected: " & real'image(ExpectedRpOutput) & LF & + "SP: " & real'image(OffsetToReal(mSpOffset)) & + " Expected: " & real'image(ExpectedSpOutput) & LF & + "Meas: " & real'image((OffsetToReal(mSpOffset-mRpOffset)*real(kMPer/1 ns)+ + real(kRPer/1 ns)-real(kSPer/1 ns))/real(kSPer/1 ns)) & + " Expected: " & real'image(ExpectedFinalMeas) + severity note; + + ClkWait(MeasClk,100); + + + -- Let it run for a while : --------------------------------------------------------- + for i in 0 to 9 loop + wait until mOffsetsValid for kMeasurementTimeout; + assert mOffsetsValid + report "Offset measurements not re-completed within timeout" + severity error; + report "Printing Results..." & LF & + "RP: " & real'image(OffsetToReal(mRpOffset)) & + " Expected: " & real'image(ExpectedRpOutput) & LF & + "SP: " & real'image(OffsetToReal(mSpOffset)) & + " Expected: " & real'image(ExpectedSpOutput) & LF & + "Meas: " & real'image((OffsetToReal(mSpOffset-mRpOffset)*real(kMPer/1 ns)+ + real(kRPer/1 ns)-real(kSPer/1 ns))/real(kSPer/1 ns)) & + " Expected: " & real'image(ExpectedFinalMeas) + severity note; + end loop; + + + -- And stop it : -------------------------------------------------------------------- + report "Stopping Repeating TDC Measurements..." severity note; + ClkWait(RefClk); + rReRunEnable <= false; + -- Wait to make sure it doesn't keep going. + wait until mOffsetsValid + for 2*(kMPer*(kMeasClksPerRp*(2**kSyncPeriodsToStampSize) + 40*(2**kSyncPeriodsToStampSize))); + assert not mOffsetsValid; + + + + -- Let it run for a while : --------------------------------------------------------- + report "Starting again Repeating TDC Measurements..." severity note; + ClkWait(RefClk); + rReRunEnable <= true; + for i in 0 to 2 loop + wait until mOffsetsValid for kMeasurementTimeout; + assert mOffsetsValid + report "Offset measurements not re-completed within timeout" + severity error; + report "Printing Results..." & LF & + "RP: " & real'image(OffsetToReal(mRpOffset)) & + " Expected: " & real'image(ExpectedRpOutput) & LF & + "SP: " & real'image(OffsetToReal(mSpOffset)) & + " Expected: " & real'image(ExpectedSpOutput) & LF & + "Meas: " & real'image((OffsetToReal(mSpOffset-mRpOffset)*real(kMPer/1 ns)+ + real(kRPer/1 ns)-real(kSPer/1 ns))/real(kSPer/1 ns)) & + " Expected: " & real'image(ExpectedFinalMeas) + severity note; + end loop; + + + StopSim <= true; + wait; + end process; + + + ExpectedFinalMeasGen : process + variable StartTime : time := 0 ns; + begin + wait until rPpsPulse; + wait until rRpTransfer; + StartTime := now; + wait until sSpTransfer; + ExpectedFinalMeas <= real((now - StartTime)/1 ps)/real((kSPer/1 ps)); + wait until rResetTdc; + end process; + + + ExpectedRpOutputGen : process + variable StartTime : time := 0 ns; + begin + wait until mRunTdc; + StartTime := now; + wait until mRP; + ExpectedRpOutput <= real((now - StartTime)/1 ps)/real((kMPer/1 ps)); + wait until mOffsetsValid; + end process; + + ExpectedSpOutputGen : process + variable StartTime : time := 0 ns; + begin + wait until mRunTdc; + StartTime := now; + wait until mSP; + ExpectedSpOutput <= real((now - StartTime)/1 ps)/real((kMPer/1 ps)); + wait until mOffsetsValid; + end process; + + CheckOutput : process(MeasClk) + begin + if falling_edge(MeasClk) then + if EnableOutputChecks then + + if mOffsetsValid then + assert (OffsetToReal(mRpOffset) < ExpectedRpOutput + 1.0) and + (OffsetToReal(mRpOffset) > ExpectedRpOutput - 1.0) + report "Mismatch between mRpOffset and expected!" & LF & + "Actual: " & real'image(OffsetToReal(mRpOffset)) & LF & + "Expect: " & real'image(ExpectedRpOutput) + severity error; + assert (OffsetToReal(mSpOffset) < ExpectedSpOutput + 1.0) and + (OffsetToReal(mSpOffset) > ExpectedSpOutput - 1.0) + report "Mismatch between mSpOffset and expected!" & LF & + "Actual: " & real'image(OffsetToReal(mSpOffset)) & LF & + "Expect: " & real'image(ExpectedSpOutput) + severity error; + end if; + end if; + end if; + end process; + + + --vhook_e TdcTop dutx + --vhook_a rRpPeriodInRClks to_unsigned(kRpPeriodInRClks, kRClksPerRpPeriodBitsMax) + --vhook_a rRpHighTimeInRClks to_unsigned(kRpHighTimeInRClks, kRClksPerRpPeriodBitsMax) + --vhook_a sSpPeriodInSClks to_unsigned(kSpPeriodInSClks, kSClksPerSpPeriodBitsMax) + --vhook_a sSpHighTimeInSClks to_unsigned(kSpHighTimeInSClks, kSClksPerSpPeriodBitsMax) + --vhook_a rRptPeriodInRClks to_unsigned(kRptPeriodInRClks, kRClksPerRpPeriodBitsMax) + --vhook_a rRptHighTimeInRClks to_unsigned(kRptHighTimeInRClks, kRClksPerRpPeriodBitsMax) + --vhook_a sSptPeriodInSClks to_unsigned(kSptPeriodInSClks, kSClksPerSpPeriodBitsMax) + --vhook_a sSptHighTimeInSClks to_unsigned(kSptHighTimeInSClks, kSClksPerSpPeriodBitsMax) + --vhook_a rRePulsePeriodInRClks to_unsigned(kRePulsePeriodInRClks, kRClksPerRePulsePeriodBitsMax) + --vhook_a rRePulseHighTimeInRClks to_unsigned(kRePulseHighTimeInRClks, kRClksPerRePulsePeriodBitsMax) + dutx: entity work.TdcTop (struct) + generic map ( + kRClksPerRePulsePeriodBitsMax => kRClksPerRePulsePeriodBitsMax, --integer range 3:32 :=24 + kRClksPerRpPeriodBitsMax => kRClksPerRpPeriodBitsMax, --integer range 3:16 :=16 + kSClksPerSpPeriodBitsMax => kSClksPerSpPeriodBitsMax, --integer range 3:16 :=16 + kPulsePeriodCntSize => kPulsePeriodCntSize, --integer:=13 + kFreqRefPeriodsToCheckSize => kFreqRefPeriodsToCheckSize, --integer:=17 + kSyncPeriodsToStampSize => kSyncPeriodsToStampSize) --integer:=10 + port map ( + aReset => aReset, --in boolean + RefClk => RefClk, --in std_logic + SampleClk => SampleClk, --in std_logic + MeasClk => MeasClk, --in std_logic + rResetTdc => rResetTdc, --in boolean + rResetTdcDone => rResetTdcDone, --out boolean + rEnableTdc => rEnableTdc, --in boolean + rReRunEnable => rReRunEnable, --in boolean + rPpsPulse => rPpsPulse, --in boolean + rPpsPulseCaptured => rPpsPulseCaptured, --out boolean + rPulserEnableDelayVal => rPulserEnableDelayVal, --in unsigned(3:0) + rEnablePpsCrossing => rEnablePpsCrossing, --in boolean + sPpsClkCrossDelayVal => sPpsClkCrossDelayVal, --in unsigned(3:0) + sPpsPulse => sPpsPulse, --out boolean + mRpOffset => mRpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mSpOffset => mSpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mOffsetsDone => mOffsetsDone, --out boolean + mOffsetsValid => mOffsetsValid, --out boolean + rLoadRePulseCounts => rLoadRePulseCounts, --in boolean + rRePulsePeriodInRClks => to_unsigned(kRePulsePeriodInRClks, kRClksPerRePulsePeriodBitsMax), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0) + rRePulseHighTimeInRClks => to_unsigned(kRePulseHighTimeInRClks, kRClksPerRePulsePeriodBitsMax), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0) + rLoadRpCounts => rLoadRpCounts, --in boolean + rRpPeriodInRClks => to_unsigned(kRpPeriodInRClks, kRClksPerRpPeriodBitsMax), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rRpHighTimeInRClks => to_unsigned(kRpHighTimeInRClks, kRClksPerRpPeriodBitsMax), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rLoadRptCounts => rLoadRptCounts, --in boolean + rRptPeriodInRClks => to_unsigned(kRptPeriodInRClks, kRClksPerRpPeriodBitsMax), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rRptHighTimeInRClks => to_unsigned(kRptHighTimeInRClks, kRClksPerRpPeriodBitsMax), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + sLoadSpCounts => sLoadSpCounts, --in boolean + sSpPeriodInSClks => to_unsigned(kSpPeriodInSClks, kSClksPerSpPeriodBitsMax), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sSpHighTimeInSClks => to_unsigned(kSpHighTimeInSClks, kSClksPerSpPeriodBitsMax), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sLoadSptCounts => sLoadSptCounts, --in boolean + sSptPeriodInSClks => to_unsigned(kSptPeriodInSClks, kSClksPerSpPeriodBitsMax), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sSptHighTimeInSClks => to_unsigned(kSptHighTimeInSClks, kSClksPerSpPeriodBitsMax), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + rRpTransfer => rRpTransfer, --out boolean + sSpTransfer => sSpTransfer, --out boolean + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + +end test; +--synopsys translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/TdcWrapper.vhd b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcWrapper.vhd new file mode 100644 index 000000000..1ab235fe2 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcWrapper.vhd @@ -0,0 +1,397 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- +-- Purpose: +-- +-- Wrapper for the TDC and register control modules. +-- +-- vreview_group Tdc +-- vreview_reviewers dabaker sgupta jmarsar +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + +entity TdcWrapper is + port ( + -- Clocks and Resets : -------------------------------------------------------------- + -- Bus Clock and synchronous bus reset. + BusClk : in std_logic; + bBusReset : in std_logic; + -- Reference Clock + RefClk : in std_logic; + -- Sample Clock + SampleClk : in std_logic; + -- Measurement Clock must run at a very specific frequency, determined by the + -- SampleClk, RefClk, and Sync Pulse rates... oh and a lot of math. + MeasClk : in std_logic; + + + -- Register Port: ------------------------------------------------------------------- + bSyncRegPortOut : out RegPortOut_t; + bSyncRegPortIn : in RegPortIn_t; + + + -- PPS In and Out : ----------------------------------------------------------------- + -- Only required to pulse 1 RefClk cycle. + rPpsPulse : in std_logic; + -- PPS pulse output on the SampleClk domain. + sPpsPulse : out std_logic; + + + -- Sync Pulse Outputs : ------------------------------------------------------------- + -- The repeating pulses can be useful for many things, including passing triggers. + rRpTransfer : out std_logic; + sSpTransfer : out std_logic; + + -- Pin bouncers out and in. Must go to unused and unconnected pins on the FPGA! + rGatedPulseToPin : inout std_logic; + sGatedPulseToPin : inout std_logic + ); +end TdcWrapper; + + +architecture struct of TdcWrapper is + + component SyncRegsIfc + port ( + aBusReset : in std_logic; + bBusReset : in std_logic; + BusClk : in std_logic; + aTdcReset : out std_logic; + bRegPortInFlat : in std_logic_vector(49 downto 0); + bRegPortOutFlat : out std_logic_vector(33 downto 0); + RefClk : in std_logic; + rResetTdc : out std_logic; + rResetTdcDone : in std_logic; + rEnableTdc : out std_logic; + rReRunEnable : out std_logic; + rEnablePpsCrossing : out std_logic; + rPpsPulseCaptured : in std_logic; + rPulserEnableDelayVal : out std_logic_vector(3 downto 0); + SampleClk : in std_logic; + sPpsClkCrossDelayVal : out std_logic_vector(3 downto 0); + MeasClk : in std_logic; + mRpOffset : in std_logic_vector(39 downto 0); + mSpOffset : in std_logic_vector(39 downto 0); + mOffsetsDone : in std_logic; + mOffsetsValid : in std_logic; + rLoadRePulseCounts : out std_logic; + rRePulsePeriodInRClks : out std_logic_vector(23 downto 0); + rRePulseHighTimeInRClks : out std_logic_vector(23 downto 0); + rLoadRpCounts : out std_logic; + rRpPeriodInRClks : out std_logic_vector(15 downto 0); + rRpHighTimeInRClks : out std_logic_vector(15 downto 0); + rLoadRptCounts : out std_logic; + rRptPeriodInRClks : out std_logic_vector(15 downto 0); + rRptHighTimeInRClks : out std_logic_vector(15 downto 0); + sLoadSpCounts : out std_logic; + sSpPeriodInSClks : out std_logic_vector(15 downto 0); + sSpHighTimeInSClks : out std_logic_vector(15 downto 0); + sLoadSptCounts : out std_logic; + sSptPeriodInSClks : out std_logic_vector(15 downto 0); + sSptHighTimeInSClks : out std_logic_vector(15 downto 0)); + end component; + + -- Generic values for the TdcTop instantiation below. These generics are the maximum + -- of possible values for all combinations of Sample and Reference clocks for the N3xx + -- family of devices. + constant kRClksPerRePulsePeriodBitsMax : integer := 24; + constant kRClksPerRpPeriodBitsMax : integer := 16; + constant kSClksPerSpPeriodBitsMax : integer := 16; + constant kPulsePeriodCntSize : integer := 13; + -- The following are ideal values for balancing measurement time and accuracy, based + -- on calcs given in the spec doc. + constant kFreqRefPeriodsToCheckSize : integer := 17; + constant kSyncPeriodsToStampSize : integer := 10; + + --vhook_sigstart + signal aTdcReset: std_logic; + signal bSyncRegPortInFlat: std_logic_vector(49 downto 0); + signal bSyncRegPortOutFlat: std_logic_vector(33 downto 0); + signal mOffsetsDone: boolean; + signal mOffsetsValid: boolean; + signal mRpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + signal mSpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + signal rEnablePpsCrossing: std_logic; + signal rEnableTdc: std_logic; + signal rLoadRePulseCounts: std_logic; + signal rLoadRpCounts: std_logic; + signal rLoadRptCounts: std_logic; + signal rPpsPulseCaptured: boolean; + signal rPulserEnableDelayVal: std_logic_vector(3 downto 0); + signal rRePulseHighTimeInRClks: std_logic_vector(kRClksPerRePulsePeriodBitsMax-1 downto 0); + signal rRePulsePeriodInRClks: std_logic_vector(kRClksPerRePulsePeriodBitsMax-1 downto 0); + signal rReRunEnable: std_logic; + signal rResetTdc: std_logic; + signal rResetTdcDone: boolean; + signal rRpHighTimeInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0); + signal rRpPeriodInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0); + signal rRptHighTimeInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0); + signal rRptPeriodInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0); + signal rRpTransferBool: boolean; + signal sLoadSpCounts: std_logic; + signal sLoadSptCounts: std_logic; + signal sPpsClkCrossDelayVal: std_logic_vector(3 downto 0); + signal sPpsPulseAsyncReset: boolean; + signal sSpHighTimeInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0); + signal sSpPeriodInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0); + signal sSptHighTimeInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0); + signal sSptPeriodInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0); + signal sSpTransferBool: boolean; + --vhook_sigend + + signal rPpsPulseAsyncReset_ms, rPpsPulseAsyncReset, + sPpsPulseOut_ms, sPpsPulseOut : std_logic := '0'; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of rPpsPulseAsyncReset_ms : signal is "true"; + attribute ASYNC_REG of rPpsPulseAsyncReset : signal is "true"; + attribute ASYNC_REG of sPpsPulseOut_ms : signal is "true"; + attribute ASYNC_REG of sPpsPulseOut : signal is "true"; + +begin + + -- Cross the PPS from the no-reset domain into the aTdcReset domain since there is a + -- reset crossing going into the TdcWrapper (reset by aTdcReset)! No clock domain + -- crossing here, so crossing a single-cycle pulse is safe. + DoubleSyncToAsyncReset : process (aTdcReset, RefClk) + begin + if to_boolean(aTdcReset) then + rPpsPulseAsyncReset_ms <= '0'; + rPpsPulseAsyncReset <= '0'; + elsif rising_edge(RefClk) then + rPpsPulseAsyncReset_ms <= rPpsPulse; + rPpsPulseAsyncReset <= rPpsPulseAsyncReset_ms; + end if; + end process; + + -- In a similar fashion, cross the output PPS trigger from the async aTdcReset domain + -- to the no-reset of the rest of the design. The odds of this signal triggering a + -- failure are astronomically low (since it only pulses one clock cycle per second), + -- but two flops is worth the assurance it won't mess something else up downstream. + -- Note this double-sync mainly protects against the reset assertion case, since in the + -- de-assertion case sPpsPulseAsyncReset should be zero and not transition for a long + -- time afterwards. Again no clock crossing here, so crossing a single-cycle pulse + -- is safe. + DoubleSyncToNoReset : process (SampleClk) + begin + if rising_edge(SampleClk) then + sPpsPulseOut_ms <= to_stdlogic(sPpsPulseAsyncReset); + sPpsPulseOut <= sPpsPulseOut_ms; + end if; + end process; + + sPpsPulse <= sPpsPulseOut; + + + rRpTransfer <= to_stdlogic(rRpTransferBool); + sSpTransfer <= to_stdlogic(sSpTransferBool); + + --vhook_e TdcTop + --vhook_a aReset to_boolean(aTdcReset) + --vhook_a rResetTdc to_boolean(rResetTdc) + --vhook_a rEnableTdc to_boolean(rEnableTdc) + --vhook_a rReRunEnable to_boolean(rReRunEnable) + --vhook_a rPpsPulse to_boolean(rPpsPulseAsyncReset) + --vhook_a rLoadRePulseCounts to_boolean(rLoadRePulseCounts) + --vhook_a rLoadRpCounts to_boolean(rLoadRpCounts) + --vhook_a rLoadRptCounts to_boolean(rLoadRptCounts) + --vhook_a sLoadSpCounts to_boolean(sLoadSpCounts) + --vhook_a sLoadSptCounts to_boolean(sLoadSptCounts) + --vhook_a rEnablePpsCrossing to_boolean(rEnablePpsCrossing) + --vhook_a rPulserEnableDelayVal unsigned(rPulserEnableDelayVal) + --vhook_a sPpsClkCrossDelayVal unsigned(sPpsClkCrossDelayVal) + --vhook_a rRpTransfer rRpTransferBool + --vhook_a sSpTransfer sSpTransferBool + --vhook_a sPpsPulse sPpsPulseAsyncReset + --vhook_p {^rR(.*)In(.*)Clks} unsigned(rR$1In$2Clks) + --vhook_p {^sS(.*)In(.*)Clks} unsigned(sS$1In$2Clks) + TdcTopx: entity work.TdcTop (struct) + generic map ( + kRClksPerRePulsePeriodBitsMax => kRClksPerRePulsePeriodBitsMax, --integer range 3:32 :=24 + kRClksPerRpPeriodBitsMax => kRClksPerRpPeriodBitsMax, --integer range 3:16 :=16 + kSClksPerSpPeriodBitsMax => kSClksPerSpPeriodBitsMax, --integer range 3:16 :=16 + kPulsePeriodCntSize => kPulsePeriodCntSize, --integer:=13 + kFreqRefPeriodsToCheckSize => kFreqRefPeriodsToCheckSize, --integer:=17 + kSyncPeriodsToStampSize => kSyncPeriodsToStampSize) --integer:=10 + port map ( + aReset => to_boolean(aTdcReset), --in boolean + RefClk => RefClk, --in std_logic + SampleClk => SampleClk, --in std_logic + MeasClk => MeasClk, --in std_logic + rResetTdc => to_boolean(rResetTdc), --in boolean + rResetTdcDone => rResetTdcDone, --out boolean + rEnableTdc => to_boolean(rEnableTdc), --in boolean + rReRunEnable => to_boolean(rReRunEnable), --in boolean + rPpsPulse => to_boolean(rPpsPulseAsyncReset), --in boolean + rPpsPulseCaptured => rPpsPulseCaptured, --out boolean + rPulserEnableDelayVal => unsigned(rPulserEnableDelayVal), --in unsigned(3:0) + rEnablePpsCrossing => to_boolean(rEnablePpsCrossing), --in boolean + sPpsClkCrossDelayVal => unsigned(sPpsClkCrossDelayVal), --in unsigned(3:0) + sPpsPulse => sPpsPulseAsyncReset, --out boolean + mRpOffset => mRpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mSpOffset => mSpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mOffsetsDone => mOffsetsDone, --out boolean + mOffsetsValid => mOffsetsValid, --out boolean + rLoadRePulseCounts => to_boolean(rLoadRePulseCounts), --in boolean + rRePulsePeriodInRClks => unsigned(rRePulsePeriodInRClks), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0) + rRePulseHighTimeInRClks => unsigned(rRePulseHighTimeInRClks), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0) + rLoadRpCounts => to_boolean(rLoadRpCounts), --in boolean + rRpPeriodInRClks => unsigned(rRpPeriodInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rRpHighTimeInRClks => unsigned(rRpHighTimeInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rLoadRptCounts => to_boolean(rLoadRptCounts), --in boolean + rRptPeriodInRClks => unsigned(rRptPeriodInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rRptHighTimeInRClks => unsigned(rRptHighTimeInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + sLoadSpCounts => to_boolean(sLoadSpCounts), --in boolean + sSpPeriodInSClks => unsigned(sSpPeriodInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sSpHighTimeInSClks => unsigned(sSpHighTimeInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sLoadSptCounts => to_boolean(sLoadSptCounts), --in boolean + sSptPeriodInSClks => unsigned(sSptPeriodInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sSptHighTimeInSClks => unsigned(sSptHighTimeInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + rRpTransfer => rRpTransferBool, --out boolean + sSpTransfer => sSpTransferBool, --out boolean + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + -- Expand/compress the RegPort for moving through the netlist boundary. + bSyncRegPortOut <= Unflatten(bSyncRegPortOutFlat); + bSyncRegPortInFlat <= Flatten(bSyncRegPortIn); + + --vhook SyncRegsIfc + --vhook_# Tying this low is safe because the sync reset is used inside SyncRegsIfc. + --vhook_a aBusReset '0' + --vhook_a bRegPortInFlat bSyncRegPortInFlat + --vhook_a bRegPortOutFlat bSyncRegPortOutFlat + --vhook_a rResetTdcDone to_stdlogic(rResetTdcDone) + --vhook_a rPpsPulseCaptured to_stdlogic(rPpsPulseCaptured) + --vhook_a mOffsetsDone to_stdlogic(mOffsetsDone) + --vhook_a mOffsetsValid to_stdlogic(mOffsetsValid) + --vhook_a mRpOffset std_logic_vector(mRpOffset) + --vhook_a mSpOffset std_logic_vector(mSpOffset) + SyncRegsIfcx: SyncRegsIfc + port map ( + aBusReset => '0', --in std_logic + bBusReset => bBusReset, --in std_logic + BusClk => BusClk, --in std_logic + aTdcReset => aTdcReset, --out std_logic + bRegPortInFlat => bSyncRegPortInFlat, --in std_logic_vector(49:0) + bRegPortOutFlat => bSyncRegPortOutFlat, --out std_logic_vector(33:0) + RefClk => RefClk, --in std_logic + rResetTdc => rResetTdc, --out std_logic + rResetTdcDone => to_stdlogic(rResetTdcDone), --in std_logic + rEnableTdc => rEnableTdc, --out std_logic + rReRunEnable => rReRunEnable, --out std_logic + rEnablePpsCrossing => rEnablePpsCrossing, --out std_logic + rPpsPulseCaptured => to_stdlogic(rPpsPulseCaptured), --in std_logic + rPulserEnableDelayVal => rPulserEnableDelayVal, --out std_logic_vector(3:0) + SampleClk => SampleClk, --in std_logic + sPpsClkCrossDelayVal => sPpsClkCrossDelayVal, --out std_logic_vector(3:0) + MeasClk => MeasClk, --in std_logic + mRpOffset => std_logic_vector(mRpOffset), --in std_logic_vector(39:0) + mSpOffset => std_logic_vector(mSpOffset), --in std_logic_vector(39:0) + mOffsetsDone => to_stdlogic(mOffsetsDone), --in std_logic + mOffsetsValid => to_stdlogic(mOffsetsValid), --in std_logic + rLoadRePulseCounts => rLoadRePulseCounts, --out std_logic + rRePulsePeriodInRClks => rRePulsePeriodInRClks, --out std_logic_vector(23:0) + rRePulseHighTimeInRClks => rRePulseHighTimeInRClks, --out std_logic_vector(23:0) + rLoadRpCounts => rLoadRpCounts, --out std_logic + rRpPeriodInRClks => rRpPeriodInRClks, --out std_logic_vector(15:0) + rRpHighTimeInRClks => rRpHighTimeInRClks, --out std_logic_vector(15:0) + rLoadRptCounts => rLoadRptCounts, --out std_logic + rRptPeriodInRClks => rRptPeriodInRClks, --out std_logic_vector(15:0) + rRptHighTimeInRClks => rRptHighTimeInRClks, --out std_logic_vector(15:0) + sLoadSpCounts => sLoadSpCounts, --out std_logic + sSpPeriodInSClks => sSpPeriodInSClks, --out std_logic_vector(15:0) + sSpHighTimeInSClks => sSpHighTimeInSClks, --out std_logic_vector(15:0) + sLoadSptCounts => sLoadSptCounts, --out std_logic + sSptPeriodInSClks => sSptPeriodInSClks, --out std_logic_vector(15:0) + sSptHighTimeInSClks => sSptHighTimeInSClks); --out std_logic_vector(15:0) + + +end struct; + + +-------------------------------------------------------------------------------- +-- Testbench for TdcWrapper +-------------------------------------------------------------------------------- + +--synopsys translate_off +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + +entity tb_TdcWrapper is end tb_TdcWrapper; + +architecture test of tb_TdcWrapper is + + --vhook_sigstart + signal bBusReset: std_logic; + signal bSyncRegPortIn: RegPortIn_t; + signal bSyncRegPortOut: RegPortOut_t; + signal BusClk: std_logic := '0'; + signal MeasClk: std_logic := '0'; + signal RefClk: std_logic := '0'; + signal rGatedPulseToPin: std_logic; + signal rPpsPulse: std_logic; + signal rRpTransfer: std_logic; + signal SampleClk: std_logic := '0'; + signal sGatedPulseToPin: std_logic; + signal sPpsPulse: std_logic; + signal sSpTransfer: std_logic; + --vhook_sigend + +begin + + --vhook_e TdcWrapper dutx + dutx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => RefClk, --in std_logic + SampleClk => SampleClk, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rPpsPulse, --in std_logic + sPpsPulse => sPpsPulse, --out std_logic + rRpTransfer => rRpTransfer, --out std_logic + sSpTransfer => sSpTransfer, --out std_logic + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + main: process + + begin + report "TdcWrapper Test is EMPTY! (but that's ok in this case)" severity note; + --vhook_nowarn tb_TdcWrapper.test.* + wait; + end process; + +end test; +--synopsys translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/mg/Makefile.srcs b/fpga/usrp3/top/n3xx/dboards/mg/Makefile.srcs new file mode 100644 index 000000000..85bb60752 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/Makefile.srcs @@ -0,0 +1,34 @@ +# +# Copyright 2017 Ettus Research LLC +# + +################################################## +# DB IFC Sources +################################################## +MAGNESIUM_DB_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/db_ifc/, \ +DbCore.vhd \ +DaughterboardRegs.vhd \ +ClockingRegs.vhd \ +PkgMgPersonality.vhd \ +PkgDaughterboardRegMap.vhd \ +PkgClockingRegMap.vhd \ +PkgJesdConfig.vhd \ +RadioClocking.vhd \ +Jesd204bXcvrCore.edf \ +)) + +MAGNESIUM_TOP_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \ +n3xx.v \ +)) + +MAGNESIUM_DB_TIMING_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \ +db_timing.xdc \ +)) + +MAGNESIUM_DB0_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \ +db0_pins.xdc \ +)) + +MAGNESIUM_DB1_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \ +db1_pins.xdc \ +)) diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/Makefile b/fpga/usrp3/top/n3xx/dboards/mg/cpld/Makefile new file mode 100644 index 000000000..3fbb7d3bb --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/Makefile @@ -0,0 +1,22 @@ +# +# Copyright 2018 Ettus Research, a National Instruments Company +# + +.PHONY: all clean + +SRCS=TopCpld.qpf TopCpld.qsf Timing.sdc PkgMgCpld.vhd PkgSetup.vhd TopCpld.vhd + +all: output_files/TopCpld.svf + +cpld-magnesium-revc.svf: output_files/TopCpld.pof + quartus_cpf --convert --frequency 10.0MHz --voltage 3.3 --operation p $? $@ + +output_files/TopCpld.pof: $(SRCS) + quartus_map TopCpld + quartus_fit TopCpld + quartus_asm TopCpld + quartus_sta TopCpld + +clean: + rm -rf db incremental_db output_files simulation cpld-magnesium-revc.svf + diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgMgCpld.vhd b/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgMgCpld.vhd new file mode 100644 index 000000000..327183bea --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgMgCpld.vhd @@ -0,0 +1,424 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgMgCpld.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgMgCpld is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- SignatureReg : 0x0 (TopCpld.vhd) + -- MinorRevReg : 0x1 (TopCpld.vhd) + -- MajorRevReg : 0x2 (TopCpld.vhd) + -- BuildCodeLSB : 0x3 (TopCpld.vhd) + -- BuildCodeMSB : 0x4 (TopCpld.vhd) + -- Scratch : 0x5 (TopCpld.vhd) + -- CpldControl : 0x10 (TopCpld.vhd) + -- LmkControl : 0x11 (TopCpld.vhd) + -- LoStatus : 0x12 (TopCpld.vhd) + -- MykonosControl : 0x13 (TopCpld.vhd) + -- PlScratch : 0x40 (TopCpld.vhd) + -- PlCpldControl : 0x41 (TopCpld.vhd) + -- TxCh1_Idle : 0x50 (TopCpld.vhd) + -- RxCh1_0_Idle : 0x51 (TopCpld.vhd) + -- RxCh1_1_Idle : 0x52 (TopCpld.vhd) + -- TxCh1_TxOn : 0x53 (TopCpld.vhd) + -- RxCh1_0_RxOn : 0x54 (TopCpld.vhd) + -- RxCh1_1_RxOn : 0x55 (TopCpld.vhd) + -- TxCh2_Idle : 0x60 (TopCpld.vhd) + -- RxCh2_0_Idle : 0x61 (TopCpld.vhd) + -- RxCh2_1_Idle : 0x62 (TopCpld.vhd) + -- TxCh2_TxOn : 0x63 (TopCpld.vhd) + -- RxCh2_0_RxOn : 0x64 (TopCpld.vhd) + -- RxCh2_1_RxOn : 0x65 (TopCpld.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group PsSpi_CpldRegisters +--=============================================================================== + + -- SignatureReg Register (from TopCpld.vhd) + constant kSignatureReg : integer := 16#0#; -- Register Offset + constant kSignatureRegSize: integer := 16; -- register width in bits + constant kSignatureRegMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kProductSignatureSize : integer := 16; --SignatureReg:ProductSignature + constant kProductSignatureMsb : integer := 15; --SignatureReg:ProductSignature + constant kProductSignature : integer := 0; --SignatureReg:ProductSignature + + -- MinorRevReg Register (from TopCpld.vhd) + constant kMinorRevReg : integer := 16#1#; -- Register Offset + constant kMinorRevRegSize: integer := 16; -- register width in bits + constant kMinorRevRegMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kCpldMinorRevisionSize : integer := 16; --MinorRevReg:CpldMinorRevision + constant kCpldMinorRevisionMsb : integer := 15; --MinorRevReg:CpldMinorRevision + constant kCpldMinorRevision : integer := 0; --MinorRevReg:CpldMinorRevision + + -- MajorRevReg Register (from TopCpld.vhd) + constant kMajorRevReg : integer := 16#2#; -- Register Offset + constant kMajorRevRegSize: integer := 16; -- register width in bits + constant kMajorRevRegMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kCpldMajorRevisionSize : integer := 16; --MajorRevReg:CpldMajorRevision + constant kCpldMajorRevisionMsb : integer := 15; --MajorRevReg:CpldMajorRevision + constant kCpldMajorRevision : integer := 0; --MajorRevReg:CpldMajorRevision + + -- BuildCodeLSB Register (from TopCpld.vhd) + constant kBuildCodeLSB : integer := 16#3#; -- Register Offset + constant kBuildCodeLSBSize: integer := 16; -- register width in bits + constant kBuildCodeLSBMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kBuildCodeHHSize : integer := 8; --BuildCodeLSB:BuildCodeHH + constant kBuildCodeHHMsb : integer := 7; --BuildCodeLSB:BuildCodeHH + constant kBuildCodeHH : integer := 0; --BuildCodeLSB:BuildCodeHH + constant kBuildCodeDDSize : integer := 8; --BuildCodeLSB:BuildCodeDD + constant kBuildCodeDDMsb : integer := 15; --BuildCodeLSB:BuildCodeDD + constant kBuildCodeDD : integer := 8; --BuildCodeLSB:BuildCodeDD + + -- BuildCodeMSB Register (from TopCpld.vhd) + constant kBuildCodeMSB : integer := 16#4#; -- Register Offset + constant kBuildCodeMSBSize: integer := 16; -- register width in bits + constant kBuildCodeMSBMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kBuildCodeMMSize : integer := 8; --BuildCodeMSB:BuildCodeMM + constant kBuildCodeMMMsb : integer := 7; --BuildCodeMSB:BuildCodeMM + constant kBuildCodeMM : integer := 0; --BuildCodeMSB:BuildCodeMM + constant kBuildCodeYYSize : integer := 8; --BuildCodeMSB:BuildCodeYY + constant kBuildCodeYYMsb : integer := 15; --BuildCodeMSB:BuildCodeYY + constant kBuildCodeYY : integer := 8; --BuildCodeMSB:BuildCodeYY + + -- Scratch Register (from TopCpld.vhd) + constant kScratch : integer := 16#5#; -- Register Offset + constant kScratchSize: integer := 16; -- register width in bits + constant kScratchMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kScratchValSize : integer := 16; --Scratch:ScratchVal + constant kScratchValMsb : integer := 15; --Scratch:ScratchVal + constant kScratchVal : integer := 0; --Scratch:ScratchVal + + -- CpldControl Register (from TopCpld.vhd) + constant kCpldControl : integer := 16#10#; -- Register Offset + constant kCpldControlSize: integer := 16; -- register width in bits + constant kCpldControlMask : std_logic_vector(15 downto 0) := X"0001"; + constant kCpldResetSize : integer := 1; --CpldControl:CpldReset + constant kCpldResetMsb : integer := 0; --CpldControl:CpldReset + constant kCpldReset : integer := 0; --CpldControl:CpldReset + + -- LmkControl Register (from TopCpld.vhd) + constant kLmkControl : integer := 16#11#; -- Register Offset + constant kLmkControlSize: integer := 16; -- register width in bits + constant kLmkControlMask : std_logic_vector(15 downto 0) := X"0010"; + constant kVcxoControlSize : integer := 1; --LmkControl:VcxoControl + constant kVcxoControlMsb : integer := 4; --LmkControl:VcxoControl + constant kVcxoControl : integer := 4; --LmkControl:VcxoControl + + -- LoStatus Register (from TopCpld.vhd) + constant kLoStatus : integer := 16#12#; -- Register Offset + constant kLoStatusSize: integer := 16; -- register width in bits + constant kLoStatusMask : std_logic_vector(15 downto 0) := X"0011"; + constant kRxLoLockDetectSize : integer := 1; --LoStatus:RxLoLockDetect + constant kRxLoLockDetectMsb : integer := 0; --LoStatus:RxLoLockDetect + constant kRxLoLockDetect : integer := 0; --LoStatus:RxLoLockDetect + constant kTxLoLockDetectSize : integer := 1; --LoStatus:TxLoLockDetect + constant kTxLoLockDetectMsb : integer := 4; --LoStatus:TxLoLockDetect + constant kTxLoLockDetect : integer := 4; --LoStatus:TxLoLockDetect + + -- MykonosControl Register (from TopCpld.vhd) + constant kMykonosControl : integer := 16#13#; -- Register Offset + constant kMykonosControlSize: integer := 16; -- register width in bits + constant kMykonosControlMask : std_logic_vector(15 downto 0) := X"0001"; + constant kMykonosResetSize : integer := 1; --MykonosControl:MykonosReset + constant kMykonosResetMsb : integer := 0; --MykonosControl:MykonosReset + constant kMykonosReset : integer := 0; --MykonosControl:MykonosReset + +--=============================================================================== +-- Register Group PlSpi_FrontEndControl +--=============================================================================== + + -- Enumerated type Rx1Switch1 + constant kRx1Switch1Size : integer := 4; + constant kTxRxInput : integer := 0; -- Rx1Switch1:TxRxInput + constant kRxLoCalInput : integer := 1; -- Rx1Switch1:RxLoCalInput + constant kTrxSwitchOutput : integer := 2; -- Rx1Switch1:TrxSwitchOutput + constant kRx2Input : integer := 3; -- Rx1Switch1:Rx2Input + + -- Enumerated type Rx1Switch2 + constant kRx1Switch2Size : integer := 4; + constant kShutdownSw2 : integer := 0; -- Rx1Switch2:ShutdownSw2 + constant kLowerFilterBankToSwitch3 : integer := 1; -- Rx1Switch2:LowerFilterBankToSwitch3 + constant kBypassPathToSwitch6 : integer := 2; -- Rx1Switch2:BypassPathToSwitch6 + constant kUpperFilterBankToSwitch4 : integer := 3; -- Rx1Switch2:UpperFilterBankToSwitch4 + + -- Enumerated type Rx1Switch3 + constant kRx1Switch3Size : integer := 7; + constant kFilter2100x2850MHz : integer := 0; -- Rx1Switch3:Filter2100x2850MHz + constant kFilter0490LpMHz : integer := 1; -- Rx1Switch3:Filter0490LpMHz + constant kFilter1600x2250MHz : integer := 2; -- Rx1Switch3:Filter1600x2250MHz + constant kFilter0440x0530MHz : integer := 4; -- Rx1Switch3:Filter0440x0530MHz + constant kFilter0650x1000MHz : integer := 5; -- Rx1Switch3:Filter0650x1000MHz + constant kFilter1100x1575MHz : integer := 6; -- Rx1Switch3:Filter1100x1575MHz + constant kShutdownSw3 : integer := 7; -- Rx1Switch3:ShutdownSw3 + + -- Enumerated type Rx1Switch4 + constant kRx1Switch4Size : integer := 3; + constant kFilter2100x2850MHzFrom : integer := 1; -- Rx1Switch4:Filter2100x2850MHzFrom + constant kFilter1600x2250MHzFrom : integer := 2; -- Rx1Switch4:Filter1600x2250MHzFrom + constant kFilter2700HpMHz : integer := 4; -- Rx1Switch4:Filter2700HpMHz + + -- Enumerated type Rx1Switch5 + constant kRx1Switch5Size : integer := 4; + constant kFilter0440x0530MHzFrom : integer := 1; -- Rx1Switch5:Filter0440x0530MHzFrom + constant kFilter1100x1575MHzFrom : integer := 2; -- Rx1Switch5:Filter1100x1575MHzFrom + constant kFilter0490LpMHzFrom : integer := 4; -- Rx1Switch5:Filter0490LpMHzFrom + constant kFilter0650x1000MHzFrom : integer := 8; -- Rx1Switch5:Filter0650x1000MHzFrom + + -- Enumerated type Rx1Switch6 + constant kRx1Switch6Size : integer := 3; + constant kLowerFilterBankFromSwitch5 : integer := 1; -- Rx1Switch6:LowerFilterBankFromSwitch5 + constant kUpperFilterBankFromSwitch4 : integer := 2; -- Rx1Switch6:UpperFilterBankFromSwitch4 + constant kBypassPathFromSwitch2 : integer := 4; -- Rx1Switch6:BypassPathFromSwitch2 + + -- Enumerated type TrxSwitch + constant kTrxSwitchSize : integer := 4; + constant kFromLowerFilterBankTxSw1 : integer := 0; -- TrxSwitch:FromLowerFilterBankTxSw1 + constant kFromTxUpperFilterBankLp6400MHz : integer := 1; -- TrxSwitch:FromTxUpperFilterBankLp6400MHz + constant kRxChannelPath : integer := 2; -- TrxSwitch:RxChannelPath + constant kBypassPathToTxSw3 : integer := 3; -- TrxSwitch:BypassPathToTxSw3 + + -- Enumerated type TxSwitch1 + constant kTxSwitch1Size : integer := 4; + constant kShutdownTxSw1 : integer := 0; -- TxSwitch1:ShutdownTxSw1 + constant kFromTxFilterLp1700MHz : integer := 1; -- TxSwitch1:FromTxFilterLp1700MHz + constant kFromTxFilterLp3400MHz : integer := 2; -- TxSwitch1:FromTxFilterLp3400MHz + constant kFromTxFilterLp0800MHz : integer := 3; -- TxSwitch1:FromTxFilterLp0800MHz + + -- Enumerated type TxSwitch2 + constant kTxSwitch2Size : integer := 4; + constant kToTxFilterLp3400MHz : integer := 1; -- TxSwitch2:ToTxFilterLp3400MHz + constant kToTxFilterLp1700MHz : integer := 2; -- TxSwitch2:ToTxFilterLp1700MHz + constant kToTxFilterLp0800MHz : integer := 4; -- TxSwitch2:ToTxFilterLp0800MHz + constant kToTxFilterLp6400MHz : integer := 8; -- TxSwitch2:ToTxFilterLp6400MHz + + -- Enumerated type TxSwitch3 + constant kTxSwitch3Size : integer := 2; + constant kToTxFilterBanks : integer := 0; -- TxSwitch3:ToTxFilterBanks + constant kBypassPathToTrxSw : integer := 1; -- TxSwitch3:BypassPathToTrxSw + + -- PlScratch Register (from TopCpld.vhd) + constant kPlScratch : integer := 16#40#; -- Register Offset + constant kPlScratchSize: integer := 16; -- register width in bits + constant kPlScratchMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kPlScratchValSize : integer := 16; --PlScratch:PlScratchVal + constant kPlScratchValMsb : integer := 15; --PlScratch:PlScratchVal + constant kPlScratchVal : integer := 0; --PlScratch:PlScratchVal + + -- PlCpldControl Register (from TopCpld.vhd) + constant kPlCpldControl : integer := 16#41#; -- Register Offset + constant kPlCpldControlSize: integer := 16; -- register width in bits + constant kPlCpldControlMask : std_logic_vector(15 downto 0) := X"0001"; + constant kPlCpldResetSize : integer := 1; --PlCpldControl:PlCpldReset + constant kPlCpldResetMsb : integer := 0; --PlCpldControl:PlCpldReset + constant kPlCpldReset : integer := 0; --PlCpldControl:PlCpldReset + + -- TxCh1_Idle Register (from TopCpld.vhd) + constant kTxCh1_Idle : integer := 16#50#; -- Register Offset + constant kTxCh1_IdleSize: integer := 16; -- register width in bits + constant kTxCh1_IdleMask : std_logic_vector(15 downto 0) := X"7fff"; + constant kCh1TxSw1Size : integer := 2; --TxCh1_Idle:Ch1TxSw1 + constant kCh1TxSw1Msb : integer := 1; --TxCh1_Idle:Ch1TxSw1 + constant kCh1TxSw1 : integer := 0; --TxCh1_Idle:Ch1TxSw1 + constant kCh1TxSw2Size : integer := 4; --TxCh1_Idle:Ch1TxSw2 + constant kCh1TxSw2Msb : integer := 5; --TxCh1_Idle:Ch1TxSw2 + constant kCh1TxSw2 : integer := 2; --TxCh1_Idle:Ch1TxSw2 + constant kCh1TxSw3Size : integer := 1; --TxCh1_Idle:Ch1TxSw3 + constant kCh1TxSw3Msb : integer := 6; --TxCh1_Idle:Ch1TxSw3 + constant kCh1TxSw3 : integer := 6; --TxCh1_Idle:Ch1TxSw3 + constant kCh1TxLowbandMixerPathSelectSize : integer := 1; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect + constant kCh1TxLowbandMixerPathSelectMsb : integer := 7; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect + constant kCh1TxLowbandMixerPathSelect : integer := 7; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect + constant kCh1TxMixerEnSize : integer := 1; --TxCh1_Idle:Ch1TxMixerEn + constant kCh1TxMixerEnMsb : integer := 8; --TxCh1_Idle:Ch1TxMixerEn + constant kCh1TxMixerEn : integer := 8; --TxCh1_Idle:Ch1TxMixerEn + constant kCh1TxAmpEnSize : integer := 1; --TxCh1_Idle:Ch1TxAmpEn + constant kCh1TxAmpEnMsb : integer := 9; --TxCh1_Idle:Ch1TxAmpEn + constant kCh1TxAmpEn : integer := 9; --TxCh1_Idle:Ch1TxAmpEn + constant kCh1TxPaEnSize : integer := 1; --TxCh1_Idle:Ch1TxPaEn + constant kCh1TxPaEnMsb : integer := 10; --TxCh1_Idle:Ch1TxPaEn + constant kCh1TxPaEn : integer := 10; --TxCh1_Idle:Ch1TxPaEn + constant kCh1SwTrxSize : integer := 2; --TxCh1_Idle:Ch1SwTrx + constant kCh1SwTrxMsb : integer := 12; --TxCh1_Idle:Ch1SwTrx + constant kCh1SwTrx : integer := 11; --TxCh1_Idle:Ch1SwTrx + constant kCh1TxLedSize : integer := 1; --TxCh1_Idle:Ch1TxLed + constant kCh1TxLedMsb : integer := 13; --TxCh1_Idle:Ch1TxLed + constant kCh1TxLed : integer := 13; --TxCh1_Idle:Ch1TxLed + constant kCh1MykEnTxSize : integer := 1; --TxCh1_Idle:Ch1MykEnTx + constant kCh1MykEnTxMsb : integer := 14; --TxCh1_Idle:Ch1MykEnTx + constant kCh1MykEnTx : integer := 14; --TxCh1_Idle:Ch1MykEnTx + + -- RxCh1_0_Idle Register (from TopCpld.vhd) + constant kRxCh1_0_Idle : integer := 16#51#; -- Register Offset + constant kRxCh1_0_IdleSize: integer := 16; -- register width in bits + constant kRxCh1_0_IdleMask : std_logic_vector(15 downto 0) := X"3fff"; + constant kCh1RxSw1Size : integer := 2; --RxCh1_0_Idle:Ch1RxSw1 + constant kCh1RxSw1Msb : integer := 1; --RxCh1_0_Idle:Ch1RxSw1 + constant kCh1RxSw1 : integer := 0; --RxCh1_0_Idle:Ch1RxSw1 + constant kCh1RxSw2Size : integer := 2; --RxCh1_0_Idle:Ch1RxSw2 + constant kCh1RxSw2Msb : integer := 3; --RxCh1_0_Idle:Ch1RxSw2 + constant kCh1RxSw2 : integer := 2; --RxCh1_0_Idle:Ch1RxSw2 + constant kCh1RxSw3Size : integer := 3; --RxCh1_0_Idle:Ch1RxSw3 + constant kCh1RxSw3Msb : integer := 6; --RxCh1_0_Idle:Ch1RxSw3 + constant kCh1RxSw3 : integer := 4; --RxCh1_0_Idle:Ch1RxSw3 + constant kCh1RxSw4Size : integer := 3; --RxCh1_0_Idle:Ch1RxSw4 + constant kCh1RxSw4Msb : integer := 9; --RxCh1_0_Idle:Ch1RxSw4 + constant kCh1RxSw4 : integer := 7; --RxCh1_0_Idle:Ch1RxSw4 + constant kCh1RxSw5Size : integer := 4; --RxCh1_0_Idle:Ch1RxSw5 + constant kCh1RxSw5Msb : integer := 13; --RxCh1_0_Idle:Ch1RxSw5 + constant kCh1RxSw5 : integer := 10; --RxCh1_0_Idle:Ch1RxSw5 + + -- RxCh1_1_Idle Register (from TopCpld.vhd) + constant kRxCh1_1_Idle : integer := 16#52#; -- Register Offset + constant kRxCh1_1_IdleSize: integer := 16; -- register width in bits + constant kRxCh1_1_IdleMask : std_logic_vector(15 downto 0) := X"07ff"; + constant kCh1RxSw6Size : integer := 3; --RxCh1_1_Idle:Ch1RxSw6 + constant kCh1RxSw6Msb : integer := 2; --RxCh1_1_Idle:Ch1RxSw6 + constant kCh1RxSw6 : integer := 0; --RxCh1_1_Idle:Ch1RxSw6 + constant kCh1RxLowbandMixerPathSelectSize : integer := 1; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect + constant kCh1RxLowbandMixerPathSelectMsb : integer := 3; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect + constant kCh1RxLowbandMixerPathSelect : integer := 3; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect + constant kCh1RxMixerEnSize : integer := 1; --RxCh1_1_Idle:Ch1RxMixerEn + constant kCh1RxMixerEnMsb : integer := 4; --RxCh1_1_Idle:Ch1RxMixerEn + constant kCh1RxMixerEn : integer := 4; --RxCh1_1_Idle:Ch1RxMixerEn + constant kCh1RxAmpEnSize : integer := 1; --RxCh1_1_Idle:Ch1RxAmpEn + constant kCh1RxAmpEnMsb : integer := 5; --RxCh1_1_Idle:Ch1RxAmpEn + constant kCh1RxAmpEn : integer := 5; --RxCh1_1_Idle:Ch1RxAmpEn + constant kCh1RxLna1EnSize : integer := 1; --RxCh1_1_Idle:Ch1RxLna1En + constant kCh1RxLna1EnMsb : integer := 6; --RxCh1_1_Idle:Ch1RxLna1En + constant kCh1RxLna1En : integer := 6; --RxCh1_1_Idle:Ch1RxLna1En + constant kCh1RxLna2EnSize : integer := 1; --RxCh1_1_Idle:Ch1RxLna2En + constant kCh1RxLna2EnMsb : integer := 7; --RxCh1_1_Idle:Ch1RxLna2En + constant kCh1RxLna2En : integer := 7; --RxCh1_1_Idle:Ch1RxLna2En + constant kCh1Rx2LedSize : integer := 1; --RxCh1_1_Idle:Ch1Rx2Led + constant kCh1Rx2LedMsb : integer := 8; --RxCh1_1_Idle:Ch1Rx2Led + constant kCh1Rx2Led : integer := 8; --RxCh1_1_Idle:Ch1Rx2Led + constant kCh1RxLedSize : integer := 1; --RxCh1_1_Idle:Ch1RxLed + constant kCh1RxLedMsb : integer := 9; --RxCh1_1_Idle:Ch1RxLed + constant kCh1RxLed : integer := 9; --RxCh1_1_Idle:Ch1RxLed + constant kCh1MykEnRxSize : integer := 1; --RxCh1_1_Idle:Ch1MykEnRx + constant kCh1MykEnRxMsb : integer := 10; --RxCh1_1_Idle:Ch1MykEnRx + constant kCh1MykEnRx : integer := 10; --RxCh1_1_Idle:Ch1MykEnRx + + -- TxCh1_TxOn Register (from TopCpld.vhd) + constant kTxCh1_TxOn : integer := 16#53#; -- Register Offset + constant kTxCh1_TxOnSize: integer := 16; -- register width in bits + constant kTxCh1_TxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh1_0_RxOn Register (from TopCpld.vhd) + constant kRxCh1_0_RxOn : integer := 16#54#; -- Register Offset + constant kRxCh1_0_RxOnSize: integer := 16; -- register width in bits + constant kRxCh1_0_RxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh1_1_RxOn Register (from TopCpld.vhd) + constant kRxCh1_1_RxOn : integer := 16#55#; -- Register Offset + constant kRxCh1_1_RxOnSize: integer := 16; -- register width in bits + constant kRxCh1_1_RxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- TxCh2_Idle Register (from TopCpld.vhd) + constant kTxCh2_Idle : integer := 16#60#; -- Register Offset + constant kTxCh2_IdleSize: integer := 16; -- register width in bits + constant kTxCh2_IdleMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh2_0_Idle Register (from TopCpld.vhd) + constant kRxCh2_0_Idle : integer := 16#61#; -- Register Offset + constant kRxCh2_0_IdleSize: integer := 16; -- register width in bits + constant kRxCh2_0_IdleMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh2_1_Idle Register (from TopCpld.vhd) + constant kRxCh2_1_Idle : integer := 16#62#; -- Register Offset + constant kRxCh2_1_IdleSize: integer := 16; -- register width in bits + constant kRxCh2_1_IdleMask : std_logic_vector(15 downto 0) := X"0000"; + + -- TxCh2_TxOn Register (from TopCpld.vhd) + constant kTxCh2_TxOn : integer := 16#63#; -- Register Offset + constant kTxCh2_TxOnSize: integer := 16; -- register width in bits + constant kTxCh2_TxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh2_0_RxOn Register (from TopCpld.vhd) + constant kRxCh2_0_RxOn : integer := 16#64#; -- Register Offset + constant kRxCh2_0_RxOnSize: integer := 16; -- register width in bits + constant kRxCh2_0_RxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh2_1_RxOn Register (from TopCpld.vhd) + constant kRxCh2_1_RxOn : integer := 16#65#; -- Register Offset + constant kRxCh2_1_RxOnSize: integer := 16; -- register width in bits + constant kRxCh2_1_RxOnMask : std_logic_vector(15 downto 0) := X"0000"; + +end package; + +package body PkgMgCpld is + + -- function kSignatureRegRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMinorRevRegRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMajorRevRegRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kBuildCodeLSBRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kBuildCodeMSBRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kScratchRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kCpldControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kLmkControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kLoStatusRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMykonosControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kPlScratchRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kPlCpldControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kTxCh1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh1_0_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh1_1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kTxCh1_TxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh1_0_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh1_1_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kTxCh2_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh2_0_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh2_1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kTxCh2_TxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh2_0_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh2_1_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgSetup.vhd b/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgSetup.vhd new file mode 100644 index 000000000..e19358912 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgSetup.vhd @@ -0,0 +1,259 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgSetup.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 22 September 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Default values for front end config and CPLD constants. +-- +-- Contains the revision constants that must be bumped when the CPLD is updated. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgMgCpld.all; + +package PkgSetup is + + + constant kRdWtWidth : integer := 1; + constant kAddrWidth : integer := 7; + constant kDataWidth : integer := 16; + constant kTotalWidth : integer := kRdWtWidth + kAddrWidth + kDataWidth; + + subtype InterfaceData_t is std_logic_vector(kDataWidth-1 downto 0); + + constant kSignature : InterfaceData_t := x"CAFE"; + + + -- UPDATE THESE REVISIONS when making changes to the CPLD ----------------------------- + -- ------------------------------------------------------------------------------------ + constant kMinorRev : InterfaceData_t := std_logic_vector(to_unsigned(0,kDataWidth)); + constant kMajorRev : InterfaceData_t := std_logic_vector(to_unsigned(5,kDataWidth)); + -- Currently just the timestamp of the build time/date: yymmddhh + constant kBuildCode : std_logic_vector(31 downto 0) := X"18010408"; + + + function kTxChDefault return InterfaceData_t; + function kTxChDefaultRun return InterfaceData_t; + function kRxChDefault0 return InterfaceData_t; + function kRxChDefault1 return InterfaceData_t; + function kRxChDefault0Run return InterfaceData_t; + function kRxChDefault1Run return InterfaceData_t; + + function Tx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Tx2TrxMod (kCh1Val : std_logic_vector) return std_logic_vector; + + function Rx2Switch1Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch3Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch4Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch5Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch6Mod(kCh1Val : std_logic_vector) return std_logic_vector; + + +end package; + +package body PkgSetup is + + function kTxChDefault return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1SwTrxMsb downto kCh1SwTrx) := std_logic_vector(to_unsigned(kFromLowerFilterBankTxSw1, kCh1SwTrxSize)); + RetVal(kCh1TxSw1Msb downto kCh1TxSw1) := std_logic_vector(to_unsigned(kShutdownTxSw1, kCh1TxSw1Size)); + RetVal(kCh1TxSw2Msb downto kCh1TxSw2) := std_logic_vector(to_unsigned(kToTxFilterLp3400MHz, kCh1TxSw2Size)); + RetVal(kCh1TxSw3 downto kCh1TxSw3) := std_logic_vector(to_unsigned(kToTxFilterBanks, kCh1TxSw3Size)); + RetVal(kCh1TxLowbandMixerPathSelect) := '0'; + RetVal(kCh1TxMixerEn) := '0'; + RetVal(kCh1TxAmpEn) := '0'; + RetVal(kCh1TxPaEn) := '0'; + RetVal(kCh1TxLed) := '0'; + RetVal(kCh1MykEnTx) := '1'; + return RetVal; + end kTxChDefault; + + function kTxChDefaultRun return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1SwTrxMsb downto kCh1SwTrx) := std_logic_vector(to_unsigned(kFromLowerFilterBankTxSw1, kCh1SwTrxSize)); + RetVal(kCh1TxSw1Msb downto kCh1TxSw1) := std_logic_vector(to_unsigned(kFromTxFilterLp3400MHz, kCh1TxSw1Size)); + RetVal(kCh1TxSw2Msb downto kCh1TxSw2) := std_logic_vector(to_unsigned(kToTxFilterLp3400MHz, kCh1TxSw2Size)); + RetVal(kCh1TxSw3 downto kCh1TxSw3) := std_logic_vector(to_unsigned(kToTxFilterBanks, kCh1TxSw3Size)); + RetVal(kCh1TxLowbandMixerPathSelect) := '0'; + RetVal(kCh1TxMixerEn) := '0'; + RetVal(kCh1TxAmpEn) := '1'; + RetVal(kCh1TxPaEn) := '1'; + RetVal(kCh1TxLed) := '1'; + RetVal(kCh1MykEnTx) := '1'; + return RetVal; + end kTxChDefaultRun; + + + + + function kRxChDefault0 return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1RxSw1Msb downto kCh1RxSw1) := std_logic_vector(to_unsigned(kRx2Input, kCh1RxSw1Size)); + RetVal(kCh1RxSw2Msb downto kCh1RxSw2) := std_logic_vector(to_unsigned(kShutdownSw2, kCh1RxSw2Size)); + RetVal(kCh1RxSw3Msb downto kCh1RxSw3) := std_logic_vector(to_unsigned(kShutdownSw3, kCh1RxSw3Size)); + RetVal(kCh1RxSw4Msb downto kCh1RxSw4) := std_logic_vector(to_unsigned(kFilter2100x2850MHzFrom, kCh1RxSw4Size)); + RetVal(kCh1RxSw5Msb downto kCh1RxSw5) := std_logic_vector(to_unsigned(kFilter0490LpMHzFrom, kCh1RxSw5Size)); + return RetVal; + end kRxChDefault0; + + function kRxChDefault1 return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1RxSw6Msb downto kCh1RxSw6) := std_logic_vector(to_unsigned(kUpperFilterBankFromSwitch4, kCh1RxSw6Size)); + RetVal(kCh1RxLowbandMixerPathSelect) := '0'; + RetVal(kCh1RxMixerEn) := '0'; + RetVal(kCh1RxAmpEn) := '0'; + RetVal(kCh1RxLna1En) := '0'; + RetVal(kCh1RxLna2En) := '0'; + RetVal(kCh1Rx2Led) := '0'; + RetVal(kCh1RxLed) := '0'; + RetVal(kCh1MykEnRx) := '1'; + return RetVal; + end kRxChDefault1; + + function kRxChDefault0Run return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1RxSw1Msb downto kCh1RxSw1) := std_logic_vector(to_unsigned(kRx2Input, kCh1RxSw1Size)); + RetVal(kCh1RxSw2Msb downto kCh1RxSw2) := std_logic_vector(to_unsigned(kLowerFilterBankToSwitch3, kCh1RxSw2Size)); + RetVal(kCh1RxSw3Msb downto kCh1RxSw3) := std_logic_vector(to_unsigned(kFilter2100x2850MHz, kCh1RxSw3Size)); + RetVal(kCh1RxSw4Msb downto kCh1RxSw4) := std_logic_vector(to_unsigned(kFilter2100x2850MHzFrom, kCh1RxSw4Size)); + RetVal(kCh1RxSw5Msb downto kCh1RxSw5) := std_logic_vector(to_unsigned(kFilter0490LpMHzFrom, kCh1RxSw5Size)); + return RetVal; + end kRxChDefault0Run; + + function kRxChDefault1Run return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1RxSw6Msb downto kCh1RxSw6) := std_logic_vector(to_unsigned(kUpperFilterBankFromSwitch4, kCh1RxSw6Size)); + RetVal(kCh1RxLowbandMixerPathSelect) := '0'; + RetVal(kCh1RxMixerEn) := '0'; + RetVal(kCh1RxAmpEn) := '1'; + RetVal(kCh1RxLna1En) := '1'; + RetVal(kCh1RxLna2En) := '1'; + RetVal(kCh1Rx2Led) := '1'; -- turn on a LED for grins + RetVal(kCh1RxLed) := '0'; + RetVal(kCh1MykEnRx) := '1'; + return RetVal; + end kRxChDefault1Run; + + + + + + + function Tx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is one-hot, so we just flip around the bits here. + RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 0); + RetVal(kCh1Val'low + 3) := kCh1Val(kCh1Val'low + 1); + RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 2); + RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 3); + return RetVal; + end Tx2Switch2Mod; + + function Tx2TrxMod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + if kCh1Val = "00" then RetVal := "00"; + elsif kCh1Val = "01" then RetVal := "10"; + elsif kCh1Val = "10" then RetVal := "01"; + elsif kCh1Val = "11" then RetVal := "11"; + else RetVal := "00"; end if; + return RetVal; + end Tx2TrxMod; + + + + function Rx2Switch1Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is binary, so we need to mux. + if kCh1Val = "00" then RetVal := "01"; + elsif kCh1Val = "01" then RetVal := "00"; + elsif kCh1Val = "10" then RetVal := "11"; + elsif kCh1Val = "11" then RetVal := "10"; + else RetVal := "00"; end if; + return RetVal; + end Rx2Switch1Mod; + + function Rx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is binary, so we need to mux. + if kCh1Val = "00" then RetVal := "00"; + elsif kCh1Val = "01" then RetVal := "11"; + elsif kCh1Val = "10" then RetVal := "10"; + elsif kCh1Val = "11" then RetVal := "01"; + else RetVal := "00"; end if; + return RetVal; + end Rx2Switch2Mod; + + function Rx2Switch3Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is binary, so we need to mux. + if kCh1Val = "000" then RetVal := "100"; + elsif kCh1Val = "001" then RetVal := "101"; + elsif kCh1Val = "010" then RetVal := "110"; + elsif kCh1Val = "011" then RetVal := "011"; + elsif kCh1Val = "100" then RetVal := "001"; + elsif kCh1Val = "101" then RetVal := "000"; + elsif kCh1Val = "110" then RetVal := "010"; + elsif kCh1Val = "111" then RetVal := "111"; + else RetVal := "000"; end if; + return RetVal; + end Rx2Switch3Mod; + + function Rx2Switch4Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is one-hot, so we just flip around the bits here. + RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 0); + RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 1); + RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 2); + return RetVal; + end Rx2Switch4Mod; + + function Rx2Switch5Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is one-hot, so we just flip around the bits here. + RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 0); + RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 1); + RetVal(kCh1Val'low + 3) := kCh1Val(kCh1Val'low + 2); + RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 3); + return RetVal; + end Rx2Switch5Mod; + + function Rx2Switch6Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is one-hot, so we just flip around the bits here. + RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 0); + RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 1); + RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 2); + return RetVal; + end Rx2Switch6Mod; + + +end package body; \ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/Timing.sdc b/fpga/usrp3/top/n3xx/dboards/mg/cpld/Timing.sdc new file mode 100644 index 000000000..496814662 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/Timing.sdc @@ -0,0 +1,160 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + +# All the magic numbers come from the "/n3xx/dboards/mg/doc/mg_timing.xlsx" timing +# analysis spreadsheet. Analysis should be re-performed every time a board rev occurs +# that affects the CPLD interfaces. + +## PS Slave Constraints ################################################################# +# - PsClk Rate +# - PsClk to SDI +# - PsClk to LE (sync and async paths) +# - PsClk to SDO + +# Maximum 4 MHz clock rate! This is heavily limited by the read data turnaround time... +# and could be up to 20 MHz if only performing writes. +create_clock -name PsClk -period 250 [get_ports {PsSpiSck}] + +# SDI is both registered in the CPLD and used as a direct passthrough. First constrain +# the input delay on the local paths inside the CPLD. Passthrough constraints +# are handled elsewhere. + +set PsSdiInputDelayMax 22.303 +set PsSdiInputDelayMin -19.019 + +# SDI is driven from the PS on the falling edge of the Clk. Worst-case data-clock skew +# is around +/-20ns due to FPGA routing delays and board buffering. Complete timing +# analysis is performed and recorded elsewhere. +set_input_delay -clock PsClk -max $PsSdiInputDelayMax [get_ports sPsSpiSdi] -clock_fall +set_input_delay -clock PsClk -min $PsSdiInputDelayMin [get_ports sPsSpiSdi] -clock_fall + +# For the CPLD Cs_n, the latch enable is used both as an asynchronous reset and +# synchronously to latch data. First, constrain the overall input delay for sync use. +# Technically, Cs_n is asserted and de-asserted many nanoseconds before the clock arrives +# but we still constrain it identically to the SDI in case something goes amiss. +set_input_delay -clock PsClk -max $PsSdiInputDelayMax [get_ports sPsSpiLe] -clock_fall +set_input_delay -clock PsClk -min $PsSdiInputDelayMin [get_ports sPsSpiLe] -clock_fall +# Then set a false path only on the async reset flops. +set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMosiIndex[*]|*] +set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMisoIndex[*]|*] + +# Constrain MISO as snugly as possible through the CPLD without making the tools work +# too hard. At a 200 ns period, this sets the clock-to-out for the CPLD at [10, 65]ns. +# Math for Max = T_clk/2 - 60 = 250/2 - 60 = 65 ns. +set PsSdoOutputDelayMax 60 +set PsSdoOutputDelayMin -10 + +set_output_delay -clock PsClk -max $PsSdoOutputDelayMax [get_ports sPsSpiSdo] +set_output_delay -clock PsClk -min $PsSdoOutputDelayMin [get_ports sPsSpiSdo] + + + +## PL Slave Constraints ################################################################# +# - PlClk Rate +# - PlClk to SDI +# - PlClk to LE (sync and async paths) +# - PlClk to SDO + +# Maximum 5 MHz clock rate! +create_clock -name PlClk -period 200 [get_ports {PlSpiSck}] + +# SDI is both registered in the CPLD and used as a direct passthrough. First constrain +# the input delay on the local paths inside the CPLD. Passthrough constraints +# are handled elsewhere. + +set PlSdiInputDelayMax 10.445 +set PlSdiInputDelayMin -10.378 + +# SDI is driven from the FPGA on the falling edge of the Clk. Worst-case data-clock skew +# is around +/-10ns. Complete timing analysis is performed and recorded elsewhere. +set_input_delay -clock PlClk -max $PlSdiInputDelayMax [get_ports lPlSpiSdi] -clock_fall +set_input_delay -clock PlClk -min $PlSdiInputDelayMin [get_ports lPlSpiSdi] -clock_fall + +# For the CPLD Cs_n, the latch enable is used both as an asynchronous reset and +# synchronously to latch data. First, constrain the overall input delay for sync use. +# Technically, Cs_n is asserted and de-asserted many nanoseconds before the clock arrives +# but we still constrain it identically to the SDI in case something goes amiss. +set_input_delay -clock PlClk -max $PlSdiInputDelayMax [get_ports lPlSpiLe] -clock_fall +set_input_delay -clock PlClk -min $PlSdiInputDelayMin [get_ports lPlSpiLe] -clock_fall +# Then set a false path only on the async reset flops. +set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMosiIndex[*]|*}] +set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMisoIndex[*]|*}] + +# Constrain MISO as snugly as possible through the CPLD without making the tools work +# too hard. At a 200 ns period, this sets the clock-to-out for the CPLD at [10, 65]ns. +# Math for Max = T_clk/2 - 35 = 200/2 - 35 = 65 ns. +set PlSdoOutputDelayMax 35 +set PlSdoOutputDelayMin -10 + +set_output_delay -clock PlClk -max $PlSdoOutputDelayMax [get_ports lPlSpiSdo] +set_output_delay -clock PlClk -min $PlSdoOutputDelayMin [get_ports lPlSpiSdo] + + + +## Passthrough Constraints ############################################################## +# - LMK SYNC +# - PlClk/PsClk passthrough +# - SDI passthrough for both +# - SDO return mux passthrough for both +# - Cs_n passthrough for both + +# LMK Sync Passthrough: constrain min and max delays for output +set_max_delay -from [get_ports {aPlSpiAddr[2]}] -to [get_ports {aLmkSync}] 17 +set_min_delay -from [get_ports {aPlSpiAddr[2]}] -to [get_ports {aLmkSync}] 2 + +# SPI Passthroughs: constrain min and max delays for outputs and inputs. +# Since the SDI ports have input delays pre-defined above, we have to remove those from +# the delay analysis here by adding the input delay to the constraint. +# Similarly, for the SDO pins add the output delay to the constraint. +set SpiMaxDelay 25 +set SpiMinDelay 5 + +# PS +set_max_delay -to [get_ports {aDacDin aLmkSpiSdio}] [expr $PsSdiInputDelayMax + $SpiMaxDelay] +set_min_delay -to [get_ports {aDacDin aLmkSpiSdio}] [expr $PsSdiInputDelayMin + $SpiMinDelay] +set_max_delay -to [get_ports {aDacSync_n aLmkSpiCs_n}] $SpiMaxDelay +set_min_delay -to [get_ports {aDacSync_n aLmkSpiCs_n}] $SpiMinDelay +set_max_delay -to [get_ports {aDacSck aLmkSpiSck}] $SpiMaxDelay +set_min_delay -to [get_ports {aDacSck aLmkSpiSck}] $SpiMinDelay +set_max_delay -from [get_ports {aLmkClkinSel*}] [expr $SpiMaxDelay + $PsSdoOutputDelayMax] +set_min_delay -from [get_ports {aLmkClkinSel*}] [expr $SpiMinDelay + $PsSdoOutputDelayMin] + +# PL +set_max_delay -to [get_ports {aRxLoDin aTxLoDin}] [expr $PlSdiInputDelayMax + $SpiMaxDelay] +set_min_delay -to [get_ports {aRxLoDin aTxLoDin}] [expr $PlSdiInputDelayMin + $SpiMinDelay] +set_max_delay -to [get_ports {aRxLoCs_n aTxLoCs_n}] $SpiMaxDelay +set_min_delay -to [get_ports {aRxLoCs_n aTxLoCs_n}] $SpiMinDelay +set_max_delay -to [get_ports {aRxLoSck aTxLoSck}] $SpiMaxDelay +set_min_delay -to [get_ports {aRxLoSck aTxLoSck}] $SpiMinDelay +set_max_delay -from [get_ports {aTxLoMuxOut aRxLoMuxOut}] [expr $SpiMaxDelay + $PlSdoOutputDelayMax] +set_min_delay -from [get_ports {aTxLoMuxOut aRxLoMuxOut}] [expr $SpiMinDelay + $PlSdoOutputDelayMin] + + + +## Async Inputs ######################################################################### +# aLmkStatus2 aRxLoLockDetect aTxLoLockDetect +set_false_path -from [get_ports {aRxLoLockDetect}] +set_false_path -from [get_ports {aTxLoLockDetect}] + + + +## Async Outputs ######################################################################## +# aMkReset_n aVcxoCtrl +set_false_path -to [get_ports {aMkReset_n}] +set_false_path -to [get_ports {aVcxoCtrl}] + + + +## Sync Front End Outputs ############################################################### +# All we need to do here is constrain for maximum path delay from the aAtr(Rx|Tx)(1|2) +# control bits toggling to the outputs for aCh1* and aCh2* toggling. Just in case the +# user attempts to write the ATR while it's in use, we also constrain from the flops +# to the pins... which covers all paths... so just to -to option is needed. +set_max_delay -to [get_ports {aCh1* aCh2* aMk*x*En}] 40 +set_min_delay -to [get_ports {aCh1* aCh2* aMk*x*En}] 5 + +# We don't care about the LED timing whatsoever. Let's not have them clogging up our +# precious timing paths. +set_false_path -to [get_ports {aCh*Led*}] diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qpf b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qpf new file mode 100644 index 000000000..e16aaf0af --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 14:51:27 February 24, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "14:51:27 February 24, 2017" + +# Revisions + +PROJECT_REVISION = "TopCpld" diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qsf b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qsf new file mode 100644 index 000000000..64238c87a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qsf @@ -0,0 +1,313 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 14:51:27 February 24, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# TopCpld_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX V" +set_global_assignment -name DEVICE 5M570ZF256I5 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:51:27 FEBRUARY 24, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name SDC_FILE Timing.sdc +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name GENERATE_SVF_FILE ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" + +set_location_assignment PIN_C3 -to aCh2RxSw4[0] +set_location_assignment PIN_C2 -to aCh2TxPaEn +set_location_assignment PIN_D3 -to aCh2RxSw6[0] +set_location_assignment PIN_D1 -to aCh2RxSw4[1] +set_location_assignment PIN_D2 -to aCh2TxSw3 +set_location_assignment PIN_E1 -to aCh2RxSw4[2] +set_location_assignment PIN_E4 -to aCh2RxSw7[1] +set_location_assignment PIN_F2 -to aCh2RxSw6[1] +set_location_assignment PIN_E3 -to aCh2RxSw7[0] +set_location_assignment PIN_F1 -to aCh2RxSw5[0] +set_location_assignment PIN_E2 -to aCh2RxSw5[1] +set_location_assignment PIN_G2 -to aCh2RxSw5[3] +set_location_assignment PIN_F3 -to aCh2TxSw4[0] +set_location_assignment PIN_G1 -to aCh2RxSw6[2] +set_location_assignment PIN_G3 -to aCh2TxSw4[1] +set_location_assignment PIN_H2 -to aCh2TxAmpEn +set_location_assignment PIN_H1 -to aCh2RxSw5[2] +set_location_assignment PIN_J1 -to aCh2TxMixerEn +set_location_assignment PIN_H5 -to aLoSpiSync +set_location_assignment PIN_J2 -to aCh2RxMixerEn +#set_location_assignment PIN_L3 -to aLmkSpiSdio +set_location_assignment PIN_K1 -to aCh2TxSw5[1] +set_location_assignment PIN_K2 -to aCh2TxSw5[0] +set_location_assignment PIN_M2 -to aLmkSpiSdio +set_location_assignment PIN_L1 -to aCh2RxSw8[0] +set_location_assignment PIN_M3 -to lPlSpiSdi +set_location_assignment PIN_L2 -to aCh2RxSw8[1] +set_location_assignment PIN_M1 -to aCh2RxAmpEn +set_location_assignment PIN_N2 -to aLmkSpiSck +set_location_assignment PIN_N1 -to aLmkSpiCs_n +set_location_assignment PIN_N3 -to PlSpiSck +# set_location_assignment PIN_P2 -to lPlSpiLe +set_location_assignment PIN_R3 -to aMkReset_n +set_location_assignment PIN_R1 -to lPlSpiLe +set_location_assignment PIN_T2 -to aLmkSync +set_location_assignment PIN_R4 -to aVcxoCtrl +set_location_assignment PIN_T4 -to aDacDin +set_location_assignment PIN_T5 -to aDacSync_n +set_location_assignment PIN_R6 -to aPlSpiAddr[2] +set_location_assignment PIN_R5 -to aDacSck +set_location_assignment PIN_T6 -to aPlSpiAddr[1] +set_location_assignment PIN_R7 -to aLmkClkinSel[0] +set_location_assignment PIN_T7 -to lPlSpiSdo +set_location_assignment PIN_P8 -to sPsSpiLe +set_location_assignment PIN_R8 -to aPsSpiAddr[1] +set_location_assignment PIN_P9 -to aPlSpiAddr[0] +set_location_assignment PIN_T8 -to PsSpiSck +set_location_assignment PIN_T9 -to aPsSpiAddr[0] +set_location_assignment PIN_R9 -to sPsSpiSdi +set_location_assignment PIN_P10 -to aAtrRx1 +set_location_assignment PIN_T10 -to sPsSpiSdo +set_location_assignment PIN_P11 -to aAtrTx2 +set_location_assignment PIN_R10 -to aRxLoLockDetect +set_location_assignment PIN_R12 -to aRxLoSck +set_location_assignment PIN_T11 -to aTxLoLockDetect +set_location_assignment PIN_P12 -to aAtrRx2 +set_location_assignment PIN_R11 -to aRxLoDin +set_location_assignment PIN_T12 -to aRxLoCs_n +set_location_assignment PIN_R13 -to aTxLoDin +set_location_assignment PIN_T13 -to aRxLoMuxOut +set_location_assignment PIN_P13 -to aAtrTx1 +set_location_assignment PIN_T15 -to aTxLoSck +set_location_assignment PIN_R14 -to aTxLoCs_n +set_location_assignment PIN_R16 -to aTxLoMuxOut +set_location_assignment PIN_P14 -to aMkTx1En +set_location_assignment PIN_N15 -to aMkRx2En +set_location_assignment PIN_P15 -to aMkRx1En +set_location_assignment PIN_N16 -to aMkTx2En +set_location_assignment PIN_K15 -to aCh1TxSw5[1] +set_location_assignment PIN_L14 -to aCh1RxMixerEn +set_location_assignment PIN_K16 -to aCh1TxMixerEn +set_location_assignment PIN_K14 -to aCh1RxSw8[0] +set_location_assignment PIN_J15 -to aCh1TxAmpEn +set_location_assignment PIN_J14 -to aCh1RxSw8[1] +set_location_assignment PIN_J16 -to aCh1TxSw5[0] +set_location_assignment PIN_H14 -to aCh1RxAmpEn +set_location_assignment PIN_H16 -to aCh1TxSw4[0] +set_location_assignment PIN_G14 -to aCh1TxSw4[1] +set_location_assignment PIN_H15 -to aCh1RxSw5[1] +set_location_assignment PIN_F14 -to aCh1RxSw7[1] +set_location_assignment PIN_G16 -to aCh1RxSw5[0] +set_location_assignment PIN_G15 -to aCh1RxSw4[0] +set_location_assignment PIN_E14 -to aCh1RxSw6[1] +set_location_assignment PIN_F16 -to aCh1RxSw2[1] +set_location_assignment PIN_E13 -to aCh1RxSw7[0] +set_location_assignment PIN_F15 -to aCh1RxSw2[0] +set_location_assignment PIN_D14 -to aCh1RxSw6[2] +set_location_assignment PIN_E16 -to aCh1RxSw6[0] +set_location_assignment PIN_E15 -to aCh1TxSw3 +set_location_assignment PIN_C15 -to aCh1RxSw5[2] +set_location_assignment PIN_D16 -to aCh1TxPaEn +set_location_assignment PIN_C14 -to aCh1RxSw4[1] +set_location_assignment PIN_D15 -to aCh1RxSw5[3] +set_location_assignment PIN_B14 -to aCh1TxSw2[3] +set_location_assignment PIN_B16 -to aCh1RxLna2En +set_location_assignment PIN_C13 -to aCh1RxSw4[2] +set_location_assignment PIN_A15 -to aCh1TxSw2[2] +set_location_assignment PIN_B13 -to aCh1TxSw2[1] +set_location_assignment PIN_A13 -to aCh1TxSw2[0] +set_location_assignment PIN_C12 -to aCh1RxSw1[0] +set_location_assignment PIN_B12 -to aCh1TxSw1[0] +set_location_assignment PIN_D12 -to aCh1RxSw1[1] +set_location_assignment PIN_A12 -to aCh1TxSw1[1] +set_location_assignment PIN_C11 -to aCh1LedTx +set_location_assignment PIN_B11 -to aCh1RxLna1En +set_location_assignment PIN_D11 -to aCh2RxSw1[1] +set_location_assignment PIN_A11 -to aCh1RxSw3[2] +set_location_assignment PIN_C10 -to aCh1LedRx +set_location_assignment PIN_B10 -to aCh1RxSw3[1] +set_location_assignment PIN_C9 -to aCh1LedRx2 +set_location_assignment PIN_A10 -to aCh1RxSw3[0] +set_location_assignment PIN_C8 -to aCh2LedRx2 +set_location_assignment PIN_B9 -to aCh1SwTrx[1] +set_location_assignment PIN_A9 -to aCh1SwTrx[0] +set_location_assignment PIN_A8 -to aCh2SwTrx[0] +set_location_assignment PIN_C7 -to aCh2RxSw3[0] +set_location_assignment PIN_B8 -to aCh2SwTrx[1] +set_location_assignment PIN_C6 -to aCh2LedRx +set_location_assignment PIN_A7 -to aCh2RxSw3[1] +set_location_assignment PIN_B5 -to aCh2TxSw1[0] +set_location_assignment PIN_C5 -to aCh2RxSw1[0] +set_location_assignment PIN_A6 -to aCh2TxSw1[1] +set_location_assignment PIN_D5 -to aCh2LedTx +set_location_assignment PIN_B6 -to aCh2RxSw3[2] +set_location_assignment PIN_B4 -to aCh2RxLna2En +set_location_assignment PIN_A5 -to aCh2RxLna1En +set_location_assignment PIN_C4 -to aCh2RxSw2[0] +set_location_assignment PIN_A4 -to aCh2TxSw2[1] +set_location_assignment PIN_D4 -to aCh2RxSw2[1] +set_location_assignment PIN_A2 -to aCh2TxSw2[3] +set_location_assignment PIN_B3 -to aCh2TxSw2[0] +set_location_assignment PIN_B1 -to aCh2TxSw2[2] + +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name GENERATE_JAM_FILE ON +set_global_assignment -name GENERATE_JBC_FILE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxPaEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw7[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw7[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw4[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw4[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxAmpEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxMixerEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxMixerEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw5[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw5[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiSdio +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw8[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw8[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxAmpEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiSck +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiCs_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkReset_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSync +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aVcxoCtrl +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacDin +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacSync_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacSck +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to lPlSpiSdo +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to sPsSpiSdo +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoSck +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoDin +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoCs_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoDin +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoSck +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoCs_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkTx1En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkRx2En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkRx1En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkTx2En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxMixerEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw5[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxMixerEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw8[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxAmpEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw8[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw5[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxAmpEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw4[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw4[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw7[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw2[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw7[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw2[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxPaEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxLna2En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw1[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw1[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw1[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw1[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedTx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxLna1En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw1[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedRx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedRx2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedRx2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1SwTrx[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1SwTrx[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2SwTrx[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2SwTrx[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedRx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw1[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw1[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw1[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedTx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxLna2En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxLna1En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw2[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw2[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[2] +set_global_assignment -name SEED 11 +set_global_assignment -name VHDL_FILE PkgMgCpld.vhd +set_global_assignment -name VHDL_FILE PkgSetup.vhd +set_global_assignment -name VHDL_FILE TopCpld.vhd +set_global_assignment -name TOP_LEVEL_ENTITY TopCpld diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.vhd b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.vhd new file mode 100644 index 000000000..4e3488f54 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.vhd @@ -0,0 +1,1228 @@ +------------------------------------------------------------------------------- +-- +-- File: TopCpld.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 24 October 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Top level file for the Magnesium CPLD. +-- +-- This file instantiates two SPI slave ports. One slave port comes from the PS +-- of the motherboard Zynq. It has three slave select pins, mapped as follows: +-- sPlsSpiLe = CPLD Internal Registers +-- aPsSpiAddr(0) = LMK Endpoint +-- aPsSpiAddr(1) = Phase DAC Endpoint +-- +-- The other slave port comes from the PL of the motherboard Zynq. It also has +-- three slave select pins: +-- lPlSpiLe = CPLD Internal Registers +-- aPlSpiAddr(0) = TX Lowband LO +-- aPlSpiAddr(1) = RX Lowband LO +-- +-- The final address line for the PL slave is used as a passthrough for the LMK +-- SYNC pin. +-- +-- +-- For either SPI interface, the CPLD has internal registers that can be addressed +-- whenever the appropriate slave select is driven asserted. These register groups +-- are completely independent from one another, meaning the PS SPI interface cannot +-- access the PL registers, and vice-versa. +-- +-- See the register interface XML at the bottom of this file for details on how +-- each SPI port is expected to be driven, and for the register maps for the PS +-- and PL slaves. +-- +-- +-- BUMPING THE REVISION: +-- In PkgSetup the kMinorRev and kMajorRev are defined. Whenever a change +-- is made to the CPLD, no matter how small, bump the kMinorRev value. If this change +-- breaks compatibility with current HW or SW drivers, increment the kMajorRev value +-- and reset the kMinorRev to zero. Similarly, there is a constant to define the build +-- code, kBuildCode. Currently this is simply the year, month, day, and hour the CPLD is +-- built, but could be user-definable. +-- +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +library work; + use work.PkgMgCpld.all; + use work.PkgSetup.all; + +entity TopCpld is + port( + + -- SPI Port Incoming from FPGA -- + PlSpiSck : in std_logic; + lPlSpiSdi : in std_logic; + lPlSpiSdo : out std_logic; + lPlSpiLe : in std_logic; + aPlSpiAddr : in std_logic_vector(2 downto 0); + + -- SPI Port Incoming from PS -- + PsSpiSck : in std_logic; + sPsSpiSdi : in std_logic; + sPsSpiSdo : out std_logic; + sPsSpiLe : in std_logic; + aPsSpiAddr : in std_logic_vector(1 downto 0); + + -- ATR bits from FPGA -- + aAtrRx1 : in std_logic; + aAtrRx2 : in std_logic; + aAtrTx1 : in std_logic; + aAtrTx2 : in std_logic; + + -- Ch 1 TX (15 bits) -- + aCh1LedTx : out std_logic; + + aCh1TxPaEn : out std_logic; + aCh1TxAmpEn : out std_logic; + aCh1TxMixerEn : out std_logic; + + aCh1TxSw1 : out std_logic_vector(1 downto 0); + aCh1TxSw2 : out std_logic_vector(3 downto 0); + aCh1TxSw3 : out std_logic; + aCh1TxSw4 : out std_logic_vector(1 downto 0); + aCh1TxSw5 : out std_logic_vector(1 downto 0); + + -- Ch 1 RX (29 bits) -- + aCh1LedRx : out std_logic; + aCh1LedRx2 : out std_logic; + + aCh1RxAmpEn : out std_logic; + aCh1RxMixerEn : out std_logic; + aCh1RxLna1En : out std_logic; + aCh1RxLna2En : out std_logic; + aCh1SwTrx : out std_logic_vector(1 downto 0); + + aCh1RxSw1 : out std_logic_vector(1 downto 0); + aCh1RxSw2 : out std_logic_vector(1 downto 0); + aCh1RxSw3 : out std_logic_vector(2 downto 0); + aCh1RxSw4 : out std_logic_vector(2 downto 0); + aCh1RxSw5 : out std_logic_vector(3 downto 0); + aCh1RxSw6 : out std_logic_vector(2 downto 0); + aCh1RxSw7 : out std_logic_vector(1 downto 0); + aCh1RxSw8 : out std_logic_vector(1 downto 0); + + -- Ch 2 TX -- + aCh2LedTx : out std_logic; + + aCh2TxPaEn : out std_logic; + aCh2TxAmpEn : out std_logic; + aCh2TxMixerEn : out std_logic; + + aCh2TxSw1 : out std_logic_vector(1 downto 0); + aCh2TxSw2 : out std_logic_vector(3 downto 0); + aCh2TxSw3 : out std_logic; + aCh2TxSw4 : out std_logic_vector(1 downto 0); + aCh2TxSw5 : out std_logic_vector(1 downto 0); + + -- Ch 2 RX -- + aCh2LedRx : out std_logic; + aCh2LedRx2 : out std_logic; + + aCh2RxAmpEn : out std_logic; + aCh2RxMixerEn : out std_logic; + aCh2RxLna1En : out std_logic; + aCh2RxLna2En : out std_logic; + aCh2SwTrx : out std_logic_vector(1 downto 0); + + aCh2RxSw1 : out std_logic_vector(1 downto 0); + aCh2RxSw2 : out std_logic_vector(1 downto 0); + aCh2RxSw3 : out std_logic_vector(2 downto 0); + aCh2RxSw4 : out std_logic_vector(2 downto 0); + aCh2RxSw5 : out std_logic_vector(3 downto 0); + aCh2RxSw6 : out std_logic_vector(2 downto 0); + aCh2RxSw7 : out std_logic_vector(1 downto 0); + aCh2RxSw8 : out std_logic_vector(1 downto 0); + + -- LMK -- + aLmkSpiSdio : out std_logic; + aLmkSpiSck : out std_logic; + aLmkSpiCs_n : out std_logic; + aLmkClkinSel : in std_logic_vector(0 downto 0); -- SDO + aLmkSync : out std_logic; -- direct connect to aPlSpiAddr(2) + + -- Phase DAC -- + aDacDin : out std_logic; + aDacSync_n : out std_logic; + aDacSck : out std_logic; + aVcxoCtrl : out std_logic; -- @PS-REG-WR + + -- RX and TX LOs -- (timed) + aLoSpiSync : in std_logic; -- Clock! (unused atm, only for reclocking + aRxLoSck : out std_logic; -- the SPI bus if needed for sync) + aRxLoDin : out std_logic; + aRxLoCs_n : out std_logic; + aRxLoMuxOut : in std_logic; + aRxLoLockDetect : in std_logic; -- @PS-REG-RD + aTxLoSck : out std_logic; + aTxLoDin : out std_logic; + aTxLoCs_n : out std_logic; + aTxLoMuxOut : in std_logic; + aTxLoLockDetect : in std_logic; -- @PS-REG-RD + + -- Mykonos Interface -- + aMkReset_n : out std_logic; -- @PS-REG-WR + aMkRx1En : out std_logic; + aMkRx2En : out std_logic; + aMkTx1En : out std_logic; + aMkTx2En : out std_logic + + ); +end TopCpld; + + +architecture RTL of TopCpld is + + -- PS MOSI + signal sCpldPsSpiActive : boolean; + signal sPsMosiIndex : unsigned(integer(ceil(log2(real(kTotalWidth)))) downto 0); + signal sPsMosiBuffer : InterfaceData_t := (others => '0'); + signal sPsRd : boolean := false; + signal sPsRegAddr : unsigned(kAddrWidth-1 downto 0) := (others => '0'); + + -- PS MISO + signal sPsCpldMiso : std_logic; + signal sPsMisoIndex : unsigned(integer(ceil(log2(real(kTotalWidth)))) downto 0); + signal sPsMisoBuffer : std_logic_vector(kTotalWidth-1 downto 0); + + -- PS Register Signals + signal aRxLoLockDetect_ms, sRxLoLockDetect, + aTxLoLockDetect_ms, sTxLoLockDetect : std_logic := '0'; + signal sReset : boolean := false; + signal sScratchVal : InterfaceData_t := (others => '0'); + signal sVcxoControl : std_logic := '1'; + signal sMykonosReset : std_logic := '0'; + + -- PL MOSI + signal lCpldPlSpiActive : boolean; + signal lPlMosiIndex : unsigned(integer(ceil(log2(real(kTotalWidth)))) downto 0); + signal lPlMosiBuffer : InterfaceData_t := (others => '0'); + signal lPlRd : boolean := false; + signal lPlRegAddr : unsigned(kAddrWidth-1 downto 0) := (others => '0'); + + -- PL MISO + signal lPlCpldMiso : std_logic; + signal lPlMisoIndex : unsigned(integer(ceil(log2(real(kTotalWidth)))) downto 0); + signal lPlMisoBuffer : std_logic_vector(kTotalWidth-1 downto 0); + + -- PL Register Signals + signal lScratchVal : InterfaceData_t := (others => '0'); + signal lReset : boolean := false; + + -- See PkgSetup for each Default definition. + signal lTxCh1IdleReg : InterfaceData_t := kTxChDefault; + signal lTxCh2IdleReg : InterfaceData_t := kTxChDefault; + + signal lTxCh1TxOnReg : InterfaceData_t := kTxChDefaultRun; + signal lTxCh2TxOnReg : InterfaceData_t := kTxChDefaultRun; + + signal lRxCh1_0IdleReg : InterfaceData_t := kRxChDefault0; + signal lRxCh1_1IdleReg : InterfaceData_t := kRxChDefault1; + signal lRxCh2_0IdleReg : InterfaceData_t := kRxChDefault0; + signal lRxCh2_1IdleReg : InterfaceData_t := kRxChDefault1; + + signal lRxCh1_0RxOnReg : InterfaceData_t := kRxChDefault0Run; + signal lRxCh1_1RxOnReg : InterfaceData_t := kRxChDefault1Run; + signal lRxCh2_0RxOnReg : InterfaceData_t := kRxChDefault0Run; + signal lRxCh2_1RxOnReg : InterfaceData_t := kRxChDefault1Run; + + signal lTxCh1 : InterfaceData_t; + signal lTxCh2 : InterfaceData_t; + signal lRxCh1_0 : InterfaceData_t; + signal lRxCh1_1 : InterfaceData_t; + signal lRxCh2_0 : InterfaceData_t; + signal lRxCh2_1 : InterfaceData_t; + +begin + + + -- Direct Pass-through Pins : --------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + -- LMK SYNC assignment for direct passthrough to LMK from SPI Addr line. + aLmkSync <= aPlSpiAddr(2); + + + + -- PS SPI Interface : ----------------------------------------------------------------- + -- Composed of a few modules: + -- 1) PsMosiIndex - generate pointer for MOSI Buffer + -- 2) PsMosiBuffer - actually implement the buffer, only when the CPLD is targeted. + -- 3) PsMosiProcessing - process the MOSI data: sort into Rd/!Wt, Address, and Data. + -- This process works on the falling edge of the clock to register the pieces + -- of the MOSI packet as they are complete. The final falling edge registers + -- the data into the individual registers, so it is critical that the clock idle + -- LOW after the transaction is complete such that this final falling edge occurs. + -- 4) PsMisoBuffer - generate pointer for the MISO buffer. The buffer itself is + -- completely async. + -- 5) PsMisoBufferMux - Mux all the register data back into the MISO buffer. + -- 6) StatusSynchronizer - double-synchronizers for status bits from the LMK and LOs. + -- ------------------------------------------------------------------------------------ + + -- Decode the PS SPI Address bits... which are actually going to be used as individual + -- chip selects coming from the PS. + sCpldPsSpiActive <= sPsSpiLe = '0'; + aLmkSpiCs_n <= aPsSpiAddr(0); + aDacSync_n <= aPsSpiAddr(1); + + -- Assign the remainder of the SPI lines to the LMK and DAC. + aLmkSpiSck <= PsSpiSck; + aLmkSpiSdio <= sPsSpiSdi; + aDacSck <= PsSpiSck; + aDacDin <= sPsSpiSdi; + + -- Output mux for data back to the FPGA (PS core). The LMK and CPLD are the only + -- endpoints that have readback enabled. + sPsSpiSdo <= aLmkClkinSel(0) when aPsSpiAddr(0) = '0' else + sPsCpldMiso; + + + + -- Use the LE signal (Cs_n) as the asynchronous reset to the shift register counter. + -- LE will hold the counter in reset until this endpoint is targeted, when it will + -- release the reset (long before the clock toggles) and allow the shift operation + -- to begin. + -- + -- !!! SAFE COUNTER STARTUP!!! + -- This counter starts safely from reset because the PsSpiSck will not start toggling + -- until long after the asynchronous reset (sCpldPsSpiActive) de-asserts. Similarly, + -- the reset will only assert long after the last clock edge is received. + PsMosiIndex : process(PsSpiSck, sCpldPsSpiActive) + begin + if not sCpldPsSpiActive then + sPsMosiIndex <= (others => '0'); + elsif rising_edge(PsSpiSck) then + sPsMosiIndex <= sPsMosiIndex + 1; + end if; + end process PsMosiIndex; + + + -- Shift in SDI (MOSI) data from the PS on the rising edge of the clock. Only use + -- synchronous resets from here on out. + PsMosiBuffer : process(PsSpiSck) + begin + if rising_edge(PsSpiSck) then + if sReset then + sPsMosiBuffer <= (others => '0'); + else + if sCpldPsSpiActive then + sPsMosiBuffer <= sPsMosiBuffer(sPsMosiBuffer'high-1 downto 0) & sPsSpiSdi; -- left shift + end if; + end if; + end if; + end process PsMosiBuffer; + + + -- As portions of the command and data packets become available, register them here + -- using the falling edge of the PS SPI clock. + PsMosiProcessing : process(PsSpiSck) + begin + if falling_edge(PsSpiSck) then + if sReset then + -- sReset is intentionally self-clearing. It clears on the first falling edge of + -- the next SPI transaction after it is set. Logic on the first rising edge of + -- that next transaction is therefore held in reset. This will not matter + -- as long as SW follows the recommended reset procedure (writing a '1' to reset + -- then writing a '0'), since the first bit of the transaction is '0' for a + -- write operation. + sReset <= false; + sScratchVal <= (others => '0'); + sVcxoControl <= '1'; + sMykonosReset <= '0'; + sPsRd <= false; + sPsRegAddr <= (others => '0'); + else + -- After the first bit is captured, we can determine if it is a write or read. + if (sPsMosiIndex = (kRdWtWidth)) then + sPsRd <= sPsMosiBuffer(0) = '1'; + end if; + + -- After the entire command word is captured, the address is ready for capture. + if (sPsMosiIndex = (kAddrWidth + kRdWtWidth)) then + sPsRegAddr <= unsigned(sPsMosiBuffer(kAddrWidth - 1 downto 0)); + end if; + + -- And finally after the entire transaction is complete we can save off the data + -- on the final falling edge of the SPI clock into it's appropriate place, based + -- off the address value captured above. + if (sPsMosiIndex = kTotalWidth) and (not sPsRd) then + + -- ---------------------------------------------------------------------------- + -- Assign writable register values here! -------------------------------------- + -- ---------------------------------------------------------------------------- + if (sPsRegAddr = kScratch) then + sScratchVal <= sPsMosiBuffer; + end if; + + if (sPsRegAddr = kCpldControl) then + sReset <= sPsMosiBuffer(kCpldReset) = '1'; + end if; + + if (sPsRegAddr = kLmkControl) then + sVcxoControl <= sPsMosiBuffer(kVcxoControl); + end if; + + if (sPsRegAddr = kMykonosControl) then + sMykonosReset <= sPsMosiBuffer(kMykonosReset); + end if; + + end if; + end if; + end if; + end process PsMosiProcessing; + + + -- Send MISO back to FPGA (PS) on the falling edge as well. + -- + -- !!! SAFE COUNTER STARTUP!!! + -- This counter starts safely from reset because the PsSpiSck will not start toggling + -- until long after the asynchronous reset (sCpldPsSpiActive) de-asserts. Similarly, + -- the reset will only assert long after the last clock edge is received. + PsMisoBuffer : process(PsSpiSck, sCpldPsSpiActive) + begin + if not sCpldPsSpiActive then + sPsMisoIndex <= to_unsigned(kTotalWidth-1, sPsMisoIndex'length); + elsif falling_edge(PsSpiSck) then + if sPsMisoIndex > 0 then + sPsMisoIndex <= sPsMisoIndex - 1; + end if; + end if; + end process PsMisoBuffer; + + sPsCpldMiso <= sPsMisoBuffer(to_integer(sPsMisoIndex)); + + + -- Mux the register data from the CPLD back to the FPGA. + PsMisoBufferMux : process(sPsRegAddr, sScratchVal, sVcxoControl, + sTxLoLockDetect, sRxLoLockDetect, sMykonosReset) + begin + sPsMisoBuffer <= (others => '0'); + case to_integer(sPsRegAddr) is + when kSignatureReg => sPsMisoBuffer(kDataWidth-1 downto 0) <= kSignature; + when kMinorRevReg => sPsMisoBuffer(kDataWidth-1 downto 0) <= kMinorRev; + when kMajorRevReg => sPsMisoBuffer(kDataWidth-1 downto 0) <= kMajorRev; + when kBuildCodeLSB => sPsMisoBuffer(kDataWidth-1 downto 0) <= kBuildCode(15 downto 0); + when kBuildCodeMSB => sPsMisoBuffer(kDataWidth-1 downto 0) <= kBuildCode(31 downto 16); + when kScratch => sPsMisoBuffer(kDataWidth-1 downto 0) <= sScratchVal; + when kLmkControl => sPsMisoBuffer(kVcxoControl) <= sVcxoControl; + when kLoStatus => sPsMisoBuffer(kTxLoLockDetect) <= sTxLoLockDetect; + sPsMisoBuffer(kRxLoLockDetect) <= sRxLoLockDetect; + when kMykonosControl => sPsMisoBuffer(kMykonosReset) <= sMykonosReset; + when others => sPsMisoBuffer(kDataWidth-1 downto 0) <= (others => '0'); + end case; + end process PsMisoBufferMux; + + + -- Double-synchronize the async inputs to the PS clock domain. However, this clock + -- isn't toggling all the time. Whenever it is toggling, let's capture these bits. + StatusSynchronizer : process(PsSpiSck) + begin + if rising_edge(PsSpiSck) then + aRxLoLockDetect_ms <= aRxLoLockDetect; + sRxLoLockDetect <= aRxLoLockDetect_ms; + + aTxLoLockDetect_ms <= aTxLoLockDetect; + sTxLoLockDetect <= aTxLoLockDetect_ms; + end if; + end process; + + + -- PS SPI locals to outputs. + aVcxoCtrl <= sVcxoControl; + aMkReset_n <= not sMykonosReset; + + + + -- PL SPI Interface : ----------------------------------------------------------------- + -- Composed of a few modules: + -- 1) PlMosiIndex - generate pointer for MOSI Buffer + -- 2) PlMosiBuffer - actually implement the buffer, only when the CPLD is targeted. + -- 3) PlMosiProcessing - process the MOSI data: sort into Rd/!Wt, Address, and Data. + -- This process works on the falling edge of the clock to register the pieces + -- of the MOSI packet as they are complete. The final falling edge registers + -- the data into the individual registers, so it is critical that the clock idle + -- LOW after the transaction is complete such that this final falling edge occurs. + -- 4) PlMisoBuffer - generate pointer for the MISO buffer. The buffer itself is + -- completely async. + -- 5) PlMisoBufferMux - Mux all the register data back into the MISO buffer. + -- 6) StatusSynchronizer - double-synchronizers for status bits from the LMK and LOs. + -- ------------------------------------------------------------------------------------ + + -- Decode the PL SPI Address bits... which are actually going to be used as individual + -- chip selects coming from the PL. + lCpldPlSpiActive <= lPlSpiLe = '0'; + aTxLoCs_n <= aPlSpiAddr(0); + aRxLoCs_n <= aPlSpiAddr(1); + + -- Assign the remainder of the SPI lines to the LOs. + aRxLoSck <= PlSpiSck; + aRxLoDin <= lPlSpiSdi; + aTxLoSck <= PlSpiSck; + aTxLoDin <= lPlSpiSdi; + + -- Output mux for data back to the FPGA (PL core). The LMK and CPLD are the only + -- endpoints that have readback enabled. + lPlSpiSdo <= aTxLoMuxOut when aPlSpiAddr(0) = '0' else + aRxLoMuxOut when aPlSpiAddr(1) = '0' else + lPlCpldMiso; + + + + -- Use the LE signal (Cs_n) as the asynchronous reset to the shift register counter. + -- LE will hold the counter in reset until this endpoint is targeted, when it will + -- release the reset (long before the clock toggles) and allow the shift operation + -- to begin. + -- + -- !!! SAFE COUNTER STARTUP!!! + -- This counter starts safely from reset because the PlSpiSck will not start toggling + -- until long after the asynchronous reset (lCpldPlSpiActive) de-asserts. Similarly, + -- the reset will only assert long after the last clock edge is received. + PlMosiIndex : process(PlSpiSck, lCpldPlSpiActive) + begin + if not lCpldPlSpiActive then + lPlMosiIndex <= (others => '0'); + elsif rising_edge(PlSpiSck) then + lPlMosiIndex <= lPlMosiIndex + 1; + end if; + end process PlMosiIndex; + + + -- Shift in SDI (MOSI) data from the PL on the rising edge of the clock. Only use + -- synchronous resets from here on out. + PlMosiBuffer : process(PlSpiSck) + begin + if rising_edge(PlSpiSck) then + if lReset then + lPlMosiBuffer <= (others => '0'); + else + if lCpldPlSpiActive then + lPlMosiBuffer <= lPlMosiBuffer(lPlMosiBuffer'high-1 downto 0) & lPlSpiSdi; -- left shift + end if; + end if; + end if; + end process PlMosiBuffer; + + + -- As portions of the command and data packets become available, register them here + -- using the falling edge of the PL SPI clock. + PlMosiProcessing : process(PlSpiSck) + begin + if falling_edge(PlSpiSck) then + if lReset then + -- lReset is intentionally self-clearing. It clears on the first falling edge of + -- the next SPI transaction after it is set. Logic on the first rising edge of + -- that next transaction is therefore held in reset. This will not matter + -- as long as SW follows the recommended reset procedure (writing a '1' to reset + -- then writing a '0'), since the first bit of the transaction is '0' for a + -- write operation. + lReset <= false; + lScratchVal <= (others => '0'); + lTxCh1IdleReg <= kTxChDefault; + lTxCh1TxOnReg <= kTxChDefault; + lTxCh2IdleReg <= kTxChDefault; + lTxCh2TxOnReg <= kTxChDefault; + lRxCh1_0IdleReg <= kRxChDefault0; + lRxCh1_1IdleReg <= kRxChDefault1; + lRxCh1_0RxOnReg <= kRxChDefault0; + lRxCh1_1RxOnReg <= kRxChDefault1; + lRxCh2_0IdleReg <= kRxChDefault0; + lRxCh2_1IdleReg <= kRxChDefault1; + lRxCh2_0RxOnReg <= kRxChDefault0; + lRxCh2_1RxOnReg <= kRxChDefault1; + lPlRd <= false; + lPlRegAddr <= (others => '0'); + else + -- After the first bit is captured, we can determine if it is a write or read. + if (lPlMosiIndex = (kRdWtWidth)) then + lPlRd <= lPlMosiBuffer(0) = '1'; + end if; + + -- After the entire command word is captured, the address is ready for capture. + if (lPlMosiIndex = (kAddrWidth + kRdWtWidth)) then + lPlRegAddr <= unsigned(lPlMosiBuffer(kAddrWidth - 1 downto 0)); + end if; + + -- And finally after the entire transaction is complete we can save off the data + -- on the final falling edge of the SPI clock into it's appropriate place, based + -- off the address value captured above. + if (lPlMosiIndex = kTotalWidth) and (not lPlRd) then + + -- ---------------------------------------------------------------------------- + -- Assign writable register values here! -------------------------------------- + -- ---------------------------------------------------------------------------- + if (lPlRegAddr = kPlScratch) then + lScratchVal <= lPlMosiBuffer; + end if; + + if (lPlRegAddr = kPlCpldControl) then + lReset <= lPlMosiBuffer(kCpldReset) = '1'; + end if; + + if (lPlRegAddr = kTxCh1_Idle) then + lTxCh1IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kTxCh1_TxOn) then + lTxCh1TxOnReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kTxCh2_Idle) then + lTxCh2IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kTxCh2_TxOn) then + lTxCh2TxOnReg <= lPlMosiBuffer; + end if; + + if (lPlRegAddr = kRxCh1_0_Idle) then + lRxCh1_0IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh1_1_Idle) then + lRxCh1_1IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh1_0_RxOn) then + lRxCh1_0RxOnReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh1_1_RxOn) then + lRxCh1_1RxOnReg <= lPlMosiBuffer; + end if; + + if (lPlRegAddr = kRxCh2_0_Idle) then + lRxCh2_0IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh2_1_Idle) then + lRxCh2_1IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh2_0_RxOn) then + lRxCh2_0RxOnReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh2_1_RxOn) then + lRxCh2_1RxOnReg <= lPlMosiBuffer; + end if; + + end if; + end if; + end if; + end process PlMosiProcessing; + + + -- Send MISO back to FPGA (PL) on the falling edge as well. + -- + -- !!! SAFE COUNTER STARTUP!!! + -- This counter starts safely from reset because the PlSpiSck will not start toggling + -- until long after the asynchronous reset (lCpldPlSpiActive) de-asserts. Similarly, + -- the reset will only assert long after the last clock edge is received. + PlMisoBuffer : process(PlSpiSck, lCpldPlSpiActive) + begin + if not lCpldPlSpiActive then + lPlMisoIndex <= to_unsigned(kTotalWidth-1, lPlMisoIndex'length); + elsif falling_edge(PlSpiSck) then + if lPlMisoIndex > 0 then + lPlMisoIndex <= lPlMisoIndex - 1; + end if; + end if; + end process PlMisoBuffer; + + lPlCpldMiso <= lPlMisoBuffer(to_integer(lPlMisoIndex)); + + + -- Mux the register data from the CPLD back to the FPGA. + PlMisoBufferMux : process(lPlRegAddr, lScratchVal, lTxCh1IdleReg, lTxCh1TxOnReg, + lTxCh2IdleReg, lTxCh2TxOnReg, lRxCh1_0IdleReg, + lRxCh1_1IdleReg, lRxCh1_0RxOnReg, lRxCh1_1RxOnReg, + lRxCh2_0IdleReg, lRxCh2_1IdleReg, lRxCh2_0RxOnReg, + lRxCh2_1RxOnReg) + begin + lPlMisoBuffer <= (others => '0'); + case to_integer(lPlRegAddr) is + when kPlScratch => lPlMisoBuffer(kDataWidth-1 downto 0) <= lScratchVal; + when kTxCh1_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lTxCh1IdleReg; + when kTxCh1_TxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lTxCh1TxOnReg; + when kTxCh2_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lTxCh2IdleReg; + when kTxCh2_TxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lTxCh2TxOnReg; + when kRxCh1_0_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh1_0IdleReg; + when kRxCh1_1_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh1_1IdleReg; + when kRxCh1_0_RxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh1_0RxOnReg; + when kRxCh1_1_RxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh1_1RxOnReg; + when kRxCh2_0_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh2_0IdleReg; + when kRxCh2_1_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh2_1IdleReg; + when kRxCh2_0_RxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh2_0RxOnReg; + when kRxCh2_1_RxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh2_1RxOnReg; + when others => lPlMisoBuffer(kDataWidth-1 downto 0) <= (others => '0'); + end case; + end process PlMisoBufferMux; + + + -- Use the ATR bits to mux the output values. + lTxCh1 <= lTxCh1IdleReg when aAtrTx1 = '0' else lTxCh1TxOnReg; + lTxCh2 <= lTxCh2IdleReg when aAtrTx2 = '0' else lTxCh2TxOnReg; + + lRxCh1_0 <= lRxCh1_0IdleReg when aAtrRx1 = '0' else lRxCh1_0RxOnReg; + lRxCh1_1 <= lRxCh1_1IdleReg when aAtrRx1 = '0' else lRxCh1_1RxOnReg; + lRxCh2_0 <= lRxCh2_0IdleReg when aAtrRx2 = '0' else lRxCh2_0RxOnReg; + lRxCh2_1 <= lRxCh2_1IdleReg when aAtrRx2 = '0' else lRxCh2_1RxOnReg; + + -- PL SPI locals to outputs. All the register values are set for Channel 1. Channel 2 + -- values are mixed around here in order for the same register settings to work for + -- Channel 1 and Channel 2, even though Ch2 switch configuration is different in HW. + aCh1LedTx <= lTxCh1(kCh1TxLed); + aCh1TxPaEn <= lTxCh1(kCh1TxPaEn); + aCh1TxAmpEn <= lTxCh1(kCh1TxAmpEn); + aCh1TxMixerEn <= lTxCh1(kCh1TxMixerEn); + aCh1TxSw1 <= lTxCh1(kCh1TxSw1Msb downto kCh1TxSw1); + aCh1TxSw2 <= lTxCh1(kCh1TxSw2Msb downto kCh1TxSw2); + aCh1TxSw3 <= lTxCh1(kCh1TxSw3); + aCh1TxSw4 <= "01" when lTxCh1(kCh1TxLowbandMixerPathSelect) = '1' else "10"; + aCh1TxSw5 <= "10" when lTxCh1(kCh1TxLowbandMixerPathSelect) = '1' else "01"; + aCh1SwTrx <= lTxCh1(kCh1SwTrxMsb downto kCh1SwTrx); + aMkTx1En <= lTxCh1(kCh1MykEnTx); + + aCh2LedTx <= lTxCh2(kCh1TxLed); + aCh2TxPaEn <= lTxCh2(kCh1TxPaEn); + aCh2TxAmpEn <= lTxCh2(kCh1TxAmpEn); + aCh2TxMixerEn <= lTxCh2(kCh1TxMixerEn); + aCh2TxSw1 <= lTxCh2(kCh1TxSw1Msb downto kCh1TxSw1); + aCh2TxSw2 <= Tx2Switch2Mod(lTxCh2(kCh1TxSw2Msb downto kCh1TxSw2)); + aCh2TxSw3 <= lTxCh2(kCh1TxSw3); + aCh2TxSw4 <= "10" when lTxCh2(kCh1TxLowbandMixerPathSelect) = '1' else "01"; + aCh2TxSw5 <= "01" when lTxCh2(kCh1TxLowbandMixerPathSelect) = '1' else "10"; + aCh2SwTrx <= Tx2TrxMod(lTxCh2(kCh1SwTrxMsb downto kCh1SwTrx)); + aMkTx2En <= lTxCh2(kCh1MykEnTx); + + aCh1RxSw1 <= lRxCh1_0(kCh1RxSw1Msb downto kCh1RxSw1); + aCh1RxSw2 <= lRxCh1_0(kCh1RxSw2Msb downto kCh1RxSw2); + aCh1RxSw3 <= lRxCh1_0(kCh1RxSw3Msb downto kCh1RxSw3); + aCh1RxSw4 <= lRxCh1_0(kCh1RxSw4Msb downto kCh1RxSw4); + aCh1RxSw5 <= lRxCh1_0(kCh1RxSw5Msb downto kCh1RxSw5); + aCh1RxSw6 <= lRxCh1_1(kCh1RxSw6Msb downto kCh1RxSw6); + aCh1RxSw7 <= "01" when lRxCh1_1(kCh1RxLowbandMixerPathSelect) = '1' else "10"; + aCh1RxSw8 <= "01" when lRxCh1_1(kCh1RxLowbandMixerPathSelect) = '1' else "10"; + aCh1LedRx <= lRxCh1_1(kCh1RxLed) and not lTxCh1(kCh1TxLed); + aCh1LedRx2 <= lRxCh1_1(kCh1Rx2Led); + aCh1RxAmpEn <= lRxCh1_1(kCh1RxAmpEn); + aCh1RxMixerEn <= lRxCh1_1(kCh1RxMixerEn); + aCh1RxLna1En <= lRxCh1_1(kCh1RxLna1En); + aCh1RxLna2En <= lRxCh1_1(kCh1RxLna2En); + aMkRx1En <= lRxCh1_1(kCh1MykEnRx); + + aCh2RxSw1 <= Rx2Switch1Mod(lRxCh2_0(kCh1RxSw1Msb downto kCh1RxSw1)); + aCh2RxSw2 <= Rx2Switch2Mod(lRxCh2_0(kCh1RxSw2Msb downto kCh1RxSw2)); + aCh2RxSw3 <= Rx2Switch3Mod(lRxCh2_0(kCh1RxSw3Msb downto kCh1RxSw3)); + aCh2RxSw4 <= Rx2Switch4Mod(lRxCh2_0(kCh1RxSw4Msb downto kCh1RxSw4)); + aCh2RxSw5 <= Rx2Switch5Mod(lRxCh2_0(kCh1RxSw5Msb downto kCh1RxSw5)); + aCh2RxSw6 <= Rx2Switch6Mod(lRxCh2_1(kCh1RxSw6Msb downto kCh1RxSw6)); + aCh2RxSw7 <= "10" when lRxCh2_1(kCh1RxLowbandMixerPathSelect) = '1' else "01"; + aCh2RxSw8 <= "10" when lRxCh2_1(kCh1RxLowbandMixerPathSelect) = '1' else "01"; + aCh2LedRx <= lRxCh2_1(kCh1RxLed) and not lTxCh2(kCh1TxLed); + aCh2LedRx2 <= lRxCh2_1(kCh1Rx2Led); + aCh2RxAmpEn <= lRxCh2_1(kCh1RxAmpEn); + aCh2RxMixerEn <= lRxCh2_1(kCh1RxMixerEn); + aCh2RxLna1En <= lRxCh2_1(kCh1RxLna1En); + aCh2RxLna2En <= lRxCh2_1(kCh1RxLna2En); + aMkRx2En <= lRxCh2_1(kCh1MykEnRx); + + +end RTL; + + + + +--XmlParse xml_on +-- +-- +-- +-- +-- +-- These registers are accessed via the PS SPI interface to the CPLD. They are all +-- internal to the CPLD. The SPI format is 24 bits total. On MOSI, shift (msb first) +-- Rd/!Wt | Addr(6:0) | Data(15:0) (lsb). The SPI clock {b}MUST{/b} idle LOW before +-- and after the transaction. CPOL=CPHA=0. To access these registers, use the chip +-- select line named "CPLD-PS-SPI-SLE-33" as an active-low select. +-- +-- +-- +-- +-- This register contains the device signature. +-- +-- +-- +-- Represents the product family name/number. This field reads back as +-- 0xCAFE. +-- +-- +-- +-- +-- +-- +-- This register contains the device revision numeric code. +-- +-- +-- +-- Contains minor revision code (0,1,2,...). +-- +-- +-- +-- +-- +-- +-- This register contains the major revision value. +-- +-- +-- +-- Contains major revision code. +-- +-- +-- +-- +-- +-- +-- Build code... right now it's the date it was built. LSB in this register. +-- +-- +-- +-- Contains build code hour code. +-- +-- +-- +-- +-- Contains build code day code. +-- +-- +-- +-- +-- +-- +-- Build code... right now it's the date it was built. MSB in this register. +-- +-- +-- +-- Contains build code month code. +-- +-- +-- +-- +-- Contains build code revision year code. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Contains scratch value for testing. The state of this register has +-- no effect on any other operation in the CPLD. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Asserting this bit resets all the CPLD logic. +-- This reset will return all registers on the PS SPI interface to their default +-- state! To use this reset correctly, first write CpldReset to '1', then write +-- it to '0'. Registers will be reset on the _falling_ edge of CpldReset. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Setting this bit to '0' will allow the Phase DAC to exclusively control the +-- VCXO voltage. Defaults to '1', which allows the Phase DAC to adjust the +-- voltage (but the LMK still has control as well). +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Live lock detect status from the RX LO. +-- +-- +-- +-- +-- Live lock detect status from the TX LO. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Drives the Mykonos hard reset line. Defaults to de-asserted. Write a '1' to +-- assert the reset, and a '0' to de-assert. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- These registers are accessed via the PL SPI interface to the CPLD. They are all +-- internal to the CPLD. The SPI format is 24 bits total. On MOSI, shift (msb first) +-- Rd/!Wt | Addr(6:0) | Data(15:0) (lsb). The SPI clock {b}MUST{/b} idle LOW before +-- and after the transaction. CPOL=CPHA=0. To access these registers, use the chip +-- select line named "CPLD-PL-SPI-LE-25" as an active-low select. {br}{br} +-- +-- The ATR bits ultimately control which of these registers actually control +-- the RF front end. +-- +-- +-- +-- +-- +-- Contains scratch value for testing. The state of this register has no effect +-- on any other operation in the CPLD. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Asserting this bit resets all the CPLD logic on the PL SPI interface. +-- This reset will return all registers to their default state! To use this +-- reset correctly, first write PlCpldReset to '1', then write it to '0'. +-- Registers will be reset on the _falling_ edge of PlCpldReset. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel TX 1 when the +-- ATR bits are configured: TX = 0, RX = don't-care. +-- +-- +-- +-- Controls Switch 1. Filter bank receive switch. +-- +-- +-- +-- +-- Controls Switch 2. Filter bank distribution switch. +-- +-- +-- +-- +-- Controls Switch 3. Bypasses the filter bank and PA, or doesn't. +-- +-- +-- +-- +-- Controls Switches 4 and 5. Write a '1' to select the Lowband Mixer path. +-- Writing '0' will select the bypass path around the mixer. Default is '0'. Note: +-- Individual control over these switches was removed as an optimization to +-- allow all TX controls to fit in one 16 bit register. +-- +-- +-- +-- +-- Write a '1' to enable the lowband mixer. Note that Ch1TxLowbandMixerPathSelect +-- must be properly configured to select the mixer path. +-- +-- +-- +-- +-- Write a '1' to enable the TX path Amp in between TX switches 3 and 4. The path +-- (from Mykonos) is: TxSw4 -> Amp -> DSA -> TxSw3. +-- +-- +-- +-- +-- Write a '1' to enable the TX path PA in between TX switches 2 and 3. +-- +-- +-- +-- +-- TRX switch control. +-- +-- +-- +-- +-- Red/Green combo LED for the TRX channel. +-- +-- +-- +-- +-- Drives the Mykonos input port TX1_ENABLE. +-- +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel TX 1 when the +-- ATR bits are configured: TX = 1, RX = don't-care. The bitfields are the same +-- as for the Tx1_Off register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel TX 2 when the +-- ATR bits are configured: TX = 0, RX = don't-care. The bitfields are the same +-- as for the Tx1_Off register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel TX 2 when the +-- ATR bits are configured: TX = 1, RX = don't-care. The bitfields are the same +-- as for the Tx1_Off register. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 1 when the +-- ATR bits are configured: TX = don't-care, RX = 0. +-- +-- +-- +-- Controls Switch 1. Selects between the cal, bypass, RX2, and TRX paths. +-- +-- +-- +-- +-- Controls Switch 2. First filter switch. Selects between bypass path and +-- the upper/lower filter banks. +-- +-- +-- +-- +-- Controls Switch 3. Lower filter bank transmit switch. +-- +-- +-- +-- +-- Controls Switch 4. Upper filter bank receive switch. +-- +-- +-- +-- +-- Controls Switch 5. Lower filter bank receive switch. +-- +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 1 when the +-- ATR bits are configured: TX = don't-care, RX = 0. +-- +-- +-- +-- Controls Switch 6. Selects between the upper and lower filter banks and +-- bypass path. +-- +-- +-- +-- +-- Controls Switches 7 and 8. Write a '1' to select the Lowband Mixer path. +-- Writing '0' will select the bypass path around the mixer. Default is '0'. Note: +-- Individual control over these switches was removed as an optimization to +-- allow all TX controls to fit in one 16 bit register... so the same was done +-- for the RX path for continuity. +-- +-- +-- +-- +-- Write a '1' to enable the lowband mixer. Note that Ch1RxLowbandMixerPathSelect +-- must be properly configured to select the mixer path. +-- +-- +-- +-- +-- Write a '1' to enable the RX path Amp directly before the Mykonos inputs. +-- +-- +-- +-- +-- Write a '1' to enable the RX path LNA1 between RxSw4 and RxSw6. +-- +-- +-- +-- +-- Write a '1' to enable the RX path LNA2 between RxSw5 and RxSw6. +-- +-- +-- +-- +-- Green LED for RX2 channel. +-- +-- +-- +-- +-- Red/Green combo LED for the TRX channel. +-- +-- +-- +-- +-- Drives the Mykonos input port RX1_ENABLE. +-- +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 1 when the +-- ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same +-- as for the RxCh1_0_Idle register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 1 when the +-- ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same +-- as for the RxCh1_1_Idle register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 2 when the +-- ATR bits are configured: TX = don't-care, RX = 0. The bitfields are the same +-- as for the RxCh1_0_Idle register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 2 when the +-- ATR bits are configured: TX = don't-care, RX = 0. The bitfields are the same +-- as for the RxCh1_1_Idle register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 2 when the +-- ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same +-- as for the RxCh1_0_Idle register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 2 when the +-- ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same +-- as for the RxCh1_1_Idle register. +-- +-- +-- +-- +-- +-- +--XmlParse xml_off + + + diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db0_pins.xdc b/fpga/usrp3/top/n3xx/dboards/mg/db0_pins.xdc new file mode 100644 index 000000000..b89183a2e --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db0_pins.xdc @@ -0,0 +1,156 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Daughterboard Pin Definitions for the N310. +# + +## TDC : ################################################################################ +## Bank 10, 2.5V (DB A) +######################################################################################### + +set_property PACKAGE_PIN AB15 [get_ports {UNUSED_PIN_TDCA_0}] +set_property PACKAGE_PIN AB14 [get_ports {UNUSED_PIN_TDCA_1}] +set_property PACKAGE_PIN AB16 [get_ports {UNUSED_PIN_TDCA_2}] +set_property PACKAGE_PIN AB17 [get_ports {UNUSED_PIN_TDCA_3}] +set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCA_*}] +set_property IOB TRUE [get_ports {UNUSED_PIN_TDCA_*}] + +## USRP IO A : ########################################################################## +## Banks 10/33 +######################################################################################### + +## HP GPIO, Bank 33, 1.8V + +set_property PACKAGE_PIN G1 [get_ports {DBA_CPLD_PS_SPI_LE}] +set_property PACKAGE_PIN H2 [get_ports {DBA_CPLD_PS_SPI_SCLK}] +set_property PACKAGE_PIN D1 [get_ports {DBA_CH1_TX_DSA_DATA[5]}] +# set_property PACKAGE_PIN E1 [get_ports {nc}] +set_property PACKAGE_PIN H1 [get_ports {DBA_CPLD_PS_SPI_ADDR[0]}] +set_property PACKAGE_PIN J1 [get_ports {DBA_CPLD_PS_SPI_ADDR[1]}] +set_property PACKAGE_PIN A5 [get_ports {DBA_CH1_TX_DSA_DATA[3]}] +set_property PACKAGE_PIN A4 [get_ports {DBA_CH1_TX_DSA_DATA[4]}] +set_property PACKAGE_PIN F5 [get_ports {DBA_CPLD_PS_SPI_SDO}] +set_property PACKAGE_PIN E5 [get_ports {DBA_CPLD_PS_SPI_SDI}] +set_property PACKAGE_PIN E3 [get_ports {DBA_CH1_RX_DSA_DATA[0]}] +set_property PACKAGE_PIN E2 [get_ports {DBA_CH1_RX_DSA_DATA[1]}] +set_property PACKAGE_PIN A3 [get_ports {DBA_CH1_TX_DSA_DATA[2]}] +set_property PACKAGE_PIN A2 [get_ports {DBA_CH1_TX_DSA_DATA[1]}] +set_property PACKAGE_PIN K1 [get_ports {DBA_ATR_RX_1}] +set_property PACKAGE_PIN L1 [get_ports {DBA_ATR_TX_2}] +set_property PACKAGE_PIN C4 [get_ports {DBA_CH1_TX_DSA_DATA[0]}] +set_property PACKAGE_PIN C3 [get_ports {DBA_CH1_RX_DSA_DATA[5]}] +set_property PACKAGE_PIN F4 [get_ports {DBA_ATR_TX_1}] +set_property PACKAGE_PIN F3 [get_ports {DBA_ATR_RX_2}] +# set_property PACKAGE_PIN B1 [get_ports {nc}] +set_property PACKAGE_PIN B2 [get_ports {DBA_CH1_RX_DSA_DATA[3]}] +set_property PACKAGE_PIN C1 [get_ports {DBA_CH1_RX_DSA_DATA[4]}] +set_property PACKAGE_PIN C2 [get_ports {DBA_CH1_RX_DSA_DATA[2]}] + +## HR GPIO, Bank 10, 2.5V + +set_property PACKAGE_PIN AG12 [get_ports {DBA_MYK_SYNC_IN_n}] +set_property PACKAGE_PIN AH12 [get_ports {DBA_CPLD_PL_SPI_ADDR[0]}] +set_property PACKAGE_PIN AJ13 [get_ports {DBA_MYK_SPI_SDO}] +set_property PACKAGE_PIN AJ14 [get_ports {DBA_MYK_SPI_SDIO}] +set_property PACKAGE_PIN AG15 [get_ports {DBA_CPLD_PL_SPI_ADDR[1]}] +set_property PACKAGE_PIN AF15 [get_ports {DBA_CH2_TX_DSA_DATA[5]}] +set_property PACKAGE_PIN AH13 [get_ports {DBA_CPLD_JTAG_TDI}] +set_property PACKAGE_PIN AH14 [get_ports {DBA_CPLD_JTAG_TDO}] +set_property PACKAGE_PIN AK15 [get_ports {DBA_MYK_GPIO_1}] +set_property PACKAGE_PIN AJ15 [get_ports {DBA_MYK_GPIO_4}] +set_property PACKAGE_PIN AH16 [get_ports {DBA_CH2_TX_DSA_DATA[4]}] +set_property PACKAGE_PIN AH17 [get_ports {DBA_CH2_TX_DSA_DATA[3]}] +set_property PACKAGE_PIN AE12 [get_ports {DBA_MYK_SYNC_OUT_n}] +set_property PACKAGE_PIN AF12 [get_ports {DBA_CPLD_PL_SPI_SDO}] +set_property PACKAGE_PIN AK12 [get_ports {DBA_MYK_GPIO_13}] +set_property PACKAGE_PIN AK13 [get_ports {DBA_MYK_GPIO_0}] +set_property PACKAGE_PIN AK16 [get_ports {DBA_MYK_INTRQ}] +set_property PACKAGE_PIN AJ16 [get_ports {DBA_CH2_TX_DSA_DATA[2]}] +set_property PACKAGE_PIN AH18 [get_ports {DBA_CH2_TX_DSA_DATA[0]}] +set_property PACKAGE_PIN AJ18 [get_ports {DBA_CH2_TX_DSA_DATA[1]}] +set_property PACKAGE_PIN AF14 [get_ports {DBA_FPGA_CLK_P}] +set_property PACKAGE_PIN AG14 [get_ports {DBA_FPGA_CLK_N}] +set_property PACKAGE_PIN AG17 [get_ports {DBA_FPGA_SYSREF_P}] +set_property PACKAGE_PIN AG16 [get_ports {DBA_FPGA_SYSREF_N}] +set_property PACKAGE_PIN AD15 [get_ports {DBA_CH2_RX_DSA_DATA[3]}] +set_property PACKAGE_PIN AD16 [get_ports {DBA_CH2_RX_DSA_DATA[5]}] +set_property PACKAGE_PIN AE13 [get_ports {DBA_CPLD_JTAG_TMS}] +set_property PACKAGE_PIN AF13 [get_ports {DBA_CPLD_JTAG_TCK}] +set_property PACKAGE_PIN AE15 [get_ports {DBA_MYK_GPIO_15}] +set_property PACKAGE_PIN AE16 [get_ports {DBA_MYK_SPI_CS_n}] +set_property PACKAGE_PIN AF17 [get_ports {DBA_CH2_RX_DSA_DATA[1]}] +set_property PACKAGE_PIN AF18 [get_ports {DBA_CH2_RX_DSA_DATA[2]}] +set_property PACKAGE_PIN AC16 [get_ports {DBA_CPLD_PL_SPI_LE}] +set_property PACKAGE_PIN AC17 [get_ports {DBA_CPLD_PL_SPI_SDI}] +set_property PACKAGE_PIN AD13 [get_ports {DBA_MYK_GPIO_12}] +set_property PACKAGE_PIN AD14 [get_ports {DBA_MYK_GPIO_14}] +set_property PACKAGE_PIN AE17 [get_ports {DBA_MYK_SPI_SCLK}] +set_property PACKAGE_PIN AE18 [get_ports {DBA_MYK_GPIO_3}] +set_property PACKAGE_PIN AB12 [get_ports {DBA_CH2_RX_DSA_DATA[0]}] +set_property PACKAGE_PIN AC12 [get_ports {DBA_CH2_RX_DSA_DATA[4]}] +set_property PACKAGE_PIN AC13 [get_ports {DBA_CPLD_PL_SPI_ADDR[2]}] +set_property PACKAGE_PIN AC14 [get_ports {DBA_CPLD_PL_SPI_SCLK}] + +# set_property PACKAGE_PIN AB25 [get_ports {DBA_SWITCHER_CLOCK}] +# set_property IOSTANDARD LVCMOS33 [get_ports {DBA_SWITCHER_CLOCK}] +# set_property DRIVE 4 [get_ports {DBA_SWITCHER_CLOCK}] +# set_property SLEW SLOW [get_ports {DBA_SWITCHER_CLOCK}] + +# During SI measurements with default drive strength, many of the FPGA-driven lines to +# the DB were showing high over/undershoot. Therefore for single-ended lines to the DBs +# we are decreasing the drive strength to the minimum value (4mA) and explicitly +# declaring the (default) slew rate as SLOW. + +set UsrpIoAHpPinsSe [get_ports {DBA_CPLD_PS_* \ + DBA_CH1_* \ + DBA_ATR*}] +set_property IOSTANDARD LVCMOS18 $UsrpIoAHpPinsSe +set_property DRIVE 4 $UsrpIoAHpPinsSe +set_property SLEW SLOW $UsrpIoAHpPinsSe + +set UsrpIoAHrPinsSe [get_ports {DBA_MYK_SPI_* \ + DBA_MYK_INTRQ \ + DBA_MYK_SYNC* \ + DBA_MYK_GPIO* \ + DBA_CPLD_PL_* \ + DBA_CPLD_JTAG_* \ + DBA_CH2*}] +set_property IOSTANDARD LVCMOS25 $UsrpIoAHrPinsSe +set_property DRIVE 4 $UsrpIoAHrPinsSe +set_property SLEW SLOW $UsrpIoAHrPinsSe + +set UsrpIoAHrPinsDiff [get_ports {DBA_FPGA_CLK_* \ + DBA_FPGA_SYSREF_*}] +set_property IOSTANDARD LVDS_25 $UsrpIoAHrPinsDiff +set_property DIFF_TERM TRUE $UsrpIoAHrPinsDiff + +# Do not allow the DSA lines to float... give them a weak pull if undriven. +set_property PULLUP TRUE [get_ports {DBA_CH*_*X_DSA_DATA[*]}] + + +### MGTs, Bank 112 + +set_property PACKAGE_PIN N8 [get_ports {USRPIO_A_MGTCLK_P}] +set_property PACKAGE_PIN N7 [get_ports {USRPIO_A_MGTCLK_N}] + +# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado +# places the transceivers in the correct places. The mixup in lanes is accounted for +# in the Mykonos lane crossbar settings. +set_property PACKAGE_PIN V6 [get_ports {USRPIO_A_RX_P[0]}] +set_property PACKAGE_PIN V5 [get_ports {USRPIO_A_RX_N[0]}] +set_property PACKAGE_PIN U4 [get_ports {USRPIO_A_RX_P[1]}] +set_property PACKAGE_PIN U3 [get_ports {USRPIO_A_RX_N[1]}] +set_property PACKAGE_PIN T6 [get_ports {USRPIO_A_RX_P[2]}] +set_property PACKAGE_PIN T5 [get_ports {USRPIO_A_RX_N[2]}] +set_property PACKAGE_PIN P6 [get_ports {USRPIO_A_RX_P[3]}] +set_property PACKAGE_PIN P5 [get_ports {USRPIO_A_RX_N[3]}] + +set_property PACKAGE_PIN T2 [get_ports {USRPIO_A_TX_P[0]}] +set_property PACKAGE_PIN T1 [get_ports {USRPIO_A_TX_N[0]}] +set_property PACKAGE_PIN R4 [get_ports {USRPIO_A_TX_P[1]}] +set_property PACKAGE_PIN R3 [get_ports {USRPIO_A_TX_N[1]}] +set_property PACKAGE_PIN P2 [get_ports {USRPIO_A_TX_P[2]}] +set_property PACKAGE_PIN P1 [get_ports {USRPIO_A_TX_N[2]}] +set_property PACKAGE_PIN N4 [get_ports {USRPIO_A_TX_P[3]}] +set_property PACKAGE_PIN N3 [get_ports {USRPIO_A_TX_N[3]}] diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db1_pins.xdc b/fpga/usrp3/top/n3xx/dboards/mg/db1_pins.xdc new file mode 100644 index 000000000..f95051ba7 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db1_pins.xdc @@ -0,0 +1,156 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Daughterboard Pin Definitions for the N310. +# + +## TDC : ################################################################################ +## Bank 11, 2.5V (DB B) +######################################################################################### + +set_property PACKAGE_PIN W21 [get_ports {UNUSED_PIN_TDCB_0}] +set_property PACKAGE_PIN Y21 [get_ports {UNUSED_PIN_TDCB_1}] +set_property PACKAGE_PIN Y22 [get_ports {UNUSED_PIN_TDCB_2}] +set_property PACKAGE_PIN Y23 [get_ports {UNUSED_PIN_TDCB_3}] +set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCB_*}] +set_property IOB TRUE [get_ports {UNUSED_PIN_TDCB_*}] + +### USRP IO B : ######################################################################### +## Bank 11/33 +######################################################################################### + +## HP GPIO, Bank 33, 1.8V + +set_property PACKAGE_PIN J4 [get_ports {DBB_CPLD_PS_SPI_LE}] +set_property PACKAGE_PIN J3 [get_ports {DBB_CPLD_PS_SPI_SCLK}] +set_property PACKAGE_PIN D4 [get_ports {DBB_CH1_TX_DSA_DATA[5]}] +# set_property PACKAGE_PIN D3 [get_ports {nc}] +set_property PACKAGE_PIN K2 [get_ports {DBB_CPLD_PS_SPI_ADDR[0]}] +set_property PACKAGE_PIN K3 [get_ports {DBB_CPLD_PS_SPI_ADDR[1]}] +set_property PACKAGE_PIN B5 [get_ports {DBB_CH1_TX_DSA_DATA[3]}] +set_property PACKAGE_PIN B4 [get_ports {DBB_CH1_TX_DSA_DATA[4]}] +set_property PACKAGE_PIN G5 [get_ports {DBB_CPLD_PS_SPI_SDO}] +set_property PACKAGE_PIN G4 [get_ports {DBB_CPLD_PS_SPI_SDI}] +set_property PACKAGE_PIN J5 [get_ports {DBB_CH1_RX_DSA_DATA[0]}] +set_property PACKAGE_PIN K5 [get_ports {DBB_CH1_RX_DSA_DATA[1]}] +set_property PACKAGE_PIN D5 [get_ports {DBB_CH1_TX_DSA_DATA[2]}] +set_property PACKAGE_PIN E6 [get_ports {DBB_CH1_TX_DSA_DATA[1]}] +set_property PACKAGE_PIN L3 [get_ports {DBB_ATR_RX_1}] +set_property PACKAGE_PIN L2 [get_ports {DBB_ATR_TX_2}] +set_property PACKAGE_PIN G6 [get_ports {DBB_CH1_TX_DSA_DATA[0]}] +set_property PACKAGE_PIN H6 [get_ports {DBB_CH1_RX_DSA_DATA[5]}] +set_property PACKAGE_PIN H4 [get_ports {DBB_ATR_TX_1}] +set_property PACKAGE_PIN H3 [get_ports {DBB_ATR_RX_2}] +# set_property PACKAGE_PIN F2 [get_ports {nc}] +set_property PACKAGE_PIN G2 [get_ports {DBB_CH1_RX_DSA_DATA[3]}] +set_property PACKAGE_PIN J6 [get_ports {DBB_CH1_RX_DSA_DATA[4]}] +set_property PACKAGE_PIN K6 [get_ports {DBB_CH1_RX_DSA_DATA[2]}] + +## HR GPIO, Bank 10, 2.5V + +set_property PACKAGE_PIN AK17 [get_ports {DBB_MYK_SYNC_IN_n}] +set_property PACKAGE_PIN AK18 [get_ports {DBB_CPLD_PL_SPI_ADDR[0]}] +set_property PACKAGE_PIN AK21 [get_ports {DBB_MYK_SPI_SDO}] +set_property PACKAGE_PIN AJ21 [get_ports {DBB_MYK_SPI_SDIO}] +set_property PACKAGE_PIN AF19 [get_ports {DBB_CPLD_PL_SPI_ADDR[1]}] +set_property PACKAGE_PIN AG19 [get_ports {DBB_CH2_TX_DSA_DATA[5]}] +set_property PACKAGE_PIN AH19 [get_ports {DBB_CPLD_JTAG_TDI}] +set_property PACKAGE_PIN AJ19 [get_ports {DBB_CPLD_JTAG_TDO}] +set_property PACKAGE_PIN AK22 [get_ports {DBB_MYK_GPIO_1}] +set_property PACKAGE_PIN AK23 [get_ports {DBB_MYK_GPIO_4}] +set_property PACKAGE_PIN AF20 [get_ports {DBB_CH2_TX_DSA_DATA[4]}] +set_property PACKAGE_PIN AG20 [get_ports {DBB_CH2_TX_DSA_DATA[3]}] +set_property PACKAGE_PIN AF23 [get_ports {DBB_MYK_SYNC_OUT_n}] +set_property PACKAGE_PIN AF24 [get_ports {DBB_CPLD_PL_SPI_SDO}] +set_property PACKAGE_PIN AK20 [get_ports {DBB_MYK_GPIO_13}] +set_property PACKAGE_PIN AJ20 [get_ports {DBB_MYK_GPIO_0}] +set_property PACKAGE_PIN AJ23 [get_ports {DBB_MYK_INTRQ}] +set_property PACKAGE_PIN AJ24 [get_ports {DBB_CH2_TX_DSA_DATA[2]}] +set_property PACKAGE_PIN AG24 [get_ports {DBB_CH2_TX_DSA_DATA[0]}] +set_property PACKAGE_PIN AG25 [get_ports {DBB_CH2_TX_DSA_DATA[1]}] +set_property PACKAGE_PIN AG21 [get_ports {DBB_FPGA_CLK_P}] +set_property PACKAGE_PIN AH21 [get_ports {DBB_FPGA_CLK_N}] +set_property PACKAGE_PIN AE22 [get_ports {DBB_FPGA_SYSREF_P}] +set_property PACKAGE_PIN AF22 [get_ports {DBB_FPGA_SYSREF_N}] +set_property PACKAGE_PIN AJ25 [get_ports {DBB_CH2_RX_DSA_DATA[3]}] +set_property PACKAGE_PIN AK25 [get_ports {DBB_CH2_RX_DSA_DATA[5]}] +set_property PACKAGE_PIN AB21 [get_ports {DBB_CPLD_JTAG_TMS}] +set_property PACKAGE_PIN AB22 [get_ports {DBB_CPLD_JTAG_TCK}] +set_property PACKAGE_PIN AD23 [get_ports {DBB_MYK_GPIO_15}] +set_property PACKAGE_PIN AE23 [get_ports {DBB_MYK_SPI_CS_n}] +set_property PACKAGE_PIN AB24 [get_ports {DBB_CH2_RX_DSA_DATA[1]}] +set_property PACKAGE_PIN AA24 [get_ports {DBB_CH2_RX_DSA_DATA[2]}] +set_property PACKAGE_PIN AG22 [get_ports {DBB_CPLD_PL_SPI_LE}] +set_property PACKAGE_PIN AH22 [get_ports {DBB_CPLD_PL_SPI_SDI}] +set_property PACKAGE_PIN AD21 [get_ports {DBB_MYK_GPIO_12}] +set_property PACKAGE_PIN AE21 [get_ports {DBB_MYK_GPIO_14}] +set_property PACKAGE_PIN AC22 [get_ports {DBB_MYK_SPI_SCLK}] +set_property PACKAGE_PIN AC23 [get_ports {DBB_MYK_GPIO_3}] +set_property PACKAGE_PIN AC24 [get_ports {DBB_CH2_RX_DSA_DATA[0]}] +set_property PACKAGE_PIN AD24 [get_ports {DBB_CH2_RX_DSA_DATA[4]}] +set_property PACKAGE_PIN AH23 [get_ports {DBB_CPLD_PL_SPI_ADDR[2]}] +set_property PACKAGE_PIN AH24 [get_ports {DBB_CPLD_PL_SPI_SCLK}] + +# set_property PACKAGE_PIN AA25 [get_ports DBB_SWITCHER_CLOCK] +# set_property IOSTANDARD LVCMOS33 [get_ports DBB_SWITCHER_CLOCK] +# set_property DRIVE 4 [get_ports DBB_SWITCHER_CLOCK] +# set_property SLEW SLOW [get_ports DBB_SWITCHER_CLOCK] + +# During SI measurements with default drive strength, many of the FPGA-driven lines to +# the DB were showing high over/undershoot. Therefore for single-ended lines to the DBs +# we are decreasing the drive strength to the minimum value (4mA) and explicitly +# declaring the (default) slew rate as SLOW. + +set UsrpIoBHpPinsSe [get_ports {DBB_CPLD_PS_* \ + DBB_CH1_* \ + DBB_ATR*}] +set_property IOSTANDARD LVCMOS18 $UsrpIoBHpPinsSe +set_property DRIVE 4 $UsrpIoBHpPinsSe +set_property SLEW SLOW $UsrpIoBHpPinsSe + +set UsrpIoBHrPinsSe [get_ports {DBB_MYK_SPI_* \ + DBB_MYK_INTRQ \ + DBB_MYK_SYNC* \ + DBB_MYK_GPIO* \ + DBB_CPLD_PL_* \ + DBB_CPLD_JTAG_* \ + DBB_CH2*}] +set_property IOSTANDARD LVCMOS25 $UsrpIoBHrPinsSe +set_property DRIVE 4 $UsrpIoBHrPinsSe +set_property SLEW SLOW $UsrpIoBHrPinsSe + +set UsrpIoBHrPinsDiff [get_ports {DBB_FPGA_CLK_* \ + DBB_FPGA_SYSREF_*}] +set_property IOSTANDARD LVDS_25 $UsrpIoBHrPinsDiff +set_property DIFF_TERM TRUE $UsrpIoBHrPinsDiff + +# Do not allow the DSA lines to float... give them a weak pull if undriven. +set_property PULLUP TRUE [get_ports {DBB_CH*_*X_DSA_DATA[*]}] + + +### MGTs, Bank 112 + +set_property PACKAGE_PIN W8 [get_ports {USRPIO_B_MGTCLK_P}] +set_property PACKAGE_PIN W7 [get_ports {USRPIO_B_MGTCLK_N}] + +# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado +# places the transceivers in the correct places. The mixup in lanes is accounted for +# in the Mykonos lane crossbar settings. +set_property PACKAGE_PIN AC4 [get_ports {USRPIO_B_RX_P[0]}] +set_property PACKAGE_PIN AC3 [get_ports {USRPIO_B_RX_N[0]}] +set_property PACKAGE_PIN AB6 [get_ports {USRPIO_B_RX_P[1]}] +set_property PACKAGE_PIN AB5 [get_ports {USRPIO_B_RX_N[1]}] +set_property PACKAGE_PIN Y6 [get_ports {USRPIO_B_RX_P[2]}] +set_property PACKAGE_PIN Y5 [get_ports {USRPIO_B_RX_N[2]}] +set_property PACKAGE_PIN AA4 [get_ports {USRPIO_B_RX_P[3]}] +set_property PACKAGE_PIN AA3 [get_ports {USRPIO_B_RX_N[3]}] + +set_property PACKAGE_PIN AB2 [get_ports {USRPIO_B_TX_P[0]}] +set_property PACKAGE_PIN AB1 [get_ports {USRPIO_B_TX_N[0]}] +set_property PACKAGE_PIN Y2 [get_ports {USRPIO_B_TX_P[1]}] +set_property PACKAGE_PIN Y1 [get_ports {USRPIO_B_TX_N[1]}] +set_property PACKAGE_PIN W4 [get_ports {USRPIO_B_TX_P[2]}] +set_property PACKAGE_PIN W3 [get_ports {USRPIO_B_TX_N[2]}] +set_property PACKAGE_PIN V2 [get_ports {USRPIO_B_TX_P[3]}] +set_property PACKAGE_PIN V1 [get_ports {USRPIO_B_TX_N[3]}] diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/ClockingRegs.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/ClockingRegs.vhd new file mode 100644 index 000000000..ffaa64f68 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/ClockingRegs.vhd @@ -0,0 +1,345 @@ +------------------------------------------------------------------------------- +-- +-- File: ClockingRegs.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 17 March 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Register access to the control/status bits and interfaces for the +-- RadioClocking module. +-- +-- XML register definition is included below the module. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library work; + use work.PkgClockingRegMap.all; + use work.PkgRegs.all; + + +entity ClockingRegs is + port( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + -- Register Bus Clock -- this module connects the BusClk to PsClk, so it's limited + -- to 200 MHz! + BusClk : in std_logic; + + bRegPortOut : out RegPortOut_t; + bRegPortIn : in RegPortIn_t; + + -- Phase shift interface to the RadioClkMmcm. + -- There is a reset crossing here between the MMCM reset and aReset. The outgoing + -- crossing is safe because (a) the enable signal driven to the MMCM is a strobe-only + -- signal and (b) this interface should only be used when the MMCM is not in reset + -- (SW waits for the MMCM to be out of reset and locked before using this interface). + -- The only input signal, pPsDone, is double-synced in this file before being used. + -- This is OK (even though it is a strobe signal) because there is only a reset + -- crossing and not a clock domain crossing. + pPsInc : out std_logic; + pPsEn : out std_logic; + pPsDone : in std_logic; + + -- PsClk is driven directly by BusClk, so p = b in the logic below! + PsClk : out std_logic; + + -- Sync reset strobes from the register bus to the RadioClkMmcm. + bRadioClkMmcmReset : out std_logic; + -- Status of RadioClk MMCM lock to register bus. + aRadioClksValid : in std_logic; + + bRadioClk1xEnabled : out std_logic; + bRadioClk2xEnabled : out std_logic; + bRadioClk3xEnabled : out std_logic; + + bJesdRefClkPresent : in std_logic + ); +end ClockingRegs; + + +architecture RTL of ClockingRegs is + + --vhook_sigstart + --vhook_sigend + + signal bRadioClkMmcmResetInt : std_logic := '1'; + + signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero; + + signal bPsDone, + bPsEn, + bPsInc, + pPsDoneDs_ms, + pPsDoneDs : std_logic := '0'; + + signal bRadioClk1xEnabledInt, + bRadioClk2xEnabledInt, + bRadioClk3xEnabledInt, + bRadioClksValid_ms, + bRadioClksValid : std_logic := '0'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of bRadioClksValid_ms : signal is "true"; + attribute ASYNC_REG of bRadioClksValid : signal is "true"; + attribute ASYNC_REG of pPsDoneDs_ms : signal is "true"; + attribute ASYNC_REG of pPsDoneDs : signal is "true"; + +begin + + -- Locals to outputs. + PsClk <= BusClk; + pPsInc <= bPsInc; + pPsEn <= bPsEn; + + bRadioClkMmcmReset <= bRadioClkMmcmResetInt; + + bRadioClk1xEnabled <= bRadioClk1xEnabledInt; + bRadioClk2xEnabled <= bRadioClk2xEnabledInt; + bRadioClk3xEnabled <= bRadioClk3xEnabledInt; + + + -- Write Registers : ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + WriteRegisters: process(aReset, BusClk) + begin + if aReset then + bRadioClkMmcmResetInt <= '1'; + bPsInc <= '0'; + bPsEn <= '0'; + bRadioClk1xEnabledInt <= '0'; + bRadioClk2xEnabledInt <= '0'; + bRadioClk3xEnabledInt <= '0'; + elsif rising_edge(BusClk) then + + if bReset then + bRadioClkMmcmResetInt <= '1'; + bPsInc <= '0'; + bPsEn <= '0'; + bRadioClk1xEnabledInt <= '0'; + bRadioClk2xEnabledInt <= '0'; + bRadioClk3xEnabledInt <= '0'; + else + -- Clear strobe + bPsEn <= '0'; + + if RegWrite(kPhaseShiftControl, bRegPortIn) then + if bRegPortIn.Data(kPsInc) = '1' then + bPsInc <= '1'; + bPsEn <= '1'; + elsif bRegPortIn.Data(kPsDec) = '1' then + bPsInc <= '0'; + bPsEn <= '1'; + end if; + end if; + + if RegWrite(kRadioClkMmcm, bRegPortIn) then + -- Set/Clear pair + if bRegPortIn.Data(kRadioClkMmcmResetSet) = '1' then + bRadioClkMmcmResetInt <= '1'; + elsif bRegPortIn.Data(kRadioClkMmcmResetClear) = '1' then + bRadioClkMmcmResetInt <= '0'; + end if; + end if; + + if RegWrite(kRadioClkEnables, bRegPortIn) then + bRadioClk1xEnabledInt <= bRegPortIn.Data(kRadioClk1xEnabled); + bRadioClk2xEnabledInt <= bRegPortIn.Data(kRadioClk2xEnabled); + bRadioClk3xEnabledInt <= bRegPortIn.Data(kRadioClk3xEnabled); + end if; + + end if; + end if; + end process WriteRegisters; + + + DoubleSyncs : process (aReset, BusClk) + begin + if aReset then + bRadioClksValid_ms <= '0'; + bRadioClksValid <= '0'; + pPsDoneDs_ms <= '0'; + pPsDoneDs <= '0'; + elsif rising_edge(BusClk) then + -- No sync reset on double-syncs (however there are default assignments above)! + bRadioClksValid_ms <= aRadioClksValid; + bRadioClksValid <= bRadioClksValid_ms; + pPsDoneDs_ms <= pPsDone; + pPsDoneDs <= pPsDoneDs_ms; + end if; + end process; + + + -- Read Registers : ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + ReadRegisters: process(aReset, BusClk) + begin + if aReset then + bRegPortOutLcl <= kRegPortOutZero; + bPsDone <= '0'; + elsif rising_edge(BusClk) then + + if bReset then + bRegPortOutLcl <= kRegPortOutZero; + bPsDone <= '0'; + else + -- Deassert strobes + bRegPortOutLcl.Data <= kRegPortDataZero; + + -- All of these transactions only take one clock cycle, so we do not have to + -- de-assert the Ready signal (ever). + bRegPortOutLcl.Ready <= true; + + -- Process the returned data from the phase shifter in the MMCM. Note that even + -- though the prefixes are different (p and b), we drive the PsClk from the BusClk + -- so this "crossing" is actually safe. Whenever the Done signal asserts (pPsDone - + -- pay attention to the prefix!) from the MMCM, we set a sticky bit to tell SW + -- that the shift operation is complete. + -- + -- However, if pPsDone asserts at the same time that SW tries to read the register, + -- we should accurately report that the operation is indeed complete and then NOT + -- store the sticky (since it has already been read by SW). If a read does not come + -- through at the same time pPsDone is asserted, then we store the done state as a + -- sticky, bPsDone, which is only cleared by a read to this register. + if RegRead(kPhaseShiftControl, bRegPortIn) then + -- The phase shift is always enabled for the feedback clock in RadioClocking.vhd + bRegPortOutLcl.Data(kPsEnabledForFdbClk) <= '1'; + bRegPortOutLcl.Data(kPsDone) <= bPsDone or pPsDoneDs; + bPsDone <= '0'; + elsif pPsDoneDs = '1' then + bPsDone <= '1'; + end if; + + if RegRead(kRadioClkMmcm, bRegPortIn) then + bRegPortOutLcl.Data(kRadioClkMmcmLocked) <= bRadioClksValid; + end if; + + if RegRead(kRadioClkEnables, bRegPortIn) then + bRegPortOutLcl.Data(kRadioClk1xEnabled) <= bRadioClk1xEnabledInt; + bRegPortOutLcl.Data(kRadioClk2xEnabled) <= bRadioClk2xEnabledInt; + bRegPortOutLcl.Data(kRadioClk3xEnabled) <= bRadioClk3xEnabledInt; + end if; + + if RegRead(kMgtRefClkStatus, bRegPortIn) then + bRegPortOutLcl.Data(kJesdRefClkPresent) <= bJesdRefClkPresent; + end if; + + end if; + end if; + end process ReadRegisters; + + -- Local to output + bRegPortOut <= bRegPortOutLcl; + + +end RTL; + + +--XmlParse xml_on +-- +-- +-- +-- +-- +-- +-- +-- +-- Reflects the locked status of the MMCM. '1' = locked. This bit is only valid +-- when the MMCM reset is de-asserted. Read-only. +-- +-- +-- +-- +-- Controls the reset to the Radio Clock MMCM. Strobe this bit to de-assert the +-- reset to the MMCM. Default is reset asserted. Write-only. +-- +-- +-- +-- +-- Controls the reset to the Radio Clock MMCM. Strobe this bit to assert the +-- reset to the MMCM. Default is reset asserted. Write-only. +-- +-- +-- +-- +-- +-- +-- Phase Shift for RadioClkMmcm. +-- +-- +-- +-- This bit should set after a shift operation successfully completes. +-- Reading this register will clear this bit. Read-only. +-- +-- +-- +-- +-- Strobe this bit to increment the phase. This bit is self-clearing and will +-- always return '0' when read. If PsInc and PsDec are asserted together, +-- the phase will increment. +-- +-- +-- +-- +-- Strobe this bit to decrement the phase. This bit is self-clearing and will +-- always return '0' when read. If PsInc and PsDec are asserted together, +-- the phase will increment. +-- +-- +-- +-- +-- Read-only. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- +-- +-- +-- +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- +-- +-- +-- +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Live indicator of the MGT Reference Clock toggling and within expected +-- frequency limits. If this bit is de-asserted, then the JESD204b core will +-- not function correctly! +-- +-- +-- +-- +-- +-- +-- +--XmlParse xml_off diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DaughterboardRegs.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DaughterboardRegs.vhd new file mode 100644 index 000000000..7f8ef388a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DaughterboardRegs.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------- +-- +-- File: DaughterboardRegs.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 27 April 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Register interface to the semi-static control lines for the Mg +-- Daughterboard. +-- +-- XML register definition is included below the module. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library work; + use work.PkgDaughterboardRegMap.all; + use work.PkgRegs.all; + + +entity DaughterboardRegs is + port( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + BusClk : in std_logic; + + bRegPortOut : out RegPortOut_t; + bRegPortIn : in RegPortIn_t; + + -- Slot and DB ID values. These should be tied to constants! + kDbId : in std_logic_vector(15 downto 0); + kSlotId : in std_logic + + ); +end DaughterboardRegs; + + +architecture RTL of DaughterboardRegs is + + --vhook_sigstart + --vhook_sigend + + signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero; + +begin + + + -- Read Registers : ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + ReadRegisters: process(aReset, BusClk) + begin + if aReset then + bRegPortOutLcl <= kRegPortOutZero; + elsif rising_edge(BusClk) then + if bReset then + bRegPortOutLcl <= kRegPortOutZero; + else + -- De-assert strobes + bRegPortOutLcl.Data <= kRegPortDataZero; + + -- All of these transactions only take one clock cycle, so we do not have to + -- de-assert the Ready signal (ever). + bRegPortOutLcl.Ready <= true; + + if RegRead(kDaughterboardId, bRegPortIn) then + bRegPortOutLcl.Data(kDbIdValMsb downto kDbIdVal) <= kDbId; + bRegPortOutLcl.Data(kSlotIdVal) <= kSlotId; + end if; + + end if; + end if; + end process ReadRegisters; + + -- Local to output + bRegPortOut <= bRegPortOutLcl; + + +end RTL; + + +--XmlParse xml_on +-- +-- +-- +-- +-- +-- +-- +-- +-- ID for the DB with which this file is designed to communicate. Matches the DB +-- EEPROM ID. +-- +-- +-- +-- +-- ID for the Slot this module controls. Options are 0 and 1 for the N310 MB. +-- +-- +-- +-- +-- +-- +-- +-- +--XmlParse xml_off diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DbCore.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DbCore.vhd new file mode 100644 index 000000000..e1369ec00 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DbCore.vhd @@ -0,0 +1,562 @@ +------------------------------------------------------------------------------- +-- +-- File: DbCore.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 12 April 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2017-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Wrapper file for Daughterboard Control. This includes the semi-static control +-- and status registers, clocking, synchronization, and JESD204B cores. +-- +-- There is no version register for the plain-text files here. +-- Version control for the Sync and JESD204B cores is internal to the netlists. +-- +-- The resets for this core are almost entirely local and/or synchronous. +-- bBusReset is a Synchronous reset on the BusClk domain that resets all of the +-- registers connected to the RegPort, as well as any other stray registers +-- connected to the BusClk. All other resets are local to the modules they touch. +-- No other reset drives all modules universally. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgMgPersonality.all; + use work.PkgRegs.all; + use work.PkgJesdConfig.all; + + +entity DbCore is + generic( + -- Set to '1' to include the White Rabbit TDC. + kInclWhiteRabbitTdc : std_logic := '0' + ); + port( + + -- Resets -- + -- Synchronous Reset for the BusClk domain (mainly for the RegPort) + bBusReset : in std_logic; + + -- Clocks -- + -- Register Bus Clock (any frequency) + BusClk : in std_logic; + -- Always-on at 40 MHz + Clk40 : in std_logic; + -- Super secret crazy awesome measurement clock at weird frequencies. + MeasClk : in std_logic; + -- FPGA Sample Clock from DB LMK + FpgaClk_p : in std_logic; + FpgaClk_n : in std_logic; + + -- Sample Clock Sharing. The clocks generated in this module are exported out to the + -- top level so they can be shared amongst daughterboards. Therefore they must be + -- driven back into the SampleClk*x inputs at a higher level in order for this module + -- to work correctly. There are a few isolated cases where SampleClk*xOut is used + -- directly in this module, and those are documented below. + SampleClk1xOut : out std_logic; + SampleClk1x : in std_logic; + SampleClk2xOut : out std_logic; + SampleClk2x : in std_logic; + + + -- Register Ports -- + -- + -- Only synchronous resets can be used for these ports! + bRegPortInFlat : in std_logic_vector(49 downto 0); + bRegPortOutFlat : out std_logic_vector(33 downto 0); + + -- Slot ID value. This should be tied to a constant! + kSlotId : in std_logic; + + + -- SYSREF -- + -- + -- SYSREF direct from the LMK + sSysRefFpgaLvds_p, + sSysRefFpgaLvds_n : in std_logic; + -- SYNC directly to the LMK + aLmkSync : out std_logic; + + + -- JESD Signals -- + -- + -- GTX Sample Clock Reference Input. Direct connect to FPGA pins. + JesdRefClk_p, + JesdRefClk_n : in std_logic; + + -- ADC JESD PHY Interface. Direct connect to FPGA pins. + aAdcRx_p, + aAdcRx_n : in std_logic_vector(3 downto 0); + aSyncAdcOut_n : out std_logic; + + -- DAC JESD PHY Interface. Direct connect to FPGA pins. + aDacTx_p, + aDacTx_n : out std_logic_vector(3 downto 0); + aSyncDacIn_n : in std_logic; + + + -- Data Pipes to/from the DACs/ADCs -- + -- + -- - Data is presented as one sample per cycle. + -- - sAdcDataValid asserts when ADC data is valid. + -- - sDacReadyForInput asserts when DAC data is ready to be received. + -- + -- Reset Crossings: + -- The ADC data and valid outputs are synchronously cleared before the asynchronous + -- reset is asserted--preventing any reset crossing issues here between the RX + -- (internal to the core) reset and the no-reset domain of RFNoC. + -- + -- The DAC samples should be zeros on reset de-assertion due to RFI being de-asserted + -- in reset. If they are not zeros, then it is still OK because data is ignored until + -- RFI is asserted. DAC RFI is double-synchronized to protect against the reset + -- crossing. This is safe to do because it simply delays the output of RFI by two + -- cycles on the assertion edge, and as long as reset is held for more than two + -- cycles, the de-assertion edge of RFI should come long before the TX module is + -- taken out of reset. + sAdcDataValid : out std_logic; + sAdcDataSamples0I : out std_logic_vector(15 downto 0); + sAdcDataSamples0Q : out std_logic_vector(15 downto 0); + sAdcDataSamples1I : out std_logic_vector(15 downto 0); + sAdcDataSamples1Q : out std_logic_vector(15 downto 0); + sDacReadyForInput : out std_logic; + sDacDataSamples0I : in std_logic_vector(15 downto 0); + sDacDataSamples0Q : in std_logic_vector(15 downto 0); + sDacDataSamples1I : in std_logic_vector(15 downto 0); + sDacDataSamples1Q : in std_logic_vector(15 downto 0); + + + -- RefClk & Timing & Sync -- + RefClk : in std_logic; + rPpsPulse : in std_logic; + rGatedPulseToPin : inout std_logic; -- straight to pin + sGatedPulseToPin : inout std_logic; -- straight to pin + sPps : out std_logic; + sPpsToIob : out std_logic; + + -- White Rabbit Timing & Sync -- + WrRefClk : in std_logic; + rWrPpsPulse : in std_logic; + rWrGatedPulseToPin : inout std_logic; -- straight to pin + sWrGatedPulseToPin : inout std_logic; -- straight to pin + aPpsSfpSel : in std_logic_vector(1 downto 0); + + + -- Debug for JESD + sAdcSync : out std_logic; + sDacSync : out std_logic; + sSysRef : out std_logic; + + -- Debug for Timing & Sync + rRpTransfer : out std_logic; + sSpTransfer : out std_logic; + rWrRpTransfer : out std_logic; + sWrSpTransfer : out std_logic + ); + +end DbCore; + + +architecture RTL of DbCore is + + component Jesd204bXcvrCore + port ( + bBusReset : in STD_LOGIC; + BusClk : in STD_LOGIC; + ReliableClk40 : in STD_LOGIC; + FpgaClk1x : in STD_LOGIC; + FpgaClk2x : in STD_LOGIC; + bFpgaClksStable : in STD_LOGIC; + bRegPortInFlat : in STD_LOGIC_VECTOR(49 downto 0); + bRegPortOutFlat : out STD_LOGIC_VECTOR(33 downto 0); + aLmkSync : out STD_LOGIC; + cSysRefFpgaLvds_p : in STD_LOGIC; + cSysRefFpgaLvds_n : in STD_LOGIC; + fSysRef : out STD_LOGIC; + CaptureSysRefClk : in STD_LOGIC; + JesdRefClk_p : in STD_LOGIC; + JesdRefClk_n : in STD_LOGIC; + bJesdRefClkPresent : out STD_LOGIC; + aAdcRx_p : in STD_LOGIC_VECTOR(3 downto 0); + aAdcRx_n : in STD_LOGIC_VECTOR(3 downto 0); + aSyncAdcOut_n : out STD_LOGIC; + aDacTx_p : out STD_LOGIC_VECTOR(3 downto 0); + aDacTx_n : out STD_LOGIC_VECTOR(3 downto 0); + aSyncDacIn_n : in STD_LOGIC; + fAdc0DataFlat : out STD_LOGIC_VECTOR(31 downto 0); + fAdc1DataFlat : out STD_LOGIC_VECTOR(31 downto 0); + fDac0DataFlat : in STD_LOGIC_VECTOR(31 downto 0); + fDac1DataFlat : in STD_LOGIC_VECTOR(31 downto 0); + fAdcDataValid : out STD_LOGIC; + fDacReadyForInput : out STD_LOGIC; + aDacSync : out STD_LOGIC; + aAdcSync : out STD_LOGIC); + end component; + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + --vhook_sigstart + signal aAdcSync: STD_LOGIC; + signal aDacSync: STD_LOGIC; + signal bClockingRegPortOut: RegPortOut_t; + signal bDbRegPortOut: RegPortOut_t; + signal bFpgaClksStable: STD_LOGIC; + signal bJesdCoreRegPortInFlat: STD_LOGIC_VECTOR(49 downto 0); + signal bJesdCoreRegPortOutFlat: STD_LOGIC_VECTOR(33 downto 0); + signal bJesdRefClkPresent: STD_LOGIC; + signal bRadioClk1xEnabled: std_logic; + signal bRadioClk2xEnabled: std_logic; + signal bRadioClk3xEnabled: std_logic; + signal bRadioClkMmcmReset: std_logic; + signal bRadioClksValid: std_logic; + signal pPsDone: std_logic; + signal pPsEn: std_logic; + signal pPsInc: std_logic; + signal PsClk: std_logic; + signal sAdc0DataFlat: STD_LOGIC_VECTOR(31 downto 0); + signal sAdc1DataFlat: STD_LOGIC_VECTOR(31 downto 0); + signal SampleClk1xOutLcl: std_logic; + signal sDac0DataFlat: STD_LOGIC_VECTOR(31 downto 0); + signal sDac1DataFlat: STD_LOGIC_VECTOR(31 downto 0); + signal sDacReadyForInputAsyncReset: STD_LOGIC; + signal sRegPps: std_logic; + signal sSysRefAsyncReset: STD_LOGIC; + signal sWrPps: std_logic; + --vhook_sigend + + signal bJesdRegPortInGrp, bSyncRegPortIn, bWrSyncRegPortIn, bRegPortIn : RegPortIn_t; + signal bJesdRegPortOut, bSyncRegPortOut, bWrSyncRegPortOut, bRegPortOut : RegPortOut_t; + + signal sDacReadyForInput_ms, sDacReadyForInputLcl, + sDacSync_ms, sDacSyncLcl, + sAdcSync_ms, sAdcSyncLcl, + sSysRef_ms, sSysRefLcl : std_logic := '0'; + + signal sAdc0Data, sAdc1Data : AdcData_t; + signal sDac0Data, sDac1Data : DacData_t; + + signal sPpsSfpSel_ms, sPpsSfpSel : std_logic_vector(1 downto 0) := (others => '0'); + signal sUseWrTdcPps : boolean := false; + signal sPpsInt, sPpsMuxed : std_logic := '0'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of sDacReadyForInput_ms : signal is "true"; + attribute ASYNC_REG of sDacReadyForInputLcl : signal is "true"; + attribute ASYNC_REG of sDacSync_ms : signal is "true"; + attribute ASYNC_REG of sDacSyncLcl : signal is "true"; + attribute ASYNC_REG of sAdcSync_ms : signal is "true"; + attribute ASYNC_REG of sAdcSyncLcl : signal is "true"; + attribute ASYNC_REG of sSysRef_ms : signal is "true"; + attribute ASYNC_REG of sSysRefLcl : signal is "true"; + attribute ASYNC_REG of sPpsSfpSel_ms : signal is "true"; + attribute ASYNC_REG of sPpsSfpSel : signal is "true"; + +begin + + bRegPortOutFlat <= Flatten(bRegPortOut); + bRegPortIn <= Unflatten(bRegPortInFlat); + + + -- Combine return RegPorts. + bRegPortOut <= bJesdRegPortOut + + bClockingRegPortOut + + bSyncRegPortOut + bWrSyncRegPortOut + + bDbRegPortOut; + + + -- Clocking : ------------------------------------------------------------------------- + -- Automatically export the Sample Clocks and only use the incoming clocks in the + -- remainder of the logic. For a single module, the clocks must be looped back + -- in at a higher level! + -- ------------------------------------------------------------------------------------ + + --vhook_e RadioClocking + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a RadioClk1x SampleClk1xOutLcl + --vhook_a RadioClk2x SampleClk2xOut + --vhook_a RadioClk3x open + RadioClockingx: entity work.RadioClocking (rtl) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRadioClkMmcmReset => bRadioClkMmcmReset, --in std_logic + bRadioClksValid => bRadioClksValid, --out std_logic + bRadioClk1xEnabled => bRadioClk1xEnabled, --in std_logic + bRadioClk2xEnabled => bRadioClk2xEnabled, --in std_logic + bRadioClk3xEnabled => bRadioClk3xEnabled, --in std_logic + pPsInc => pPsInc, --in std_logic + pPsEn => pPsEn, --in std_logic + PsClk => PsClk, --in std_logic + pPsDone => pPsDone, --out std_logic + FpgaClk_n => FpgaClk_n, --in std_logic + FpgaClk_p => FpgaClk_p, --in std_logic + RadioClk1x => SampleClk1xOutLcl, --out std_logic + RadioClk2x => SampleClk2xOut, --out std_logic + RadioClk3x => open); --out std_logic + + -- We need an internal copy of SampleClk1x for the TDC, since we don't want to try + -- and align the other DB's clock accidentally. + SampleClk1xOut <= SampleClk1xOutLcl; + + --vhook_e ClockingRegs + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a bRegPortOut bClockingRegPortOut + --vhook_a aRadioClksValid bRadioClksValid + ClockingRegsx: entity work.ClockingRegs (RTL) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRegPortOut => bClockingRegPortOut, --out RegPortOut_t + bRegPortIn => bRegPortIn, --in RegPortIn_t + pPsInc => pPsInc, --out std_logic + pPsEn => pPsEn, --out std_logic + pPsDone => pPsDone, --in std_logic + PsClk => PsClk, --out std_logic + bRadioClkMmcmReset => bRadioClkMmcmReset, --out std_logic + aRadioClksValid => bRadioClksValid, --in std_logic + bRadioClk1xEnabled => bRadioClk1xEnabled, --out std_logic + bRadioClk2xEnabled => bRadioClk2xEnabled, --out std_logic + bRadioClk3xEnabled => bRadioClk3xEnabled, --out std_logic + bJesdRefClkPresent => bJesdRefClkPresent); --in std_logic + + + + -- JESD204B : ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + bJesdRegPortInGrp <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kJesdRegGroupInDbRegs); -- 0x2000 to 0x3FFC + + -- Expand/compress the RegPort for moving through the netlist boundary. + bJesdRegPortOut <= Unflatten(bJesdCoreRegPortOutFlat); + bJesdCoreRegPortInFlat <= Flatten(bJesdRegPortInGrp); + + --vhook Jesd204bXcvrCore + --vhook_a bRegPortInFlat bJesdCoreRegPortInFlat + --vhook_a bRegPortOutFlat bJesdCoreRegPortOutFlat + --vhook_a FpgaClk1x SampleClk1x + --vhook_a FpgaClk2x SampleClk2x + --vhook_a ReliableClk40 Clk40 + --vhook_a CaptureSysRefClk SampleClk1xOutLcl + --vhook_a cSysRefFpgaLvds_p sSysRefFpgaLvds_p + --vhook_a cSysRefFpgaLvds_n sSysRefFpgaLvds_n + --vhook_a fSysRef sSysRefAsyncReset + --vhook_a fDacReadyForInput sDacReadyForInputAsyncReset + --vhook_a {^f(.*)} s$1 + Jesd204bXcvrCorex: Jesd204bXcvrCore + port map ( + bBusReset => bBusReset, --in STD_LOGIC + BusClk => BusClk, --in STD_LOGIC + ReliableClk40 => Clk40, --in STD_LOGIC + FpgaClk1x => SampleClk1x, --in STD_LOGIC + FpgaClk2x => SampleClk2x, --in STD_LOGIC + bFpgaClksStable => bFpgaClksStable, --in STD_LOGIC + bRegPortInFlat => bJesdCoreRegPortInFlat, --in STD_LOGIC_VECTOR(49:0) + bRegPortOutFlat => bJesdCoreRegPortOutFlat, --out STD_LOGIC_VECTOR(33:0) + aLmkSync => aLmkSync, --out STD_LOGIC + cSysRefFpgaLvds_p => sSysRefFpgaLvds_p, --in STD_LOGIC + cSysRefFpgaLvds_n => sSysRefFpgaLvds_n, --in STD_LOGIC + fSysRef => sSysRefAsyncReset, --out STD_LOGIC + CaptureSysRefClk => SampleClk1xOutLcl, --in STD_LOGIC + JesdRefClk_p => JesdRefClk_p, --in STD_LOGIC + JesdRefClk_n => JesdRefClk_n, --in STD_LOGIC + bJesdRefClkPresent => bJesdRefClkPresent, --out STD_LOGIC + aAdcRx_p => aAdcRx_p, --in STD_LOGIC_VECTOR(3:0) + aAdcRx_n => aAdcRx_n, --in STD_LOGIC_VECTOR(3:0) + aSyncAdcOut_n => aSyncAdcOut_n, --out STD_LOGIC + aDacTx_p => aDacTx_p, --out STD_LOGIC_VECTOR(3:0) + aDacTx_n => aDacTx_n, --out STD_LOGIC_VECTOR(3:0) + aSyncDacIn_n => aSyncDacIn_n, --in STD_LOGIC + fAdc0DataFlat => sAdc0DataFlat, --out STD_LOGIC_VECTOR(31:0) + fAdc1DataFlat => sAdc1DataFlat, --out STD_LOGIC_VECTOR(31:0) + fDac0DataFlat => sDac0DataFlat, --in STD_LOGIC_VECTOR(31:0) + fDac1DataFlat => sDac1DataFlat, --in STD_LOGIC_VECTOR(31:0) + fAdcDataValid => sAdcDataValid, --out STD_LOGIC + fDacReadyForInput => sDacReadyForInputAsyncReset, --out STD_LOGIC + aDacSync => aDacSync, --out STD_LOGIC + aAdcSync => aAdcSync); --out STD_LOGIC + + JesdDoubleSyncToNoResetSampleClk : process (SampleClk1x) + begin + if rising_edge(SampleClk1x) then + sDacReadyForInput_ms <= sDacReadyForInputAsyncReset; + sDacReadyForInputLcl <= sDacReadyForInput_ms; + -- No clock crossing here -- just reset, although the prefix declares otherwise... + sDacSync_ms <= aDacSync; + sDacSyncLcl <= sDacSync_ms; + sAdcSync_ms <= aAdcSync; + sAdcSyncLcl <= sAdcSync_ms; + sSysRef_ms <= sSysRefAsyncReset; + sSysRefLcl <= sSysRef_ms; + end if; + end process; + + -- Locals to outputs. + sDacReadyForInput <= sDacReadyForInputLcl; + sDacSync <= sDacSyncLcl; + sAdcSync <= sAdcSyncLcl; + sSysRef <= sSysRefLcl; + + -- Just combine the first two enables, since they're the ones that are used for JESD. + -- No reset crossing here, since bFpgaClksStable is only received by a no-reset domain + -- and the MGTs directly. + bFpgaClksStable <= bRadioClksValid and bRadioClk1xEnabled and bRadioClk2xEnabled; + + -- Compress/expand the flat data types from the netlist and route to top level. + sAdc0Data <= Unflatten(sAdc0DataFlat); + sAdc1Data <= Unflatten(sAdc1DataFlat); + sDac0DataFlat <= Flatten(sDac0Data); + sDac1DataFlat <= Flatten(sDac1Data); + + sAdcDataSamples0I <= sAdc0Data.I; + sAdcDataSamples0Q <= sAdc0Data.Q; + sAdcDataSamples1I <= sAdc1Data.I; + sAdcDataSamples1Q <= sAdc1Data.Q; + + sDac0Data.I <= sDacDataSamples0I; + sDac0Data.Q <= sDacDataSamples0Q; + sDac1Data.I <= sDacDataSamples1I; + sDac1Data.Q <= sDacDataSamples1Q; + + + -- Timing and Sync : ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + bSyncRegPortIn <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kTdc0OffsetsInEndpoint); -- 0x0200 + + --vhook_e TdcWrapper + --vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the + --vhook_# clock offset for this daughterboard, not the global SampleClock. + --vhook_a SampleClk SampleClk1xOutLcl + --vhook_a sPpsPulse sRegPps + TdcWrapperx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => RefClk, --in std_logic + SampleClk => SampleClk1xOutLcl, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rPpsPulse, --in std_logic + sPpsPulse => sRegPps, --out std_logic + rRpTransfer => rRpTransfer, --out std_logic + sSpTransfer => sSpTransfer, --out std_logic + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + WrTdcGen: if kInclWhiteRabbitTdc = '1' generate + bWrSyncRegPortIn <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kTdc1OffsetsInEndpoint); -- 0x0400 + + --vhook_e TdcWrapper WrTdcWrapperx + --vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the + --vhook_# clock offset for this daughterboard, not the global SampleClock. + --vhook_a bSyncRegPortIn bWrSyncRegPortIn + --vhook_a bSyncRegPortOut bWrSyncRegPortOut + --vhook_a SampleClk SampleClk1xOutLcl + --vhook_a RefClk WrRefClk + --vhook_a rPpsPulse rWrPpsPulse + --vhook_a sPpsPulse sWrPps + --vhook_a rRpTransfer rWrRpTransfer + --vhook_a sSpTransfer sWrSpTransfer + --vhook_a rGatedPulseToPin rWrGatedPulseToPin + --vhook_a sGatedPulseToPin sWrGatedPulseToPin + WrTdcWrapperx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => WrRefClk, --in std_logic + SampleClk => SampleClk1xOutLcl, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bWrSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bWrSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rWrPpsPulse, --in std_logic + sPpsPulse => sWrPps, --out std_logic + rRpTransfer => rWrRpTransfer, --out std_logic + sSpTransfer => sWrSpTransfer, --out std_logic + rGatedPulseToPin => rWrGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sWrGatedPulseToPin); --inout std_logic + end generate WrTdcGen; + + WrTdcNotGen: if kInclWhiteRabbitTdc = '0' generate + bWrSyncRegPortOut <= kRegPortOutZero; + sWrPps <= '0'; + rWrRpTransfer <= '0'; + sWrSpTransfer <= '0'; + rWrGatedPulseToPin <= '0'; + sWrGatedPulseToPin <= '0'; + end generate WrTdcNotGen; + + -- Mux the output PPS based on the SFP selection bits. Encoding is one-hot, with zero + -- also a valid state. Regardless of whether the user selects SFP0 or SFP1 as the time + -- source, there is only one White Rabbit TDC, so '01' and '10' are equivalent. + -- '00': Use the PPS output from the "regular" TDC. + -- '01': Use the PPS output from the "white rabbit" TDC. + -- '10': Use the PPS output from the "white rabbit" TDC. + PpsOutputMux : process (SampleClk1xOutLcl) + begin + if rising_edge(SampleClk1xOutLcl) then + -- Double-sync the control bits to the Sample Clock domain. + sPpsSfpSel_ms <= aPpsSfpSel; + sPpsSfpSel <= sPpsSfpSel_ms; + + -- OR the control bits together to produce a single override enable for the WR TDC. + sUseWrTdcPps <= to_boolean(sPpsSfpSel(0) or sPpsSfpSel(1)); + + -- Flop the outputs. One flop for the PPS output IOB, the other for use internally. + sPpsInt <= sPpsMuxed; + end if; + end process PpsOutputMux; + + sPpsMuxed <= sWrPps when sUseWrTdcPps else sRegPps; + sPps <= sPpsInt; + sPpsToIob <= sPpsMuxed; -- No added flop here since there's an IOB outside this module. + + -- Daughterboard Control : ------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + --vhook_e DaughterboardRegs + --vhook_# Tying this low is safe because the sync reset is used inside DaughterboardRegs. + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a bRegPortOut bDbRegPortOut + --vhook_a kDbId std_logic_vector(to_unsigned(16#150#,16)) + DaughterboardRegsx: entity work.DaughterboardRegs (RTL) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRegPortOut => bDbRegPortOut, --out RegPortOut_t + bRegPortIn => bRegPortIn, --in RegPortIn_t + kDbId => std_logic_vector(to_unsigned(16#150#,16)), --in std_logic_vector(15:0) + kSlotId => kSlotId); --in std_logic + + +end RTL; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore.edf b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore.edf new file mode 100644 index 000000000..27619d2a0 Binary files /dev/null and b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore.edf differ diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore_stub.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore_stub.vhd new file mode 100644 index 000000000..84c461d26 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore_stub.vhd @@ -0,0 +1,56 @@ +-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016 +-- Date : Wed Jan 10 10:53:33 2018 +-- Host : djepson-lt running 64-bit major release (build 9200) +-- Command : write_vhdl -mode synth_stub -force -file ./Jesd204bXcvrCore_stub.vhd +-- Design : Jesd204bXcvrCore +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Jesd204bXcvrCore is + Port ( + bBusReset : in STD_LOGIC; + BusClk : in STD_LOGIC; + ReliableClk40 : in STD_LOGIC; + FpgaClk1x : in STD_LOGIC; + FpgaClk2x : in STD_LOGIC; + bFpgaClksStable : in STD_LOGIC; + bRegPortInFlat : in STD_LOGIC_VECTOR ( 49 downto 0 ); + bRegPortOutFlat : out STD_LOGIC_VECTOR ( 33 downto 0 ); + aLmkSync : out STD_LOGIC; + cSysRefFpgaLvds_p : in STD_LOGIC; + cSysRefFpgaLvds_n : in STD_LOGIC; + fSysRef : out STD_LOGIC; + CaptureSysRefClk : in STD_LOGIC; + JesdRefClk_p : in STD_LOGIC; + JesdRefClk_n : in STD_LOGIC; + bJesdRefClkPresent : out STD_LOGIC; + aAdcRx_p : in STD_LOGIC_VECTOR ( 3 downto 0 ); + aAdcRx_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); + aSyncAdcOut_n : out STD_LOGIC; + aDacTx_p : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aDacTx_n : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aSyncDacIn_n : in STD_LOGIC; + fAdc0DataFlat : out STD_LOGIC_VECTOR ( 31 downto 0 ); + fAdc1DataFlat : out STD_LOGIC_VECTOR ( 31 downto 0 ); + fDac0DataFlat : in STD_LOGIC_VECTOR ( 31 downto 0 ); + fDac1DataFlat : in STD_LOGIC_VECTOR ( 31 downto 0 ); + fAdcDataValid : out STD_LOGIC; + fDacReadyForInput : out STD_LOGIC; + aDacSync : out STD_LOGIC; + aAdcSync : out STD_LOGIC + ); + +end Jesd204bXcvrCore; + +architecture stub of Jesd204bXcvrCore is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "bBusReset,BusClk,ReliableClk40,FpgaClk1x,FpgaClk2x,bFpgaClksStable,bRegPortInFlat[49:0],bRegPortOutFlat[33:0],aLmkSync,cSysRefFpgaLvds_p,cSysRefFpgaLvds_n,fSysRef,CaptureSysRefClk,JesdRefClk_p,JesdRefClk_n,bJesdRefClkPresent,aAdcRx_p[3:0],aAdcRx_n[3:0],aSyncAdcOut_n,aDacTx_p[3:0],aDacTx_n[3:0],aSyncDacIn_n,fAdc0DataFlat[31:0],fAdc1DataFlat[31:0],fDac0DataFlat[31:0],fDac1DataFlat[31:0],fAdcDataValid,fDacReadyForInput,aDacSync,aAdcSync"; +begin +end; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgClockingRegMap.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgClockingRegMap.vhd new file mode 100644 index 000000000..03b95c100 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgClockingRegMap.vhd @@ -0,0 +1,107 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgClockingRegMap.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgClockingRegMap is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- RadioClkMmcm : 0x20 (ClockingRegs.vhd) + -- PhaseShiftControl : 0x24 (ClockingRegs.vhd) + -- RadioClkEnables : 0x28 (ClockingRegs.vhd) + -- MgtRefClkStatus : 0x30 (ClockingRegs.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group ClockingRegs +--=============================================================================== + + -- RadioClkMmcm Register (from ClockingRegs.vhd) + constant kRadioClkMmcm : integer := 16#20#; -- Register Offset + constant kRadioClkMmcmSize: integer := 32; -- register width in bits + constant kRadioClkMmcmMask : std_logic_vector(31 downto 0) := X"00000013"; + constant kRadioClkMmcmResetSetSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetSetMsb : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetSet : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetClearSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmResetClearMsb : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmResetClear : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmLockedSize : integer := 1; --RadioClkMmcm:RadioClkMmcmLocked + constant kRadioClkMmcmLockedMsb : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked + constant kRadioClkMmcmLocked : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked + + -- PhaseShiftControl Register (from ClockingRegs.vhd) + constant kPhaseShiftControl : integer := 16#24#; -- Register Offset + constant kPhaseShiftControlSize: integer := 32; -- register width in bits + constant kPhaseShiftControlMask : std_logic_vector(31 downto 0) := X"10010011"; + constant kPsIncSize : integer := 1; --PhaseShiftControl:PsInc + constant kPsIncMsb : integer := 0; --PhaseShiftControl:PsInc + constant kPsInc : integer := 0; --PhaseShiftControl:PsInc + constant kPsDecSize : integer := 1; --PhaseShiftControl:PsDec + constant kPsDecMsb : integer := 4; --PhaseShiftControl:PsDec + constant kPsDec : integer := 4; --PhaseShiftControl:PsDec + constant kPsEnabledForFdbClkSize : integer := 1; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsEnabledForFdbClkMsb : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsEnabledForFdbClk : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsDoneSize : integer := 1; --PhaseShiftControl:PsDone + constant kPsDoneMsb : integer := 28; --PhaseShiftControl:PsDone + constant kPsDone : integer := 28; --PhaseShiftControl:PsDone + + -- RadioClkEnables Register (from ClockingRegs.vhd) + constant kRadioClkEnables : integer := 16#28#; -- Register Offset + constant kRadioClkEnablesSize: integer := 32; -- register width in bits + constant kRadioClkEnablesMask : std_logic_vector(31 downto 0) := X"00000111"; + constant kRadioClk1xEnabledSize : integer := 1; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk1xEnabledMsb : integer := 0; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk1xEnabled : integer := 0; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk2xEnabledSize : integer := 1; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk2xEnabledMsb : integer := 4; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk2xEnabled : integer := 4; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk3xEnabledSize : integer := 1; --RadioClkEnables:RadioClk3xEnabled + constant kRadioClk3xEnabledMsb : integer := 8; --RadioClkEnables:RadioClk3xEnabled + constant kRadioClk3xEnabled : integer := 8; --RadioClkEnables:RadioClk3xEnabled + + -- MgtRefClkStatus Register (from ClockingRegs.vhd) + constant kMgtRefClkStatus : integer := 16#30#; -- Register Offset + constant kMgtRefClkStatusSize: integer := 32; -- register width in bits + constant kMgtRefClkStatusMask : std_logic_vector(31 downto 0) := X"00000001"; + constant kJesdRefClkPresentSize : integer := 1; --MgtRefClkStatus:JesdRefClkPresent + constant kJesdRefClkPresentMsb : integer := 0; --MgtRefClkStatus:JesdRefClkPresent + constant kJesdRefClkPresent : integer := 0; --MgtRefClkStatus:JesdRefClkPresent + +end package; + +package body PkgClockingRegMap is + + -- function kRadioClkMmcmRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kPhaseShiftControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRadioClkEnablesRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMgtRefClkStatusRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgDaughterboardRegMap.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgDaughterboardRegMap.vhd new file mode 100644 index 000000000..06708cde3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgDaughterboardRegMap.vhd @@ -0,0 +1,56 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgDaughterboardRegMap.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgDaughterboardRegMap is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- DaughterboardId : 0x630 (DaughterboardRegs.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group StaticControl +--=============================================================================== + + -- DaughterboardId Register (from DaughterboardRegs.vhd) + constant kDaughterboardId : integer := 16#630#; -- Register Offset + constant kDaughterboardIdSize: integer := 32; -- register width in bits + constant kDaughterboardIdMask : std_logic_vector(31 downto 0) := X"0001ffff"; + constant kDbIdValSize : integer := 16; --DaughterboardId:DbIdVal + constant kDbIdValMsb : integer := 15; --DaughterboardId:DbIdVal + constant kDbIdVal : integer := 0; --DaughterboardId:DbIdVal + constant kSlotIdValSize : integer := 1; --DaughterboardId:SlotIdVal + constant kSlotIdValMsb : integer := 16; --DaughterboardId:SlotIdVal + constant kSlotIdVal : integer := 16; --DaughterboardId:SlotIdVal + +end package; + +package body PkgDaughterboardRegMap is + + -- function kDaughterboardIdRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgJesdConfig.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgJesdConfig.vhd new file mode 100644 index 000000000..c0f5244b5 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgJesdConfig.vhd @@ -0,0 +1,234 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgJesdConfig.vhd +-- Author: National Instruments +-- Original Project: NI 5840 +-- Date: 11 March 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: JESD204B setup constants and functions. These constants are shared +-- between RX and TX JESD cores. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + + +package PkgJesdConfig is + + -- "JESD" in ASCII - with the core number 0 or 1 on the LSb. + constant kJesdSignature : std_logic_vector(31 downto 0) := x"4a455344"; + + -- Register endpoints + constant kJesdDrpRegsInEndpoint : RegOffset_t := (kOffset => 16#0800#, -- 0x2800 to + kWidth => 16#0800#); -- 0x2FFF + + -- Selects the UsrClk2 for the transceivers. For 64-bit wide transceivers, the + -- UsrClk = 2*UserClk2 frequency. For 32-bit wide transceivers, UsrClk = UserClk2 + -- frequency. This is a generalization, the clock ratio should be confirmed based on + -- the transceiver configuration. + -- The N310 transceivers use the single rate reference, hence = false. + constant kDoubleRateUsrClk : boolean := false; + + -- For the N310, all lanes are in one quad and we use the QPLL. + constant kJesdUseQpll : boolean := true; + + constant kAdcDataWidth : integer := 16; -- ADC data width in bits + constant kDacDataWidth : integer := 16; -- DAC data width in bits + constant kSamplesPerCycle : integer := 1; -- Number of samples per SampleClk1x + + constant kGtxDrpAddrWidth : natural := 9; + constant kQpllDrpAddrWidth : natural := 8; + -- Max supported number of lanes + constant kMaxNumLanes : natural := 4; + -- Max supported number of quads (normally there is 1 quad per 4 lanes but disconnect + -- the definitions to allow quad sharing) + constant kMaxNumQuads : natural := 1; + + + -- JESD shared setup - LMFS = 4421, HD = 0 + constant kNumLanes : natural := 4; -- L + constant kNumConvs : positive := 4; -- M + constant kOctetsPerFrame : natural := 2; -- F + constant kDacJesdSamplesPerCycle : integer := 1; -- S + constant kOctetsPerLane : natural := 2; -- MGT data is kOctetsPerLane*8 = 16 bits wide + constant kNumQuads : natural := kNumLanes/4; -- 4 lanes per quad + constant kHighDensity : boolean := false; -- HD + constant kConvResBits : positive := kDacDataWidth-2; -- Converter resolution in bits + constant kConvSampleBits : positive := kDacDataWidth; -- Sample Length in bits + constant kInitLaneAlignCnt : positive := 4; + constant kFramesPerMulti : natural := 20; -- K + + -- In the N310 case we are one SPC, so this value is simply the number of frames + -- (samples) per multiframe. + constant kUserClksPerMulti : integer := kFramesPerMulti; + + + type NaturalVector is array ( natural range <>) of natural; + + -- The PCB connections are as follows: + -- + -- Transceiver MGT Channel ADC Lane DAC Lane + -- *********** *********** ******** ******** + -- GT0: X0Y8 0 0 0 + -- GT1: X0Y9 1 1 1 + -- GT2: X0Y10 2 2 2 + -- GT3: X0Y11 3 3 3 + constant kRxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- MGT => ADC (in above table) + 0 => 0, + 1 => 1, + 2 => 2, + 3 => 3 + ); + + constant kTxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- MGT => DAC lane + 0 => 0, + 1 => 1, + 2 => 2, + 3 => 3 + ); + + constant kLaneToQuadMap : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- All lanes are in one quad + 0 => 0, + 1 => 0, + 2 => 0, + 3 => 0 + ); + + + -- The master transceiver channel for channel bonding. E(kMasterBondingChannel) + -- must have the highest value decrementing to b"000" for that last channels to bond. + constant kMasterBondingChannel : integer := 1; + + -- Channel bonding occurs when a master detects a K-char sequence and aligns its + -- internal FIFO to the start of this sequence. A signal is then generated to other + -- slave transceivers that cause them to bond to the sequence - this bonding signal is + -- cascaded from master to slave to slave to slave, etc where each slave must know how + -- many levels to the master there are. The last slave to bond must be at level b"000" + -- and the master is at the highest level; the number of levels in the sequence is + -- governed by the size of the transceiver FIFO (see the Xilinx user guides for more + -- information). + type BondLevels_t is array(0 to kNumLanes - 1) of std_logic_vector(2 downto 0); + constant kBondLevel : BondLevels_t := ( + 0 => b"000", -- Control from 1 + 1 => b"001", -- Master + 2 => b"000", -- Control from 1 + 3 => b"000" -- Control from 1 + ); + + -- Option to pipeline stages to improve timing, if needed + constant kPipelineDetectCharsStage : boolean := false; + constant kPipelineCharReplStage : boolean := false; + + + -- ADC & DAC Data Types + -- + + -- ADC Words from JESD204B RX Core. The array is 4 elements wide to accommodate the + -- I & Q elements from both RX channels. + subtype AdcWord_t is std_logic_vector(kAdcDataWidth - 1 downto 0); + type AdcWordArray_t is array(4 - 1 downto 0) of AdcWord_t; + + -- Data types for manipulation and presentation to outside world. + type AdcData_t is record + I : std_logic_vector(kAdcDataWidth - 1 downto 0); + Q : std_logic_vector(kAdcDataWidth - 1 downto 0); + end record; + + type DacData_t is record + I : std_logic_vector(kDacDataWidth - 1 downto 0); + Q : std_logic_vector(kDacDataWidth - 1 downto 0); + end record; + + + -- Flattened data types for passing into and out of pre-synthesized components. + subtype AdcDataFlat_t is std_logic_vector(2*kAdcDataWidth - 1 downto 0); + subtype DacDataFlat_t is std_logic_vector(2*kDacDataWidth - 1 downto 0); + + -- Functions to convert to/from types defined above. + function Flatten (AdcData : AdcData_t) return AdcDataFlat_t; + function Unflatten(AdcData : AdcDataFlat_t) return AdcData_t; + + function Flatten (DacData : DacData_t) return DacDataFlat_t; + function Unflatten(DacData : DacDataFlat_t) return DacData_t; + + +end package; + + +package body PkgJesdConfig is + + + + + + -- Flattens AdcData_t to AdcDataFlat_t + function Flatten (AdcData : AdcData_t) return AdcDataFlat_t + is + variable ReturnVar : AdcDataFlat_t; + begin + ReturnVar := (others => '0'); + -- MSB is I + ReturnVar := AdcData.I & AdcData.Q; + return ReturnVar; + end function Flatten; + + + -- UnFlattens AdcDataFlat_t to AdcData_t + function Unflatten(AdcData : AdcDataFlat_t) return AdcData_t + is + variable ReturnVar : AdcData_t; + begin + ReturnVar := (others => (others => '0')); + -- MSB is I + ReturnVar.I := AdcData(2*kAdcDataWidth - 1 downto kAdcDataWidth); + ReturnVar.Q := AdcData( kAdcDataWidth - 1 downto 0); + return ReturnVar; + end function Unflatten; + + + + -- Flattens DacData_t to DacDataFlat_t + function Flatten (DacData : DacData_t) return DacDataFlat_t + is + variable ReturnVar : DacDataFlat_t; + begin + ReturnVar := (others => '0'); + -- MSB is I + ReturnVar := DacData.I & DacData.Q; + return ReturnVar; + end function Flatten; + + + -- UnFlattens DacDataFlat_t to DacData_t + function Unflatten(DacData : DacDataFlat_t) return DacData_t + is + variable ReturnVar : DacData_t; + begin + ReturnVar := (others => (others => '0')); + -- MSB is I + ReturnVar.I := DacData(2*kDacDataWidth - 1 downto kDacDataWidth); + ReturnVar.Q := DacData( kDacDataWidth - 1 downto 0); + return ReturnVar; + end function Unflatten; + + + + + +end package body; \ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgMgPersonality.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgMgPersonality.vhd new file mode 100644 index 000000000..904653a8e --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgMgPersonality.vhd @@ -0,0 +1,61 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgMgPersonality.vhd +-- Author: National Instruments +-- Original Project: N310 +-- Date: 13 April 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: This package contains constants and helpful functions that enable +-- the FPGA to be compiled with different features. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + + +package PkgMgPersonality is + + + -- RegPort Address Definitions : ------------------------------------------------------ + -- + -- DB Regs ... + -- + -- Clocking Offset: 0x 000 Width: 0x 200 + -- Tdco0 Offset: 0x 200 Width: 0x 200 + -- Tdco1 Offset: 0x 400 Width: 0x 200 + -- Daughterboard Ctrl Offset: 0x 600 Width: 0x 200 + -- Total: 0x2000 + -- JESD 2x - A Offset: 0x2000 Width: 0x1000 + -- JESD 2x - B Offset: 0x3000 Width: 0x1000 + -- Total: 0x4000 + -- Total: 0x8000 for two DBs + -- ------------------------------------------------------------------------------------ + + -- A single RegPort runs to the JESD204B Core. + constant kJesdRegGroupInDbRegs : RegOffset_t := (kOffset => 16#2000#, -- 0x2000 to + kWidth => 16#1000#); -- 0x2FFF + + -- DB Regs : -------------------------------------------------------------------------- + constant kClockingOffsetInEndpoint : RegOffset_t := (kOffset => 16#0000#, -- 0x0000 to + kWidth => 16#0200#); -- 0x01FF + constant kTdc0OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0200#, -- 0x0200 to + kWidth => 16#0200#); -- 0x03FF + constant kTdc1OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0400#, -- 0x0400 to + kWidth => 16#0200#); -- 0x05FF + constant kDaughterboardOffsetInEndpoint : RegOffset_t := (kOffset => 16#0600#, -- 0x0600 to + kWidth => 16#0200#); -- 0x07FF + + + + +end package PkgMgPersonality; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/RadioClocking.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/RadioClocking.vhd new file mode 100644 index 000000000..ee0da9f84 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/RadioClocking.vhd @@ -0,0 +1,304 @@ +------------------------------------------------------------------------------- +-- +-- File: RadioClocking.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 22 February 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Instantiates a MMCM to produce 1x, 2x, and 3x versions of the Radio Clock +-- coming from the FPGA input pin. Handles all the buffering for the input clock. +-- Additionally allows the clocks to be turned on and off, and phase shifted. +-- +-- NOTE: This module hard-codes the MMCM settings for a SPECIFIC clock rate! +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library unisim; + use unisim.vcomponents.all; + + +entity RadioClocking is + port ( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + + -- Should be a always-on clock + BusClk : in std_logic; + + -- Sync reset to the RadioClkMmcm. + bRadioClkMmcmReset : in std_logic; + + -- Locked indication from the RadioClkMmcm in BusClk and aReset domains. + bRadioClksValid : out std_logic; + + bRadioClk1xEnabled : in std_logic; + bRadioClk2xEnabled : in std_logic; + bRadioClk3xEnabled : in std_logic; + + -- Phase shift interface for the RadioClkMmcm. PsClk must be <= 200 MHz. + pPsInc : in std_logic; + pPsEn : in std_logic; + PsClk : in std_logic; + pPsDone : out std_logic; + + -- Straight from pins. Buffer included in here. + FpgaClk_n : in std_logic; + FpgaClk_p : in std_logic; + + RadioClk1x : out std_logic; + RadioClk2x : out std_logic; + RadioClk3x : out std_logic + + ); +end RadioClocking; + + +architecture rtl of RadioClocking is + + --vhook_sigstart + signal RadioClk1xLcl: std_logic; + signal RadioClk1xPll: std_logic; + signal RadioClk2xLcl: std_logic; + signal RadioClk2xPll: std_logic; + signal RadioClk3xLcl: std_logic; + signal RadioClk3xPll: std_logic; + --vhook_sigend + + signal RadioClkMmcmFeedbackIn, + RadioClkMmcmFeedbackOut, + FpgaClkSE, + aRadioClkMmcmLocked : std_logic; + + signal bRadioClkMmcmLocked_ms, + bRadioClkMmcmLocked, + bEnableRadioClkBufgOutputs, + bEnableRadioClk1xBufgOutput, + bEnableRadioClk2xBufgOutput, + bEnableRadioClk3xBufgOutput : std_logic := '0'; + + signal aRadioClkMmcmResetInternal : std_logic := '1'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of bRadioClkMmcmLocked_ms : signal is "true"; + attribute ASYNC_REG of bRadioClkMmcmLocked : signal is "true"; + +begin + + -- Radio Clock Buffering : ------------------------------------------------------------ + -- + -- ------------------------------------------------------------------------------------ + --vhook_i IBUFDS FpgaClkIbufg hidegeneric=true + --vhook_a I FpgaClk_p + --vhook_a IB FpgaClk_n + --vhook_a O FpgaClkSE + FpgaClkIbufg: IBUFDS + port map ( + O => FpgaClkSE, --out std_ulogic + I => FpgaClk_p, --in std_ulogic + IB => FpgaClk_n); --in std_ulogic + + ResetDelay : process(aReset, BusClk) + begin + if aReset then + aRadioClkMmcmResetInternal <= '1'; + elsif rising_edge(BusClk) then + if bReset then + aRadioClkMmcmResetInternal <= '1'; + else + -- Delay by 1 to allow the BUFGs to turn off before the MMCM is reset. + aRadioClkMmcmResetInternal <= bRadioClkMmcmReset; + end if; + end if; + end process ResetDelay; + + + RadioClkMmcm: MMCME2_ADV + generic map( + COMPENSATION => "ZHOLD", + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 6.000, -- Feedback + CLKOUT0_DIVIDE_F => 6.000, -- Data Clock 1x, RadioClk1xPll + CLKOUT1_DIVIDE => 3, -- Data Clock 2x, RadioClk2xPll + CLKOUT2_DIVIDE => 2, -- Data Clock 3x, RadioClk3xPll + CLKOUT3_DIVIDE => 1, -- unused + CLKOUT4_DIVIDE => 1, -- unused + CLKOUT5_DIVIDE => 1, -- unused + CLKOUT6_DIVIDE => 1, -- unused + CLKFBOUT_PHASE => 0.000, -- Feedback + CLKOUT0_PHASE => 0.000, -- Data Clock 1x + CLKOUT1_PHASE => 0.000, -- Data Clock 2x + CLKOUT2_PHASE => 0.000, -- Data Clock 3x + CLKOUT3_PHASE => 0.000, -- unused + CLKOUT4_PHASE => 0.000, -- unused + CLKOUT5_PHASE => 0.000, -- unused + CLKOUT6_PHASE => 0.000, -- unused + CLKOUT0_DUTY_CYCLE => 0.500, + CLKOUT1_DUTY_CYCLE => 0.500, + CLKOUT2_DUTY_CYCLE => 0.500, + CLKOUT3_DUTY_CYCLE => 0.500, + CLKOUT4_DUTY_CYCLE => 0.500, + CLKOUT5_DUTY_CYCLE => 0.500, + CLKOUT6_DUTY_CYCLE => 0.500, + DIVCLK_DIVIDE => 1, + REF_JITTER1 => 0.010, + CLKIN1_PERIOD => 6.510, -- 153.6 MHz max + CLKFBOUT_USE_FINE_PS => true, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_USE_FINE_PS => false, + STARTUP_WAIT => false, + CLKOUT4_CASCADE => false) + port map ( + CLKINSEL => '1', + CLKIN1 => FpgaClkSE, + CLKIN2 => '0', + CLKFBIN => RadioClkMmcmFeedbackIn, + RST => aRadioClkMmcmResetInternal, + PWRDWN => '0', + DADDR => (others => '0'), + DI => (others => '0'), + DWE => '0', + DEN => '0', + DCLK => '0', + DO => open, + DRDY => open, + PSINCDEC => pPsInc, + PSEN => pPsEn, + PSCLK => PsClk, + PSDONE => pPsDone, + CLKOUT0 => RadioClk1xPll, + CLKOUT0B => open, + CLKOUT1 => RadioClk2xPll, + CLKOUT1B => open, + CLKOUT2 => RadioClk3xPll, + CLKOUT2B => open, + CLKOUT3 => open, + CLKOUT3B => open, + CLKOUT4 => open, + CLKOUT5 => open, + CLKOUT6 => open, + CLKFBOUT => RadioClkMmcmFeedbackOut, + CLKFBOUTB => open, + LOCKED => aRadioClkMmcmLocked, + CLKINSTOPPED => open, + CLKFBSTOPPED => open); + + RadioClkMmcmFeedbackBufg: BUFG + port map ( + I => RadioClkMmcmFeedbackOut, + O => RadioClkMmcmFeedbackIn + ); + + + -- Only enable the WRAPBUFGs when the MMCM is locked. If the MMCM is ever placed in + -- reset, we turn off the clocks one cycle before the asynchronous version + -- (aRadioClkMmcmResetInternal) reaches the MMCM inputs in order to prevent + -- output glitches. + CombineEnablesForBuffers : process(aReset, BusClk) + begin + if aReset then + bRadioClkMmcmLocked_ms <= '0'; + bRadioClkMmcmLocked <= '0'; + bEnableRadioClk1xBufgOutput <= '0'; + bEnableRadioClk2xBufgOutput <= '0'; + bEnableRadioClk3xBufgOutput <= '0'; + bEnableRadioClkBufgOutputs <= '0'; + elsif rising_edge(BusClk) then + if bReset then + bRadioClkMmcmLocked_ms <= '0'; + bRadioClkMmcmLocked <= '0'; + bEnableRadioClk1xBufgOutput <= '0'; + bEnableRadioClk2xBufgOutput <= '0'; + bEnableRadioClk3xBufgOutput <= '0'; + bEnableRadioClkBufgOutputs <= '0'; + else + bRadioClkMmcmLocked_ms <= aRadioClkMmcmLocked; + bRadioClkMmcmLocked <= bRadioClkMmcmLocked_ms; + + bEnableRadioClkBufgOutputs <= bRadioClkMmcmLocked and + not bRadioClkMmcmReset; + bEnableRadioClk1xBufgOutput <= bRadioClk1xEnabled and bEnableRadioClkBufgOutputs; + bEnableRadioClk2xBufgOutput <= bRadioClk2xEnabled and bEnableRadioClkBufgOutputs; + bEnableRadioClk3xBufgOutput <= bRadioClk3xEnabled and bEnableRadioClkBufgOutputs; + end if; + end if; + end process CombineEnablesForBuffers; + + bRadioClksValid <= bEnableRadioClkBufgOutputs; + + --vhook_e WrapBufg RadioClk1xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk1xPll + --vhook_a aCe bEnableRadioClk1xBufgOutput + --vhook_a ClkOut RadioClk1xLcl + RadioClk1xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk1xPll, --in std_logic + aCe => bEnableRadioClk1xBufgOutput, --in std_logic + ClkOut => RadioClk1xLcl); --out std_logic + + --vhook_e WrapBufg RadioClk2xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk2xPll + --vhook_a aCe bEnableRadioClk2xBufgOutput + --vhook_a ClkOut RadioClk2xLcl + RadioClk2xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk2xPll, --in std_logic + aCe => bEnableRadioClk2xBufgOutput, --in std_logic + ClkOut => RadioClk2xLcl); --out std_logic + + --vhook_e WrapBufg RadioClk3xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk3xPll + --vhook_a aCe bEnableRadioClk3xBufgOutput + --vhook_a ClkOut RadioClk3xLcl + RadioClk3xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk3xPll, --in std_logic + aCe => bEnableRadioClk3xBufgOutput, --in std_logic + ClkOut => RadioClk3xLcl); --out std_logic + + + -- Assign outputs from locals. + RadioClk1x <= RadioClk1xLcl; + RadioClk2x <= RadioClk2xLcl; + RadioClk3x <= RadioClk3xLcl; + + + +end rtl; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_timing.xdc b/fpga/usrp3/top/n3xx/dboards/mg/db_timing.xdc new file mode 100644 index 000000000..142ba9ab4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_timing.xdc @@ -0,0 +1,347 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Timing analysis is performed in "/n3xx/dboards/mg/doc/mg_timing.xlsx". See +# the spreadsheet for more details and explanations. + +#******************************************************************************* +## Daughterboard Clocks + +# 122.88, 125, and 153.6 MHz Sample Clocks are allowable. Constrain the paths to the max +# rate in order to support all rates in a single FPGA image. +set SAMPLE_CLK_PERIOD 6.510 +create_clock -name fpga_clk_a -period $SAMPLE_CLK_PERIOD [get_ports DBA_FPGA_CLK_P] +create_clock -name fpga_clk_b -period $SAMPLE_CLK_PERIOD [get_ports DBB_FPGA_CLK_P] +create_clock -name mgt_clk_dba -period $SAMPLE_CLK_PERIOD [get_ports USRPIO_A_MGTCLK_P] +create_clock -name mgt_clk_dbb -period $SAMPLE_CLK_PERIOD [get_ports USRPIO_B_MGTCLK_P] + +# The Radio Clocks coming from the DBs are synchronized together (at the ADCs) to a +# typical value of less than 100ps. To give ourselves and Vivado some margin, we claim +# here that the DB-B Radio Clock can arrive 500ps before or after the DB-A clock at +# the FPGA (note that the trace lengths of the Radio Clocks coming from the DBs to the +# FPGA are about 0.5" different, thereby incurring ~80ps of additional skew at the FPGA). +# There is one spot in the FPGA where we cross domains between the DB-A and +# DB-B clock, so we must ensure that Vivado can analyze that path safely. +set FPGA_CLK_EARLY -0.5 +set FPGA_CLK_LATE 0.5 +set_clock_latency -source -early $FPGA_CLK_EARLY [get_clocks fpga_clk_b] +set_clock_latency -source -late $FPGA_CLK_LATE [get_clocks fpga_clk_b] + +# Virtual clocks for constraining I/O (used below) +create_clock -name fpga_clk_a_v -period $SAMPLE_CLK_PERIOD +create_clock -name fpga_clk_b_v -period $SAMPLE_CLK_PERIOD + +# The set_clock_latency constraints set on fpga_clk_b are problematic when used with +# I/O timing, since the analyzer gives us a double-hit on the latency. One workaround +# (used here) is to simply swap the early and late times for the virtual clock so that +# it cancels out the source latency during analysis. I tested this by setting the +# early and late numbers to zero and then their actual value, running timing reports +# on each. The slack report matches for both cases, showing that the reversed early/late +# numbers on the virtual clock zero out the latency effects on the actual clock. +# +# Note this is not a problem for the fpga_clk_a, since no latency is added. So only apply +# it to fpga_clk_b_v. +set_clock_latency -source -early $FPGA_CLK_LATE [get_clocks fpga_clk_b_v] +set_clock_latency -source -late $FPGA_CLK_EARLY [get_clocks fpga_clk_b_v] + + + +#******************************************************************************* +## Aliases for auto-generated clocks + +create_generated_clock -name radio_clk_fb [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}] +create_generated_clock -name radio_clk [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT0}] +create_generated_clock -name radio_clk_2x [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT1}] + +create_generated_clock -name radio_clk_b_fb [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}] +create_generated_clock -name radio_clk_b [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT0}] +create_generated_clock -name radio_clk_b_2x [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT1}] + + + +#******************************************************************************* +## Generated clocks for output busses to the daughterboard +# +# These clock definitions need to come above the set_clock_groups commands below to work! + +# Define clocks on the PL SPI clock output pins for both DBs. Actual divider values are +# set by SW at run-time. Divider values are 123, 125, or 154 based on what radio clock +# rate is set. To be ultra-conservative (which still provides 10s of ns of slack), we +# set an over-constrained divider value of 50. +set PL_SPI_DIVIDE_VAL 50 +set PL_SPI_CLK_A [get_ports DBA_CPLD_PL_SPI_SCLK] +create_generated_clock -name pl_spi_clk_a \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_A]/C] \ + -divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_A +set PL_SPI_CLK_B [get_ports DBB_CPLD_PL_SPI_SCLK] +create_generated_clock -name pl_spi_clk_b \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_B]/C] \ + -divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_B + +# Define one of the outputs of each bus as a clock (even though it isn't a clock). This +# allows us to constrain the overall bus skew with respect to one of the bus outputs. +# See the remainder of this constraint below for more details. +set DSA_CLK [get_ports {DBA_CH1_RX_DSA_DATA[0]}] +create_generated_clock -name dsa_bus_clk \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $DSA_CLK]/C] \ + -divide_by 2 $DSA_CLK + +set ATR_CLK [get_ports DBA_ATR_RX_1] +create_generated_clock -name atr_bus_clk \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $ATR_CLK]/C] \ + -divide_by 2 $ATR_CLK + +# Interface Unused +# set MGPIO_CLK [get_ports DBA_MYK_GPIO_0] +# create_generated_clock -name myk_gpio_bus_clk \ + # -source [get_pins [all_fanin -flat -only_cells -startpoints_only [get_ports $MGPIO_CLK]]/C] \ + # -divide_by 2 [get_ports $MGPIO_CLK] + + + +#******************************************************************************* +## Asynchronous clock groups + +# MGT reference clocks are also async to everything. +set_clock_groups -asynchronous -group [get_clocks mgt_clk_dba -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks mgt_clk_dbb -include_generated_clocks] + +# fpga_clk_a and fpga_clk_b are related to one another after synchronization. +# However, we do need to declare that these clocks (both a and b) and their children +# are async to the remainder of the design. Use the wildcard at the end to grab the +# virtual clock as well as the real ones. +set_clock_groups -asynchronous -group [get_clocks {fpga_clk_a* fpga_clk_b*} -include_generated_clocks] + + + +#******************************************************************************* +## PS SPI: since these lines all come from the PS and I don't have access to the +# driving clock (or anything for that matter), I'm left with constraining the maximum +# and minimum delay on these lines, per a Xilinx AR: +# https://www.xilinx.com/support/answers/62122.html +set CPLD_SPI_OUTS [get_ports {DB*_CPLD_PS_SPI_SCLK \ + DB*_CPLD_PS_SPI_SDI \ + DB*_CPLD_PS_SPI_LE \ + DB*_CPLD_PS_SPI_ADDR[0] \ + DB*_CPLD_PS_SPI_ADDR[1]}] + +set_max_delay 12.0 -to $CPLD_SPI_OUTS +set_min_delay 3.0 -to $CPLD_SPI_OUTS + +set MYK_SPI_OUTS [get_ports {DB*_MYK_SPI_SCLK \ + DB*_MYK_SPI_SDIO \ + DB*_MYK_SPI_CS_n}] + +set_max_delay 14.0 -to $MYK_SPI_OUTS +set_min_delay 3.0 -to $MYK_SPI_OUTS + +# report_timing -to $CPLD_SPI_OUTS -max_paths 20 -delay_type min_max -name CpldSpiOutTiming +# report_timing -to $MYK_SPI_OUTS -max_paths 20 -delay_type min_max -name MykSpiOutTiming + +set MIN_IN_DELAY 2.0 +set MAX_IN_DELAY 10.0 + +set PS_SPI_INPUTS_0 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI0MI"}] +set PS_SPI_INPUTS_1 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI1MI"}] + +set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_0 +set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_0 +set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_1 +set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_1 + +# report_timing -to $PS_SPI_INPUTS_0 -max_paths 30 -delay_type min_max -nworst 30 -name Spi0InTiming +# report_timing -to $PS_SPI_INPUTS_1 -max_paths 30 -delay_type min_max -nworst 30 -name Spi1InTiming + + + +#******************************************************************************* +## PL SPI to the CPLD +# +# All of these lines are driven or received from flops in simple_spi_core. The CPLD +# calculations assume the FPGA has less than 20 ns of skew between the SCK and +# SDI/CS_n. Pretty easy constraint to write! See above for the clock definition. +# Do this for DBA and DBB independently. +set MAX_SKEW 20.0 +set SETUP_SKEW [expr {$MAX_SKEW / 2}] +set HOLD_SKEW [expr {$MAX_SKEW / 2}] +# Do not set the output delay constraint on the clock line! +set PORT_LIST_A [get_ports {DBA_CPLD_PL_SPI_LE \ + DBA_CPLD_PL_SPI_SDI \ + DBA_CPLD_PL_SPI_ADDR[0] \ + DBA_CPLD_PL_SPI_ADDR[1]}] +set PORT_LIST_B [get_ports {DBB_CPLD_PL_SPI_LE \ + DBB_CPLD_PL_SPI_SDI \ + DBB_CPLD_PL_SPI_ADDR[0] \ + DBB_CPLD_PL_SPI_ADDR[1]}] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A +set_output_delay -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A +set_output_delay -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B +set_output_delay -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -1 +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -1 + +# For SDO input timing (MISO), we need to look at the CPLD's constraints on turnaround +# time plus any board propagation delay. +set MISO_INPUT_A [get_ports DBA_CPLD_PL_SPI_SDO] +set MISO_INPUT_B [get_ports DBB_CPLD_PL_SPI_SDO] +set_input_delay -clock [get_clocks pl_spi_clk_a] -clock_fall -max 68.041 $MISO_INPUT_A +set_input_delay -clock [get_clocks pl_spi_clk_a] -clock_fall -min 12.218 $MISO_INPUT_A +set_input_delay -clock [get_clocks pl_spi_clk_b] -clock_fall -max 68.041 $MISO_INPUT_B +set_input_delay -clock [get_clocks pl_spi_clk_b] -clock_fall -min 12.218 $MISO_INPUT_B +# Since the input delay span is clearly more than a period of the radio_clk, we need to +# add a multicycle path here as well to define the clock divider ratio. The MISO data +# is driven on the falling edge of the SPI clock and captured on the rising edge, so we +# only have one half of a SPI clock cycle for our setup. Hold is left alone and is OK +# as-is due to the delays in the CPLD and board. +set SETUP_CYCLES [expr {$PL_SPI_DIVIDE_VAL / 2}] +set HOLD_CYCLES 0 +set_multicycle_path -setup -from [get_clocks pl_spi_clk_a] -through $MISO_INPUT_A \ + $SETUP_CYCLES +set_multicycle_path -hold -from [get_clocks pl_spi_clk_a] -through $MISO_INPUT_A -end \ + [expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}] +set_multicycle_path -setup -from [get_clocks pl_spi_clk_b] -through $MISO_INPUT_B \ + $SETUP_CYCLES +set_multicycle_path -hold -from [get_clocks pl_spi_clk_b] -through $MISO_INPUT_B -end \ + [expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}] + +# One of the PL_SPI_ADDR lines is used instead for the LMK SYNC strobe. This line is +# driven asynchronously. +set_output_delay -clock [get_clocks async_out_clk] 0.000 [get_ports DB*_CPLD_PL_SPI_ADDR[2]] +set_max_delay -to [get_ports DB*_CPLD_PL_SPI_ADDR[2]] 50.000 +set_min_delay -to [get_ports DB*_CPLD_PL_SPI_ADDR[2]] 0.000 + + + +#******************************************************************************* +## DSA Bus +# The DSA controls are driven from the DB-A radio clock. Although they are received async +# at the DSAs, they should be tightly constrained in the FPGA to arrive as closely as +# possible. The best way to do this is a skew constraint across all the bits. +set MAX_SKEW 2.5 +set SETUP_SKEW [expr {($MAX_SKEW / 2)+0.5}] +set HOLD_SKEW [expr {($MAX_SKEW / 2)-0.5}] +set PORT_LIST [get_ports {DB*_CH*_*X_DSA_DATA[*]}] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks dsa_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks dsa_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -clock [get_clocks dsa_bus_clk] -min $HOLD_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks dsa_bus_clk] -min $HOLD_SKEW $PORT_LIST +# Finally, make both the setup and hold checks use the same launching and latching edges. +# The clock, which is essentially one of the data lines, should arrive at the pin +# +/- MAX_DELAY compared to the other data lines, so setup and hold checks need to be +# relative to the SAME edges for both the clock and the data. +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks dsa_bus_clk] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks dsa_bus_clk] -1 +# Remove analysis from the output "clock" pin. There are ways to do this using TCL, but +# they aren't supported in XDC files... so we do it the old fashioned way. +set_output_delay -clock [get_clocks async_out_clk] 0.000 $DSA_CLK +set_max_delay -to $DSA_CLK 50.000 +set_min_delay -to $DSA_CLK 0.000 + + + +#******************************************************************************* +## ATR Bus +# The ATR bits are driven from the DB-A radio clock. Although they are received async in +# the CPLD, they should be tightly constrained in the FPGA to avoid any race conditions. +# The best way to do this is a skew constraint across all the bits. +set MAX_SKEW 2.5 +set SETUP_SKEW [expr {($MAX_SKEW / 2)+0.5}] +set HOLD_SKEW [expr {($MAX_SKEW / 2)-0.5}] +set PORT_LIST [get_ports DB*_ATR_*X_*] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks atr_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks atr_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -clock [get_clocks atr_bus_clk] -min $HOLD_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks atr_bus_clk] -min $HOLD_SKEW $PORT_LIST +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -to [get_clocks atr_bus_clk] -start 0 +set_multicycle_path -hold -to [get_clocks atr_bus_clk] -1 +# Remove analysis from the output "clock" pin. There are ways to do this using TCL, but +# they aren't supported in XDC files... so we do it the old fashioned way. +set_output_delay -clock [get_clocks async_out_clk] 0.000 $ATR_CLK +set_max_delay -to $ATR_CLK 50.000 +set_min_delay -to $ATR_CLK 0.000 + + + +#******************************************************************************* +## Mykonos Ports +# Mykonos GPIO is driven from the DB-A radio clock. Although they are received async in +# Mykonos, they should be tightly constrained in the FPGA to avoid any race conditions. +# The best way to do this is a skew constraint across all the bits. +# set MAX_SKEW 2.5 +# set SETUP_SKEW [expr {($MAX_SKEW / 2)+0.5}] +# set HOLD_SKEW [expr {($MAX_SKEW / 2)-0.5}] +# set PORT_LIST [get_ports DB*_ATR_*X_*] +# # Then add the output delay on each of the ports. +# set_output_delay -clock [get_clocks myk_gpio_bus_clk] -max -$SETUP_SKEW $PORT_LIST +# set_output_delay -add_delay -clock_fall -clock [get_clocks myk_gpio_bus_clk] -max -$SETUP_SKEW $PORT_LIST +# set_output_delay -clock [get_clocks myk_gpio_bus_clk] -min $HOLD_SKEW $PORT_LIST +# set_output_delay -add_delay -clock_fall -clock [get_clocks myk_gpio_bus_clk] -min $HOLD_SKEW $PORT_LIST +# # Finally, make both the setup and hold checks use the same launching and latching edges. +# set_multicycle_path -setup -to [get_clocks myk_gpio_bus_clk] -start 0 +# set_multicycle_path -hold -to [get_clocks myk_gpio_bus_clk] -1 +# # Remove analysis from the output "clock" pin. There are ways to do this using TCL, but +# # they aren't supported in XDC files... so we do it the old fashioned way. +# set_output_delay -clock [get_clocks async_out_clk] 0.000 $MGPIO_CLK +# set_max_delay -to $MGPIO_CLK 50.000 +# set_min_delay -to $MGPIO_CLK 0.000 + +# Mykonos Interrupt is received asynchronously, and driven directly to the PS. +set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports DB*_MYK_INTRQ] +set_max_delay -from [get_ports DB*_MYK_INTRQ] 50.000 +set_min_delay -from [get_ports DB*_MYK_INTRQ] 0.000 + + + +#******************************************************************************* +## SYSREF/SYNC JESD Timing +# +# SYNC is async, SYSREF is tightly timed. + +# The SYNC output for both DBs is governed by the JESD cores, which are solely driven by +# DB-A clock... but it is an asynchronous signal so we use the async_out_clk. +set_output_delay -clock [get_clocks async_out_clk] 0.000 [get_ports DB*_MYK_SYNC_IN_n] +set_max_delay -to [get_ports DB*_MYK_SYNC_IN_n] 50.000 +set_min_delay -to [get_ports DB*_MYK_SYNC_IN_n] 0.000 + +# The SYNC input for both DBs is received by the DB-A clock inside the JESD cores... but +# again, it is asynchronous and therefore uses the async_in_clk. +set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports DB*_MYK_SYNC_OUT_n] +set_max_delay -from [get_ports DB*_MYK_SYNC_OUT_n] 50.000 +set_min_delay -from [get_ports DB*_MYK_SYNC_OUT_n] 0.000 + +# SYSREF is driven by the LMK directly to the FPGA. Timing analysis was performed once +# for the worst-case numbers across both DBs to produce one set of numbers for both DBs. +# Since we easily meet setup and hold in Vivado, then this is an acceptable approach. +# SYSREF is captured by the local clock from each DB, so we have two sets of constraints. +set_input_delay -clock fpga_clk_a_v -min -0.906 [get_ports DBA_FPGA_SYSREF_*] +set_input_delay -clock fpga_clk_a_v -max 0.646 [get_ports DBA_FPGA_SYSREF_*] + +set_input_delay -clock fpga_clk_b_v -min -0.906 [get_ports DBB_FPGA_SYSREF_*] +set_input_delay -clock fpga_clk_b_v -max 0.646 [get_ports DBB_FPGA_SYSREF_*] + + + +#******************************************************************************* +## PPS Timing + +# Due to the N3xx synchronization and clocking structure, the PPS output is driven from +# the Sample Clock domain instead of the input Reference Clock. Constrain the output as +# tightly as possible to accurately mimic the internal Sample Clock timing. +set SETUP_SKEW 2.0 +set HOLD_SKEW -0.5 +set_output_delay -clock [get_clocks fpga_clk_a_v] -max -$SETUP_SKEW [get_ports REF_1PPS_OUT] +set_output_delay -clock [get_clocks fpga_clk_a_v] -min $HOLD_SKEW [get_ports REF_1PPS_OUT] +set_multicycle_path -setup -to [get_ports REF_1PPS_OUT] -start 0 +set_multicycle_path -hold -to [get_ports REF_1PPS_OUT] -1 diff --git a/fpga/usrp3/top/n3xx/dboards/mg/doc/CPLD.md b/fpga/usrp3/top/n3xx/dboards/mg/doc/CPLD.md new file mode 100644 index 000000000..2071c46ba --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/doc/CPLD.md @@ -0,0 +1,2 @@ +Timing closure of the CPLD design relies on the pre-set seed value. The build +requires Quartus 16.1.2. diff --git a/fpga/usrp3/top/n3xx/dboards/mg/doc/mg_timing.xlsx b/fpga/usrp3/top/n3xx/dboards/mg/doc/mg_timing.xlsx new file mode 100644 index 000000000..c4ad8ac5c Binary files /dev/null and b/fpga/usrp3/top/n3xx/dboards/mg/doc/mg_timing.xlsx differ diff --git a/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v b/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v new file mode 100644 index 000000000..32fa84153 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v @@ -0,0 +1,3915 @@ +/////////////////////////////////////////////////////////////////// +/// +// Copyright 2016-2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx +// Description: +// Top Level for N3xx devices +// +////////////////////////////////////////////////////////////////////// + +module n3xx ( + inout [11:0] FPGA_GPIO, + + input FPGA_REFCLK_P, + input FPGA_REFCLK_N, + input REF_1PPS_IN, + input NETCLK_REF_P, + input NETCLK_REF_N, + //input REF_1PPS_IN_MGMT, + output REF_1PPS_OUT, + + //TDC + inout UNUSED_PIN_TDCA_0, + inout UNUSED_PIN_TDCA_1, + inout UNUSED_PIN_TDCA_2, + inout UNUSED_PIN_TDCA_3, + inout UNUSED_PIN_TDCB_0, + inout UNUSED_PIN_TDCB_1, + inout UNUSED_PIN_TDCB_2, + inout UNUSED_PIN_TDCB_3, + +`ifdef NPIO_LANES + input NPIO_RX0_P, + input NPIO_RX0_N, + output NPIO_TX0_P, + output NPIO_TX0_N, + input NPIO_RX1_P, + input NPIO_RX1_N, + output NPIO_TX1_P, + output NPIO_TX1_N, +`endif +`ifdef QSFP_LANES + input [`QSFP_LANES-1:0] QSFP_RX_P, + input [`QSFP_LANES-1:0] QSFP_RX_N, + output [`QSFP_LANES-1:0] QSFP_TX_P, + output [`QSFP_LANES-1:0] QSFP_TX_N, + output QSFP_RESET_B, + output QSFP_LED, + output QSFP_MODSEL_B, + output QSFP_LPMODE, + input QSFP_PRESENT_B, + input QSFP_INT_B, + inout QSFP_I2C_SCL, + inout QSFP_I2C_SDA, +`endif + //TODO: Uncomment when connected here + //input NPIO_0_RXSYNC_0_P, NPIO_0_RXSYNC_1_P, + //input NPIO_0_RXSYNC_0_N, NPIO_0_RXSYNC_1_N, + //output NPIO_0_TXSYNC_0_P, NPIO_0_TXSYNC_1_P, + //output NPIO_0_TXSYNC_0_N, NPIO_0_TXSYNC_1_N, + //input NPIO_1_RXSYNC_0_P, NPIO_1_RXSYNC_1_P, + //input NPIO_1_RXSYNC_0_N, NPIO_1_RXSYNC_1_N, + //output NPIO_1_TXSYNC_0_P, NPIO_1_TXSYNC_1_P, + //output NPIO_1_TXSYNC_0_N, NPIO_1_TXSYNC_1_N, + //input NPIO_2_RXSYNC_0_P, NPIO_2_RXSYNC_1_P, + //input NPIO_2_RXSYNC_0_N, NPIO_2_RXSYNC_1_N, + //output NPIO_2_TXSYNC_0_P, NPIO_2_TXSYNC_1_P, + //output NPIO_2_TXSYNC_0_N, NPIO_2_TXSYNC_1_N, + + //GPS + input GPS_1PPS, + //input GPS_1PPS_RAW, + + //Misc + input ENET0_CLK125, + //inout ENET0_PTP, + //output ENET0_PTP_DIR, + //inout ATSHA204_SDA, + input FPGA_PL_RESETN, // TODO: Add to reset logic + // output reg [1:0] FPGA_TEST, + //input PWR_CLK_FPGA, // TODO: check direction + input FPGA_PUDC_B, + + //White Rabbit + input WB_20MHZ_P, + input WB_20MHZ_N, + output WB_DAC_DIN, + output WB_DAC_NCLR, + output WB_DAC_NLDAC, + output WB_DAC_NSYNC, + output WB_DAC_SCLK, + + //LEDS + output PANEL_LED_GPS, + output PANEL_LED_LINK, + output PANEL_LED_PPS, + output PANEL_LED_REF, + + // ARM Connections (PS) + inout [53:0] MIO, + inout PS_SRSTB, + inout PS_CLK, + inout PS_PORB, + inout DDR_Clk, + inout DDR_Clk_n, + inout DDR_CKE, + inout DDR_CS_n, + inout DDR_RAS_n, + inout DDR_CAS_n, + inout DDR_WEB, + inout [2:0] DDR_BankAddr, + inout [14:0] DDR_Addr, + inout DDR_ODT, + inout DDR_DRSTB, + inout [31:0] DDR_DQ, + inout [3:0] DDR_DM, + inout [3:0] DDR_DQS, + inout [3:0] DDR_DQS_n, + inout DDR_VRP, + inout DDR_VRN, + + + /////////////////////////////////// + // + // High Speed SPF+ signals and clocking + // + /////////////////////////////////// + + // These clock inputs must always be enabled with a buffer regardless of the build + // target to avoid damage to the FPGA. + input NETCLK_P, + input NETCLK_N, + input MGT156MHZ_CLK1_P, + input MGT156MHZ_CLK1_N, + + input SFP_0_RX_P, input SFP_0_RX_N, + output SFP_0_TX_P, output SFP_0_TX_N, + input SFP_1_RX_P, input SFP_1_RX_N, + output SFP_1_TX_P, output SFP_1_TX_N, + + + /////////////////////////////////// + // + // DRAM Interface + // + /////////////////////////////////// + inout [31:0] ddr3_dq, // Data pins. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_n, // Data Strobes. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_p, + // + output [15:0] ddr3_addr, // Address + output [2:0] ddr3_ba, // Bank Address + output ddr3_ras_n, // Row Address Strobe. + output ddr3_cas_n, // Column address select + output ddr3_we_n, // Write Enable + output ddr3_reset_n, // SDRAM reset pin. + output [0:0] ddr3_ck_p, // Differential clock + output [0:0] ddr3_ck_n, + output [0:0] ddr3_cke, // Clock Enable + output [0:0] ddr3_cs_n, // Chip Select + output [3:0] ddr3_dm, // Data Mask [3] = UDM.U26, [2] = LDM.U26, ... + output [0:0] ddr3_odt, // On-Die termination enable. + // + input sys_clk_p, // Differential + input sys_clk_n, // 100MHz clock source to generate DDR3 clocking. + + + /////////////////////////////////// + // + // Supporting I/O for SPF+ interfaces + // (non high speed stuff) + // + /////////////////////////////////// + + //SFP+ 0, Slow Speed, Bank 13 3.3V + input SFP_0_I2C_NPRESENT, + output SFP_0_LED_A, + output SFP_0_LED_B, + input SFP_0_LOS, + output SFP_0_RS0, + output SFP_0_RS1, + output SFP_0_TXDISABLE, + input SFP_0_TXFAULT, + + //SFP+ 1, Slow Speed, Bank 13 3.3V + //input SFP_1_I2C_NPRESENT, + output SFP_1_LED_A, + output SFP_1_LED_B, + input SFP_1_LOS, + output SFP_1_RS0, + output SFP_1_RS1, + output SFP_1_TXDISABLE, + input SFP_1_TXFAULT, + + //USRP IO A + output DBA_CPLD_PS_SPI_SCLK, + output DBA_CPLD_PS_SPI_LE, + output DBA_CPLD_PS_SPI_SDI, + input DBA_CPLD_PS_SPI_SDO, + output [1:0] DBA_CPLD_PS_SPI_ADDR, + + output DBA_ATR_RX_1, + output DBA_ATR_RX_2, + output DBA_ATR_TX_1, + output DBA_ATR_TX_2, + + output [5:0] DBA_CH1_TX_DSA_DATA, + output [5:0] DBA_CH1_RX_DSA_DATA, + output [5:0] DBA_CH2_TX_DSA_DATA, + output [5:0] DBA_CH2_RX_DSA_DATA, + + output DBA_CPLD_PL_SPI_SCLK, + output DBA_CPLD_PL_SPI_LE, + output DBA_CPLD_PL_SPI_SDI, + input DBA_CPLD_PL_SPI_SDO, + output [2:0] DBA_CPLD_PL_SPI_ADDR, + + output DBA_MYK_SPI_SCLK, + output DBA_MYK_SPI_CS_n, + input DBA_MYK_SPI_SDO, + output DBA_MYK_SPI_SDIO, + input DBA_MYK_INTRQ, + + output DBA_MYK_SYNC_IN_n, + input DBA_MYK_SYNC_OUT_n, + + inout DBA_CPLD_JTAG_TCK, + inout DBA_CPLD_JTAG_TMS, + inout DBA_CPLD_JTAG_TDI, + input DBA_CPLD_JTAG_TDO, + + output DBA_MYK_GPIO_0, + output DBA_MYK_GPIO_1, + output DBA_MYK_GPIO_3, + output DBA_MYK_GPIO_4, + output DBA_MYK_GPIO_12, + output DBA_MYK_GPIO_13, + output DBA_MYK_GPIO_14, + output DBA_MYK_GPIO_15, + + input DBA_FPGA_CLK_P, + input DBA_FPGA_CLK_N, + input DBA_FPGA_SYSREF_P, + input DBA_FPGA_SYSREF_N, + + input USRPIO_A_MGTCLK_P, + input USRPIO_A_MGTCLK_N, + + input [3:0] USRPIO_A_RX_P, + input [3:0] USRPIO_A_RX_N, + output [3:0] USRPIO_A_TX_P, + output [3:0] USRPIO_A_TX_N + +`ifndef N300 + //USRP IO B + ,output DBB_CPLD_PS_SPI_SCLK, + output DBB_CPLD_PS_SPI_LE, + output DBB_CPLD_PS_SPI_SDI, + input DBB_CPLD_PS_SPI_SDO, + output [1:0] DBB_CPLD_PS_SPI_ADDR, + + output DBB_ATR_RX_1, + output DBB_ATR_RX_2, + output DBB_ATR_TX_1, + output DBB_ATR_TX_2, + + output [5:0] DBB_CH1_TX_DSA_DATA, + output [5:0] DBB_CH1_RX_DSA_DATA, + output [5:0] DBB_CH2_TX_DSA_DATA, + output [5:0] DBB_CH2_RX_DSA_DATA, + + output DBB_CPLD_PL_SPI_SCLK, + output DBB_CPLD_PL_SPI_LE, + output DBB_CPLD_PL_SPI_SDI, + input DBB_CPLD_PL_SPI_SDO, + output [2:0] DBB_CPLD_PL_SPI_ADDR, + + output DBB_MYK_SPI_SCLK, + output DBB_MYK_SPI_CS_n, + input DBB_MYK_SPI_SDO, + output DBB_MYK_SPI_SDIO, + input DBB_MYK_INTRQ, + + output DBB_MYK_SYNC_IN_n, + input DBB_MYK_SYNC_OUT_n, + + inout DBB_CPLD_JTAG_TCK, + inout DBB_CPLD_JTAG_TMS, + inout DBB_CPLD_JTAG_TDI, + input DBB_CPLD_JTAG_TDO, + + output DBB_MYK_GPIO_0, + output DBB_MYK_GPIO_1, + output DBB_MYK_GPIO_3, + output DBB_MYK_GPIO_4, + output DBB_MYK_GPIO_12, + output DBB_MYK_GPIO_13, + output DBB_MYK_GPIO_14, + output DBB_MYK_GPIO_15, + + input DBB_FPGA_CLK_P, + input DBB_FPGA_CLK_N, + input DBB_FPGA_SYSREF_P, + input DBB_FPGA_SYSREF_N, + + input USRPIO_B_MGTCLK_P, + input USRPIO_B_MGTCLK_N, + + input [3:0] USRPIO_B_RX_P, + input [3:0] USRPIO_B_RX_N, + output [3:0] USRPIO_B_TX_P, + output [3:0] USRPIO_B_TX_N +`endif +); + + localparam N_AXILITE_SLAVES = 4; + localparam REG_AWIDTH = 14; // log2(0x4000) + localparam QSFP_REG_AWIDTH = 17; // log2(0x20000) + localparam REG_DWIDTH = 32; + localparam FP_GPIO_OFFSET = 32; + localparam FP_GPIO_WIDTH = 12; + +`ifdef N310 + localparam NUM_RADIOS = 2; + localparam NUM_CHANNELS_PER_RADIO = 2; + localparam NUM_DBOARDS = 2; +`elsif N300 + localparam NUM_RADIOS = 1; + localparam NUM_CHANNELS_PER_RADIO = 2; + localparam NUM_DBOARDS = 1; +`endif + localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO; + localparam [15:0] RFNOC_PROTOVER = {8'd1, 8'd0}; + + // Internal connections to PS + // HP0 -- High Performance port 0, FPGA is the master + wire [5:0] S_AXI_HP0_AWID; + wire [31:0] S_AXI_HP0_AWADDR; + wire [2:0] S_AXI_HP0_AWPROT; + wire S_AXI_HP0_AWVALID; + wire S_AXI_HP0_AWREADY; + wire [63:0] S_AXI_HP0_WDATA; + wire [7:0] S_AXI_HP0_WSTRB; + wire S_AXI_HP0_WVALID; + wire S_AXI_HP0_WREADY; + wire [1:0] S_AXI_HP0_BRESP; + wire S_AXI_HP0_BVALID; + wire S_AXI_HP0_BREADY; + wire [5:0] S_AXI_HP0_ARID; + wire [31:0] S_AXI_HP0_ARADDR; + wire [2:0] S_AXI_HP0_ARPROT; + wire S_AXI_HP0_ARVALID; + wire S_AXI_HP0_ARREADY; + wire [63:0] S_AXI_HP0_RDATA; + wire [1:0] S_AXI_HP0_RRESP; + wire S_AXI_HP0_RVALID; + wire S_AXI_HP0_RREADY; + wire S_AXI_HP0_RLAST; + wire [3:0] S_AXI_HP0_ARCACHE; + wire [7:0] S_AXI_HP0_AWLEN; + wire [2:0] S_AXI_HP0_AWSIZE; + wire [1:0] S_AXI_HP0_AWBURST; + wire [3:0] S_AXI_HP0_AWCACHE; + wire S_AXI_HP0_WLAST; + wire [7:0] S_AXI_HP0_ARLEN; + wire [1:0] S_AXI_HP0_ARBURST; + wire [2:0] S_AXI_HP0_ARSIZE; + + // GP0 -- General Purpose port 0, FPGA is the master + wire [4:0] S_AXI_GP0_AWID; + wire [31:0] S_AXI_GP0_AWADDR; + wire [2:0] S_AXI_GP0_AWPROT; + wire S_AXI_GP0_AWVALID; + wire S_AXI_GP0_AWREADY; + wire [31:0] S_AXI_GP0_WDATA; + wire [3:0] S_AXI_GP0_WSTRB; + wire S_AXI_GP0_WVALID; + wire S_AXI_GP0_WREADY; + wire [1:0] S_AXI_GP0_BRESP; + wire S_AXI_GP0_BVALID; + wire S_AXI_GP0_BREADY; + wire [4:0] S_AXI_GP0_ARID; + wire [31:0] S_AXI_GP0_ARADDR; + wire [2:0] S_AXI_GP0_ARPROT; + wire S_AXI_GP0_ARVALID; + wire S_AXI_GP0_ARREADY; + wire [31:0] S_AXI_GP0_RDATA; + wire [1:0] S_AXI_GP0_RRESP; + wire S_AXI_GP0_RVALID; + wire S_AXI_GP0_RREADY; + wire S_AXI_GP0_RLAST; + wire [3:0] S_AXI_GP0_ARCACHE; + wire [7:0] S_AXI_GP0_AWLEN; + wire [2:0] S_AXI_GP0_AWSIZE; + wire [1:0] S_AXI_GP0_AWBURST; + wire [3:0] S_AXI_GP0_AWCACHE; + wire S_AXI_GP0_WLAST; + wire [7:0] S_AXI_GP0_ARLEN; + wire [1:0] S_AXI_GP0_ARBURST; + wire [2:0] S_AXI_GP0_ARSIZE; + + // HP1 -- High Performance port 1, FPGA is the master + wire [5:0] S_AXI_HP1_AWID; + wire [31:0] S_AXI_HP1_AWADDR; + wire [2:0] S_AXI_HP1_AWPROT; + wire S_AXI_HP1_AWVALID; + wire S_AXI_HP1_AWREADY; + wire [63:0] S_AXI_HP1_WDATA; + wire [7:0] S_AXI_HP1_WSTRB; + wire S_AXI_HP1_WVALID; + wire S_AXI_HP1_WREADY; + wire [1:0] S_AXI_HP1_BRESP; + wire S_AXI_HP1_BVALID; + wire S_AXI_HP1_BREADY; + wire [5:0] S_AXI_HP1_ARID; + wire [31:0] S_AXI_HP1_ARADDR; + wire [2:0] S_AXI_HP1_ARPROT; + wire S_AXI_HP1_ARVALID; + wire S_AXI_HP1_ARREADY; + wire [63:0] S_AXI_HP1_RDATA; + wire [1:0] S_AXI_HP1_RRESP; + wire S_AXI_HP1_RVALID; + wire S_AXI_HP1_RREADY; + wire S_AXI_HP1_RLAST; + wire [3:0] S_AXI_HP1_ARCACHE; + wire [7:0] S_AXI_HP1_AWLEN; + wire [2:0] S_AXI_HP1_AWSIZE; + wire [1:0] S_AXI_HP1_AWBURST; + wire [3:0] S_AXI_HP1_AWCACHE; + wire S_AXI_HP1_WLAST; + wire [7:0] S_AXI_HP1_ARLEN; + wire [1:0] S_AXI_HP1_ARBURST; + wire [2:0] S_AXI_HP1_ARSIZE; + + // GP1 -- General Purpose port 1, FPGA is the master + wire [4:0] S_AXI_GP1_AWID; + wire [31:0] S_AXI_GP1_AWADDR; + wire [2:0] S_AXI_GP1_AWPROT; + wire S_AXI_GP1_AWVALID; + wire S_AXI_GP1_AWREADY; + wire [31:0] S_AXI_GP1_WDATA; + wire [3:0] S_AXI_GP1_WSTRB; + wire S_AXI_GP1_WVALID; + wire S_AXI_GP1_WREADY; + wire [1:0] S_AXI_GP1_BRESP; + wire S_AXI_GP1_BVALID; + wire S_AXI_GP1_BREADY; + wire [4:0] S_AXI_GP1_ARID; + wire [31:0] S_AXI_GP1_ARADDR; + wire [2:0] S_AXI_GP1_ARPROT; + wire S_AXI_GP1_ARVALID; + wire S_AXI_GP1_ARREADY; + wire [31:0] S_AXI_GP1_RDATA; + wire [1:0] S_AXI_GP1_RRESP; + wire S_AXI_GP1_RVALID; + wire S_AXI_GP1_RREADY; + wire S_AXI_GP1_RLAST; + wire [3:0] S_AXI_GP1_ARCACHE; + wire [7:0] S_AXI_GP1_AWLEN; + wire [2:0] S_AXI_GP1_AWSIZE; + wire [1:0] S_AXI_GP1_AWBURST; + wire [3:0] S_AXI_GP1_AWCACHE; + wire S_AXI_GP1_WLAST; + wire [7:0] S_AXI_GP1_ARLEN; + wire [1:0] S_AXI_GP1_ARBURST; + wire [2:0] S_AXI_GP1_ARSIZE; + + // GP0 -- General Purpose port 0, FPGA is the slave + wire M_AXI_GP0_ARVALID; + wire M_AXI_GP0_AWVALID; + wire M_AXI_GP0_BREADY; + wire M_AXI_GP0_RREADY; + wire M_AXI_GP0_WVALID; + wire [11:0] M_AXI_GP0_ARID; + wire [11:0] M_AXI_GP0_AWID; + wire [11:0] M_AXI_GP0_WID; + wire [31:0] M_AXI_GP0_ARADDR; + wire [31:0] M_AXI_GP0_AWADDR; + wire [31:0] M_AXI_GP0_WDATA; + wire [3:0] M_AXI_GP0_WSTRB; + wire M_AXI_GP0_ARREADY; + wire M_AXI_GP0_AWREADY; + wire M_AXI_GP0_BVALID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RVALID; + wire M_AXI_GP0_WREADY; + wire [1:0] M_AXI_GP0_BRESP; + wire [1:0] M_AXI_GP0_RRESP; + wire [31:0] M_AXI_GP0_RDATA; + + wire M_AXI_ETH_DMA0_ARVALID; + wire M_AXI_ETH_DMA0_AWVALID; + wire M_AXI_ETH_DMA0_BREADY; + wire M_AXI_ETH_DMA0_RREADY; + wire M_AXI_ETH_DMA0_WVALID; + wire [11:0] M_AXI_ETH_DMA0_ARID; + wire [11:0] M_AXI_ETH_DMA0_AWID; + wire [11:0] M_AXI_ETH_DMA0_WID; + wire [31:0] M_AXI_ETH_DMA0_ARADDR; + wire [31:0] M_AXI_ETH_DMA0_AWADDR; + wire [31:0] M_AXI_ETH_DMA0_WDATA; + wire [3:0] M_AXI_ETH_DMA0_WSTRB; + wire M_AXI_ETH_DMA0_ARREADY; + wire M_AXI_ETH_DMA0_AWREADY; + wire M_AXI_ETH_DMA0_BVALID; + wire M_AXI_ETH_DMA0_RLAST; + wire M_AXI_ETH_DMA0_RVALID; + wire M_AXI_ETH_DMA0_WREADY; + wire [1:0] M_AXI_ETH_DMA0_BRESP; + wire [1:0] M_AXI_ETH_DMA0_RRESP; + wire [31:0] M_AXI_ETH_DMA0_RDATA; + + wire M_AXI_NET0_ARVALID; + wire M_AXI_NET0_AWVALID; + wire M_AXI_NET0_BREADY; + wire M_AXI_NET0_RREADY; + wire M_AXI_NET0_WVALID; + wire [11:0] M_AXI_NET0_ARID; + wire [11:0] M_AXI_NET0_AWID; + wire [11:0] M_AXI_NET0_WID; + wire [31:0] M_AXI_NET0_ARADDR; + wire [31:0] M_AXI_NET0_AWADDR; + wire [31:0] M_AXI_NET0_WDATA; + wire [3:0] M_AXI_NET0_WSTRB; + wire M_AXI_NET0_ARREADY; + wire M_AXI_NET0_AWREADY; + wire M_AXI_NET0_BVALID; + wire M_AXI_NET0_RLAST; + wire M_AXI_NET0_RVALID; + wire M_AXI_NET0_WREADY; + wire [1:0] M_AXI_NET0_BRESP; + wire [1:0] M_AXI_NET0_RRESP; + wire [31:0] M_AXI_NET0_RDATA; + + wire M_AXI_ETH_DMA1_ARVALID; + wire M_AXI_ETH_DMA1_AWVALID; + wire M_AXI_ETH_DMA1_BREADY; + wire M_AXI_ETH_DMA1_RREADY; + wire M_AXI_ETH_DMA1_WVALID; + wire [11:0] M_AXI_ETH_DMA1_ARID; + wire [11:0] M_AXI_ETH_DMA1_AWID; + wire [11:0] M_AXI_ETH_DMA1_WID; + wire [31:0] M_AXI_ETH_DMA1_ARADDR; + wire [31:0] M_AXI_ETH_DMA1_AWADDR; + wire [31:0] M_AXI_ETH_DMA1_WDATA; + wire [3:0] M_AXI_ETH_DMA1_WSTRB; + wire M_AXI_ETH_DMA1_ARREADY; + wire M_AXI_ETH_DMA1_AWREADY; + wire M_AXI_ETH_DMA1_BVALID; + wire M_AXI_ETH_DMA1_RLAST; + wire M_AXI_ETH_DMA1_RVALID; + wire M_AXI_ETH_DMA1_WREADY; + wire [1:0] M_AXI_ETH_DMA1_BRESP; + wire [1:0] M_AXI_ETH_DMA1_RRESP; + wire [31:0] M_AXI_ETH_DMA1_RDATA; + + wire M_AXI_NET1_ARVALID; + wire M_AXI_NET1_AWVALID; + wire M_AXI_NET1_BREADY; + wire M_AXI_NET1_RREADY; + wire M_AXI_NET1_WVALID; + wire [11:0] M_AXI_NET1_ARID; + wire [11:0] M_AXI_NET1_AWID; + wire [11:0] M_AXI_NET1_WID; + wire [31:0] M_AXI_NET1_ARADDR; + wire [31:0] M_AXI_NET1_AWADDR; + wire [31:0] M_AXI_NET1_WDATA; + wire [3:0] M_AXI_NET1_WSTRB; + wire M_AXI_NET1_ARREADY; + wire M_AXI_NET1_AWREADY; + wire M_AXI_NET1_BVALID; + wire M_AXI_NET1_RLAST; + wire M_AXI_NET1_RVALID; + wire M_AXI_NET1_WREADY; + wire [1:0] M_AXI_NET1_BRESP; + wire [1:0] M_AXI_NET1_RRESP; + wire [31:0] M_AXI_NET1_RDATA; + + wire M_AXI_NET2_ARVALID; + wire M_AXI_NET2_AWVALID; + wire M_AXI_NET2_BREADY; + wire M_AXI_NET2_RREADY; + wire M_AXI_NET2_WVALID; + wire [11:0] M_AXI_NET2_ARID; + wire [11:0] M_AXI_NET2_AWID; + wire [11:0] M_AXI_NET2_WID; + wire [31:0] M_AXI_NET2_ARADDR; + wire [31:0] M_AXI_NET2_AWADDR; + wire [31:0] M_AXI_NET2_WDATA; + wire [3:0] M_AXI_NET2_WSTRB; + wire M_AXI_NET2_ARREADY; + wire M_AXI_NET2_AWREADY; + wire M_AXI_NET2_BVALID; + wire M_AXI_NET2_RLAST; + wire M_AXI_NET2_RVALID; + wire M_AXI_NET2_WREADY; + wire [1:0] M_AXI_NET2_BRESP; + wire [1:0] M_AXI_NET2_RRESP; + wire [31:0] M_AXI_NET2_RDATA; + + wire M_AXI_XBAR_ARVALID; + wire M_AXI_XBAR_AWVALID; + wire M_AXI_XBAR_BREADY; + wire M_AXI_XBAR_RREADY; + wire M_AXI_XBAR_WVALID; + wire [11:0] M_AXI_XBAR_ARID; + wire [11:0] M_AXI_XBAR_AWID; + wire [11:0] M_AXI_XBAR_WID; + wire [31:0] M_AXI_XBAR_ARADDR; + wire [31:0] M_AXI_XBAR_AWADDR; + wire [31:0] M_AXI_XBAR_WDATA; + wire [3:0] M_AXI_XBAR_WSTRB; + wire M_AXI_XBAR_ARREADY; + wire M_AXI_XBAR_AWREADY; + wire M_AXI_XBAR_BVALID; + wire M_AXI_XBAR_RLAST; + wire M_AXI_XBAR_RVALID; + wire M_AXI_XBAR_WREADY; + wire [1:0] M_AXI_XBAR_BRESP; + wire [1:0] M_AXI_XBAR_RRESP; + wire [31:0] M_AXI_XBAR_RDATA; + + wire M_AXI_JESD0_ARVALID; + wire M_AXI_JESD0_AWVALID; + wire M_AXI_JESD0_BREADY; + wire M_AXI_JESD0_RREADY; + wire M_AXI_JESD0_WVALID; + wire [11:0] M_AXI_JESD0_ARID; + wire [11:0] M_AXI_JESD0_AWID; + wire [11:0] M_AXI_JESD0_WID; + wire [31:0] M_AXI_JESD0_ARADDR; + wire [31:0] M_AXI_JESD0_AWADDR; + wire [31:0] M_AXI_JESD0_WDATA; + wire [3:0] M_AXI_JESD0_WSTRB; + wire M_AXI_JESD0_ARREADY; + wire M_AXI_JESD0_AWREADY; + wire M_AXI_JESD0_BVALID; + wire M_AXI_JESD0_RLAST; + wire M_AXI_JESD0_RVALID; + wire M_AXI_JESD0_WREADY; + wire [1:0] M_AXI_JESD0_BRESP; + wire [1:0] M_AXI_JESD0_RRESP; + wire [31:0] M_AXI_JESD0_RDATA; + + wire M_AXI_JESD1_ARVALID; + wire M_AXI_JESD1_AWVALID; + wire M_AXI_JESD1_BREADY; + wire M_AXI_JESD1_RREADY; + wire M_AXI_JESD1_WVALID; + wire [11:0] M_AXI_JESD1_ARID; + wire [11:0] M_AXI_JESD1_AWID; + wire [11:0] M_AXI_JESD1_WID; + wire [31:0] M_AXI_JESD1_ARADDR; + wire [31:0] M_AXI_JESD1_AWADDR; + wire [31:0] M_AXI_JESD1_WDATA; + wire [3:0] M_AXI_JESD1_WSTRB; + wire M_AXI_JESD1_ARREADY; + wire M_AXI_JESD1_AWREADY; + wire M_AXI_JESD1_BVALID; + wire M_AXI_JESD1_RLAST; + wire M_AXI_JESD1_RVALID; + wire M_AXI_JESD1_WREADY; + wire [1:0] M_AXI_JESD1_BRESP; + wire [1:0] M_AXI_JESD1_RRESP; + wire [31:0] M_AXI_JESD1_RDATA; + + // White Rabbit + wire wr_uart_txd; + wire wr_uart_rxd; + wire pps_wr_refclk; + wire wr_ref_clk; + + // AXI bus from PS to WR Core + wire m_axi_wr_clk; + wire [31:0] m_axi_wr_araddr; + wire [0:0] m_axi_wr_arready; + wire [0:0] m_axi_wr_arvalid; + wire [31:0] m_axi_wr_awaddr; + wire [0:0] m_axi_wr_awready; + wire [0:0] m_axi_wr_awvalid; + wire [0:0] m_axi_wr_bready; + wire [1:0] m_axi_wr_bresp; + wire [0:0] m_axi_wr_bvalid; + wire [31:0] m_axi_wr_rdata; + wire [0:0] m_axi_wr_rready; + wire [1:0] m_axi_wr_rresp; + wire [0:0] m_axi_wr_rvalid; + wire [31:0] m_axi_wr_wdata; + wire [0:0] m_axi_wr_wready; + wire [3:0] m_axi_wr_wstrb; + wire [0:0] m_axi_wr_wvalid; + + wire [63:0] ps_gpio_out; + wire [63:0] ps_gpio_in; + wire [63:0] ps_gpio_tri; + + wire [15:0] IRQ_F2P; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + wire clk100; + wire clk40; + wire meas_clk_ref; + wire bus_clk; + wire gige_refclk; + wire gige_refclk_bufg; + wire xgige_refclk; + wire xgige_clk156; + wire xgige_dclk; + + wire global_rst; + wire radio_rst; + wire bus_rst; + wire FCLK_RESET0_N; + wire clk40_rst; + wire clk40_rstn; + + wire [1:0] USB0_PORT_INDCTL; + wire USB0_VBUS_PWRSELECT; + wire USB0_VBUS_PWRFAULT; + + wire ref_clk; + wire wr_refclk_buf; + wire netclk_buf; + wire meas_clk; + wire ddr3_dma_clk; + wire meas_clk_reset; + wire meas_clk_locked; + wire enable_ref_clk_async; + wire pps_radioclk1x_iob; + wire pps_radioclk1x; + wire [3:0] pps_select; + wire pps_out_enb; + wire [1:0] pps_select_sfp; + wire pps_refclk; + wire export_pps_radioclk; + wire radio_clk; + wire radio_clk_2x; + + wire qsfp_sda_i; + wire qsfp_sda_o; + wire qsfp_sda_t; + wire qsfp_scl_i; + wire qsfp_scl_o; + wire qsfp_scl_t; + + ///////////////////////////////////////////////////////////////////// + // + // Resets + // + ////////////////////////////////////////////////////////////////////// + + // Global synchronous reset, on the bus_clk domain. De-asserts after 85 + // bus_clk cycles. Asserted by default. + por_gen por_gen(.clk(bus_clk), .reset_out(global_rst)); + + // Synchronous reset for the radio_clk domain, based on the global_rst. + reset_sync radio_reset_gen ( + .clk(radio_clk), + .reset_in(global_rst), + .reset_out(radio_rst) + ); + + // Synchronous reset for the bus_clk domain, based on the global_rst. + reset_sync bus_reset_gen ( + .clk(bus_clk), + .reset_in(global_rst), + .reset_out(bus_rst) + ); + + + // PS-based Resets // + // + // Synchronous reset for the clk40 domain. This is derived from the PS reset 0. + reset_sync clk40_reset_gen ( + .clk(clk40), + .reset_in(~FCLK_RESET0_N), + .reset_out(clk40_rst) + ); + // Invert for various modules. + assign clk40_rstn = ~clk40_rst; + + + ///////////////////////////////////////////////////////////////////// + // + // Timing + // + ////////////////////////////////////////////////////////////////////// + + // Clocks from the PS + // + // These clocks appear to have BUFGs already instantiated by the ip generator. + // Simply rename them here for clarity. + // FCLK_CLK0 : 100 MHz + // FCLK_CLK1 : 40 MHz + // FCLK_CLK2 : 166.6667 MHz + // FCLK_CLK3 : 200 MHz + assign clk100 = FCLK_CLK0; + assign clk40 = FCLK_CLK1; + assign meas_clk_ref = FCLK_CLK2; + assign bus_clk = FCLK_CLK3; + + //If bus_clk freq ever changes, update this paramter accordingly. + localparam BUS_CLK_RATE = 32'd200000000; //200 MHz bus_clk rate. + + n3xx_clocking n3xx_clocking_i ( + .enable_ref_clk_async(enable_ref_clk_async), + .FPGA_REFCLK_P(FPGA_REFCLK_P), + .FPGA_REFCLK_N(FPGA_REFCLK_N), + .ref_clk(ref_clk), + .WB_20MHz_P(WB_20MHZ_P), + .WB_20MHz_N(WB_20MHZ_N), + .wr_refclk_buf(wr_refclk_buf), + .NETCLK_REF_P(NETCLK_REF_P), + .NETCLK_REF_N(NETCLK_REF_N), + .netclk_buf(netclk_buf), + .NETCLK_P(NETCLK_P), + .NETCLK_N(NETCLK_N), + .gige_refclk_buf(gige_refclk), + .MGT156MHZ_CLK1_P(MGT156MHZ_CLK1_P), + .MGT156MHZ_CLK1_N(MGT156MHZ_CLK1_N), + .xgige_refclk_buf(xgige_refclk), + .misc_clks_ref(meas_clk_ref), + .meas_clk(meas_clk), + .ddr3_dma_clk(ddr3_dma_clk), + .misc_clks_reset(meas_clk_reset), + .misc_clks_locked(meas_clk_locked), + .ext_pps_from_pin(REF_1PPS_IN), + .gps_pps_from_pin(GPS_1PPS), + .pps_select(pps_select), + .pps_refclk(pps_refclk) + ); + + // Drive the rear panel connector with another controllable copy of the post-TDC PPS + // that SW can enable/disable. The user is free to hack this to be whatever + // they desire. Flop the PPS signal one more time in order that it can be packed into + // an IOB. This extra flop stage matches the additional flop inside DbCore to allow + // pps_radioclk1x and pps_out_radioclk to be in sync with one another. + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) pps_export_dsync ( + .clk(radio_clk), .rst(1'b0), .in(pps_out_enb), .out(export_pps_radioclk) + ); + + // The radio_clk rate is between [122.88M, 250M] for all known N3xx variants, + // resulting in approximately [8ns, 4ns] periods. To pulse-extend the PPS output, + // we create a 25 bit-wide counter, creating ~[.262s, .131s] long output high pulses, + // variable depending on our radio_clk rate. Create two of the same output signal + // in order that the PPS_OUT gets packed into an IOB for tight timing. + reg [24:0] pps_out_count = 'b0; + reg pps_out_radioclk = 1'b0; + reg pps_led_radioclk = 1'b0; + + always @(posedge radio_clk) begin + if (export_pps_radioclk) begin + if (pps_radioclk1x_iob) begin + pps_out_radioclk <= 1'b1; + pps_led_radioclk <= 1'b1; + pps_out_count <= {25{1'b1}}; + end else begin + if (pps_out_count > 0) begin + pps_out_count <= pps_out_count - 1'b1; + end else begin + pps_out_radioclk <= 1'b0; + pps_led_radioclk <= 1'b0; + end + end + end else begin + pps_out_radioclk <= 1'b0; + pps_led_radioclk <= 1'b0; + end + end + // Local to output. + assign REF_1PPS_OUT = pps_out_radioclk; + assign PANEL_LED_PPS = pps_led_radioclk; + + ///////////////////////////////////////////////////////////////////// + // + // SFP, QSFP and NPIO MGT Connections + // + ////////////////////////////////////////////////////////////////////// + wire reg_wr_req_npio; + wire [REG_AWIDTH-1:0] reg_wr_addr_npio; + wire [REG_DWIDTH-1:0] reg_wr_data_npio; + wire reg_rd_req_npio; + wire [REG_AWIDTH-1:0] reg_rd_addr_npio; + wire reg_rd_resp_npio, reg_rd_resp_npio0, reg_rd_resp_npio1; + wire [REG_DWIDTH-1:0] reg_rd_data_npio, reg_rd_data_npio0, reg_rd_data_npio1; + + localparam NPIO_REG_BASE = 14'h0200; + + regport_resp_mux #( + .WIDTH (REG_DWIDTH), + .NUM_SLAVES (2) + ) npio_resp_mux_i( + .clk(bus_clk), .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_npio0, reg_rd_resp_npio1}), + .sla_rd_data({reg_rd_data_npio0, reg_rd_data_npio1}), + .mst_rd_resp(reg_rd_resp_npio), .mst_rd_data(reg_rd_data_npio) + ); + + //-------------------------------------------------------------- + // SFP/MGT Reference Clocks + //-------------------------------------------------------------- + + // We support the HG, XG, XA, AA targets, all of which require + // the 156.25MHz reference clock. Instantiate it here. + ten_gige_phy_clk_gen xgige_clk_gen_i ( + .refclk_ibuf(xgige_refclk), + .clk156(xgige_clk156), + .dclk(xgige_dclk) + ); + + wire qpllreset; + wire qpllreset_sfp0, qpllreset_sfp1, qpllreset_npio0, qpllreset_npio1; + wire qplllock; + wire qplloutclk; + wire qplloutrefclk; + + // We reuse this GT_COMMON wrapper for both ethernet and Aurora because + // the behavior is identical + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) ten_gig_eth_pcs_pma_gt_common_block ( + .refclk(xgige_refclk), + .qpllreset(qpllreset), //from 2nd sfp + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclksel(3'b101 /*GTSOUTHREFCLK0*/) + ); + + // The quad's QPLL should reset if any of the channels request it + // This should never really happen because we are not changing the reference clock + // source for the QPLL. + assign qpllreset = qpllreset_sfp0 | qpllreset_sfp1 | qpllreset_npio0 | qpllreset_npio1; + + // Use the 156.25MHz reference clock for Aurora + wire aurora_refclk = xgige_refclk; + wire aurora_clk156 = xgige_clk156; + wire aurora_init_clk = xgige_dclk; + + // White Rabbit and 1GbE both use the same clocking +`ifdef SFP0_1GBE + `define SFP0_WR_1GBE +`endif +`ifdef SFP0_WR + `define SFP0_WR_1GBE +`endif + +`ifdef SFP0_WR_1GBE + // HG and WX targets require the 1GbE clock support + BUFG bufg_gige_refclk_i ( + .I(gige_refclk), + .O(gige_refclk_bufg) + ); + assign SFP_0_RS0 = 1'b0; + assign SFP_0_RS1 = 1'b0; +`else + assign SFP_0_RS0 = 1'b1; + assign SFP_0_RS1 = 1'b1; +`endif + + // SFP 1 is always set to run at ~10Gbps rates. + assign SFP_1_RS0 = 1'b1; + assign SFP_1_RS1 = 1'b1; + + // SFP port specific reference clocks + wire sfp0_gt_refclk, sfp1_gt_refclk; + wire sfp0_gb_refclk, sfp1_gb_refclk; + wire sfp0_misc_clk, sfp1_misc_clk; + +`ifdef SFP0_10GBE + assign sfp0_gt_refclk = xgige_refclk; + assign sfp0_gb_refclk = xgige_clk156; + assign sfp0_misc_clk = xgige_dclk; +`endif +`ifdef SFP0_WR_1GBE + assign sfp0_gt_refclk = gige_refclk; + assign sfp0_gb_refclk = gige_refclk_bufg; + assign sfp0_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP0_AURORA + assign sfp0_gt_refclk = aurora_refclk; + assign sfp0_gb_refclk = aurora_clk156; + assign sfp0_misc_clk = aurora_init_clk; +`endif + +`ifdef SFP1_10GBE + assign sfp1_gt_refclk = xgige_refclk; + assign sfp1_gb_refclk = xgige_clk156; + assign sfp1_misc_clk = xgige_dclk; +`endif +`ifdef SFP1_1GBE + assign sfp1_gt_refclk = gige_refclk; + assign sfp1_gb_refclk = gige_refclk_bufg; + assign sfp1_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP1_AURORA + assign sfp1_gt_refclk = aurora_refclk; + assign sfp1_gb_refclk = aurora_clk156; + assign sfp1_misc_clk = aurora_init_clk; +`endif + + // Instantiate Aurora MMCM if either of the SFPs + // or NPIOs are Aurora + wire au_tx_clk; + wire au_mmcm_reset; + wire au_user_clk; + wire au_sync_clk; + wire au_mmcm_locked; + wire sfp0_tx_out_clk, sfp1_tx_out_clk; + wire sfp0_gt_pll_lock, sfp1_gt_pll_lock; + wire npio0_tx_out_clk, npio1_tx_out_clk; + wire npio0_gt_pll_lock, npio1_gt_pll_lock; + + //NOTE: need to declare one of these defines in order to enable Aurora on + //any SFP or NPIO lane. +`ifdef SFP1_AURORA + `define SFP_AU_MMCM + assign au_tx_clk = sfp1_tx_out_clk; + assign au_mmcm_reset = ~sfp1_gt_pll_lock; +`elsif NPIO0 + `define SFP_AU_MMCM + assign au_tx_clk = npio0_tx_out_clk; + assign au_mmcm_reset = ~npio0_gt_pll_lock; +`elsif NPIO1 + `define SFP_AU_MMCM + assign au_tx_clk = npio1_tx_out_clk; + assign au_mmcm_reset = ~npio1_gt_pll_lock; +`endif + + +`ifdef SFP_AU_MMCM + aurora_phy_mmcm au_phy_mmcm_i ( + .aurora_tx_clk_unbuf(au_tx_clk), + .mmcm_reset(au_mmcm_reset), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .mmcm_locked(au_mmcm_locked) + ); +`else + assign au_user_clk = 1'b0; + assign au_sync_clk = 1'b0; + assign au_mmcm_locked = 1'b0; +`endif + + //-------------------------------------------------------------- + // NPIO-QSFP MGT Lanes (Example loopback config) + //-------------------------------------------------------------- + +`ifdef QSFP_LANES + localparam NUM_QSFP_LANES = `QSFP_LANES; + + // QSFP wires to the ARM core and the crossbar + // These will only be connected if QSFP is 2x10 GbE + wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_tx_tdata_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tvalid_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tlast_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tready_b; + wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_tx_tuser_b; + wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_tx_tkeep_b; + + wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_rx_tdata_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tvalid_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tlast_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tready_b; + wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_rx_tuser_b; + wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_rx_tkeep_b; + + wire [NUM_QSFP_LANES*64-1:0] v2e_qsfp_tdata; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tlast; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tvalid; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tready; + + wire [NUM_QSFP_LANES*64-1:0] e2v_qsfp_tdata; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tlast; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tvalid; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tready; + + wire [NUM_QSFP_LANES-1:0] qsfp_link_up; + + // QSFP quad's specific reference clocks + wire qsfp_gt_refclk; + wire qsfp_gb_refclk; + wire qsfp_misc_clk; + + wire qsfp_qplloutclk; + wire qsfp_qplloutrefclk; + wire qsfp_qplllock; + wire qsfp_qpllreset; + + wire qsfp_gt_tx_out_clk; + wire qsfp_gt_pll_lock; + + wire qsfp_au_user_clk; + wire qsfp_au_sync_clk; + wire qsfp_au_mmcm_locked; + + +`ifdef QSFP_10GBE + assign qsfp_gt_refclk = xgige_refclk; + assign qsfp_gb_refclk = xgige_clk156; + assign qsfp_misc_clk = xgige_dclk; +`endif +`ifdef QSFP_AURORA + assign qsfp_gt_refclk = aurora_refclk; + assign qsfp_gb_refclk = aurora_clk156; + assign qsfp_misc_clk = aurora_init_clk; +`endif + + // We reuse this GT_COMMON wrapper for both ethernet and Aurora because + // the behavior is identical + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) qsfp_gt_common_block ( + .refclk(xgige_refclk), + .qpllreset(qsfp_qpllreset), + .qplllock(qsfp_qplllock), + .qplloutclk(qsfp_qplloutclk), + .qplloutrefclk(qsfp_qplloutrefclk), + .qpllrefclksel(3'b001 /*GTREFCLK0*/) + ); + + `ifdef QSFP_AURORA + aurora_phy_mmcm aurora_phy_mmcm ( + .aurora_tx_clk_unbuf(qsfp_gt_tx_out_clk), + .mmcm_reset(~qsfp_gt_pll_lock), + .user_clk(qsfp_au_user_clk), + .sync_clk(qsfp_au_sync_clk), + .mmcm_locked(qsfp_au_mmcm_locked) + ); + `else + assign qsfp_au_user_clk = 1'b0; + assign qsfp_au_sync_clk = 1'b0; + assign qsfp_au_mmcm_locked = 1'b0; + `endif + + n3xx_mgt_channel_wrapper #( + `ifdef QSFP_10GBE + .PROTOCOL ("10GbE"), + .MDIO_EN (1'b1), + .MDIO_PHYADDR (5'd4), + `elsif QSFP_AURORA + .PROTOCOL ("Aurora"), + .MDIO_EN (1'b0), + `endif + .LANES (NUM_QSFP_LANES), + .PORTNUM_BASE (4), + .REG_DWIDTH (REG_DWIDTH), + .REG_AWIDTH (QSFP_REG_AWIDTH) + ) qsfp_wrapper_i ( + .areset (global_rst), + .gt_refclk (qsfp_gt_refclk), + .gb_refclk (qsfp_gb_refclk), + .misc_clk (qsfp_misc_clk), + .user_clk (qsfp_au_user_clk), + .sync_clk (qsfp_au_sync_clk), + .gt_tx_out_clk_unbuf(qsfp_gt_tx_out_clk), + + .bus_clk (bus_clk), + .bus_rst (bus_rst), + + // GT Common + .qpllrefclklost (), + .qplllock (qsfp_qplllock), + .qplloutclk (qsfp_qplloutclk), + .qplloutrefclk (qsfp_qplloutrefclk), + .qpllreset (qsfp_qpllreset), + + // Aurora MMCM + .mmcm_locked (qsfp_au_mmcm_locked), + .gt_pll_lock (qsfp_gt_pll_lock), + + .txp (QSFP_TX_P), + .txn (QSFP_TX_N), + .rxp (QSFP_RX_P), + .rxn (QSFP_RX_N), + + .mod_present_n (QSFP_PRESENT_B), + .mod_rxlos (1'b0), + .mod_tx_fault (1'b0), + .mod_tx_disable (), + .mod_int_n (QSFP_INT_B), + .mod_reset_n (QSFP_RESET_B), + .mod_lpmode (QSFP_LPMODE), + .mod_sel_n (QSFP_MODSEL_B), + + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_aresetn (clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr (M_AXI_NET2_AWADDR[QSFP_REG_AWIDTH-1:0]), + .s_axi_awvalid (M_AXI_NET2_AWVALID), + .s_axi_awready (M_AXI_NET2_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata (M_AXI_NET2_WDATA), + .s_axi_wstrb (M_AXI_NET2_WSTRB), + .s_axi_wvalid (M_AXI_NET2_WVALID), + .s_axi_wready (M_AXI_NET2_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp (M_AXI_NET2_BRESP), + .s_axi_bvalid (M_AXI_NET2_BVALID), + .s_axi_bready (M_AXI_NET2_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr (M_AXI_NET2_ARADDR[QSFP_REG_AWIDTH-1:0]), + .s_axi_arvalid (M_AXI_NET2_ARVALID), + .s_axi_arready (M_AXI_NET2_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_NET2_RDATA), + .s_axi_rresp (M_AXI_NET2_RRESP), + .s_axi_rvalid (M_AXI_NET2_RVALID), + .s_axi_rready (M_AXI_NET2_RREADY), + + // Ethernet to Vita + .e2v_tdata (e2v_qsfp_tdata), + .e2v_tlast (e2v_qsfp_tlast), + .e2v_tvalid (e2v_qsfp_tvalid), + .e2v_tready (e2v_qsfp_tready), + + // Vita to Ethernet + .v2e_tdata (v2e_qsfp_tdata), + .v2e_tlast (v2e_qsfp_tlast), + .v2e_tvalid (v2e_qsfp_tvalid), + .v2e_tready (v2e_qsfp_tready), + + // Ethernet to CPU + .e2c_tdata (arm_eth_qsfp_rx_tdata_b), + .e2c_tkeep (arm_eth_qsfp_rx_tkeep_b), + .e2c_tlast (arm_eth_qsfp_rx_tlast_b), + .e2c_tvalid (arm_eth_qsfp_rx_tvalid_b), + .e2c_tready (arm_eth_qsfp_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata (arm_eth_qsfp_tx_tdata_b), + .c2e_tkeep (arm_eth_qsfp_tx_tkeep_b), + .c2e_tlast (arm_eth_qsfp_tx_tlast_b), + .c2e_tvalid (arm_eth_qsfp_tx_tvalid_b), + .c2e_tready (arm_eth_qsfp_tx_tready_b), + + // Sideband White Rabbit Control + .wr_reset_n (1'b1), + .wr_refclk (1'b0), + + .wr_dac_sclk (), + .wr_dac_din (), + .wr_dac_clr_n (), + .wr_dac_cs_n (), + .wr_dac_ldac_n (), + + .wr_eeprom_scl_o(), + .wr_eeprom_scl_i(1'b0), + .wr_eeprom_sda_o(), + .wr_eeprom_sda_i(1'b0), + + .wr_uart_rx (1'b0), + .wr_uart_tx (), + + .mod_pps (), + .mod_refclk (), + + // WR AXI Control + .wr_axi_aclk (), + .wr_axi_aresetn (1'b1), + .wr_axi_awaddr (), + .wr_axi_awvalid (), + .wr_axi_awready (), + .wr_axi_wdata (), + .wr_axi_wstrb (), + .wr_axi_wvalid (), + .wr_axi_wready (), + .wr_axi_bresp (), + .wr_axi_bvalid (), + .wr_axi_bready (), + .wr_axi_araddr (), + .wr_axi_arvalid (), + .wr_axi_arready (), + .wr_axi_rdata (), + .wr_axi_rresp (), + .wr_axi_rvalid (), + .wr_axi_rready (), + .wr_axi_rlast (), + + .port_info (), + .device_id (device_id), + + .link_up (qsfp_link_up), + .activity () + ); + + assign QSFP_I2C_SCL = qsfp_scl_t ? 1'bz : qsfp_scl_o; + assign qsfp_scl_i = QSFP_I2C_SCL; + assign QSFP_I2C_SDA = qsfp_sda_t ? 1'bz : qsfp_sda_o; + assign qsfp_sda_i = QSFP_I2C_SDA; + + assign QSFP_LED = |qsfp_link_up; +`else + + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_qsfp ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_NET2_AWADDR), + .s_axi_awvalid(M_AXI_NET2_AWVALID), + .s_axi_awready(M_AXI_NET2_AWREADY), + + .s_axi_wdata(M_AXI_NET2_WDATA), + .s_axi_wvalid(M_AXI_NET2_WVALID), + .s_axi_wready(M_AXI_NET2_WREADY), + + .s_axi_bresp(M_AXI_NET2_BRESP), + .s_axi_bvalid(M_AXI_NET2_BVALID), + .s_axi_bready(M_AXI_NET2_BREADY), + + .s_axi_araddr(M_AXI_NET2_ARADDR), + .s_axi_arvalid(M_AXI_NET2_ARVALID), + .s_axi_arready(M_AXI_NET2_ARREADY), + + .s_axi_rdata(M_AXI_NET2_RDATA), + .s_axi_rresp(M_AXI_NET2_RRESP), + .s_axi_rvalid(M_AXI_NET2_RVALID), + .s_axi_rready(M_AXI_NET2_RREADY) + + ); + + assign qsfp_scl_i = qsfp_scl_t ? 1'b1 : qsfp_scl_o; + assign qsfp_sda_i = qsfp_sda_t ? 1'b1 : qsfp_sda_o; + +`endif + + //-------------------------------------------------------------- + // NPIO MGT Lanes (Example loopback config) + //-------------------------------------------------------------- + +`ifdef NPIO_LANES + + wire [127:0] npio_loopback_tdata; + wire [1:0] npio_loopback_tvalid; + wire [1:0] npio_loopback_tready; + wire [1:0] npio_loopback_tlast; + + n3xx_mgt_io_core #( + .PROTOCOL ("Aurora"), + .REG_BASE (NPIO_REG_BASE + 14'h00), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .PORTNUM (8'd2), + .MDIO_EN (0) + ) npio_ln_0_i ( + .areset (global_rst), + .gt_refclk (aurora_refclk), + .gb_refclk (aurora_clk156), + .misc_clk (aurora_init_clk), + .user_clk (au_user_clk), + .sync_clk (au_sync_clk), + .gt_tx_out_clk_unbuf(npio0_tx_out_clk), + + .bus_clk (bus_clk),//clk for status reg reads to mdio interface + .bus_rst (bus_rst), + .qpllreset (qpllreset_npio0), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qplllock (qplllock), + .qpllrefclklost (), + + .rxp (NPIO_RX0_P), + .rxn (NPIO_RX0_N), + .txp (NPIO_TX0_P), + .txn (NPIO_TX0_N), + + .sfpp_rxlos (1'b0), + .sfpp_tx_fault (1'b0), + + //RegPort + .reg_wr_req (reg_wr_req_npio), + .reg_wr_addr (reg_wr_addr_npio), + .reg_wr_data (reg_wr_data_npio), + .reg_rd_req (reg_rd_req_npio), + .reg_rd_addr (reg_rd_addr_npio), + .reg_rd_resp (reg_rd_resp_npio0), + .reg_rd_data (reg_rd_data_npio0), + + //DATA (loopback mode) + .s_axis_tdata (npio_loopback_tdata[63:0]), //Data to aurora core + .s_axis_tuser (4'b0), + .s_axis_tvalid (npio_loopback_tvalid[0]), + .s_axis_tlast (npio_loopback_tlast[0]), + .s_axis_tready (npio_loopback_tready[0]), + .m_axis_tdata (npio_loopback_tdata[63:0]), //Data from aurora core + .m_axis_tuser (), + .m_axis_tvalid (npio_loopback_tvalid[0]), + .m_axis_tlast (npio_loopback_tlast[0]), + .m_axis_tready (npio_loopback_tready[0]), + + .mmcm_locked (au_mmcm_locked), + .gt_pll_lock (npio0_gt_pll_lock) + ); + + n3xx_mgt_io_core #( + .PROTOCOL ("Aurora"), + .REG_BASE (NPIO_REG_BASE + 14'h40), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .PORTNUM (8'd3), + .MDIO_EN (0) + ) npio_ln_1_i ( + .areset (global_rst), + .gt_refclk (aurora_refclk), + .gb_refclk (aurora_clk156), + .misc_clk (aurora_init_clk), + .user_clk (au_user_clk), + .sync_clk (au_sync_clk), + .gt_tx_out_clk_unbuf(npio1_tx_out_clk), + + .bus_clk (bus_clk),//clk for status reg reads to mdio interface + .bus_rst (bus_rst), + .qpllreset (qpllreset_npio1), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qplllock (qplllock), + .qpllrefclklost (), + + .rxp (NPIO_RX1_P), + .rxn (NPIO_RX1_N), + .txp (NPIO_TX1_P), + .txn (NPIO_TX1_N), + + .sfpp_rxlos (1'b0), + .sfpp_tx_fault (1'b0), + + //RegPort + .reg_wr_req (reg_wr_req_npio), + .reg_wr_addr (reg_wr_addr_npio), + .reg_wr_data (reg_wr_data_npio), + .reg_rd_req (reg_rd_req_npio), + .reg_rd_addr (reg_rd_addr_npio), + .reg_rd_resp (reg_rd_resp_npio1), + .reg_rd_data (reg_rd_data_npio1), + + //DATA (loopback mode) + .s_axis_tdata (npio_loopback_tdata[127:64]), //Data to aurora core + .s_axis_tuser (4'b0), + .s_axis_tvalid (npio_loopback_tvalid[1]), + .s_axis_tlast (npio_loopback_tlast[1]), + .s_axis_tready (npio_loopback_tready[1]), + .m_axis_tdata (npio_loopback_tdata[127:64]), //Data from aurora core + .m_axis_tuser (), + .m_axis_tvalid (npio_loopback_tvalid[1]), + .m_axis_tlast (npio_loopback_tlast[1]), + .m_axis_tready (npio_loopback_tready[1]), + + .mmcm_locked (au_mmcm_locked), + .gt_pll_lock (npio1_gt_pll_lock) + ); + +`else + + assign reg_rd_resp_npio0 = 1'b0; + assign reg_rd_data_npio0 = 'h0; + assign reg_rd_resp_npio1 = 1'b0; + assign reg_rd_data_npio1 = 'h0; + assign npio0_gt_pll_lock = 1'b1; + assign npio1_gt_pll_lock = 1'b1; + assign qpllreset_npio0 = 1'b0; + assign qpllreset_npio1 = 1'b0; + +`endif + + + // ARM ethernet 0 bridge signals + wire [63:0] arm_eth0_tx_tdata; + wire arm_eth0_tx_tvalid; + wire arm_eth0_tx_tlast; + wire arm_eth0_tx_tready; + wire [3:0] arm_eth0_tx_tuser; + wire [7:0] arm_eth0_tx_tkeep; + + wire [63:0] arm_eth0_tx_tdata_b; + wire arm_eth0_tx_tvalid_b; + wire arm_eth0_tx_tlast_b; + wire arm_eth0_tx_tready_b; + wire [3:0] arm_eth0_tx_tuser_b; + wire [7:0] arm_eth0_tx_tkeep_b; + + wire [63:0] arm_eth_sfp0_tx_tdata_b; + wire arm_eth_sfp0_tx_tvalid_b; + wire arm_eth_sfp0_tx_tlast_b; + wire arm_eth_sfp0_tx_tready_b; + wire [3:0] arm_eth_sfp0_tx_tuser_b; + wire [7:0] arm_eth_sfp0_tx_tkeep_b; + + wire [63:0] arm_eth0_rx_tdata; + wire arm_eth0_rx_tvalid; + wire arm_eth0_rx_tlast; + wire arm_eth0_rx_tready; + wire [3:0] arm_eth0_rx_tuser; + wire [7:0] arm_eth0_rx_tkeep; + + wire [63:0] arm_eth0_rx_tdata_b; + wire arm_eth0_rx_tvalid_b; + wire arm_eth0_rx_tlast_b; + wire arm_eth0_rx_tready_b; + wire [3:0] arm_eth0_rx_tuser_b; + wire [7:0] arm_eth0_rx_tkeep_b; + + wire [63:0] arm_eth_sfp0_rx_tdata_b; + wire arm_eth_sfp0_rx_tvalid_b; + wire arm_eth_sfp0_rx_tlast_b; + wire arm_eth_sfp0_rx_tready_b; + wire [3:0] arm_eth_sfp0_rx_tuser_b; + wire [7:0] arm_eth_sfp0_rx_tkeep_b; + + wire arm_eth0_rx_irq; + wire arm_eth0_tx_irq; + + // ARM ethernet 1 bridge signals + wire [63:0] arm_eth1_tx_tdata; + wire arm_eth1_tx_tvalid; + wire arm_eth1_tx_tlast; + wire arm_eth1_tx_tready; + wire [3:0] arm_eth1_tx_tuser; + wire [7:0] arm_eth1_tx_tkeep; + + wire [63:0] arm_eth1_tx_tdata_b; + wire arm_eth1_tx_tvalid_b; + wire arm_eth1_tx_tlast_b; + wire arm_eth1_tx_tready_b; + wire [3:0] arm_eth1_tx_tuser_b; + wire [7:0] arm_eth1_tx_tkeep_b; + + wire [63:0] arm_eth_sfp1_tx_tdata_b; + wire arm_eth_sfp1_tx_tvalid_b; + wire arm_eth_sfp1_tx_tlast_b; + wire arm_eth_sfp1_tx_tready_b; + wire [3:0] arm_eth_sfp1_tx_tuser_b; + wire [7:0] arm_eth_sfp1_tx_tkeep_b; + + wire [63:0] arm_eth1_rx_tdata; + wire arm_eth1_rx_tvalid; + wire arm_eth1_rx_tlast; + wire arm_eth1_rx_tready; + wire [3:0] arm_eth1_rx_tuser; + wire [7:0] arm_eth1_rx_tkeep; + + wire [63:0] arm_eth1_rx_tdata_b; + wire arm_eth1_rx_tvalid_b; + wire arm_eth1_rx_tlast_b; + wire arm_eth1_rx_tready_b; + wire [3:0] arm_eth1_rx_tuser_b; + wire [7:0] arm_eth1_rx_tkeep_b; + + wire [63:0] arm_eth_sfp1_rx_tdata_b; + wire arm_eth_sfp1_rx_tvalid_b; + wire arm_eth_sfp1_rx_tlast_b; + wire arm_eth_sfp1_rx_tready_b; + wire [3:0] arm_eth_sfp1_rx_tuser_b; + wire [7:0] arm_eth_sfp1_rx_tkeep_b; + + wire arm_eth1_tx_irq; + wire arm_eth1_rx_irq; + + // Vita to Ethernet + wire [63:0] v2e0_tdata; + wire v2e0_tlast; + wire v2e0_tvalid; + wire v2e0_tready; + + wire [63:0] v2e1_tdata; + wire v2e1_tlast; + wire v2e1_tvalid; + wire v2e1_tready; + + wire [63:0] v2e_sfp0_tdata; + wire v2e_sfp0_tlast; + wire v2e_sfp0_tvalid; + wire v2e_sfp0_tready; + + wire [63:0] v2e_sfp1_tdata; + wire v2e_sfp1_tlast; + wire v2e_sfp1_tvalid; + wire v2e_sfp1_tready; + + // Ethernet to Vita + wire [63:0] e2v0_tdata; + wire e2v0_tlast; + wire e2v0_tvalid; + wire e2v0_tready; + + wire [63:0] e2v1_tdata; + wire e2v1_tlast; + wire e2v1_tvalid; + wire e2v1_tready; + + wire [63:0] e2v_sfp0_tdata; + wire e2v_sfp0_tlast; + wire e2v_sfp0_tvalid; + wire e2v_sfp0_tready; + + wire [63:0] e2v_sfp1_tdata; + wire e2v_sfp1_tlast; + wire e2v_sfp1_tvalid; + wire e2v_sfp1_tready; + + // Ethernet crossover + wire [63:0] e01_tdata, e10_tdata; + wire [3:0] e01_tuser, e10_tuser; + wire e01_tlast, e01_tvalid, e01_tready; + wire e10_tlast, e10_tvalid, e10_tready; + + + // DMA xport adapter to PS + wire [63:0] m_axis_dma_tdata; + wire [3:0] m_axis_dma_tuser; + wire m_axis_dma_tlast; + wire m_axis_dma_tready; + wire m_axis_dma_tvalid; + + wire [63:0] s_axis_dma_tdata; + wire [3:0] s_axis_dma_tdest; + wire s_axis_dma_tlast; + wire s_axis_dma_tready; + wire s_axis_dma_tvalid; + + // Misc + wire [31:0] sfp_port0_info; + wire [31:0] sfp_port1_info; + wire sfp0_link_up, sfp1_link_up; + wire [15:0] device_id; + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper 0: Network Interface (1/10G or Aurora) + // + ////////////////////////////////////////////////////////////////////// + + n3xx_mgt_channel_wrapper #( + .LANES(1), + `ifdef SFP0_10GBE + .PROTOCOL("10GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP0_AURORA + .PROTOCOL("Aurora"), + .MDIO_EN(1'b0), + `elsif SFP0_1GBE + .PROTOCOL("1GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP0_WR + .PROTOCOL("WhiteRabbit"), + .MDIO_EN(1'b0), + `endif + .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH(REG_AWIDTH), // Width of the address bus + .PORTNUM_BASE(8'd0) + ) sfp_wrapper_0 ( + .areset(global_rst), + .gt_refclk(sfp0_gt_refclk), + .gb_refclk(sfp0_gb_refclk), + .misc_clk(sfp0_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp0_tx_out_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + + .qpllreset(qpllreset_sfp0), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), + + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp0_gt_pll_lock), + + .txp(SFP_0_TX_P), + .txn(SFP_0_TX_N), + .rxp(SFP_0_RX_P), + .rxn(SFP_0_RX_N), + + .mod_present_n(SFP_0_I2C_NPRESENT), + .mod_rxlos(SFP_0_LOS), + .mod_tx_fault(SFP_0_TXFAULT), + .mod_tx_disable(SFP_0_TXDISABLE), + + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET0_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET0_AWVALID), + .s_axi_awready(M_AXI_NET0_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET0_WDATA), + .s_axi_wstrb(M_AXI_NET0_WSTRB), + .s_axi_wvalid(M_AXI_NET0_WVALID), + .s_axi_wready(M_AXI_NET0_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET0_BRESP), + .s_axi_bvalid(M_AXI_NET0_BVALID), + .s_axi_bready(M_AXI_NET0_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET0_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET0_ARVALID), + .s_axi_arready(M_AXI_NET0_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET0_RDATA), + .s_axi_rresp(M_AXI_NET0_RRESP), + .s_axi_rvalid(M_AXI_NET0_RVALID), + .s_axi_rready(M_AXI_NET0_RREADY), + + // Ethernet to Vita + .e2v_tdata(e2v_sfp0_tdata), + .e2v_tlast(e2v_sfp0_tlast), + .e2v_tvalid(e2v_sfp0_tvalid), + .e2v_tready(e2v_sfp0_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_sfp0_tdata), + .v2e_tlast(v2e_sfp0_tlast), + .v2e_tvalid(v2e_sfp0_tvalid), + .v2e_tready(v2e_sfp0_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp0_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp0_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp0_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp0_rx_tvalid_b), + .e2c_tready(arm_eth_sfp0_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp0_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp0_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp0_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp0_tx_tvalid_b), + .c2e_tready(arm_eth_sfp0_tx_tready_b), + + // White Rabbit Specific +`ifdef SFP0_WR + .wr_reset_n (~ps_gpio_out[48]), // reset for WR only + .wr_refclk (wr_refclk_buf), + .wr_dac_sclk (WB_DAC_SCLK), + .wr_dac_din (WB_DAC_DIN), + .wr_dac_clr_n (WB_DAC_NCLR), + .wr_dac_cs_n (WB_DAC_NSYNC), + .wr_dac_ldac_n(WB_DAC_NLDAC), + .wr_eeprom_scl_o(), // storage for delay characterization + .wr_eeprom_scl_i(1'b0), // temp + .wr_eeprom_sda_o(), + .wr_eeprom_sda_i(1'b0), // temp + .wr_uart_rx(wr_uart_rxd), // to/from PS + .wr_uart_tx(wr_uart_txd), + .mod_pps(pps_wr_refclk), // out, reference clock and pps + .mod_refclk(wr_ref_clk), + // WR Slave Port to PS + .wr_axi_aclk(m_axi_wr_clk), // out to PS + .wr_axi_aresetn(1'b1), // in + .wr_axi_awaddr(m_axi_wr_awaddr), + .wr_axi_awvalid(m_axi_wr_awvalid), + .wr_axi_awready(m_axi_wr_awready), + .wr_axi_wdata(m_axi_wr_wdata), + .wr_axi_wstrb(m_axi_wr_wstrb), + .wr_axi_wvalid(m_axi_wr_wvalid), + .wr_axi_wready(m_axi_wr_wready), + .wr_axi_bresp(m_axi_wr_bresp), + .wr_axi_bvalid(m_axi_wr_bvalid), + .wr_axi_bready(m_axi_wr_bready), + .wr_axi_araddr(m_axi_wr_araddr), + .wr_axi_arvalid(m_axi_wr_arvalid), + .wr_axi_arready(m_axi_wr_arready), + .wr_axi_rdata(m_axi_wr_rdata), + .wr_axi_rresp(m_axi_wr_rresp), + .wr_axi_rvalid(m_axi_wr_rvalid), + .wr_axi_rready(m_axi_wr_rready), + .wr_axi_rlast(), +`else + .wr_reset_n(1'b1), + .wr_refclk(1'b0), + .wr_eeprom_scl_i(1'b0), + .wr_eeprom_sda_i(1'b0), + .wr_uart_rx(1'b0), +`endif + + // Misc + .port_info(sfp_port0_info), + .device_id(device_id), + + // LED + .link_up(sfp0_link_up), + .activity(SFP_0_LED_A) + ); + + assign ps_gpio_in[60] = ps_gpio_tri[60] ? sfp0_link_up : ps_gpio_out[60]; + assign SFP_0_LED_B = sfp0_link_up; + +`ifndef SFP0_WR + assign WB_DAC_SCLK = 1'b0; + assign WB_DAC_DIN = 1'b0; + assign WB_DAC_NCLR = 1'b1; + assign WB_DAC_NSYNC = 1'b1; + assign WB_DAC_NLDAC = 1'b1; + assign pps_wr_refclk = 1'b0; + assign wr_ref_clk = 1'b0; +`endif + + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper 1: Network Interface (1/10G or Aurora) + // + ////////////////////////////////////////////////////////////////////// + + n3xx_mgt_channel_wrapper #( + .LANES(1), + `ifdef SFP1_10GBE + .PROTOCOL("10GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP1_AURORA + .PROTOCOL("Aurora"), + .MDIO_EN(1'b0), + `endif + .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH(REG_AWIDTH), // Width of the address bus + .PORTNUM_BASE(8'd1) + ) sfp_wrapper_1 ( + .areset(global_rst), + + .gt_refclk(sfp1_gt_refclk), + .gb_refclk(sfp1_gb_refclk), + .misc_clk(sfp1_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp1_tx_out_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + + .qpllreset(qpllreset_sfp1), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), + + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp1_gt_pll_lock), + + .txp(SFP_1_TX_P), + .txn(SFP_1_TX_N), + .rxp(SFP_1_RX_P), + .rxn(SFP_1_RX_N), + + .mod_rxlos(SFP_1_LOS), + .mod_tx_fault(SFP_1_TXFAULT), + .mod_tx_disable(SFP_1_TXDISABLE), + + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET1_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET1_AWVALID), + .s_axi_awready(M_AXI_NET1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET1_WDATA), + .s_axi_wstrb(M_AXI_NET1_WSTRB), + .s_axi_wvalid(M_AXI_NET1_WVALID), + .s_axi_wready(M_AXI_NET1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET1_BRESP), + .s_axi_bvalid(M_AXI_NET1_BVALID), + .s_axi_bready(M_AXI_NET1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET1_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET1_ARVALID), + .s_axi_arready(M_AXI_NET1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET1_RDATA), + .s_axi_rresp(M_AXI_NET1_RRESP), + .s_axi_rvalid(M_AXI_NET1_RVALID), + .s_axi_rready(M_AXI_NET1_RREADY), + + // Ethernet to Vita + .e2v_tdata(e2v_sfp1_tdata), + .e2v_tlast(e2v_sfp1_tlast), + .e2v_tvalid(e2v_sfp1_tvalid), + .e2v_tready(e2v_sfp1_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_sfp1_tdata), + .v2e_tlast(v2e_sfp1_tlast), + .v2e_tvalid(v2e_sfp1_tvalid), + .v2e_tready(v2e_sfp1_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp1_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp1_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp1_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp1_rx_tvalid_b), + .e2c_tready(arm_eth_sfp1_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp1_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp1_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp1_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp1_tx_tvalid_b), + .c2e_tready(arm_eth_sfp1_tx_tready_b), + + // Misc + .port_info(sfp_port1_info), + .device_id(device_id), + + // LED + .link_up(sfp1_link_up), + .activity(SFP_1_LED_A) + ); + + assign ps_gpio_in[61] = ps_gpio_tri[61] ? sfp1_link_up : ps_gpio_out[61]; + assign SFP_1_LED_B = sfp1_link_up; + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA 0 + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[0] = arm_eth0_rx_irq; + assign IRQ_F2P[1] = arm_eth0_tx_irq; + + assign {S_AXI_HP0_AWID, S_AXI_HP0_ARID} = 12'd0; + assign {S_AXI_GP0_AWID, S_AXI_GP0_ARID} = 10'd0; + +`ifdef QSFP_10GBE + // QSFP+ lanes connect to DMA engines and crossbar + // Connect first QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_qsfp_tx_tdata_b[0*64 +: 64] = arm_eth0_tx_tdata_b; + assign arm_eth_qsfp_tx_tvalid_b[0] = arm_eth0_tx_tvalid_b; + assign arm_eth_qsfp_tx_tlast_b[0] = arm_eth0_tx_tlast_b; + assign arm_eth0_tx_tready_b = arm_eth_qsfp_tx_tready_b[0]; + assign arm_eth_qsfp_tx_tuser_b[0*4 +: 4] = arm_eth0_tx_tuser_b; + assign arm_eth_qsfp_tx_tkeep_b[0*8 +: 8] = arm_eth0_tx_tkeep_b; + + assign arm_eth0_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[0*64 +: 64]; + assign arm_eth0_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[0]; + assign arm_eth0_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[0]; + assign arm_eth_qsfp_rx_tready_b[0] = arm_eth0_rx_tready_b; + assign arm_eth0_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[0*4 +: 4]; + assign arm_eth0_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[0*8 +: 8]; + + // Connect first QSFP+ 10 GbE port to the crossbar + assign v2e_qsfp_tdata[0*64 +: 64] = v2e0_tdata; + assign v2e_qsfp_tlast[0] = v2e0_tlast; + assign v2e_qsfp_tvalid[0] = v2e0_tvalid; + assign v2e0_tready = v2e_qsfp_tready[0]; + + assign e2v0_tdata = e2v_qsfp_tdata[0*64 +: 64]; + assign e2v0_tlast = e2v_qsfp_tlast[0]; + assign e2v0_tvalid = e2v_qsfp_tvalid[0]; + assign e2v_qsfp_tready[0] = e2v0_tready; + + // Connect second QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_qsfp_tx_tdata_b[1*64 +: 64] = arm_eth1_tx_tdata_b; + assign arm_eth_qsfp_tx_tvalid_b[1] = arm_eth1_tx_tvalid_b; + assign arm_eth_qsfp_tx_tlast_b[1] = arm_eth1_tx_tlast_b; + assign arm_eth1_tx_tready_b = arm_eth_qsfp_tx_tready_b[1]; + assign arm_eth_qsfp_tx_tuser_b[1*4 +: 4] = arm_eth1_tx_tuser_b; + assign arm_eth_qsfp_tx_tkeep_b[1*8 +: 8] = arm_eth1_tx_tkeep_b; + + assign arm_eth1_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[1*64 +: 64]; + assign arm_eth1_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[1]; + assign arm_eth1_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[1]; + assign arm_eth_qsfp_rx_tready_b[1] = arm_eth1_rx_tready_b; + assign arm_eth1_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[1*4 +: 4]; + assign arm_eth1_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[1*8 +: 8]; + + // Connect second QSFP+ 10 GbE port to the crossbar + assign v2e_qsfp_tdata[1*64 +: 64] = v2e1_tdata; + assign v2e_qsfp_tlast[1] = v2e1_tlast; + assign v2e_qsfp_tvalid[1] = v2e1_tvalid; + assign v2e1_tready = v2e_qsfp_tready[1]; + + assign e2v1_tdata = e2v_qsfp_tdata[1*64 +: 64]; + assign e2v1_tlast = e2v_qsfp_tlast[1]; + assign e2v1_tvalid = e2v_qsfp_tvalid[1]; + assign e2v_qsfp_tready[1] = e2v1_tready; +`else + // SFP+ ports connects to DMA engines and crossbar + // Connect first SFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_sfp0_tx_tdata_b = arm_eth0_tx_tdata_b; + assign arm_eth_sfp0_tx_tvalid_b = arm_eth0_tx_tvalid_b; + assign arm_eth_sfp0_tx_tlast_b = arm_eth0_tx_tlast_b; + assign arm_eth0_tx_tready_b = arm_eth_sfp0_tx_tready_b; + assign arm_eth_sfp0_tx_tuser_b = arm_eth0_tx_tuser_b; + assign arm_eth_sfp0_tx_tkeep_b = arm_eth0_tx_tkeep_b; + + assign arm_eth0_rx_tdata_b = arm_eth_sfp0_rx_tdata_b; + assign arm_eth0_rx_tvalid_b = arm_eth_sfp0_rx_tvalid_b; + assign arm_eth0_rx_tlast_b = arm_eth_sfp0_rx_tlast_b; + assign arm_eth_sfp0_rx_tready_b = arm_eth0_rx_tready_b; + assign arm_eth0_rx_tuser_b = arm_eth_sfp0_rx_tuser_b; + assign arm_eth0_rx_tkeep_b = arm_eth_sfp0_rx_tkeep_b; + + // Connect first SFP+ 10 GbE port to the crossbar + assign v2e_sfp0_tdata = v2e0_tdata; + assign v2e_sfp0_tlast = v2e0_tlast; + assign v2e_sfp0_tvalid = v2e0_tvalid; + assign v2e0_tready = v2e_sfp0_tready; + + assign e2v0_tdata = e2v_sfp0_tdata; + assign e2v0_tlast = e2v_sfp0_tlast; + assign e2v0_tvalid = e2v_sfp0_tvalid; + assign e2v_sfp0_tready = e2v0_tready; + + // Connect second SFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_sfp1_tx_tdata_b = arm_eth1_tx_tdata_b; + assign arm_eth_sfp1_tx_tvalid_b = arm_eth1_tx_tvalid_b; + assign arm_eth_sfp1_tx_tlast_b = arm_eth1_tx_tlast_b; + assign arm_eth1_tx_tready_b = arm_eth_sfp1_tx_tready_b; + assign arm_eth_sfp1_tx_tuser_b = arm_eth1_tx_tuser_b; + assign arm_eth_sfp1_tx_tkeep_b = arm_eth1_tx_tkeep_b; + + assign arm_eth1_rx_tdata_b = arm_eth_sfp1_rx_tdata_b; + assign arm_eth1_rx_tvalid_b = arm_eth_sfp1_rx_tvalid_b; + assign arm_eth1_rx_tlast_b = arm_eth_sfp1_rx_tlast_b; + assign arm_eth_sfp1_rx_tready_b = arm_eth1_rx_tready_b; + assign arm_eth1_rx_tuser_b = arm_eth_sfp1_rx_tuser_b; + assign arm_eth1_rx_tkeep_b = arm_eth_sfp1_rx_tkeep_b; + + // Connect first SFP+ 10 GbE port to the crossbar + assign v2e_sfp1_tdata = v2e1_tdata; + assign v2e_sfp1_tlast = v2e1_tlast; + assign v2e_sfp1_tvalid = v2e1_tvalid; + assign v2e1_tready = v2e_sfp1_tready; + + assign e2v1_tdata = e2v_sfp1_tdata; + assign e2v1_tlast = e2v_sfp1_tlast; + assign e2v1_tvalid = e2v_sfp1_tvalid; + assign e2v_sfp1_tready = e2v1_tready; + + // Don't actually instantiate DMA engines if protocols can't use them + `ifdef SFP0_AURORA + `define NO_ETH_DMA_0 + `elsif SFP0_WR + `define NO_ETH_DMA_0 + `endif + + `ifdef SFP1_AURORA + `define NO_ETH_DMA_1 + `endif +`endif + +`ifdef NO_ETH_DMA_0 + //If inst Aurora, tie off each axi/axi-lite interface + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_sfp0_eth_dma ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_ETH_DMA0_AWADDR), + .s_axi_awvalid(M_AXI_ETH_DMA0_AWVALID), + .s_axi_awready(M_AXI_ETH_DMA0_AWREADY), + + .s_axi_wdata(M_AXI_ETH_DMA0_WDATA), + .s_axi_wvalid(M_AXI_ETH_DMA0_WVALID), + .s_axi_wready(M_AXI_ETH_DMA0_WREADY), + + .s_axi_bresp(M_AXI_ETH_DMA0_BRESP), + .s_axi_bvalid(M_AXI_ETH_DMA0_BVALID), + .s_axi_bready(M_AXI_ETH_DMA0_BREADY), + + .s_axi_araddr(M_AXI_ETH_DMA0_ARADDR), + .s_axi_arvalid(M_AXI_ETH_DMA0_ARVALID), + .s_axi_arready(M_AXI_ETH_DMA0_ARREADY), + + .s_axi_rdata(M_AXI_ETH_DMA0_RDATA), + .s_axi_rresp(M_AXI_ETH_DMA0_RRESP), + .s_axi_rvalid(M_AXI_ETH_DMA0_RVALID), + .s_axi_rready(M_AXI_ETH_DMA0_RREADY) + + ); + //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off + assign S_AXI_GP0_AWADDR = 32'h0; + assign S_AXI_GP0_AWLEN = 8'h0; + assign S_AXI_GP0_AWSIZE = 4'h0; + assign S_AXI_GP0_AWBURST = 3'h0; + assign S_AXI_GP0_AWPROT = 3'h0; + assign S_AXI_GP0_AWCACHE = 4'h0; + assign S_AXI_GP0_AWVALID = 1'b0; + //S_AXI_GP0_AWREADY output from PS + assign S_AXI_GP0_WDATA = 32'h0; + assign S_AXI_GP0_WSTRB = 4'h0; + assign S_AXI_GP0_WLAST = 1'b0; + assign S_AXI_GP0_WVALID = 1'b0; + //S_AXI_GP0_WREADY output from PS + //S_AXI_GP0_BRESP + //S_AXI_GP0_BVALID + assign S_AXI_GP0_BREADY = 1'b1; + assign S_AXI_GP0_ARADDR = 32'h0; + assign S_AXI_GP0_ARLEN = 8'h0; + assign S_AXI_GP0_ARSIZE = 3'h0; + assign S_AXI_GP0_ARBURST = 2'h0; + assign S_AXI_GP0_ARPROT = 3'h0; + assign S_AXI_GP0_ARCACHE = 4'h0; + assign S_AXI_GP0_ARVALID = 1'b0; + //S_AXI_GP0_ARREADY + //S_AXI_GP0_RDATA + //S_AXI_GP0_RRESP + //S_AXI_GP0_RLAST + //S_AXI_GP0_RVALID + assign S_AXI_GP0_RREADY = 1'b1; + + //S_AXI_HP0 from axi_eth_dma + assign S_AXI_HP0_ARADDR = 32'h0; + assign S_AXI_HP0_ARLEN = 8'h0; + assign S_AXI_HP0_ARSIZE = 3'h0; + assign S_AXI_HP0_ARBURST = 2'h0; + assign S_AXI_HP0_ARPROT = 3'h0; + assign S_AXI_HP0_ARCACHE = 4'h0; + assign S_AXI_HP0_ARVALID = 1'b0; + //S_AXI_HP0_ARREADY + //S_AXI_HP0_RDATA + //S_AXI_HP0_RRESP + //S_AXI_HP0_RLAST + //S_AXI_HP0_RVALID + assign S_AXI_HP0_RREADY = 1'b1; + assign S_AXI_HP0_AWADDR = 32'h0; + assign S_AXI_HP0_AWLEN = 8'h0; + assign S_AXI_HP0_AWSIZE = 3'h0; + assign S_AXI_HP0_AWBURST = 2'h0; + assign S_AXI_HP0_AWPROT = 3'h0; + assign S_AXI_HP0_AWCACHE = 4'h0; + assign S_AXI_HP0_AWVALID = 1'b0; + //S_AXI_HP0_AWREADY + assign S_AXI_HP0_WDATA = 64'h0; + assign S_AXI_HP0_WSTRB = 8'h0; + assign S_AXI_HP0_WLAST = 1'b0; + assign S_AXI_HP0_WVALID = 1'b0; + //S_AXI_HP0_WREADY + //S_AXI_HP0_BRESP + //S_AXI_HP0_BVALID + assign S_AXI_HP0_BREADY = 1'b1; + +`else + + axi_eth_dma inst_axi_eth_dma0 ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(M_AXI_ETH_DMA0_AWADDR), + .s_axi_lite_awvalid(M_AXI_ETH_DMA0_AWVALID), + .s_axi_lite_awready(M_AXI_ETH_DMA0_AWREADY), + + .s_axi_lite_wdata(M_AXI_ETH_DMA0_WDATA), + .s_axi_lite_wvalid(M_AXI_ETH_DMA0_WVALID), + .s_axi_lite_wready(M_AXI_ETH_DMA0_WREADY), + + .s_axi_lite_bresp(M_AXI_ETH_DMA0_BRESP), + .s_axi_lite_bvalid(M_AXI_ETH_DMA0_BVALID), + .s_axi_lite_bready(M_AXI_ETH_DMA0_BREADY), + + .s_axi_lite_araddr(M_AXI_ETH_DMA0_ARADDR), + .s_axi_lite_arvalid(M_AXI_ETH_DMA0_ARVALID), + .s_axi_lite_arready(M_AXI_ETH_DMA0_ARREADY), + + .s_axi_lite_rdata(M_AXI_ETH_DMA0_RDATA), + .s_axi_lite_rresp(M_AXI_ETH_DMA0_RRESP), + .s_axi_lite_rvalid(M_AXI_ETH_DMA0_RVALID), + .s_axi_lite_rready(M_AXI_ETH_DMA0_RREADY), + + .m_axi_sg_awaddr(S_AXI_GP0_AWADDR), + .m_axi_sg_awlen(S_AXI_GP0_AWLEN), + .m_axi_sg_awsize(S_AXI_GP0_AWSIZE), + .m_axi_sg_awburst(S_AXI_GP0_AWBURST), + .m_axi_sg_awprot(S_AXI_GP0_AWPROT), + .m_axi_sg_awcache(S_AXI_GP0_AWCACHE), + .m_axi_sg_awvalid(S_AXI_GP0_AWVALID), + .m_axi_sg_awready(S_AXI_GP0_AWREADY), + .m_axi_sg_wdata(S_AXI_GP0_WDATA), + .m_axi_sg_wstrb(S_AXI_GP0_WSTRB), + .m_axi_sg_wlast(S_AXI_GP0_WLAST), + .m_axi_sg_wvalid(S_AXI_GP0_WVALID), + .m_axi_sg_wready(S_AXI_GP0_WREADY), + .m_axi_sg_bresp(S_AXI_GP0_BRESP), + .m_axi_sg_bvalid(S_AXI_GP0_BVALID), + .m_axi_sg_bready(S_AXI_GP0_BREADY), + .m_axi_sg_araddr(S_AXI_GP0_ARADDR), + .m_axi_sg_arlen(S_AXI_GP0_ARLEN), + .m_axi_sg_arsize(S_AXI_GP0_ARSIZE), + .m_axi_sg_arburst(S_AXI_GP0_ARBURST), + .m_axi_sg_arprot(S_AXI_GP0_ARPROT), + .m_axi_sg_arcache(S_AXI_GP0_ARCACHE), + .m_axi_sg_arvalid(S_AXI_GP0_ARVALID), + .m_axi_sg_arready(S_AXI_GP0_ARREADY), + .m_axi_sg_rdata(S_AXI_GP0_RDATA), + .m_axi_sg_rresp(S_AXI_GP0_RRESP), + .m_axi_sg_rlast(S_AXI_GP0_RLAST), + .m_axi_sg_rvalid(S_AXI_GP0_RVALID), + .m_axi_sg_rready(S_AXI_GP0_RREADY), + + .m_axi_mm2s_araddr(S_AXI_HP0_ARADDR), + .m_axi_mm2s_arlen(S_AXI_HP0_ARLEN), + .m_axi_mm2s_arsize(S_AXI_HP0_ARSIZE), + .m_axi_mm2s_arburst(S_AXI_HP0_ARBURST), + .m_axi_mm2s_arprot(S_AXI_HP0_ARPROT), + .m_axi_mm2s_arcache(S_AXI_HP0_ARCACHE), + .m_axi_mm2s_arvalid(S_AXI_HP0_ARVALID), + .m_axi_mm2s_arready(S_AXI_HP0_ARREADY), + .m_axi_mm2s_rdata(S_AXI_HP0_RDATA), + .m_axi_mm2s_rresp(S_AXI_HP0_RRESP), + .m_axi_mm2s_rlast(S_AXI_HP0_RLAST), + .m_axi_mm2s_rvalid(S_AXI_HP0_RVALID), + .m_axi_mm2s_rready(S_AXI_HP0_RREADY), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth0_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth0_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth0_tx_tvalid), + .m_axis_mm2s_tready(arm_eth0_tx_tready), + .m_axis_mm2s_tlast(arm_eth0_tx_tlast), + + .m_axi_s2mm_awaddr(S_AXI_HP0_AWADDR), + .m_axi_s2mm_awlen(S_AXI_HP0_AWLEN), + .m_axi_s2mm_awsize(S_AXI_HP0_AWSIZE), + .m_axi_s2mm_awburst(S_AXI_HP0_AWBURST), + .m_axi_s2mm_awprot(S_AXI_HP0_AWPROT), + .m_axi_s2mm_awcache(S_AXI_HP0_AWCACHE), + .m_axi_s2mm_awvalid(S_AXI_HP0_AWVALID), + .m_axi_s2mm_awready(S_AXI_HP0_AWREADY), + .m_axi_s2mm_wdata(S_AXI_HP0_WDATA), + .m_axi_s2mm_wstrb(S_AXI_HP0_WSTRB), + .m_axi_s2mm_wlast(S_AXI_HP0_WLAST), + .m_axi_s2mm_wvalid(S_AXI_HP0_WVALID), + .m_axi_s2mm_wready(S_AXI_HP0_WREADY), + .m_axi_s2mm_bresp(S_AXI_HP0_BRESP), + .m_axi_s2mm_bvalid(S_AXI_HP0_BVALID), + .m_axi_s2mm_bready(S_AXI_HP0_BREADY), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth0_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth0_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth0_rx_tvalid), + .s_axis_s2mm_tready(arm_eth0_rx_tready), + .s_axis_s2mm_tlast(arm_eth0_rx_tlast), + + .mm2s_introut(arm_eth0_tx_irq), + .s2mm_introut(arm_eth0_rx_irq), + .axi_dma_tstvec() + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_tx_0_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth0_tx_tlast, arm_eth0_tx_tkeep, arm_eth0_tx_tdata}), + .i_tvalid(arm_eth0_tx_tvalid), + .i_tready(arm_eth0_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth0_tx_tlast_b, arm_eth0_tx_tkeep_b, arm_eth0_tx_tdata_b}), + .o_tvalid(arm_eth0_tx_tvalid_b), + .o_tready(arm_eth0_tx_tready_b) + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_rx_0_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth0_rx_tlast_b, arm_eth0_rx_tkeep_b, arm_eth0_rx_tdata_b}), + .i_tvalid(arm_eth0_rx_tvalid_b), + .i_tready(arm_eth0_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth0_rx_tlast, arm_eth0_rx_tkeep, arm_eth0_rx_tdata}), + .o_tvalid(arm_eth0_rx_tvalid), + .o_tready(arm_eth0_rx_tready) + ); + +`endif + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA 1 + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[2] = arm_eth1_rx_irq; + assign IRQ_F2P[3] = arm_eth1_tx_irq; + + assign {S_AXI_HP1_AWID, S_AXI_HP1_ARID} = 12'd0; + assign {S_AXI_GP1_AWID, S_AXI_GP1_ARID} = 10'd0; + +`ifdef NO_ETH_DMA_1 + //If inst Aurora, tie off each axi/axi-lite interface + axi_dummy #(.DEC_ERR(1'b0)) inst_axi_dummy_sfp1_eth_dma + ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_ETH_DMA1_AWADDR), + .s_axi_awvalid(M_AXI_ETH_DMA1_AWVALID), + .s_axi_awready(M_AXI_ETH_DMA1_AWREADY), + + .s_axi_wdata(M_AXI_ETH_DMA1_WDATA), + .s_axi_wvalid(M_AXI_ETH_DMA1_WVALID), + .s_axi_wready(M_AXI_ETH_DMA1_WREADY), + + .s_axi_bresp(M_AXI_ETH_DMA1_BRESP), + .s_axi_bvalid(M_AXI_ETH_DMA1_BVALID), + .s_axi_bready(M_AXI_ETH_DMA1_BREADY), + + .s_axi_araddr(M_AXI_ETH_DMA1_ARADDR), + .s_axi_arvalid(M_AXI_ETH_DMA1_ARVALID), + .s_axi_arready(M_AXI_ETH_DMA1_ARREADY), + + .s_axi_rdata(M_AXI_ETH_DMA1_RDATA), + .s_axi_rresp(M_AXI_ETH_DMA1_RRESP), + .s_axi_rvalid(M_AXI_ETH_DMA1_RVALID), + .s_axi_rready(M_AXI_ETH_DMA1_RREADY) + + ); + //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off + assign S_AXI_GP1_AWADDR = 32'h0; + assign S_AXI_GP1_AWLEN = 8'h0; + assign S_AXI_GP1_AWSIZE = 4'h0; + assign S_AXI_GP1_AWBURST = 3'h0; + assign S_AXI_GP1_AWPROT = 3'h0; + assign S_AXI_GP1_AWCACHE = 4'h0; + assign S_AXI_GP1_AWVALID = 1'b0; + //S_AXI_GP1_AWREADY output from PS + assign S_AXI_GP1_WDATA = 32'h0; + assign S_AXI_GP1_WSTRB = 4'h0; + assign S_AXI_GP1_WLAST = 1'b0; + assign S_AXI_GP1_WVALID = 1'b0; + //S_AXI_GP1_WREADY output from PS + //S_AXI_GP1_BRESP + //S_AXI_GP1_BVALID + assign S_AXI_GP1_BREADY = 1'b1; + assign S_AXI_GP1_ARADDR = 32'h0; + assign S_AXI_GP1_ARLEN = 8'h0; + assign S_AXI_GP1_ARSIZE = 3'h0; + assign S_AXI_GP1_ARBURST = 2'h0; + assign S_AXI_GP1_ARPROT = 3'h0; + assign S_AXI_GP1_ARCACHE = 4'h0; + assign S_AXI_GP1_ARVALID = 1'b0; + //S_AXI_GP1_ARREADY + //S_AXI_GP1_RDATA + //S_AXI_GP1_RRESP + //S_AXI_GP1_RLAST + //S_AXI_GP1_RVALID + assign S_AXI_GP1_RREADY = 1'b1; + + //S_AXI_HP0 from axi_eth_dma + assign S_AXI_HP1_ARADDR = 32'h0; + assign S_AXI_HP1_ARLEN = 8'h0; + assign S_AXI_HP1_ARSIZE = 3'h0; + assign S_AXI_HP1_ARBURST = 2'h0; + assign S_AXI_HP1_ARPROT = 3'h0; + assign S_AXI_HP1_ARCACHE = 4'h0; + assign S_AXI_HP1_ARVALID = 1'b0; + //S_AXI_HP1_ARREADY + //S_AXI_HP1_RDATA + //S_AXI_HP1_RRESP + //S_AXI_HP1_RLAST + //S_AXI_HP1_RVALID + assign S_AXI_HP1_RREADY = 1'b1; + assign S_AXI_HP1_AWADDR = 32'h0; + assign S_AXI_HP1_AWLEN = 8'h0; + assign S_AXI_HP1_AWSIZE = 3'h0; + assign S_AXI_HP1_AWBURST = 2'h0; + assign S_AXI_HP1_AWPROT = 3'h0; + assign S_AXI_HP1_AWCACHE = 4'h0; + assign S_AXI_HP1_AWVALID = 1'b0; + //S_AXI_HP1_AWREADY + assign S_AXI_HP1_WDATA = 64'h0; + assign S_AXI_HP1_WSTRB = 8'h0; + assign S_AXI_HP1_WLAST = 1'b0; + assign S_AXI_HP1_WVALID = 1'b0; + //S_AXI_HP1_WREADY + //S_AXI_HP1_BRESP + //S_AXI_HP1_BVALID + assign S_AXI_HP1_BREADY = 1'b1; + +`else + + axi_eth_dma inst_axi_eth_dma1 ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(M_AXI_ETH_DMA1_AWADDR), + .s_axi_lite_awvalid(M_AXI_ETH_DMA1_AWVALID), + .s_axi_lite_awready(M_AXI_ETH_DMA1_AWREADY), + + .s_axi_lite_wdata(M_AXI_ETH_DMA1_WDATA), + .s_axi_lite_wvalid(M_AXI_ETH_DMA1_WVALID), + .s_axi_lite_wready(M_AXI_ETH_DMA1_WREADY), + + .s_axi_lite_bresp(M_AXI_ETH_DMA1_BRESP), + .s_axi_lite_bvalid(M_AXI_ETH_DMA1_BVALID), + .s_axi_lite_bready(M_AXI_ETH_DMA1_BREADY), + + .s_axi_lite_araddr(M_AXI_ETH_DMA1_ARADDR), + .s_axi_lite_arvalid(M_AXI_ETH_DMA1_ARVALID), + .s_axi_lite_arready(M_AXI_ETH_DMA1_ARREADY), + + .s_axi_lite_rdata(M_AXI_ETH_DMA1_RDATA), + .s_axi_lite_rresp(M_AXI_ETH_DMA1_RRESP), + .s_axi_lite_rvalid(M_AXI_ETH_DMA1_RVALID), + .s_axi_lite_rready(M_AXI_ETH_DMA1_RREADY), + + .m_axi_sg_awaddr(S_AXI_GP1_AWADDR), + .m_axi_sg_awlen(S_AXI_GP1_AWLEN), + .m_axi_sg_awsize(S_AXI_GP1_AWSIZE), + .m_axi_sg_awburst(S_AXI_GP1_AWBURST), + .m_axi_sg_awprot(S_AXI_GP1_AWPROT), + .m_axi_sg_awcache(S_AXI_GP1_AWCACHE), + .m_axi_sg_awvalid(S_AXI_GP1_AWVALID), + .m_axi_sg_awready(S_AXI_GP1_AWREADY), + .m_axi_sg_wdata(S_AXI_GP1_WDATA), + .m_axi_sg_wstrb(S_AXI_GP1_WSTRB), + .m_axi_sg_wlast(S_AXI_GP1_WLAST), + .m_axi_sg_wvalid(S_AXI_GP1_WVALID), + .m_axi_sg_wready(S_AXI_GP1_WREADY), + .m_axi_sg_bresp(S_AXI_GP1_BRESP), + .m_axi_sg_bvalid(S_AXI_GP1_BVALID), + .m_axi_sg_bready(S_AXI_GP1_BREADY), + .m_axi_sg_araddr(S_AXI_GP1_ARADDR), + .m_axi_sg_arlen(S_AXI_GP1_ARLEN), + .m_axi_sg_arsize(S_AXI_GP1_ARSIZE), + .m_axi_sg_arburst(S_AXI_GP1_ARBURST), + .m_axi_sg_arprot(S_AXI_GP1_ARPROT), + .m_axi_sg_arcache(S_AXI_GP1_ARCACHE), + .m_axi_sg_arvalid(S_AXI_GP1_ARVALID), + .m_axi_sg_arready(S_AXI_GP1_ARREADY), + .m_axi_sg_rdata(S_AXI_GP1_RDATA), + .m_axi_sg_rresp(S_AXI_GP1_RRESP), + .m_axi_sg_rlast(S_AXI_GP1_RLAST), + .m_axi_sg_rvalid(S_AXI_GP1_RVALID), + .m_axi_sg_rready(S_AXI_GP1_RREADY), + + .m_axi_mm2s_araddr(S_AXI_HP1_ARADDR), + .m_axi_mm2s_arlen(S_AXI_HP1_ARLEN), + .m_axi_mm2s_arsize(S_AXI_HP1_ARSIZE), + .m_axi_mm2s_arburst(S_AXI_HP1_ARBURST), + .m_axi_mm2s_arprot(S_AXI_HP1_ARPROT), + .m_axi_mm2s_arcache(S_AXI_HP1_ARCACHE), + .m_axi_mm2s_arvalid(S_AXI_HP1_ARVALID), + .m_axi_mm2s_arready(S_AXI_HP1_ARREADY), + .m_axi_mm2s_rdata(S_AXI_HP1_RDATA), + .m_axi_mm2s_rresp(S_AXI_HP1_RRESP), + .m_axi_mm2s_rlast(S_AXI_HP1_RLAST), + .m_axi_mm2s_rvalid(S_AXI_HP1_RVALID), + .m_axi_mm2s_rready(S_AXI_HP1_RREADY), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth1_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth1_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth1_tx_tvalid), + .m_axis_mm2s_tready(arm_eth1_tx_tready), + .m_axis_mm2s_tlast(arm_eth1_tx_tlast), + + .m_axi_s2mm_awaddr(S_AXI_HP1_AWADDR), + .m_axi_s2mm_awlen(S_AXI_HP1_AWLEN), + .m_axi_s2mm_awsize(S_AXI_HP1_AWSIZE), + .m_axi_s2mm_awburst(S_AXI_HP1_AWBURST), + .m_axi_s2mm_awprot(S_AXI_HP1_AWPROT), + .m_axi_s2mm_awcache(S_AXI_HP1_AWCACHE), + .m_axi_s2mm_awvalid(S_AXI_HP1_AWVALID), + .m_axi_s2mm_awready(S_AXI_HP1_AWREADY), + .m_axi_s2mm_wdata(S_AXI_HP1_WDATA), + .m_axi_s2mm_wstrb(S_AXI_HP1_WSTRB), + .m_axi_s2mm_wlast(S_AXI_HP1_WLAST), + .m_axi_s2mm_wvalid(S_AXI_HP1_WVALID), + .m_axi_s2mm_wready(S_AXI_HP1_WREADY), + .m_axi_s2mm_bresp(S_AXI_HP1_BRESP), + .m_axi_s2mm_bvalid(S_AXI_HP1_BVALID), + .m_axi_s2mm_bready(S_AXI_HP1_BREADY), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth1_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth1_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth1_rx_tvalid), + .s_axis_s2mm_tready(arm_eth1_rx_tready), + .s_axis_s2mm_tlast(arm_eth1_rx_tlast), + + .mm2s_introut(arm_eth1_tx_irq), + .s2mm_introut(arm_eth1_rx_irq), + .axi_dma_tstvec() + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_tx_1_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth1_tx_tlast, arm_eth1_tx_tkeep, arm_eth1_tx_tdata}), + .i_tvalid(arm_eth1_tx_tvalid), + .i_tready(arm_eth1_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth1_tx_tlast_b, arm_eth1_tx_tkeep_b, arm_eth1_tx_tdata_b}), + .o_tvalid(arm_eth1_tx_tvalid_b), + .o_tready(arm_eth1_tx_tready_b) + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_rx_1_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth1_rx_tlast_b, arm_eth1_rx_tkeep_b, arm_eth1_rx_tdata_b}), + .i_tvalid(arm_eth1_rx_tvalid_b), + .i_tready(arm_eth1_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth1_rx_tlast, arm_eth1_rx_tkeep, arm_eth1_rx_tdata}), + .o_tvalid(arm_eth1_rx_tvalid), + .o_tready(arm_eth1_rx_tready) + ); +`endif + + ///////////////////////////////////////////////////////////////////// + // + // Processing System + // + ////////////////////////////////////////////////////////////////////// + + wire spi0_sclk; + wire spi0_mosi; + wire spi0_miso; + wire spi0_ss0; + wire spi0_ss1; + wire spi0_ss2; + wire spi1_sclk; + wire spi1_mosi; + wire spi1_miso; + wire spi1_ss0; + wire spi1_ss1; + wire spi1_ss2; + + assign ps_gpio_in[10] = DBA_MYK_INTRQ; +`ifndef N300 + assign ps_gpio_in[11] = DBB_MYK_INTRQ; +`else + assign ps_gpio_in[11] = 1'b0; +`endif + + // Processing System + n310_ps_bd inst_n310_ps ( + .SPI0_SCLK_I(1'b0), + .SPI0_SCLK_O(spi0_sclk), + .SPI0_SCLK_T(), + .SPI0_MOSI_I(1'b0), + .SPI0_MOSI_O(spi0_mosi), + .SPI0_MOSI_T(), + .SPI0_MISO_I(spi0_miso), + .SPI0_MISO_O(), + .SPI0_MISO_T(), + .SPI0_SS_I(1'b1), + .SPI0_SS_O(spi0_ss0), + .SPI0_SS1_O(spi0_ss1), + .SPI0_SS2_O(spi0_ss2), + .SPI0_SS_T(), + + `ifndef N300 + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(spi1_sclk), + .SPI1_SCLK_T(), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(spi1_mosi), + .SPI1_MOSI_T(), + .SPI1_MISO_I(spi1_miso), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_SS_I(1'b1), + .SPI1_SS_O(spi1_ss0), + .SPI1_SS1_O(spi1_ss1), + .SPI1_SS2_O(spi1_ss2), + .SPI1_SS_T(), + `else + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(), + .SPI1_SCLK_T(), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(), + .SPI1_MOSI_T(), + .SPI1_MISO_I(1'b0), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_SS_I(1'b1), + .SPI1_SS_O(), + .SPI1_SS1_O(), + .SPI1_SS2_O(), + .SPI1_SS_T(), + `endif + + .bus_clk(bus_clk), + .bus_rstn(~bus_rst), + .clk40(clk40), + .clk40_rstn(clk40_rstn), + + .M_AXI_ETH_DMA0_araddr(M_AXI_ETH_DMA0_ARADDR), + .M_AXI_ETH_DMA0_arprot(), + .M_AXI_ETH_DMA0_arready(M_AXI_ETH_DMA0_ARREADY), + .M_AXI_ETH_DMA0_arvalid(M_AXI_ETH_DMA0_ARVALID), + + .M_AXI_ETH_DMA0_awaddr(M_AXI_ETH_DMA0_AWADDR), + .M_AXI_ETH_DMA0_awprot(), + .M_AXI_ETH_DMA0_awready(M_AXI_ETH_DMA0_AWREADY), + .M_AXI_ETH_DMA0_awvalid(M_AXI_ETH_DMA0_AWVALID), + + .M_AXI_ETH_DMA0_wdata(M_AXI_ETH_DMA0_WDATA), + .M_AXI_ETH_DMA0_wready(M_AXI_ETH_DMA0_WREADY), + .M_AXI_ETH_DMA0_wstrb(M_AXI_ETH_DMA0_WSTRB), + .M_AXI_ETH_DMA0_wvalid(M_AXI_ETH_DMA0_WVALID), + + .M_AXI_ETH_DMA0_rdata(M_AXI_ETH_DMA0_RDATA), + .M_AXI_ETH_DMA0_rready(M_AXI_ETH_DMA0_RREADY), + .M_AXI_ETH_DMA0_rresp(M_AXI_ETH_DMA0_RRESP), + .M_AXI_ETH_DMA0_rvalid(M_AXI_ETH_DMA0_RVALID), + + .M_AXI_ETH_DMA0_bready(M_AXI_ETH_DMA0_BREADY), + .M_AXI_ETH_DMA0_bresp(M_AXI_ETH_DMA0_BRESP), + .M_AXI_ETH_DMA0_bvalid(M_AXI_ETH_DMA0_BVALID), + + .M_AXI_ETH_DMA1_araddr(M_AXI_ETH_DMA1_ARADDR), + .M_AXI_ETH_DMA1_arprot(), + .M_AXI_ETH_DMA1_arready(M_AXI_ETH_DMA1_ARREADY), + .M_AXI_ETH_DMA1_arvalid(M_AXI_ETH_DMA1_ARVALID), + + .M_AXI_ETH_DMA1_awaddr(M_AXI_ETH_DMA1_AWADDR), + .M_AXI_ETH_DMA1_awprot(), + .M_AXI_ETH_DMA1_awready(M_AXI_ETH_DMA1_AWREADY), + .M_AXI_ETH_DMA1_awvalid(M_AXI_ETH_DMA1_AWVALID), + + .M_AXI_ETH_DMA1_bready(M_AXI_ETH_DMA1_BREADY), + .M_AXI_ETH_DMA1_bresp(M_AXI_ETH_DMA1_BRESP), + .M_AXI_ETH_DMA1_bvalid(M_AXI_ETH_DMA1_BVALID), + + .M_AXI_ETH_DMA1_rdata(M_AXI_ETH_DMA1_RDATA), + .M_AXI_ETH_DMA1_rready(M_AXI_ETH_DMA1_RREADY), + .M_AXI_ETH_DMA1_rresp(M_AXI_ETH_DMA1_RRESP), + .M_AXI_ETH_DMA1_rvalid(M_AXI_ETH_DMA1_RVALID), + + .M_AXI_ETH_DMA1_wdata(M_AXI_ETH_DMA1_WDATA), + .M_AXI_ETH_DMA1_wready(M_AXI_ETH_DMA1_WREADY), + .M_AXI_ETH_DMA1_wstrb(M_AXI_ETH_DMA1_WSTRB), + .M_AXI_ETH_DMA1_wvalid(M_AXI_ETH_DMA1_WVALID), + + .M_AXI_JESD0_araddr(M_AXI_JESD0_ARADDR), + .M_AXI_JESD0_arprot(), + .M_AXI_JESD0_arready(M_AXI_JESD0_ARREADY), + .M_AXI_JESD0_arvalid(M_AXI_JESD0_ARVALID), + + .M_AXI_JESD0_awaddr(M_AXI_JESD0_AWADDR), + .M_AXI_JESD0_awprot(), + .M_AXI_JESD0_awready(M_AXI_JESD0_AWREADY), + .M_AXI_JESD0_awvalid(M_AXI_JESD0_AWVALID), + + .M_AXI_JESD0_bready(M_AXI_JESD0_BREADY), + .M_AXI_JESD0_bresp(M_AXI_JESD0_BRESP), + .M_AXI_JESD0_bvalid(M_AXI_JESD0_BVALID), + + .M_AXI_JESD0_rdata(M_AXI_JESD0_RDATA), + .M_AXI_JESD0_rready(M_AXI_JESD0_RREADY), + .M_AXI_JESD0_rresp(M_AXI_JESD0_RRESP), + .M_AXI_JESD0_rvalid(M_AXI_JESD0_RVALID), + + .M_AXI_JESD0_wdata(M_AXI_JESD0_WDATA), + .M_AXI_JESD0_wready(M_AXI_JESD0_WREADY), + .M_AXI_JESD0_wstrb(M_AXI_JESD0_WSTRB), + .M_AXI_JESD0_wvalid(M_AXI_JESD0_WVALID), + + .M_AXI_JESD1_araddr(M_AXI_JESD1_ARADDR), + .M_AXI_JESD1_arprot(), + .M_AXI_JESD1_arready(M_AXI_JESD1_ARREADY), + .M_AXI_JESD1_arvalid(M_AXI_JESD1_ARVALID), + + .M_AXI_JESD1_awaddr(M_AXI_JESD1_AWADDR), + .M_AXI_JESD1_awprot(), + .M_AXI_JESD1_awready(M_AXI_JESD1_AWREADY), + .M_AXI_JESD1_awvalid(M_AXI_JESD1_AWVALID), + + .M_AXI_JESD1_bready(M_AXI_JESD1_BREADY), + .M_AXI_JESD1_bresp(M_AXI_JESD1_BRESP), + .M_AXI_JESD1_bvalid(M_AXI_JESD1_BVALID), + + .M_AXI_JESD1_rdata(M_AXI_JESD1_RDATA), + .M_AXI_JESD1_rready(M_AXI_JESD1_RREADY), + .M_AXI_JESD1_rresp(M_AXI_JESD1_RRESP), + .M_AXI_JESD1_rvalid(M_AXI_JESD1_RVALID), + + .M_AXI_JESD1_wdata(M_AXI_JESD1_WDATA), + .M_AXI_JESD1_wready(M_AXI_JESD1_WREADY), + .M_AXI_JESD1_wstrb(M_AXI_JESD1_WSTRB), + .M_AXI_JESD1_wvalid(M_AXI_JESD1_WVALID), + + .M_AXI_NET0_araddr(M_AXI_NET0_ARADDR), + .M_AXI_NET0_arprot(), + .M_AXI_NET0_arready(M_AXI_NET0_ARREADY), + .M_AXI_NET0_arvalid(M_AXI_NET0_ARVALID), + + .M_AXI_NET0_awaddr(M_AXI_NET0_AWADDR), + .M_AXI_NET0_awprot(), + .M_AXI_NET0_awready(M_AXI_NET0_AWREADY), + .M_AXI_NET0_awvalid(M_AXI_NET0_AWVALID), + + .M_AXI_NET0_bready(M_AXI_NET0_BREADY), + .M_AXI_NET0_bresp(M_AXI_NET0_BRESP), + .M_AXI_NET0_bvalid(M_AXI_NET0_BVALID), + + .M_AXI_NET0_rdata(M_AXI_NET0_RDATA), + .M_AXI_NET0_rready(M_AXI_NET0_RREADY), + .M_AXI_NET0_rresp(M_AXI_NET0_RRESP), + .M_AXI_NET0_rvalid(M_AXI_NET0_RVALID), + + .M_AXI_NET0_wdata(M_AXI_NET0_WDATA), + .M_AXI_NET0_wready(M_AXI_NET0_WREADY), + .M_AXI_NET0_wstrb(M_AXI_NET0_WSTRB), + .M_AXI_NET0_wvalid(M_AXI_NET0_WVALID), + + .M_AXI_NET1_araddr(M_AXI_NET1_ARADDR), + .M_AXI_NET1_arprot(), + .M_AXI_NET1_arready(M_AXI_NET1_ARREADY), + .M_AXI_NET1_arvalid(M_AXI_NET1_ARVALID), + + .M_AXI_NET1_awaddr(M_AXI_NET1_AWADDR), + .M_AXI_NET1_awprot(), + .M_AXI_NET1_awready(M_AXI_NET1_AWREADY), + .M_AXI_NET1_awvalid(M_AXI_NET1_AWVALID), + + .M_AXI_NET1_bready(M_AXI_NET1_BREADY), + .M_AXI_NET1_bresp(M_AXI_NET1_BRESP), + .M_AXI_NET1_bvalid(M_AXI_NET1_BVALID), + + .M_AXI_NET1_rdata(M_AXI_NET1_RDATA), + .M_AXI_NET1_rready(M_AXI_NET1_RREADY), + .M_AXI_NET1_rresp(M_AXI_NET1_RRESP), + .M_AXI_NET1_rvalid(M_AXI_NET1_RVALID), + + .M_AXI_NET1_wdata(M_AXI_NET1_WDATA), + .M_AXI_NET1_wready(M_AXI_NET1_WREADY), + .M_AXI_NET1_wstrb(M_AXI_NET1_WSTRB), + .M_AXI_NET1_wvalid(M_AXI_NET1_WVALID), + + .M_AXI_NET2_araddr(M_AXI_NET2_ARADDR), + .M_AXI_NET2_arprot(), + .M_AXI_NET2_arready(M_AXI_NET2_ARREADY), + .M_AXI_NET2_arvalid(M_AXI_NET2_ARVALID), + + .M_AXI_NET2_awaddr(M_AXI_NET2_AWADDR), + .M_AXI_NET2_awprot(), + .M_AXI_NET2_awready(M_AXI_NET2_AWREADY), + .M_AXI_NET2_awvalid(M_AXI_NET2_AWVALID), + + .M_AXI_NET2_bready(M_AXI_NET2_BREADY), + .M_AXI_NET2_bresp(M_AXI_NET2_BRESP), + .M_AXI_NET2_bvalid(M_AXI_NET2_BVALID), + + .M_AXI_NET2_rdata(M_AXI_NET2_RDATA), + .M_AXI_NET2_rready(M_AXI_NET2_RREADY), + .M_AXI_NET2_rresp(M_AXI_NET2_RRESP), + .M_AXI_NET2_rvalid(M_AXI_NET2_RVALID), + + .M_AXI_NET2_wdata(M_AXI_NET2_WDATA), + .M_AXI_NET2_wready(M_AXI_NET2_WREADY), + .M_AXI_NET2_wstrb(M_AXI_NET2_WSTRB), + .M_AXI_NET2_wvalid(M_AXI_NET2_WVALID), + + .M_AXI_WR_CLK(m_axi_wr_clk), + .M_AXI_WR_RSTn(1'b1), + .M_AXI_WR_araddr(m_axi_wr_araddr), + .M_AXI_WR_arready(m_axi_wr_arready), + .M_AXI_WR_arvalid(m_axi_wr_arvalid), + .M_AXI_WR_awaddr(m_axi_wr_awaddr), + .M_AXI_WR_awready(m_axi_wr_awready), + .M_AXI_WR_awvalid(m_axi_wr_awvalid), + .M_AXI_WR_bready(m_axi_wr_bready), + .M_AXI_WR_bresp(m_axi_wr_bresp), + .M_AXI_WR_bvalid(m_axi_wr_bvalid), + .M_AXI_WR_rdata(m_axi_wr_rdata), + .M_AXI_WR_rready(m_axi_wr_rready), + .M_AXI_WR_rresp(m_axi_wr_rresp), + .M_AXI_WR_rvalid(m_axi_wr_rvalid), + .M_AXI_WR_wdata(m_axi_wr_wdata), + .M_AXI_WR_wready(m_axi_wr_wready), + .M_AXI_WR_wstrb(m_axi_wr_wstrb), + .M_AXI_WR_wvalid(m_axi_wr_wvalid), + + .M_AXI_XBAR_araddr(M_AXI_XBAR_ARADDR), + .M_AXI_XBAR_arprot(), + .M_AXI_XBAR_arready(M_AXI_XBAR_ARREADY), + .M_AXI_XBAR_arvalid(M_AXI_XBAR_ARVALID), + + .M_AXI_XBAR_awaddr(M_AXI_XBAR_AWADDR), + .M_AXI_XBAR_awprot(), + .M_AXI_XBAR_awready(M_AXI_XBAR_AWREADY), + .M_AXI_XBAR_awvalid(M_AXI_XBAR_AWVALID), + + .M_AXI_XBAR_bready(M_AXI_XBAR_BREADY), + .M_AXI_XBAR_bresp(M_AXI_XBAR_BRESP), + .M_AXI_XBAR_bvalid(M_AXI_XBAR_BVALID), + + .M_AXI_XBAR_rdata(M_AXI_XBAR_RDATA), + .M_AXI_XBAR_rready(M_AXI_XBAR_RREADY), + .M_AXI_XBAR_rresp(M_AXI_XBAR_RRESP), + .M_AXI_XBAR_rvalid(M_AXI_XBAR_RVALID), + + .M_AXI_XBAR_wdata(M_AXI_XBAR_WDATA), + .M_AXI_XBAR_wready(M_AXI_XBAR_WREADY), + .M_AXI_XBAR_wstrb(M_AXI_XBAR_WSTRB), + .M_AXI_XBAR_wvalid(M_AXI_XBAR_WVALID), + + .S_AXI_GP0_ACLK(clk40), + .S_AXI_GP0_ARESETN(clk40_rstn), + .S_AXI_GP0_araddr(S_AXI_GP0_ARADDR), + .S_AXI_GP0_arburst(S_AXI_GP0_ARBURST), + .S_AXI_GP0_arcache(S_AXI_GP0_ARCACHE), + .S_AXI_GP0_arid(S_AXI_GP0_ARID), + .S_AXI_GP0_arlen(S_AXI_GP0_ARLEN), + .S_AXI_GP0_arlock(1'b0), + .S_AXI_GP0_arprot(S_AXI_GP0_ARPROT), + .S_AXI_GP0_arqos(4'b0000), + .S_AXI_GP0_arready(S_AXI_GP0_ARREADY), + .S_AXI_GP0_arsize(S_AXI_GP0_ARSIZE), + .S_AXI_GP0_arvalid(S_AXI_GP0_ARVALID), + .S_AXI_GP0_awaddr(S_AXI_GP0_AWADDR), + .S_AXI_GP0_awburst(S_AXI_GP0_AWBURST), + .S_AXI_GP0_awcache(S_AXI_GP0_AWCACHE), + .S_AXI_GP0_awid(S_AXI_GP0_AWID), + .S_AXI_GP0_awlen(S_AXI_GP0_AWLEN), + .S_AXI_GP0_awlock(1'b0), + .S_AXI_GP0_awprot(S_AXI_GP0_AWPROT), + .S_AXI_GP0_awqos(4'b0000), + .S_AXI_GP0_awregion(4'b0000), + .S_AXI_GP0_awready(S_AXI_GP0_AWREADY), + .S_AXI_GP0_awsize(S_AXI_GP0_AWSIZE), + .S_AXI_GP0_awvalid(S_AXI_GP0_AWVALID), + .S_AXI_GP0_bid(), + .S_AXI_GP0_bready(S_AXI_GP0_BREADY), + .S_AXI_GP0_bresp(S_AXI_GP0_BRESP), + .S_AXI_GP0_bvalid(S_AXI_GP0_BVALID), + .S_AXI_GP0_rdata(S_AXI_GP0_RDATA), + .S_AXI_GP0_rid(), + .S_AXI_GP0_rlast(S_AXI_GP0_RLAST), + .S_AXI_GP0_rready(S_AXI_GP0_RREADY), + .S_AXI_GP0_rresp(S_AXI_GP0_RRESP), + .S_AXI_GP0_rvalid(S_AXI_GP0_RVALID), + .S_AXI_GP0_wdata(S_AXI_GP0_WDATA), + .S_AXI_GP0_wlast(S_AXI_GP0_WLAST), + .S_AXI_GP0_wready(S_AXI_GP0_WREADY), + .S_AXI_GP0_wstrb(S_AXI_GP0_WSTRB), + .S_AXI_GP0_wvalid(S_AXI_GP0_WVALID), + + .S_AXI_GP1_ACLK(clk40), + .S_AXI_GP1_ARESETN(clk40_rstn), + .S_AXI_GP1_araddr(S_AXI_GP1_ARADDR), + .S_AXI_GP1_arburst(S_AXI_GP1_ARBURST), + .S_AXI_GP1_arcache(S_AXI_GP1_ARCACHE), + .S_AXI_GP1_arid(S_AXI_GP1_ARID), + .S_AXI_GP1_arlen(S_AXI_GP1_ARLEN), + .S_AXI_GP1_arlock(1'b0), + .S_AXI_GP1_arprot(S_AXI_GP1_ARPROT), + .S_AXI_GP1_arqos(4'b000), + .S_AXI_GP1_arready(S_AXI_GP1_ARREADY), + .S_AXI_GP1_arsize(S_AXI_GP1_ARSIZE), + .S_AXI_GP1_arvalid(S_AXI_GP1_ARVALID), + .S_AXI_GP1_awaddr(S_AXI_GP1_AWADDR), + .S_AXI_GP1_awburst(S_AXI_GP1_AWBURST), + .S_AXI_GP1_awcache(S_AXI_GP1_AWCACHE), + .S_AXI_GP1_awid(S_AXI_GP1_AWID), + .S_AXI_GP1_awlen(S_AXI_GP1_AWLEN), + .S_AXI_GP1_awlock(1'b0), + .S_AXI_GP1_awprot(S_AXI_GP1_AWPROT), + .S_AXI_GP1_awqos(4'b0000), + .S_AXI_GP1_awregion(4'b0000), + .S_AXI_GP1_awready(S_AXI_GP1_AWREADY), + .S_AXI_GP1_awsize(S_AXI_GP1_AWSIZE), + .S_AXI_GP1_awvalid(S_AXI_GP1_AWVALID), + .S_AXI_GP1_bid(), + .S_AXI_GP1_bready(S_AXI_GP1_BREADY), + .S_AXI_GP1_bresp(S_AXI_GP1_BRESP), + .S_AXI_GP1_bvalid(S_AXI_GP1_BVALID), + .S_AXI_GP1_rdata(S_AXI_GP1_RDATA), + .S_AXI_GP1_rid(), + .S_AXI_GP1_rlast(S_AXI_GP1_RLAST), + .S_AXI_GP1_rready(S_AXI_GP1_RREADY), + .S_AXI_GP1_rresp(S_AXI_GP1_RRESP), + .S_AXI_GP1_rvalid(S_AXI_GP1_RVALID), + .S_AXI_GP1_wdata(S_AXI_GP1_WDATA), + .S_AXI_GP1_wlast(S_AXI_GP1_WLAST), + .S_AXI_GP1_wready(S_AXI_GP1_WREADY), + .S_AXI_GP1_wstrb(S_AXI_GP1_WSTRB), + .S_AXI_GP1_wvalid(S_AXI_GP1_WVALID), + + .S_AXI_HP0_ACLK(clk40), + .S_AXI_HP0_ARESETN(clk40_rstn), + .S_AXI_HP0_araddr(S_AXI_HP0_ARADDR), + .S_AXI_HP0_arburst(S_AXI_HP0_ARBURST), + .S_AXI_HP0_arcache(S_AXI_HP0_ARCACHE), + .S_AXI_HP0_arid(S_AXI_HP0_ARID), + .S_AXI_HP0_arlen(S_AXI_HP0_ARLEN), + .S_AXI_HP0_arlock(1'b0), + .S_AXI_HP0_arprot(S_AXI_HP0_ARPROT), + .S_AXI_HP0_arqos(4'b0000), + .S_AXI_HP0_arready(S_AXI_HP0_ARREADY), + .S_AXI_HP0_arsize(S_AXI_HP0_ARSIZE), + .S_AXI_HP0_arvalid(S_AXI_HP0_ARVALID), + .S_AXI_HP0_awaddr(S_AXI_HP0_AWADDR), + .S_AXI_HP0_awburst(S_AXI_HP0_AWBURST), + .S_AXI_HP0_awcache(S_AXI_HP0_AWCACHE), + .S_AXI_HP0_awid(S_AXI_HP0_AWID), + .S_AXI_HP0_awlen(S_AXI_HP0_AWLEN), + .S_AXI_HP0_awlock(1'b0), + .S_AXI_HP0_awprot(S_AXI_HP0_AWPROT), + .S_AXI_HP0_awqos(4'b0000), + .S_AXI_HP0_awready(S_AXI_HP0_AWREADY), + .S_AXI_HP0_awsize(S_AXI_HP0_AWSIZE), + .S_AXI_HP0_awvalid(S_AXI_HP0_AWVALID), + .S_AXI_HP0_bid(), + .S_AXI_HP0_bready(S_AXI_HP0_BREADY), + .S_AXI_HP0_bresp(S_AXI_HP0_BRESP), + .S_AXI_HP0_bvalid(S_AXI_HP0_BVALID), + .S_AXI_HP0_rdata(S_AXI_HP0_RDATA), + .S_AXI_HP0_rid(), + .S_AXI_HP0_rlast(S_AXI_HP0_RLAST), + .S_AXI_HP0_rready(S_AXI_HP0_RREADY), + .S_AXI_HP0_rresp(S_AXI_HP0_RRESP), + .S_AXI_HP0_rvalid(S_AXI_HP0_RVALID), + .S_AXI_HP0_wdata(S_AXI_HP0_WDATA), + .S_AXI_HP0_wlast(S_AXI_HP0_WLAST), + .S_AXI_HP0_wready(S_AXI_HP0_WREADY), + .S_AXI_HP0_wstrb(S_AXI_HP0_WSTRB), + .S_AXI_HP0_wvalid(S_AXI_HP0_WVALID), + + .S_AXI_HP1_ACLK(clk40), + .S_AXI_HP1_ARESETN(clk40_rstn), + .S_AXI_HP1_araddr(S_AXI_HP1_ARADDR), + .S_AXI_HP1_arburst(S_AXI_HP1_ARBURST), + .S_AXI_HP1_arcache(S_AXI_HP1_ARCACHE), + .S_AXI_HP1_arid(S_AXI_HP1_ARID), + .S_AXI_HP1_arlen(S_AXI_HP1_ARLEN), + .S_AXI_HP1_arlock(1'b0), + .S_AXI_HP1_arprot(S_AXI_HP1_ARPROT), + .S_AXI_HP1_arqos(4'b0000), + .S_AXI_HP1_arready(S_AXI_HP1_ARREADY), + .S_AXI_HP1_arsize(S_AXI_HP1_ARSIZE), + .S_AXI_HP1_arvalid(S_AXI_HP1_ARVALID), + .S_AXI_HP1_awaddr(S_AXI_HP1_AWADDR), + .S_AXI_HP1_awburst(S_AXI_HP1_AWBURST), + .S_AXI_HP1_awcache(S_AXI_HP1_AWCACHE), + .S_AXI_HP1_awid(S_AXI_HP1_AWID), + .S_AXI_HP1_awlen(S_AXI_HP1_AWLEN), + .S_AXI_HP1_awlock(1'b0), + .S_AXI_HP1_awprot(S_AXI_HP1_AWPROT), + .S_AXI_HP1_awqos(4'b0000), + .S_AXI_HP1_awready(S_AXI_HP1_AWREADY), + .S_AXI_HP1_awsize(S_AXI_HP1_AWSIZE), + .S_AXI_HP1_awvalid(S_AXI_HP1_AWVALID), + .S_AXI_HP1_bid(), + .S_AXI_HP1_bready(S_AXI_HP1_BREADY), + .S_AXI_HP1_bresp(S_AXI_HP1_BRESP), + .S_AXI_HP1_bvalid(S_AXI_HP1_BVALID), + .S_AXI_HP1_rdata(S_AXI_HP1_RDATA), + .S_AXI_HP1_rid(), + .S_AXI_HP1_rlast(S_AXI_HP1_RLAST), + .S_AXI_HP1_rready(S_AXI_HP1_RREADY), + .S_AXI_HP1_rresp(S_AXI_HP1_RRESP), + .S_AXI_HP1_rvalid(S_AXI_HP1_RVALID), + .S_AXI_HP1_wdata(S_AXI_HP1_WDATA), + .S_AXI_HP1_wlast(S_AXI_HP1_WLAST), + .S_AXI_HP1_wready(S_AXI_HP1_WREADY), + .S_AXI_HP1_wstrb(S_AXI_HP1_WSTRB), + .S_AXI_HP1_wvalid(S_AXI_HP1_WVALID), + + // ARM DMA + .s_axis_dma_tdata(s_axis_dma_tdata), + .s_axis_dma_tdest(s_axis_dma_tdest), + .s_axis_dma_tlast(s_axis_dma_tlast), + .s_axis_dma_tready(s_axis_dma_tready), + .s_axis_dma_tvalid(s_axis_dma_tvalid), + .m_axis_dma_tdata(m_axis_dma_tdata), + .m_axis_dma_tuser(m_axis_dma_tuser), + .m_axis_dma_tlast(m_axis_dma_tlast), + .m_axis_dma_tready(m_axis_dma_tready), + .m_axis_dma_tvalid(m_axis_dma_tvalid), + + // Misc Interrupts, GPIO, clk + .IRQ_F2P(IRQ_F2P), + + .GPIO_0_tri_i(ps_gpio_in), + .GPIO_0_tri_o(ps_gpio_out), + .GPIO_0_tri_t(ps_gpio_tri), + + .JTAG0_TCK(DBA_CPLD_JTAG_TCK), + .JTAG0_TMS(DBA_CPLD_JTAG_TMS), + .JTAG0_TDI(DBA_CPLD_JTAG_TDI), + .JTAG0_TDO(DBA_CPLD_JTAG_TDO), + + `ifndef N300 + .JTAG1_TCK(DBB_CPLD_JTAG_TCK), + .JTAG1_TMS(DBB_CPLD_JTAG_TMS), + .JTAG1_TDI(DBB_CPLD_JTAG_TDI), + .JTAG1_TDO(DBB_CPLD_JTAG_TDO), + `else + .JTAG1_TCK(), + .JTAG1_TMS(), + .JTAG1_TDI(), + .JTAG1_TDO('b0), + `endif + + .FCLK_CLK0(FCLK_CLK0), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_RESET1_N(), + .FCLK_CLK2(FCLK_CLK2), + .FCLK_RESET2_N(), + .FCLK_CLK3(FCLK_CLK3), + .FCLK_RESET3_N(), + + .WR_UART_txd(wr_uart_rxd), // rx <-> tx + .WR_UART_rxd(wr_uart_txd), // rx <-> tx + + .qsfp_sda_i(qsfp_sda_i), + .qsfp_sda_o(qsfp_sda_o), + .qsfp_sda_t(qsfp_sda_t), + .qsfp_scl_i(qsfp_scl_i), + .qsfp_scl_o(qsfp_scl_o), + .qsfp_scl_t(qsfp_scl_t), + + .USBIND_0_port_indctl(), + .USBIND_0_vbus_pwrfault(), + .USBIND_0_vbus_pwrselect(), + + // Outward connections to the pins + .MIO(MIO), + .DDR_cas_n(DDR_CAS_n), + .DDR_cke(DDR_CKE), + .DDR_ck_n(DDR_Clk_n), + .DDR_ck_p(DDR_Clk), + .DDR_cs_n(DDR_CS_n), + .DDR_reset_n(DDR_DRSTB), + .DDR_odt(DDR_ODT), + .DDR_ras_n(DDR_RAS_n), + .DDR_we_n(DDR_WEB), + .DDR_ba(DDR_BankAddr), + .DDR_addr(DDR_Addr), + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_dm(DDR_DM), + .DDR_dq(DDR_DQ), + .DDR_dqs_n(DDR_DQS_n), + .DDR_dqs_p(DDR_DQS), + .PS_SRSTB(PS_SRSTB), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB) + ); + + /////////////////////////////////////////////////////////////////////////////////// + // + // Xilinx DDR3 Controller and PHY. + // + /////////////////////////////////////////////////////////////////////////////////// + + wire ddr3_axi_clk; // 1/4 DDR external clock rate (200MHz) + wire ddr3_axi_rst; // Synchronized to ddr_sys_clk + wire ddr3_running; // DRAM calibration complete. + wire [11:0] device_temp; + + // Slave Interface Write Address Ports + wire [3:0] ddr3_axi_awid; + wire [31:0] ddr3_axi_awaddr; + wire [7:0] ddr3_axi_awlen; + wire [2:0] ddr3_axi_awsize; + wire [1:0] ddr3_axi_awburst; + wire [0:0] ddr3_axi_awlock; + wire [3:0] ddr3_axi_awcache; + wire [2:0] ddr3_axi_awprot; + wire [3:0] ddr3_axi_awqos; + wire ddr3_axi_awvalid; + wire ddr3_axi_awready; + // Slave Interface Write Data Ports + wire [255:0] ddr3_axi_wdata; + wire [31:0] ddr3_axi_wstrb; + wire ddr3_axi_wlast; + wire ddr3_axi_wvalid; + wire ddr3_axi_wready; + // Slave Interface Write Response Ports + wire ddr3_axi_bready; + wire [3:0] ddr3_axi_bid; + wire [1:0] ddr3_axi_bresp; + wire ddr3_axi_bvalid; + // Slave Interface Read Address Ports + wire [3:0] ddr3_axi_arid; + wire [31:0] ddr3_axi_araddr; + wire [7:0] ddr3_axi_arlen; + wire [2:0] ddr3_axi_arsize; + wire [1:0] ddr3_axi_arburst; + wire [0:0] ddr3_axi_arlock; + wire [3:0] ddr3_axi_arcache; + wire [2:0] ddr3_axi_arprot; + wire [3:0] ddr3_axi_arqos; + wire ddr3_axi_arvalid; + wire ddr3_axi_arready; + // Slave Interface Read Data Ports + wire ddr3_axi_rready; + wire [3:0] ddr3_axi_rid; + wire [255:0] ddr3_axi_rdata; + wire [1:0] ddr3_axi_rresp; + wire ddr3_axi_rlast; + wire ddr3_axi_rvalid; + + reg ddr3_axi_rst_reg_n; + + // Copied this reset circuit from example design. + always @(posedge ddr3_axi_clk) + ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; + + + // Instantiate the DDR3 MIG core + // + // The top-level IP block has no parameters defined for some reason. + // Most of configurable parameters are hard-coded in the mig so get + // some additional knobs we pull those out into verilog headers. + // + // Synthesis params: ip/ddr3_32bit/ddr3_32bit_mig_parameters.vh + // Simulation params: ip/ddr3_32bit/ddr3_32bit_mig_sim_parameters.vh + + ddr3_32bit u_ddr3_32bit ( + // Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .init_calib_complete (ddr3_running), + .device_temp_i (device_temp), + + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + // Application interface ports + .ui_clk (ddr3_axi_clk), // 200Hz clock out + .ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 200 MHz. + .aresetn (ddr3_axi_rst_reg_n), + .app_sr_req (1'b0), + .app_sr_active (), + .app_ref_req (1'b0), + .app_ref_ack (), + .app_zq_req (1'b0), + .app_zq_ack (), + // Slave Interface Write Address Ports + .s_axi_awid (ddr3_axi_awid), + .s_axi_awaddr (ddr3_axi_awaddr), + .s_axi_awlen (ddr3_axi_awlen), + .s_axi_awsize (ddr3_axi_awsize), + .s_axi_awburst (ddr3_axi_awburst), + .s_axi_awlock (ddr3_axi_awlock), + .s_axi_awcache (ddr3_axi_awcache), + .s_axi_awprot (ddr3_axi_awprot), + .s_axi_awqos (ddr3_axi_awqos), + .s_axi_awvalid (ddr3_axi_awvalid), + .s_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .s_axi_wdata (ddr3_axi_wdata), + .s_axi_wstrb (ddr3_axi_wstrb), + .s_axi_wlast (ddr3_axi_wlast), + .s_axi_wvalid (ddr3_axi_wvalid), + .s_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .s_axi_bid (ddr3_axi_bid), + .s_axi_bresp (ddr3_axi_bresp), + .s_axi_bvalid (ddr3_axi_bvalid), + .s_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .s_axi_arid (ddr3_axi_arid), + .s_axi_araddr (ddr3_axi_araddr), + .s_axi_arlen (ddr3_axi_arlen), + .s_axi_arsize (ddr3_axi_arsize), + .s_axi_arburst (ddr3_axi_arburst), + .s_axi_arlock (ddr3_axi_arlock), + .s_axi_arcache (ddr3_axi_arcache), + .s_axi_arprot (ddr3_axi_arprot), + .s_axi_arqos (ddr3_axi_arqos), + .s_axi_arvalid (ddr3_axi_arvalid), + .s_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .s_axi_rid (ddr3_axi_rid), + .s_axi_rdata (ddr3_axi_rdata), + .s_axi_rresp (ddr3_axi_rresp), + .s_axi_rlast (ddr3_axi_rlast), + .s_axi_rvalid (ddr3_axi_rvalid), + .s_axi_rready (ddr3_axi_rready), + // System Clock Ports + .sys_clk_p (sys_clk_p), + .sys_clk_n (sys_clk_n), + .clk_ref_i (bus_clk), + + .sys_rst (~global_rst) // IJB. Poorly named active low. Should change RST_ACT_LOW. + ); + + // Temperature monitor module + mig_7series_v4_2_tempmon #( + .TEMP_MON_CONTROL("INTERNAL"), + .XADC_CLK_PERIOD(5000 /* 200MHz clock period in ps */) + ) tempmon_i ( + .clk(bus_clk), .xadc_clk(bus_clk), .rst(bus_rst), + .device_temp_i(12'd0 /* ignored */), .device_temp(device_temp) + ); + + /////////////////////////////////////////////////////// + // + // DB PS SPI Connections + // + /////////////////////////////////////////////////////// + wire [NUM_CHANNELS-1:0] rx_atr; + wire [NUM_CHANNELS-1:0] tx_atr; + (* IOB = "true" *) reg [NUM_CHANNELS-1:0] rx_atr_reg; + (* IOB = "true" *) reg [NUM_CHANNELS-1:0] tx_atr_reg; + + // Radio GPIO control for DSA + wire [16*NUM_CHANNELS-1:0] db_gpio_out; + wire [16*NUM_CHANNELS-1:0] db_gpio_ddr; + wire [16*NUM_CHANNELS-1:0] db_gpio_in; + wire [16*NUM_CHANNELS-1:0] db_gpio_fab; + + // DB A SPI Connections + wire cpld_a_cs_n; + wire lmk_a_cs_n; + wire dac_a_cs_n; + wire myk_a_cs_n; + + // Split out the SCLK and MOSI data to Mykonos and the CPLD. + assign DBA_CPLD_PS_SPI_SCLK = spi0_sclk; + assign DBA_CPLD_PS_SPI_SDI = spi0_mosi; + + assign DBA_MYK_SPI_SCLK = spi0_sclk; + assign DBA_MYK_SPI_SDIO = spi0_mosi; + // Assign individual chip selects from PS SPI MASTER 0. + assign cpld_a_cs_n = spi0_ss0; + assign lmk_a_cs_n = spi0_ss1; + assign dac_a_cs_n = ps_gpio_out[8]; // DAC select driven through GPIO. + assign myk_a_cs_n = spi0_ss2; + + // Returned data mux from the SPI interfaces. + assign spi0_miso = ~myk_a_cs_n ? DBA_MYK_SPI_SDO : // From Mykonos + DBA_CPLD_PS_SPI_SDO; + + // For the PS SPI connection to the CPLD, we use the LE and ADDR lines as individual + // chip selects for the CPLD endpoint as well as the LMK and DAC endpoints. + // LE = CPLD + // ADDR[0] = LMK + // ADDR[1] = DAC + assign DBA_CPLD_PS_SPI_LE = cpld_a_cs_n; + assign DBA_CPLD_PS_SPI_ADDR[0] = lmk_a_cs_n; + assign DBA_CPLD_PS_SPI_ADDR[1] = dac_a_cs_n; + assign DBA_MYK_SPI_CS_n = myk_a_cs_n; + + // Instantiate DSA registers in the IOB + (* IOB = "true" *) reg [5:0] dsa_tx1_a_out_iob, dsa_rx1_a_out_iob; + (* IOB = "true" *) reg [5:0] dsa_tx2_a_out_iob, dsa_rx2_a_out_iob; + always @(posedge radio_clk) begin + dsa_tx1_a_out_iob <= db_gpio_out[16*0+11:16*0+6]; + dsa_rx1_a_out_iob <= db_gpio_out[16*0+5:16*0+0]; + dsa_tx2_a_out_iob <= db_gpio_out[16*1+11:16*1+6]; + dsa_rx2_a_out_iob <= db_gpio_out[16*1+5:16*1+0]; + end + + assign DBA_CH1_TX_DSA_DATA = dsa_tx1_a_out_iob; + assign DBA_CH1_RX_DSA_DATA = dsa_rx1_a_out_iob; + assign DBA_CH2_TX_DSA_DATA = dsa_tx2_a_out_iob; + assign DBA_CH2_RX_DSA_DATA = dsa_rx2_a_out_iob; + + assign DBA_ATR_RX_1 = rx_atr_reg[0]; + assign DBA_ATR_RX_2 = rx_atr_reg[1]; + assign DBA_ATR_TX_1 = tx_atr_reg[0]; + assign DBA_ATR_TX_2 = tx_atr_reg[1]; + + assign DBA_MYK_GPIO_0 = 1'b0; + assign DBA_MYK_GPIO_1 = 1'b0; + assign DBA_MYK_GPIO_3 = 1'b0; + assign DBA_MYK_GPIO_4 = 1'b0; + assign DBA_MYK_GPIO_12 = 1'b0; + assign DBA_MYK_GPIO_13 = 1'b0; + assign DBA_MYK_GPIO_14 = 1'b0; + assign DBA_MYK_GPIO_15 = 1'b0; + +`ifndef N300 + + // DB B SPI Connections + wire cpld_b_cs_n; + wire lmk_b_cs_n; + wire dac_b_cs_n; + wire myk_b_cs_n; + + // Split out the SCLK and MOSI data to Mykonos and the CPLD. + assign DBB_CPLD_PS_SPI_SCLK = spi1_sclk; + assign DBB_CPLD_PS_SPI_SDI = spi1_mosi; + + assign DBB_MYK_SPI_SCLK = spi1_sclk; + assign DBB_MYK_SPI_SDIO = spi1_mosi; + + // Assign individual chip selects from PS SPI MASTER 1. + assign cpld_b_cs_n = spi1_ss0; + assign lmk_b_cs_n = spi1_ss1; + assign dac_b_cs_n = ps_gpio_out[9]; // DAC select driven through GPIO. + assign myk_b_cs_n = spi1_ss2; + + // Returned data mux from the SPI interfaces. + assign spi1_miso = ~myk_b_cs_n ? DBB_MYK_SPI_SDO : // From Mykonos + DBB_CPLD_PS_SPI_SDO; + + // For the PS SPI connection to the CPLD, we use the LE and ADDR lines as individual + // chip selects for the CPLD endpoint as well as the LMK and DAC endpoints. + // LE = CPLD + // ADDR[0] = LMK + // ADDR[1] = DAC + assign DBB_CPLD_PS_SPI_LE = cpld_b_cs_n; + assign DBB_CPLD_PS_SPI_ADDR[0] = lmk_b_cs_n; + assign DBB_CPLD_PS_SPI_ADDR[1] = dac_b_cs_n; + assign DBB_MYK_SPI_CS_n = myk_b_cs_n; + + // Instantiate DSA registers in the IOB + (* IOB = "true" *) reg [5:0] dsa_tx1_b_out_iob, dsa_rx1_b_out_iob; + (* IOB = "true" *) reg [5:0] dsa_tx2_b_out_iob, dsa_rx2_b_out_iob; + always @(posedge radio_clk) begin + dsa_tx1_b_out_iob <= db_gpio_out[16*2+11:16*2+6]; + dsa_rx1_b_out_iob <= db_gpio_out[16*2+5:16*2+0]; + dsa_tx2_b_out_iob <= db_gpio_out[16*3+11:16*3+6]; + dsa_rx2_b_out_iob <= db_gpio_out[16*3+5:16*3+0]; + end + + assign DBB_CH1_TX_DSA_DATA = dsa_tx1_b_out_iob; + assign DBB_CH1_RX_DSA_DATA = dsa_rx1_b_out_iob; + assign DBB_CH2_TX_DSA_DATA = dsa_tx2_b_out_iob; + assign DBB_CH2_RX_DSA_DATA = dsa_rx2_b_out_iob; + + assign DBB_ATR_RX_1 = rx_atr_reg[2]; + assign DBB_ATR_RX_2 = rx_atr_reg[3]; + assign DBB_ATR_TX_1 = tx_atr_reg[2]; + assign DBB_ATR_TX_2 = tx_atr_reg[3]; + + assign DBB_MYK_GPIO_0 = 1'b0; + assign DBB_MYK_GPIO_1 = 1'b0; + assign DBB_MYK_GPIO_3 = 1'b0; + assign DBB_MYK_GPIO_4 = 1'b0; + assign DBB_MYK_GPIO_12 = 1'b0; + assign DBB_MYK_GPIO_13 = 1'b0; + assign DBB_MYK_GPIO_14 = 1'b0; + assign DBB_MYK_GPIO_15 = 1'b0; + +`endif + + /////////////////////////////////////////////////////// + // + // N3xx CORE + // + /////////////////////////////////////////////////////// + + wire [31:0] rx[NUM_CHANNELS-1:0]; + wire [31:0] tx[NUM_CHANNELS-1:0]; + wire [32*NUM_CHANNELS-1:0] rx_flat; + wire [32*NUM_CHANNELS-1:0] tx_flat; + + wire [NUM_CHANNELS-1:0] rx_stb; + wire [NUM_CHANNELS-1:0] tx_stb; + + wire [31:0] build_datestamp; + + genvar i; + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + // Radio Data + assign rx_flat[32*i+31:32*i] = rx[i]; + assign tx[i] = tx_flat[32*i+31:32*i]; + end + endgenerate + + USR_ACCESSE2 usr_access_i ( + .DATA(build_datestamp), .CFGCLK(), .DATAVALID() + ); + + n3xx_core #( + .REG_AWIDTH(14), + .BUS_CLK_RATE(BUS_CLK_RATE), + .FP_GPIO_WIDTH(FP_GPIO_WIDTH), + .NUM_CHANNELS_PER_RADIO(NUM_CHANNELS_PER_RADIO), + .NUM_CHANNELS(NUM_CHANNELS), + .NUM_DBOARDS(NUM_DBOARDS), + `ifdef USE_REPLAY + .USE_REPLAY(1) + `else + .USE_REPLAY(0) + `endif + ) n3xx_core( + // Clocks and resets + `ifdef NO_DB + .radio_clk(bus_clk), + .radio_rst(bus_rst), + `else + .radio_clk(radio_clk), + .radio_rst(radio_rst), + `endif + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .ddr3_dma_clk(ddr3_dma_clk), + .clk40(clk40), + + // Clocking and PPS Controls/Indicators + .pps(pps_radioclk1x), + .pps_select(pps_select), + .pps_out_enb(pps_out_enb), + .pps_select_sfp(pps_select_sfp), + .ref_clk_reset(), + .meas_clk_reset(meas_clk_reset), + .ref_clk_locked(1'b1), + .meas_clk_locked(meas_clk_locked), + .enable_ref_clk_async(enable_ref_clk_async), + + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_XBAR_AWADDR), + .s_axi_awvalid(M_AXI_XBAR_AWVALID), + .s_axi_awready(M_AXI_XBAR_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_XBAR_WDATA), + .s_axi_wstrb(M_AXI_XBAR_WSTRB), + .s_axi_wvalid(M_AXI_XBAR_WVALID), + .s_axi_wready(M_AXI_XBAR_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_XBAR_BRESP), + .s_axi_bvalid(M_AXI_XBAR_BVALID), + .s_axi_bready(M_AXI_XBAR_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_XBAR_ARADDR), + .s_axi_arvalid(M_AXI_XBAR_ARVALID), + .s_axi_arready(M_AXI_XBAR_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_XBAR_RDATA), + .s_axi_rresp(M_AXI_XBAR_RRESP), + .s_axi_rvalid(M_AXI_XBAR_RVALID), + .s_axi_rready(M_AXI_XBAR_RREADY), + // ps gpio source + .ps_gpio_tri(ps_gpio_tri[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + .ps_gpio_out(ps_gpio_out[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + .ps_gpio_in(ps_gpio_in[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + // FP_GPIO + .fp_gpio_inout(FPGA_GPIO), + // Radio ATR + .rx_atr(rx_atr), + .tx_atr(tx_atr), + // Radio GPIO DSA + .db_gpio_out_flat(db_gpio_out), + .db_gpio_in_flat(db_gpio_in), + .db_gpio_ddr_flat(db_gpio_ddr), + .db_gpio_fab_flat(db_gpio_fab), + // Radio Strobes + .rx_stb(rx_stb), + .tx_stb(tx_stb), + // Radio Data + .rx(rx_flat), + .tx(tx_flat), + // CPLD RX_LO TX_LO SPI + `ifndef N300 + .sclk_flat({DBB_CPLD_PL_SPI_SCLK, + DBA_CPLD_PL_SPI_SCLK}), + .sen_flat({5'b0,DBB_CPLD_PL_SPI_ADDR[1],DBB_CPLD_PL_SPI_ADDR[0],DBB_CPLD_PL_SPI_LE, + 5'b0,DBA_CPLD_PL_SPI_ADDR[1],DBA_CPLD_PL_SPI_ADDR[0],DBA_CPLD_PL_SPI_LE}), + .mosi_flat({DBB_CPLD_PL_SPI_SDI, + DBA_CPLD_PL_SPI_SDI}), + .miso_flat({DBB_CPLD_PL_SPI_SDO, + DBA_CPLD_PL_SPI_SDO}), + `else + .sclk_flat(DBA_CPLD_PL_SPI_SCLK), + .sen_flat({5'b0,DBA_CPLD_PL_SPI_ADDR[1],DBA_CPLD_PL_SPI_ADDR[0],DBA_CPLD_PL_SPI_LE}), + .mosi_flat(DBA_CPLD_PL_SPI_SDI), + .miso_flat(DBA_CPLD_PL_SPI_SDO), + `endif + // DRAM signals + .ddr3_axi_clk (ddr3_axi_clk), + .ddr3_axi_rst (ddr3_axi_rst), + .ddr3_running (ddr3_running), + // Slave Interface Write Address Ports + .ddr3_axi_awid (ddr3_axi_awid), + .ddr3_axi_awaddr (ddr3_axi_awaddr), + .ddr3_axi_awlen (ddr3_axi_awlen), + .ddr3_axi_awsize (ddr3_axi_awsize), + .ddr3_axi_awburst (ddr3_axi_awburst), + .ddr3_axi_awlock (ddr3_axi_awlock), + .ddr3_axi_awcache (ddr3_axi_awcache), + .ddr3_axi_awprot (ddr3_axi_awprot), + .ddr3_axi_awqos (ddr3_axi_awqos), + .ddr3_axi_awvalid (ddr3_axi_awvalid), + .ddr3_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .ddr3_axi_wdata (ddr3_axi_wdata), + .ddr3_axi_wstrb (ddr3_axi_wstrb), + .ddr3_axi_wlast (ddr3_axi_wlast), + .ddr3_axi_wvalid (ddr3_axi_wvalid), + .ddr3_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .ddr3_axi_bid (ddr3_axi_bid), + .ddr3_axi_bresp (ddr3_axi_bresp), + .ddr3_axi_bvalid (ddr3_axi_bvalid), + .ddr3_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .ddr3_axi_arid (ddr3_axi_arid), + .ddr3_axi_araddr (ddr3_axi_araddr), + .ddr3_axi_arlen (ddr3_axi_arlen), + .ddr3_axi_arsize (ddr3_axi_arsize), + .ddr3_axi_arburst (ddr3_axi_arburst), + .ddr3_axi_arlock (ddr3_axi_arlock), + .ddr3_axi_arcache (ddr3_axi_arcache), + .ddr3_axi_arprot (ddr3_axi_arprot), + .ddr3_axi_arqos (ddr3_axi_arqos), + .ddr3_axi_arvalid (ddr3_axi_arvalid), + .ddr3_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .ddr3_axi_rid (ddr3_axi_rid), + .ddr3_axi_rdata (ddr3_axi_rdata), + .ddr3_axi_rresp (ddr3_axi_rresp), + .ddr3_axi_rlast (ddr3_axi_rlast), + .ddr3_axi_rvalid (ddr3_axi_rvalid), + .ddr3_axi_rready (ddr3_axi_rready), + + // DMA to PS + .m_dma_tdata(s_axis_dma_tdata), + .m_dma_tdest(s_axis_dma_tdest), + .m_dma_tlast(s_axis_dma_tlast), + .m_dma_tready(s_axis_dma_tready), + .m_dma_tvalid(s_axis_dma_tvalid), + + .s_dma_tdata(m_axis_dma_tdata), + .s_dma_tuser(m_axis_dma_tuser), + .s_dma_tlast(m_axis_dma_tlast), + .s_dma_tready(m_axis_dma_tready), + .s_dma_tvalid(m_axis_dma_tvalid), + + // VITA to Ethernet + .v2e0_tdata(v2e0_tdata), + .v2e0_tvalid(v2e0_tvalid), + .v2e0_tlast(v2e0_tlast), + .v2e0_tready(v2e0_tready), + + .v2e1_tdata(v2e1_tdata), + .v2e1_tlast(v2e1_tlast), + .v2e1_tvalid(v2e1_tvalid), + .v2e1_tready(v2e1_tready), + + // Ethernet to VITA + .e2v0_tdata(e2v0_tdata), + .e2v0_tlast(e2v0_tlast), + .e2v0_tvalid(e2v0_tvalid), + .e2v0_tready(e2v0_tready), + + .e2v1_tdata(e2v1_tdata), + .e2v1_tlast(e2v1_tlast), + .e2v1_tvalid(e2v1_tvalid), + .e2v1_tready(e2v1_tready), + + //regport interface to npio + .reg_wr_req_npio(reg_wr_req_npio), + .reg_wr_addr_npio(reg_wr_addr_npio), + .reg_wr_data_npio(reg_wr_data_npio), + .reg_rd_req_npio(reg_rd_req_npio), + .reg_rd_addr_npio(reg_rd_addr_npio), + .reg_rd_resp_npio(reg_rd_resp_npio), + .reg_rd_data_npio(reg_rd_data_npio), + + .build_datestamp(build_datestamp), + .xadc_readback({20'h0, device_temp}), + .sfp_ports_info({sfp_port1_info, sfp_port0_info}), + .device_id(device_id) + ); + + // Register the ATR bits once between sending them out to the CPLD to avoid + // glitches on the outputs! + always @(posedge radio_clk) begin + rx_atr_reg <= rx_atr; + tx_atr_reg <= tx_atr; + end + + // ////////////////////////////////////////////////////////////////////// + // + // Daughterboard Cores + // + // ////////////////////////////////////////////////////////////////////// + + wire [49:0] bRegPortInFlatA; + wire [33:0] bRegPortOutFlatA; + wire rx_a_valid; + wire tx_a_rfi; +`ifndef N300 + wire [49:0] bRegPortInFlatB; + wire [33:0] bRegPortOutFlatB; + wire rx_b_valid; + wire tx_b_rfi; +`endif + +`ifdef BUILD_WR + localparam INCL_WR_TDC = 1'b1; +`else + localparam INCL_WR_TDC = 1'b0; +`endif + + wire reg_portA_rd; + wire reg_portA_wr; + wire [14-1:0] reg_portA_addr; + wire [32-1:0] reg_portA_wr_data; + wire [32-1:0] reg_portA_rd_data; + wire reg_portA_ready; + wire validA_unused; + + assign bRegPortInFlatA = {2'b0, reg_portA_addr, reg_portA_wr_data, reg_portA_rd, reg_portA_wr}; + assign {reg_portA_rd_data, validA_unused, reg_portA_ready} = bRegPortOutFlatA; + + DbCore #( + .kInclWhiteRabbitTdc(INCL_WR_TDC) + ) dba_core ( + .bBusReset(clk40_rst), //in std_logic + .BusClk(clk40), //in std_logic + .Clk40(clk40), //in std_logic + .MeasClk(meas_clk), //in std_logic + .FpgaClk_p(DBA_FPGA_CLK_P), //in std_logic + .FpgaClk_n(DBA_FPGA_CLK_N), //in std_logic + .SampleClk1xOut(radio_clk), //out std_logic + .SampleClk1x(radio_clk), //in std_logic + .SampleClk2xOut(radio_clk_2x), //out std_logic + .SampleClk2x(radio_clk_2x), //in std_logic + .bRegPortInFlat(bRegPortInFlatA), //in std_logic_vector(49:0) + .bRegPortOutFlat(bRegPortOutFlatA), //out std_logic_vector(33:0) + .kSlotId(1'b0), //in std_logic + .sSysRefFpgaLvds_p(DBA_FPGA_SYSREF_P), //in std_logic + .sSysRefFpgaLvds_n(DBA_FPGA_SYSREF_N), //in std_logic + .aLmkSync(DBA_CPLD_PL_SPI_ADDR[2]), //out std_logic + .JesdRefClk_p(USRPIO_A_MGTCLK_P), //in std_logic + .JesdRefClk_n(USRPIO_A_MGTCLK_N), //in std_logic + .aAdcRx_p(USRPIO_A_RX_P), //in std_logic_vector(3:0) + .aAdcRx_n(USRPIO_A_RX_N), //in std_logic_vector(3:0) + .aSyncAdcOut_n(DBA_MYK_SYNC_IN_n), //out std_logic + .aDacTx_p(USRPIO_A_TX_P), //out std_logic_vector(3:0) + .aDacTx_n(USRPIO_A_TX_N), //out std_logic_vector(3:0) + .aSyncDacIn_n(DBA_MYK_SYNC_OUT_n), //in std_logic + .sAdcDataValid(rx_a_valid), //out std_logic + .sAdcDataSamples0I(rx[0][31:16]), //out std_logic_vector(15:0) + .sAdcDataSamples0Q(rx[0][15:0]), //out std_logic_vector(15:0) + .sAdcDataSamples1I(rx[1][31:16]), //out std_logic_vector(15:0) + .sAdcDataSamples1Q(rx[1][15:0]), //out std_logic_vector(15:0) + .sDacReadyForInput(tx_a_rfi), //out std_logic + .sDacDataSamples0I(tx[0][31:16]), //in std_logic_vector(15:0) + .sDacDataSamples0Q(tx[0][15:0]), //in std_logic_vector(15:0) + .sDacDataSamples1I(tx[1][31:16]), //in std_logic_vector(15:0) + .sDacDataSamples1Q(tx[1][15:0]), //in std_logic_vector(15:0) + .RefClk(ref_clk), //in std_logic + .rPpsPulse(pps_refclk), //in std_logic + .rGatedPulseToPin(UNUSED_PIN_TDCA_0), //inout std_logic + .sGatedPulseToPin(UNUSED_PIN_TDCA_1), //inout std_logic + .sPps(pps_radioclk1x), //out std_logic + .sPpsToIob(pps_radioclk1x_iob), //out std_logic + .WrRefClk(wr_ref_clk), //in std_logic + .rWrPpsPulse(pps_wr_refclk), //in std_logic + .rWrGatedPulseToPin(UNUSED_PIN_TDCA_2), //inout std_logic + .sWrGatedPulseToPin(UNUSED_PIN_TDCA_3), //inout std_logic + .aPpsSfpSel(pps_select_sfp), //out std_logic_vector(1:0) + .sAdcSync(), //out std_logic + .sDacSync(), //out std_logic + .sSysRef(), //out std_logic + .rRpTransfer(), //out std_logic + .sSpTransfer(), //out std_logic + .rWrRpTransfer(), //out std_logic + .sWrSpTransfer() //out std_logic + ); + + assign rx_stb[0] = rx_a_valid; + assign rx_stb[1] = rx_a_valid; + assign tx_stb[0] = tx_a_rfi; + assign tx_stb[1] = tx_a_rfi; + + axil_to_ni_regport #( + .RP_DWIDTH (32), + .RP_AWIDTH (14), + .TIMEOUT (512) + ) ni_regportA_inst ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD0_AWADDR), + .s_axi_awvalid(M_AXI_JESD0_AWVALID), + .s_axi_awready(M_AXI_JESD0_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD0_WDATA), + .s_axi_wstrb(M_AXI_JESD0_WSTRB), + .s_axi_wvalid(M_AXI_JESD0_WVALID), + .s_axi_wready(M_AXI_JESD0_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD0_BRESP), + .s_axi_bvalid(M_AXI_JESD0_BVALID), + .s_axi_bready(M_AXI_JESD0_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD0_ARADDR), + .s_axi_arvalid(M_AXI_JESD0_ARVALID), + .s_axi_arready(M_AXI_JESD0_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_JESD0_RDATA), + .s_axi_rresp(M_AXI_JESD0_RRESP), + .s_axi_rvalid(M_AXI_JESD0_RVALID), + .s_axi_rready(M_AXI_JESD0_RREADY), + // Register port + .reg_port_in_rd (reg_portA_rd), + .reg_port_in_wt (reg_portA_wr), + .reg_port_in_addr (reg_portA_addr), + .reg_port_in_data (reg_portA_wr_data), + .reg_port_out_data (reg_portA_rd_data), + .reg_port_out_ready(reg_portA_ready) + ); + +`ifndef N300 + wire reg_portB_rd; + wire reg_portB_wr; + wire [14-1:0] reg_portB_addr; + wire [32-1:0] reg_portB_wr_data; + wire [32-1:0] reg_portB_rd_data; + wire reg_portB_ready; + wire validB_unused; + + assign bRegPortInFlatB = {2'b0, reg_portB_addr, reg_portB_wr_data, reg_portB_rd, reg_portB_wr}; + assign {reg_portB_rd_data, validB_unused, reg_portB_ready} = bRegPortOutFlatB; + + DbCore #( + .kInclWhiteRabbitTdc(INCL_WR_TDC) + ) dbb_core ( + .bBusReset(clk40_rst), //in std_logic + .BusClk(clk40), //in std_logic + .Clk40(clk40), //in std_logic + .MeasClk(meas_clk), //in std_logic + .FpgaClk_p(DBB_FPGA_CLK_P), //in std_logic + .FpgaClk_n(DBB_FPGA_CLK_N), //in std_logic + .SampleClk1xOut(), //out std_logic + .SampleClk1x(radio_clk), //in std_logic + .SampleClk2xOut(), //out std_logic + .SampleClk2x(radio_clk_2x), //in std_logic + .bRegPortInFlat(bRegPortInFlatB), //in std_logic_vector(49:0) + .bRegPortOutFlat(bRegPortOutFlatB), //out std_logic_vector(33:0) + .kSlotId(1'b1), //in std_logic + .sSysRefFpgaLvds_p(DBB_FPGA_SYSREF_P), //in std_logic + .sSysRefFpgaLvds_n(DBB_FPGA_SYSREF_N), //in std_logic + .aLmkSync(DBB_CPLD_PL_SPI_ADDR[2]), //out std_logic + .JesdRefClk_p(USRPIO_B_MGTCLK_P), //in std_logic + .JesdRefClk_n(USRPIO_B_MGTCLK_N), //in std_logic + .aAdcRx_p(USRPIO_B_RX_P), //in std_logic_vector(3:0) + .aAdcRx_n(USRPIO_B_RX_N), //in std_logic_vector(3:0) + .aSyncAdcOut_n(DBB_MYK_SYNC_IN_n), //out std_logic + .aDacTx_p(USRPIO_B_TX_P), //out std_logic_vector(3:0) + .aDacTx_n(USRPIO_B_TX_N), //out std_logic_vector(3:0) + .aSyncDacIn_n(DBB_MYK_SYNC_OUT_n), //in std_logic + .sAdcDataValid(rx_b_valid), //out std_logic + .sAdcDataSamples0I(rx[2][31:16]), //out std_logic_vector(15:0) + .sAdcDataSamples0Q(rx[2][15:0]), //out std_logic_vector(15:0) + .sAdcDataSamples1I(rx[3][31:16]), //out std_logic_vector(15:0) + .sAdcDataSamples1Q(rx[3][15:0]), //out std_logic_vector(15:0) + .sDacReadyForInput(tx_b_rfi), //out std_logic + .sDacDataSamples0I(tx[2][31:16]), //in std_logic_vector(15:0) + .sDacDataSamples0Q(tx[2][15:0]), //in std_logic_vector(15:0) + .sDacDataSamples1I(tx[3][31:16]), //in std_logic_vector(15:0) + .sDacDataSamples1Q(tx[3][15:0]), //in std_logic_vector(15:0) + .RefClk(ref_clk), //in std_logic + .rPpsPulse(pps_refclk), //in std_logic + .rGatedPulseToPin(UNUSED_PIN_TDCB_0), //inout std_logic + .sGatedPulseToPin(UNUSED_PIN_TDCB_1), //inout std_logic + .sPps(), //out std_logic + .sPpsToIob(), //out std_logic + .WrRefClk(wr_ref_clk), //in std_logic + .rWrPpsPulse(pps_wr_refclk), //in std_logic + .rWrGatedPulseToPin(UNUSED_PIN_TDCB_2), //inout std_logic + .sWrGatedPulseToPin(UNUSED_PIN_TDCB_3), //inout std_logic + .aPpsSfpSel(2'b0), //out std_logic_vector(1:0) + .sAdcSync(), //out std_logic + .sDacSync(), //out std_logic + .sSysRef(), //out std_logic + .rRpTransfer(), //out std_logic + .sSpTransfer(), //out std_logic + .rWrRpTransfer(), //out std_logic + .sWrSpTransfer() //out std_logic + ); + + assign rx_stb[2] = rx_b_valid; + assign rx_stb[3] = rx_b_valid; + assign tx_stb[2] = tx_b_rfi; + assign tx_stb[3] = tx_b_rfi; + + axil_to_ni_regport #( + .RP_DWIDTH (32), + .RP_AWIDTH (14), + .TIMEOUT (512) + ) ni_regportB_inst ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD1_AWADDR), + .s_axi_awvalid(M_AXI_JESD1_AWVALID), + .s_axi_awready(M_AXI_JESD1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD1_WDATA), + .s_axi_wstrb(M_AXI_JESD1_WSTRB), + .s_axi_wvalid(M_AXI_JESD1_WVALID), + .s_axi_wready(M_AXI_JESD1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD1_BRESP), + .s_axi_bvalid(M_AXI_JESD1_BVALID), + .s_axi_bready(M_AXI_JESD1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD1_ARADDR), + .s_axi_arvalid(M_AXI_JESD1_ARVALID), + .s_axi_arready(M_AXI_JESD1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_JESD1_RDATA), + .s_axi_rresp (M_AXI_JESD1_RRESP), + .s_axi_rvalid (M_AXI_JESD1_RVALID), + .s_axi_rready (M_AXI_JESD1_RREADY), + // Register port + .reg_port_in_rd (reg_portB_rd), + .reg_port_in_wt (reg_portB_wr), + .reg_port_in_addr (reg_portB_addr), + .reg_port_in_data (reg_portB_wr_data), + .reg_port_out_data (reg_portB_rd_data), + .reg_port_out_ready(reg_portB_ready) + ); +`else + // Tie off second daughterboard interface + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_dbb_core ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD1_AWADDR), + .s_axi_awvalid(M_AXI_JESD1_AWVALID), + .s_axi_awready(M_AXI_JESD1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD1_WDATA), + .s_axi_wstrb(M_AXI_JESD1_WSTRB), + .s_axi_wvalid(M_AXI_JESD1_WVALID), + .s_axi_wready(M_AXI_JESD1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD1_BRESP), + .s_axi_bvalid(M_AXI_JESD1_BVALID), + .s_axi_bready(M_AXI_JESD1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD1_ARADDR), + .s_axi_arvalid(M_AXI_JESD1_ARVALID), + .s_axi_arready(M_AXI_JESD1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_JESD1_RDATA), + .s_axi_rresp (M_AXI_JESD1_RRESP), + .s_axi_rvalid (M_AXI_JESD1_RVALID), + .s_axi_rready (M_AXI_JESD1_RREADY) + ); + +`endif + + // ////////////////////////////////////////////////////////////////////// + // + // LEDS + // + // ////////////////////////////////////////////////////////////////////// + + assign PANEL_LED_LINK = ps_gpio_out[45]; + assign PANEL_LED_REF = ps_gpio_out[46]; + assign PANEL_LED_GPS = ps_gpio_out[47]; + + + ///////////////////////////////////////////////////////////////////// + // + // PUDC Workaround + // + ////////////////////////////////////////////////////////////////////// + // This is a workaround for a silicon bug in Series 7 FPGA where a + // race condition with the reading of PUDC during the erase of the FPGA + // image cause glitches on output IO pins. + // + // Workaround: + // - Define the PUDC pin in the XDC file with a pullup. + // - Implements an IBUF on the PUDC input and make sure that it does + // not get optimized out. + (* dont_touch = "true" *) wire fpga_pudc_b_buf; + IBUF pudc_ibuf_i ( + .I(FPGA_PUDC_B), + .O(fpga_pudc_b_buf)); + +endmodule diff --git a/fpga/usrp3/top/n3xx/dboards/rh/Makefile.srcs b/fpga/usrp3/top/n3xx/dboards/rh/Makefile.srcs new file mode 100644 index 000000000..1296e68e6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/Makefile.srcs @@ -0,0 +1,32 @@ +# +# Copyright 2018 Ettus Research, a National Instruments Company +# + +################################################## +# DB IFC Sources +################################################## +RHODIUM_DB_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/rh/db_ifc/, \ +DbCore.vhd \ +DaughterboardRegs.vhd \ +ClockingRegs.vhd \ +PkgRhPersonality.vhd \ +PkgDaughterboardRegMap.vhd \ +PkgClockingRegMap.vhd \ +PkgJesdConfig.vhd \ +PkgAdcDacInterfaceTypes.vhd \ +RadioClocking.vhd \ +Jesd204bXcvrCore.edf \ +)) + +RHODIUM_TOP_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/rh/, \ +n3xx.v \ +)) + +RHODIUM_DB_CLOCKS_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/rh/, \ +db_clocks.xdc \ +)) + +RHODIUM_DB_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/rh/, \ +db_pins.xdc \ +db_timing.xdc \ +)) diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile new file mode 100644 index 000000000..ff1598894 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile @@ -0,0 +1,27 @@ +# +# Copyright 2018 Ettus Research, a National Instruments Company +# + +.PHONY: all clean + +SRCS=rhodium_top.qpf rhodium_top.qsf rhodium_top.sdc rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v +SIM_SRCS=rh_tb.v rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v +SHORT_HASH=$(addprefix GIT_HASH=,$(shell ../../../../../tools/scripts/git-hash.sh)) + +all: cpld-rhodium-revb.svf + +output_files/rhodium_top.pof: $(SRCS) + quartus_map rhodium_top --verilog_macro="$(SHORT_HASH)" + quartus_fit rhodium_top + quartus_asm rhodium_top + quartus_sta rhodium_top + +cpld-rhodium-revb.svf: output_files/rhodium_top.pof + quartus_cpf --convert --frequency 10.0MHz --voltage 2.5 --operation p $? $@ + +clean: + rm -rf db incremental_db output_files simulation cpld-rhodium-revb.svf + +a.out: $(SIM_SRCS) + iverilog -tvvp -D$(SHORT_HASH) -s rh_tb $(SIM_SRCS) + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rh_tb.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rh_tb.v new file mode 100644 index 000000000..fb5f62328 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rh_tb.v @@ -0,0 +1,410 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rh_tb +// Simple testbench for rhodium_top +// This creates a rudimentary stimulus only, to allow results to be viewed +// in the waveform viewer +////////////////////////////////////////////////////////////////////// + +`timescale 1ns/1ps + + +module rh_tb; + +reg ADC_A_Over_Range_18, ADC_B_Over_Range_18; + +wire [13:0] usrpio_io; // TODO: use one of these as pl_spi_addr[3] + +wire CPLD_PS_SPI_LE_25, CPLD_PS_SPI_CLK_25, + CPLD_PS_ADDR0_25, CPLD_PS_ADDR1_25, CPLD_PS_SPI_SDI_25; +wire CPLD_PS_SPI_SDO_25; + +wire CPLD_PL_SPI_SDO_18; +wire CPLD_PL_SPI_LE_18, CPLD_PL_SPI_SCLK_18, + CPLD_PL_SPI_SDI_18, + CPLD_PL_SPI_ADDR0_18, CPLD_PL_SPI_ADDR1_18, + CPLD_PL_SPI_ADDR2_18, + CPLD_ATR_TX_18, CPLD_ATR_RX_18; +// NOTE: TxRx front-end switches are driven direct from the motherboard, so these ATR +// lines have no function at this time. + +wire ADC_SPI_CS_L_18, ADC_SPI_SCLK_18; +wire ADC_SPI_SDIO_18; + +wire DAC_SPI_CS_L_18, DAC_SPI_SCLK_18; +wire DAC_SPI_SDIO_18; +reg DAC_Alarm_18; // TODO: drive to gpio? + +wire PHDAC_SPI_CS_L, PHDAC_SPI_SCLK, PHDAC_SPI_SDI; + + +reg LO_SYNC; + +wire CLKDIST_SPI_CS_L, + CLKDIST_SPI_SCLK; +wire CLKDIST_SPI_SDIO; + +wire Tx_DSA_C1, + Tx_DSA_C2, + Tx_DSA_C4, + Tx_DSA_C8, + Tx_DSA_C16; + wire Tx_DSA1_LE, + Tx_DSA2_LE; + wire Tx_Sw1_Ctrl_1, + Tx_Sw1_Ctrl_2, + Tx_Sw2_Ctrl_1, + Tx_Sw2_Ctrl_2, + Tx_Sw3_Ctrl_1, + Tx_Sw3_Ctrl_2, + Tx_Sw3_Ctrl_3, + Tx_Sw3_Ctrl_4, + Rx_LO_Input_Select, + Rx_LO_Filter_Sw_1, + Rx_LO_Filter_Sw_2, + Tx_LO_Input_Select, + Tx_LO_Filter_Sw_1, + Tx_LO_Filter_Sw_2; +wire CLKDIST_Status_LD1, + CLKDIST_Status_LD2; +wire LOSYNTH_RX_MUXOUT, + LOSYNTH_TX_MUXOUT; + +wire LO_SPI_SCLK, + LO_SPI_SDI, + LO_TX_CS_L, + LO_RX_CS_L, + Rx_Sw1_Ctrl_1, + Rx_Sw1_Ctrl_2, + Rx_DSA_C1, + Rx_DSA_C2, + Rx_DSA_C4, + Rx_DSA_C8, + Rx_DSA_C16; + wire Rx_DSA1_LE, + Rx_DSA2_LE; + wire Rx_Sw2_Ctrl, + Rx_Sw3_Ctrl_1, + Rx_Sw3_Ctrl_2, + Rx_Sw4_Ctrl_1, + Rx_Sw4_Ctrl_2, + Rx_Sw4_Ctrl_3, + Rx_Sw4_Ctrl_4, + Rx_Demod_ADJ_1, + Rx_Demod_ADJ_2; +wire LO_DSA_C1, + LO_DSA_C2, + LO_DSA_C4, + LO_DSA_C8, + LO_DSA_C16; +wire RxLO_DSA_LE, + TxLO_DSA_LE; +wire LODIST_Bd_SPI_CS_L, + LODIST_Bd_SPI_SDI, + LODIST_Bd_SPI_SCLK, + Tx_Sw5_Ctrl_1, + Tx_Sw5_Ctrl_2, + Rx_Sw6_Ctrl_1, + Rx_Sw6_Ctrl_2; +wire LODIST_Bd_IO1; +wire Tx_HB_LB_Select, +Rx_HB_LB_Select, +Cal_iso_Sw_Ctrl; + + +parameter dly = 20; + +integer scnt; +integer acnt; +integer ccnt; +integer ccnt_max; + +reg ps_sck; +reg ps_mosi; +reg clkdis_cs_b; +reg cpld_ps_cs_b; +reg phdac_cs_b; +reg adc_cs_b; +reg dac_cs_b; + +reg pl_sck; +reg pl_mosi; +reg txlo_cs_b; +reg rxlo_cs_b; +reg lodis_cs_b; +reg cpld_pl_cs_b; + +task ps_cpld_xfer; + input [1:0] tbl; + input [5:0] cmd; + input [15:0] data; + reg [23:0] shiftreg; + integer i; +begin + ps_sck <= 1'b0; + clkdis_cs_b <= 1'b1; + cpld_ps_cs_b <= 1'b1; + phdac_cs_b <= 1'b1; + adc_cs_b <= 1'b1; + dac_cs_b <= 1'b1; + txlo_cs_b <= 1'b1; + rxlo_cs_b <= 1'b1; + lodis_cs_b <= 1'b1; + cpld_pl_cs_b <= 1'b1; + shiftreg <= {tbl,cmd,data}; + #(dly); + cpld_ps_cs_b <= 1'b0; + #(dly); + for (i = 0; i < 24; i = i + 1) begin + ps_sck <= 1'b0; + ps_mosi <= shiftreg[23-i]; + #(dly); + ps_sck <= 1'b1; + #(dly); + end + ps_sck <= 1'b0; + #(dly); + cpld_ps_cs_b <= 1'b1; + #(dly); +end +endtask + +task pl_cpld_xfer; + input [1:0] tbl; + input [5:0] cmd; + input [15:0] data; + reg [23:0] shiftreg; + integer i; +begin + pl_sck <= 1'b0; + clkdis_cs_b <= 1'b1; + cpld_ps_cs_b <= 1'b1; + phdac_cs_b <= 1'b1; + adc_cs_b <= 1'b1; + dac_cs_b <= 1'b1; + txlo_cs_b <= 1'b1; + rxlo_cs_b <= 1'b1; + lodis_cs_b <= 1'b1; + cpld_pl_cs_b <= 1'b1; + shiftreg <= {tbl,cmd,data}; + #(dly); + cpld_pl_cs_b <= 1'b0; + #(dly); + for (i = 0; i < 24; i = i + 1) begin + pl_sck <= 1'b0; + pl_mosi <= shiftreg[23-i]; + #(dly); + pl_sck <= 1'b1; + #(dly); + end + pl_sck <= 1'b0; + #(dly); + cpld_pl_cs_b <= 1'b1; + #(dly); +end +endtask + +assign CPLD_PS_SPI_LE_25 = clkdis_cs_b; +assign CPLD_PS_ADDR0_25 = cpld_ps_cs_b; +assign CPLD_PS_ADDR1_25 = phdac_cs_b; +assign usrpio_io[12] = adc_cs_b; +assign usrpio_io[13] = dac_cs_b; +assign CPLD_PS_SPI_CLK_25 = ps_sck; +assign CPLD_PS_SPI_SDI_25 = ps_mosi; + +assign CPLD_PL_SPI_LE_18 = txlo_cs_b; +assign CPLD_PL_SPI_ADDR1_18 = rxlo_cs_b; +assign CPLD_PL_SPI_ADDR2_18 = lodis_cs_b; +assign CPLD_PL_SPI_ADDR0_18 = cpld_pl_cs_b; +assign CPLD_PL_SPI_SCLK_18 = pl_sck; +assign CPLD_PL_SPI_SDI_18 = pl_mosi; + +assign CLKDIST_Status_LD1 = 1'b0; +assign LOSYNTH_RX_MUXOUT = 1'b1; +assign LOSYNTH_TX_MUXOUT = 1'b1; + +initial +begin + $dumpfile("rh_cpld.vcd"); + $dumpvars; + // Check Signature register read-back + #(dly) ps_cpld_xfer(2'b00, {5'b00000, 1'b1}, 16'h0000); + // Check Signature register is read-only + #(dly) ps_cpld_xfer(2'b00, {5'b00000, 1'b0}, 16'h1234); + #(dly) ps_cpld_xfer(2'b00, {5'b00000, 1'b1}, 16'h0000); + + // Load portions of lower RX gain table with some values + #(dly) ps_cpld_xfer(2'b00, {5'b00110, 1'b0}, 16'h0000); /* Write GAIN_BAND_SEL for lower table */ + #(dly) ps_cpld_xfer(2'b01, 6'd0, {2'd0, 5'd0, 5'd1, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd1, {2'd0, 5'd0, 5'd2, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd2, {2'd0, 5'd1, 5'd2, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd3, {2'd0, 5'd1, 5'd3, 1'b1, 3'd0}); + + // Load portions of upper RX gain table with some values + #(dly) ps_cpld_xfer(2'b00, {5'b00110, 1'b0}, 16'h0101); /* Write GAIN_BAND_SEL for upper table */ + #(dly) ps_cpld_xfer(2'b01, 6'd4, {2'd0, 5'd2, 5'd3, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd5, {2'd0, 5'd2, 5'd4, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd6, {2'd0, 5'd3, 5'd4, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd7, {2'd0, 5'd3, 5'd5, 1'b1, 3'd0}); + + // Check RX gain table readback + #(dly) ps_cpld_xfer(2'b01, 6'd0, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd1, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd2, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd3, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd4, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd5, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd6, 16'h0); + + // Check can write a couple registers on PL side + // (Also make sure we're looking at the lower gain tables) + #(dly) pl_cpld_xfer(2'b00, {5'd6, 1'b0}, 16'h0000); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h0000); + + // Check retrieval of gain values for RX table and program DSAs + #(dly) pl_cpld_xfer(2'b01, 6'd2, {2'b0, 1'b1, 6'b0, 1'b1, 6'b0}); + #(dly) pl_cpld_xfer(2'b01, 6'd3, {2'b0, 1'b0, 6'b0, 1'b1, 6'b0}); + #(dly) pl_cpld_xfer(2'b01, 6'd1, {2'b0, 1'b1, 6'b0, 1'b0, 6'b0}); + + // Check writes to RXBS and TXBS registers + #(dly) pl_cpld_xfer(2'b00, {5'd6, 1'b0}, 16'h1ABC); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h1CAB); + + // Check TX DSA programming is independent of RX DSA programming + #(dly) pl_cpld_xfer(2'b10, 6'd4, {2'b0, 1'b1, 6'b0, 1'b0, 6'b0}); + + // Check LO gain programming works + #(dly) pl_cpld_xfer(2'b11, 6'd5, {2'b0, 1'b1, 6'b0, 1'b0, 6'b0}); + #(dly) pl_cpld_xfer(2'b11, 6'd7, {2'b0, 1'b0, 6'b0, 1'b1, 6'b0}); + #(dly) pl_cpld_xfer(2'b11, 6'd0, {2'b0, 1'b0, 6'b0, 1'b0, 6'b0}); + + // More checks for PL register writes + #(dly) pl_cpld_xfer(2'b00, {5'd6, 1'b0}, 16'h0ABC); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h0CAB); + #(dly) pl_cpld_xfer(2'b00, {5'd8, 1'b0}, 16'hAA5C); + #(dly) pl_cpld_xfer(2'b00, {5'd8, 1'b0}, 16'h5A5C); + #(dly) pl_cpld_xfer(2'b00, {5'd6, 1'b0}, 16'h1C42); + + // Check low/high gain tables and independence of RX vs. TX + #(dly) pl_cpld_xfer(2'b01, 6'd0, 16'h2040); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h104C); + #(dly) pl_cpld_xfer(2'b10, 6'd0, 16'h2040); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h0C80); + #(dly) pl_cpld_xfer(2'b10, 6'd5, 16'h2040); + $finish; +end + +rhodium_top toplevel_inst(usrpio_io, // bank 1A, 1B and 6 +ADC_A_Over_Range_18, ADC_B_Over_Range_18, // bank 1A + +// bank 6 +CPLD_PS_SPI_LE_25, +CPLD_PS_SPI_CLK_25, +CPLD_PS_ADDR0_25, +CPLD_PS_ADDR1_25, +CPLD_PS_SPI_SDI_25, +CPLD_PS_SPI_SDO_25, +PHDAC_SPI_CS_L, PHDAC_SPI_SCLK, PHDAC_SPI_SDI, +LO_SYNC, + +// bank 2 +CPLD_PL_SPI_SDO_18, +CPLD_PL_SPI_LE_18, +CPLD_PL_SPI_SCLK_18, +CPLD_PL_SPI_SDI_18, +CPLD_PL_SPI_ADDR0_18, +CPLD_PL_SPI_ADDR1_18, +CPLD_PL_SPI_ADDR2_18, +CPLD_ATR_TX_18, +CPLD_ATR_RX_18, +ADC_SPI_CS_L_18, +ADC_SPI_SCLK_18, +ADC_SPI_SDIO_18, +DAC_SPI_CS_L_18, +DAC_SPI_SCLK_18, +DAC_SPI_SDIO_18, +DAC_Alarm_18, + +// bank 3 + +CLKDIST_SPI_CS_L, +CLKDIST_SPI_SCLK, +CLKDIST_SPI_SDIO, +Tx_DSA_C1, +Tx_DSA_C2, +Tx_DSA_C4, +Tx_DSA_C8, +Tx_DSA_C16, +Tx_DSA1_LE, +Tx_DSA2_LE, +Tx_Sw1_Ctrl_1, +Tx_Sw1_Ctrl_2, +Tx_Sw2_Ctrl_1, +Tx_Sw2_Ctrl_2, +Tx_Sw3_Ctrl_1, +Tx_Sw3_Ctrl_2, +Tx_Sw3_Ctrl_3, +Tx_Sw3_Ctrl_4, +Rx_LO_Input_Select, +Rx_LO_Filter_Sw_1, +Rx_LO_Filter_Sw_2, +Tx_LO_Input_Select, +Tx_LO_Filter_Sw_1, +Tx_LO_Filter_Sw_2, +CLKDIST_Status_LD1, +CLKDIST_Status_LD2, +LOSYNTH_RX_MUXOUT, +LOSYNTH_TX_MUXOUT, + +// bank 8 +LO_SPI_SCLK, // fans out to both rx & tx synths +LO_SPI_SDI, +LO_TX_CS_L, +LO_RX_CS_L, +Rx_Sw1_Ctrl_1, +Rx_Sw1_Ctrl_2, +Rx_DSA_C1, +Rx_DSA_C2, +Rx_DSA_C4, +Rx_DSA_C8, +Rx_DSA_C16, +Rx_DSA1_LE, +Rx_DSA2_LE, +Rx_Sw2_Ctrl, +Rx_Sw3_Ctrl_1, +Rx_Sw3_Ctrl_2, +Rx_Sw4_Ctrl_1, +Rx_Sw4_Ctrl_2, +Rx_Sw4_Ctrl_3, +Rx_Sw4_Ctrl_4, +Rx_Demod_ADJ_1, +Rx_Demod_ADJ_2, + +// bank 5 +LO_DSA_C1, +LO_DSA_C2, +LO_DSA_C4, +LO_DSA_C8, +LO_DSA_C16, +RxLO_DSA_LE, +TxLO_DSA_LE, +LODIST_Bd_SPI_CS_L, +LODIST_Bd_SPI_SDI, +LODIST_Bd_SPI_SCLK, +LODIST_Bd_IO1, +Tx_Sw5_Ctrl_1, +Tx_Sw5_Ctrl_2, +Rx_Sw6_Ctrl_1, +Rx_Sw6_Ctrl_2, + +Tx_HB_LB_Select, +Rx_HB_LB_Select, +Cal_iso_Sw_Ctrl + + +); +endmodule // rh_tb diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_ctrl.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_ctrl.v new file mode 100644 index 000000000..b13eca846 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_ctrl.v @@ -0,0 +1,203 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rhodium_gain_ctrl +// Description: +// Gain controller for Rhodium +// Provides 2 SPI slaves: +// The "load" slave is used to load the gain table with DSA settings for +// each index. +// The "ctrl" slave takes in a gain index and drives the DSAs with the +// setting found in the gain table. +// The SPI formats are provided below. +////////////////////////////////////////////////////////////////////// + +`default_nettype none + +/** +* SPI DATA FORMAT +* LOADER +* M {table_sel[1:0], gain_index[5:0], rsvd[1:0], dsa1[4:0], dsa2[4:0], wr_en, rsvd[2:0]} +* S {-------------------------------, rsvd[1:0], dsa1[4:0], dsa2[4:0], -------rsvd[3:0]} +* CTRL +* M {table_sel[1:0], gain_index[5:0], rsvd[1:0], wr_dsa1, -rsvd[5:0], wr_dsa2, rsvd[5:0]} +* S {-------------------------------, ---------rsvd[2:0], gain1[5:0], ---rsvd, gain2[5:0]} +*/ +module rhodium_gain_ctrl +#( + parameter TABLE_NUM = 2'b01 +) ( + input wire load_table_sel, + input wire load_sck, + input wire load_csb, + input wire load_mosi, + output wire load_miso, + input wire ctrl_table_sel, + input wire ctrl_sck, + input wire ctrl_csb, + input wire ctrl_mosi, + output reg ctrl_miso, + output wire [4:0] dsa, + output reg dsa1_le, + output reg dsa2_le +); + +localparam CNT_GAIN1_DRIVE = 10, + CNT_DSA1_LE_RISE = 11, + CNT_DSA1_LE_FALL = 14, + CNT_GAIN1_RELEASE = 17; +localparam CNT_GAIN2_DRIVE = 17, + CNT_DSA2_LE_RISE = 18, + CNT_DSA2_LE_FALL = 21, + CNT_GAIN2_RELEASE = 24; + +/****************** +* Gain table loader +*******************/ +reg [4:0] load_bit_cnt; +reg [1:0] load_tbl; +reg [5:0] load_index; +reg [15:0] load_rd_data; +reg [4:0] load_dsa1; +reg [4:0] load_dsa2; +wire [4:0] load_dsa1_prev; +wire [4:0] load_dsa2_prev; + +assign load_miso = load_rd_data[15]; // Shift out on neg edge + +wire wr_en; +assign wr_en = (!load_csb) && (load_tbl == TABLE_NUM) && (load_bit_cnt == 20) && (load_mosi); + +// Cycle counter for where we are in protocol and shift register for input +always @ (posedge load_sck or posedge load_csb) +begin + if (load_csb) begin + load_bit_cnt <= 5'd0; + end else if (!load_csb) begin + {load_dsa1, load_dsa2} <= {load_dsa1[3:0], load_dsa2, load_mosi}; + + if (load_bit_cnt < 23) begin + load_bit_cnt <= load_bit_cnt + 5'd1; + end + if (load_bit_cnt < 8) begin + {load_tbl, load_index} <= {load_tbl[0], load_index, load_mosi}; + end + end +end + +// Readback shift register +always @ (negedge load_sck) +begin + if (load_bit_cnt == 9) begin + load_rd_data <= {load_dsa1_prev, load_dsa2_prev, 5'b000}; + end else begin + load_rd_data <= {load_rd_data[14:0], 1'b0}; + end +end + +/****************** +* Gain table RAM +*******************/ +wire [4:0] ctrl_dsa1; +wire [4:0] ctrl_dsa2; + +/* Use half of table for low band, other half for high band + * Software decides address mapping + */ +rhodium_gain_table gain_table( + .wr_clk(load_sck), + .wr_en(wr_en), + .wr_addr({load_table_sel, load_index}), + .wr_data({load_dsa1, load_dsa2}), + .wr_data_prev({load_dsa1_prev, load_dsa2_prev}), + .rd_clk(ctrl_sck), + .rd_addr({ctrl_table_sel, ctrl_index}), + .rd_data({ctrl_dsa1, ctrl_dsa2}) +); + +/****************** +* Gain control +*******************/ +reg [4:0] ctrl_bit_cnt; +reg [1:0] ctrl_tbl; +reg [5:0] ctrl_index; + +reg [5:0] gain1; +reg [5:0] gain2; +reg gain1_t; +reg gain2_t; + +assign dsa = !gain1_t ? ctrl_dsa1 : + (!gain2_t ? ctrl_dsa2 : + 5'b11111); + +// Cycle counter for where we are in protocol and shift register for input +// Also controls timing of DSAs' latch enable signals +always @ (posedge ctrl_sck or posedge ctrl_csb) +begin + if (ctrl_csb) begin + ctrl_bit_cnt <= 5'd0; + dsa1_le <= 1'b0; + dsa2_le <= 1'b0; + gain1_t <= 1'b1; + gain2_t <= 1'b1; + end else if (!ctrl_csb) begin + if (ctrl_bit_cnt < 23) begin + ctrl_bit_cnt <= ctrl_bit_cnt + 5'd1; + end + + if (ctrl_bit_cnt < 8) begin + {ctrl_tbl, ctrl_index} <= {ctrl_tbl[0], ctrl_index, ctrl_mosi}; + end + + if (ctrl_tbl == TABLE_NUM) begin + if ((ctrl_bit_cnt == CNT_GAIN1_DRIVE) && (ctrl_mosi)) begin + gain1 <= ctrl_index; + gain1_t <= 1'b0; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_RISE)) begin + dsa1_le <= 1'b1; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_FALL)) begin + dsa1_le <= 1'b0; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN1_RELEASE)) begin + gain1_t <= 1'b1; + end + + if ((ctrl_bit_cnt == CNT_GAIN2_DRIVE) && (ctrl_mosi)) begin + gain2 <= ctrl_index; + gain2_t <= 1'b0; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_RISE)) begin + dsa2_le <= 1'b1; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_FALL)) begin + dsa2_le <= 1'b0; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN2_RELEASE)) begin + gain2_t <= 1'b1; + end + end + end +end + +// SPI readback for ctrl bus, based on current bit count +always @ (negedge ctrl_sck) +begin + case (ctrl_bit_cnt) // Shift out on neg edge + 11: ctrl_miso <= gain1[5]; + 12: ctrl_miso <= gain1[4]; + 13: ctrl_miso <= gain1[3]; + 14: ctrl_miso <= gain1[2]; + 15: ctrl_miso <= gain1[1]; + 16: ctrl_miso <= gain1[0]; + 18: ctrl_miso <= gain2[5]; + 19: ctrl_miso <= gain2[4]; + 20: ctrl_miso <= gain2[3]; + 21: ctrl_miso <= gain2[2]; + 22: ctrl_miso <= gain2[1]; + 23: ctrl_miso <= gain2[0]; + default: ctrl_miso <= 1'b0; + endcase +end + +endmodule // rhodium_gain_ctrl +`default_nettype wire diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_table.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_table.v new file mode 100644 index 000000000..abaca43ba --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_table.v @@ -0,0 +1,54 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rhodium_gain_table +// Description: +// Simple dual port memory for use as gain table +// Implements a 128 x 16 bit dual-port RAM for storing 10-bit gain values. +// Write and read domains are independent. Data takes 1 cycle to become valid +// on the output of the RAM once written. +////////////////////////////////////////////////////////////////////// + +`default_nettype none + +module rhodium_gain_table +( + input wire wr_clk, + input wire wr_en, + input wire [6:0] wr_addr, + input wire [9:0] wr_data, + + // Read data for wr_addr (read-first/read-before-write): One cycle latency + output wire [9:0] wr_data_prev, + + input wire rd_clk, + input wire [6:0] rd_addr, + output wire [9:0] rd_data // Read data for rd_addr: One cycle latency +); + +reg [15:0] gain_table[127:0]; +reg [15:0] wr_data_prev_r; +reg [15:0] rd_data_r; + +assign wr_data_prev = wr_data_prev_r[15:6]; +assign rd_data = rd_data_r[15:6]; + +always @ (posedge wr_clk) +begin + if (wr_en) + gain_table[wr_addr] <= {wr_data, 6'b0}; + wr_data_prev_r <= gain_table[wr_addr]; +end + +always @ (posedge rd_clk) +begin + rd_data_r <= gain_table[rd_addr]; +end + + +endmodule // rhodium_gain_table +`default_nettype wire + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_lo_gain.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_lo_gain.v new file mode 100644 index 000000000..0c4ed4c52 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_lo_gain.v @@ -0,0 +1,124 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rhodium_lo_gain +// Description: +// LO Gain controller for Rhodium +// Implements a gain index register (not a table) +// +// Provides 1 SPI slave: +// The "ctrl" slave takes in a gain index and drives the DSA with that +// value. +// The SPI formats are provided below. +////////////////////////////////////////////////////////////////////// + +`default_nettype none + +/** +* SPI DATA FORMAT (left-most bit is first) +* CTRL +* M {table_sel[1:0], rsvd, gain[4:0], rsvd[1:0], wr_dsa1, ------rsvd[5:0], wr_dsa2, ----rsvd[5:0] +* S {-------------------------------, --------------rsvd[3:0], gain1[4:0], -rsvd[1:0], gain2[4:0]} +*/ +module rhodium_lo_gain #( + parameter TABLE_NUM = 2'b01 +) ( + input wire ctrl_sck, + input wire ctrl_csb, + input wire ctrl_mosi, + output reg ctrl_miso, + output wire [4:0] dsa, + output reg dsa1_le, + output reg dsa2_le +); + +localparam CNT_GAIN1_DRIVE = 10, + CNT_DSA1_LE_RISE = 11, + CNT_DSA1_LE_FALL = 14, + CNT_GAIN1_RELEASE = 17; +localparam CNT_GAIN2_DRIVE = 17, + CNT_DSA2_LE_RISE = 18, + CNT_DSA2_LE_FALL = 21, + CNT_GAIN2_RELEASE = 24; + +reg [4:0] ctrl_bit_cnt; +reg [1:0] ctrl_tbl; +reg [5:0] ctrl_index; +reg [5:0] gain1, gain2; +reg gain1_t; +reg gain2_t; + +assign dsa = (!gain1_t | !gain2_t) ? ctrl_index[4:0] : 5'b11111; + +// Cycle counter for where we are in protocol and shift register for input +// Also controls timing of DSAs' latch enable signals +always @ (posedge ctrl_sck or posedge ctrl_csb) +begin + if (ctrl_csb) begin + ctrl_bit_cnt <= 5'd0; + dsa1_le <= 1'b0; + dsa2_le <= 1'b0; + gain1_t <= 1'b1; + gain2_t <= 1'b1; + end else if (!ctrl_csb) begin + if (ctrl_bit_cnt < 23) begin + ctrl_bit_cnt <= ctrl_bit_cnt + 5'd1; + end + + if (ctrl_bit_cnt < 8) begin + {ctrl_tbl, ctrl_index} <= {ctrl_tbl[0], ctrl_index, ctrl_mosi}; + end + + if (ctrl_tbl == TABLE_NUM) begin + if ((ctrl_bit_cnt == CNT_GAIN1_DRIVE) && (ctrl_mosi)) begin + gain1 <= ctrl_index; + gain1_t <= 1'b0; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_RISE)) begin + dsa1_le <= 1'b1; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_FALL)) begin + dsa1_le <= 1'b0; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN1_RELEASE)) begin + gain1_t <= 1'b1; + end + + if ((ctrl_bit_cnt == CNT_GAIN2_DRIVE) && (ctrl_mosi)) begin + gain2 <= ctrl_index; + gain2_t <= 1'b0; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_RISE)) begin + dsa2_le <= 1'b1; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_FALL)) begin + dsa2_le <= 1'b0; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN2_RELEASE)) begin + gain2_t <= 1'b1; + end + end + end +end + +// SPI readback for ctrl bus, based on current bit count +always @ (negedge ctrl_sck) +begin + case (ctrl_bit_cnt) // Shift out on neg edge + 11: ctrl_miso <= gain1[5]; + 12: ctrl_miso <= gain1[4]; + 13: ctrl_miso <= gain1[3]; + 14: ctrl_miso <= gain1[2]; + 15: ctrl_miso <= gain1[1]; + 16: ctrl_miso <= gain1[0]; + 18: ctrl_miso <= gain2[5]; + 19: ctrl_miso <= gain2[4]; + 20: ctrl_miso <= gain2[3]; + 21: ctrl_miso <= gain2[2]; + 22: ctrl_miso <= gain2[1]; + 23: ctrl_miso <= gain2[0]; + default: ctrl_miso <= 1'b0; + endcase +end + + +endmodule // rhodium_lo_gain +`default_nettype wire + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf new file mode 100644 index 000000000..5e1bf4d57 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition +# Date created = 08:22:34 September 13, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "08:22:34 September 13, 2017" + +# Revisions + +PROJECT_REVISION = "rhodium_top" diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf new file mode 100644 index 000000000..e94f0bbc8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf @@ -0,0 +1,306 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition +# Date created = 08:22:34 September 13, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# rhodium_top_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M04SAU169I7G +set_global_assignment -name TOP_LEVEL_ENTITY rhodium_top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:22:34 SEPTEMBER 13, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_D11 -to CPLD_PS_SPI_LE_25 +set_location_assignment PIN_F13 -to CPLD_PS_SPI_CLK_25 +set_location_assignment PIN_E10 -to CPLD_PS_ADDR0_25 +set_location_assignment PIN_A12 -to CPLD_PS_ADDR1_25 +set_location_assignment PIN_F12 -to CPLD_PS_SPI_SDI_25 +set_location_assignment PIN_F10 -to CPLD_PS_SPI_SDO_25 +set_location_assignment PIN_B1 -to ADC_A_Over_Range_18 +set_location_assignment PIN_D1 -to ADC_B_Over_Range_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_A_Over_Range_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_B_Over_Range_18 +set_instance_assignment -name IO_STANDARD LVDS -to LO_SYNC +set_location_assignment PIN_G9 -to LO_SYNC +set_location_assignment PIN_G10 -to "LO_SYNC(n)" +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_CS_L_18 +set_location_assignment PIN_C2 -to ADC_SPI_CS_L_18 +set_location_assignment PIN_C1 -to ADC_SPI_SCLK_18 +set_location_assignment PIN_E3 -to ADC_SPI_SDIO_18 +set_location_assignment PIN_M5 -to CLKDIST_SPI_CS_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_CS_L +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_SCLK_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_SDIO_18 +set_location_assignment PIN_L5 -to CLKDIST_SPI_SCLK +set_location_assignment PIN_N5 -to CLKDIST_SPI_SDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_SDIO +set_location_assignment PIN_K6 -to CLKDIST_Status_LD1 +set_location_assignment PIN_J6 -to CLKDIST_Status_LD2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_Status_LD1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_Status_LD2 +set_location_assignment PIN_M1 -to CPLD_ATR_TX_18 +set_location_assignment PIN_L1 -to CPLD_ATR_RX_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_ATR_RX_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_ATR_TX_18 +set_location_assignment PIN_H6 -to CPLD_PL_SPI_ADDR0_18 +set_location_assignment PIN_K2 -to CPLD_PL_SPI_ADDR1_18 +set_location_assignment PIN_J2 -to CPLD_PL_SPI_ADDR2_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR0_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR1_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR2_18 +set_location_assignment PIN_K1 -to CPLD_PL_SPI_LE_18 +set_location_assignment PIN_H5 -to CPLD_PL_SPI_SCLK_18 +set_location_assignment PIN_L3 -to CPLD_PL_SPI_SDI_18 +set_location_assignment PIN_L2 -to CPLD_PL_SPI_SDO_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_LE_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SCLK_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SDI_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SDO_18 +set_location_assignment PIN_M2 -to DAC_Alarm_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_Alarm_18 +set_location_assignment PIN_N3 -to DAC_SPI_SDIO_18 +set_location_assignment PIN_N2 -to DAC_SPI_SCLK_18 +set_location_assignment PIN_M3 -to DAC_SPI_CS_L_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_CS_L_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_SCLK_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_SDIO_18 +set_location_assignment PIN_M7 -to LOSYNTH_RX_MUXOUT +set_location_assignment PIN_N7 -to LOSYNTH_TX_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LOSYNTH_RX_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LOSYNTH_TX_MUXOUT +set_location_assignment PIN_E6 -to LO_RX_CS_L +set_location_assignment PIN_B2 -to LO_SPI_SCLK +set_location_assignment PIN_M4 -to LO_SPI_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_RX_CS_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_SPI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_SPI_SDI +set_location_assignment PIN_K5 -to LO_TX_CS_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_TX_CS_L +set_location_assignment PIN_B6 -to Rx_DSA1_LE +set_location_assignment PIN_A9 -to Rx_DSA2_LE +set_location_assignment PIN_D8 -to Rx_DSA_C1 +set_location_assignment PIN_D6 -to Rx_DSA_C2 +set_location_assignment PIN_A11 -to Rx_DSA_C4 +set_location_assignment PIN_B10 -to Rx_DSA_C8 +set_location_assignment PIN_A10 -to Rx_DSA_C16 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA1_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA2_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C8 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C16 +set_location_assignment PIN_B3 -to Rx_Demod_ADJ_1 +set_location_assignment PIN_N4 -to Rx_Demod_ADJ_2 +set_location_assignment PIN_J5 -to Rx_LO_Filter_Sw_1 +set_location_assignment PIN_J7 -to Rx_LO_Filter_Sw_2 +set_location_assignment PIN_L4 -to Rx_LO_Input_Select +set_location_assignment PIN_A6 -to Rx_Sw1_Ctrl_1 +set_location_assignment PIN_A7 -to Rx_Sw1_Ctrl_2 +set_location_assignment PIN_A5 -to Rx_Sw2_Ctrl +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Demod_ADJ_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Demod_ADJ_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw1_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw1_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw2_Ctrl +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Filter_Sw_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Filter_Sw_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Input_Select +set_location_assignment PIN_A4 -to Rx_Sw3_Ctrl_1 +set_location_assignment PIN_A3 -to Rx_Sw3_Ctrl_2 +set_location_assignment PIN_C10 -to Rx_Sw4_Ctrl_1 +set_location_assignment PIN_A8 -to Rx_Sw4_Ctrl_2 +set_location_assignment PIN_B9 -to Rx_Sw4_Ctrl_3 +set_location_assignment PIN_C9 -to Rx_Sw4_Ctrl_4 +set_location_assignment PIN_K13 -to Tx_DSA1_LE +set_location_assignment PIN_K12 -to Tx_DSA2_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw3_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw3_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA1_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA2_LE +set_location_assignment PIN_H13 -to Tx_DSA_C1 +set_location_assignment PIN_H8 -to Tx_DSA_C2 +set_location_assignment PIN_J13 -to Tx_DSA_C4 +set_location_assignment PIN_H10 -to Tx_DSA_C8 +set_location_assignment PIN_J12 -to Tx_DSA_C16 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C8 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C16 +set_location_assignment PIN_N6 -to Tx_LO_Filter_Sw_1 +set_location_assignment PIN_N12 -to Tx_LO_Filter_Sw_2 +set_location_assignment PIN_N8 -to Tx_LO_Input_Select +set_location_assignment PIN_L10 -to Tx_Sw1_Ctrl_1 +set_location_assignment PIN_N10 -to Tx_Sw1_Ctrl_2 +set_location_assignment PIN_N11 -to Tx_Sw2_Ctrl_1 +set_location_assignment PIN_L11 -to Tx_Sw2_Ctrl_2 +set_location_assignment PIN_L12 -to Tx_Sw3_Ctrl_1 +set_location_assignment PIN_M13 -to Tx_Sw3_Ctrl_2 +set_location_assignment PIN_K11 -to Tx_Sw3_Ctrl_3 +set_location_assignment PIN_J9 -to Tx_Sw3_Ctrl_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Filter_Sw_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Filter_Sw_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Input_Select +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw1_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw1_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw2_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw2_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_4 +set_location_assignment PIN_B11 -to PHDAC_SPI_CS_L +set_location_assignment PIN_C11 -to PHDAC_SPI_SCLK +set_location_assignment PIN_D9 -to PHDAC_SPI_SDI +set_location_assignment PIN_N9 -to LODIST_Bd_SPI_CS_L +set_location_assignment PIN_J8 -to LODIST_Bd_SPI_SCLK +set_location_assignment PIN_M9 -to LODIST_Bd_SPI_SDI +set_location_assignment PIN_L13 -to LO_DSA_C1 +set_location_assignment PIN_K10 -to LO_DSA_C2 +set_location_assignment PIN_H9 -to LO_DSA_C4 +set_location_assignment PIN_G12 -to LO_DSA_C8 +set_location_assignment PIN_G13 -to LO_DSA_C16 +set_location_assignment PIN_J10 -to RxLO_DSA_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_CS_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C8 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C16 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RxLO_DSA_LE +set_location_assignment PIN_B4 -to Rx_Sw6_Ctrl_1 +set_location_assignment PIN_B5 -to Rx_Sw6_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw6_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw6_Ctrl_2 +set_location_assignment PIN_M8 -to TxLO_DSA_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TxLO_DSA_LE +set_location_assignment PIN_M11 -to Tx_Sw5_Ctrl_1 +set_location_assignment PIN_M12 -to Tx_Sw5_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw5_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw5_Ctrl_2 +set_location_assignment PIN_D12 -to Cal_iso_Sw_Ctrl +set_location_assignment PIN_K8 -to LODIST_Bd_IO1 +set_location_assignment PIN_M10 -to Tx_HB_LB_Select +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_HB_LB_Select +set_location_assignment PIN_E8 -to Rx_HB_LB_Select +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_HB_LB_Select +set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_CS_L +set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_SCLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_SDI +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_ADDR0_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_ADDR1_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_CLK_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_LE_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_SDI_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_SDO_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to Cal_iso_Sw_Ctrl +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to LODIST_Bd_IO1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_location_assignment PIN_E4 -to usrp_io[0] +set_location_assignment PIN_G5 -to usrp_io[1] +set_location_assignment PIN_H4 -to usrp_io[2] +set_location_assignment PIN_J1 -to usrp_io[3] +set_location_assignment PIN_F1 -to usrp_io[4] +set_location_assignment PIN_C12 -to usrp_io[5] +set_location_assignment PIN_C13 -to usrp_io[6] +set_location_assignment PIN_E12 -to usrp_io[7] +set_location_assignment PIN_E13 -to usrp_io[8] +set_location_assignment PIN_B13 -to usrp_io[9] +set_location_assignment PIN_F9 -to usrp_io[10] +set_location_assignment PIN_B12 -to usrp_io[11] +set_location_assignment PIN_E9 -to usrp_io[12] +set_location_assignment PIN_F8 -to usrp_io[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[13] +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH rh_tb -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME rh_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id rh_tb +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "9000 ns" -section_id rh_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME rh_tb -section_id rh_tb +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name VERILOG_FILE rhodium_top.v +set_global_assignment -name VERILOG_FILE rhodium_gain_ctrl.v +set_global_assignment -name VERILOG_FILE rhodium_gain_table.v +set_global_assignment -name VERILOG_FILE rhodium_lo_gain.v +set_global_assignment -name VERILOG_FILE rh_tb.v +set_global_assignment -name EDA_TEST_BENCH_FILE rh_tb.v -section_id rh_tb + + +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name GENERATE_SVF_FILE ON +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.sdc b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.sdc new file mode 100644 index 000000000..4b00a5053 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.sdc @@ -0,0 +1,415 @@ +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Copyright 2019 Ettus Research, A National Instruments Company +# +# Timing constraints for Rhodium's MAX 10 board controller + +set_time_format -unit ns -decimal_places 3 + +# Some constants for constraining the design with the FPGA-centric method: +# Maximum trace propagation delay is assumed to be 0.6 ns on any traces +# to on-dboard slaves +set board_delay 0.600 +set clk_uncertainty 0.150 + +############################################################################### +# Clocks +############################################################################### + +# The PS SPI clock is maximum 10 MHz. It is driven from another source and +# provided with the data. +# CPLD_PS_SPI_CLK_25: 8 MHz +set sclk_ps_period 125.000 + +# Create clock for the PS's SPI interface +create_clock -name sclk_ps -period $sclk_ps_period \ + [get_ports CPLD_PS_SPI_CLK_25] + +# The PL SPI clock is split into two pieces. For the normal case, the clock +# frequency is 10 MHz. This is for any read operations. +# +# CPLD_PL_SPI_SCLK_18 pass through / read back ONLY: 10 MHz +set sclk_pl_period 100.000 +create_clock -name sclk_pl -period $sclk_pl_period \ + [get_ports CPLD_PL_SPI_SCLK_18] + +# We can go faster for the PL writes to the internal registers and LOs. +# This rate is not supported for readback, but it helps with getting the DSA +# settings and LO settings in faster. +# CPLD_PL_SPI_SCLK_18 internal ONLY: 25 MHz +set sclk_pl_wr_period 40.000 +create_clock -name sclk_pl_wr -period $sclk_pl_wr_period \ + [get_ports CPLD_PL_SPI_SCLK_18] -add + +# Output clocks for the MAX 10's SPI master interfaces (1 for each slave IC) +create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \ + -name clkdist_clk [get_ports CLKDIST_SPI_SCLK] +create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \ + -name adc_clk [get_ports ADC_SPI_SCLK_18] +create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \ + -name dac_clk [get_ports DAC_SPI_SCLK_18] +create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \ + -name phdac_clk [get_ports PHDAC_SPI_SCLK] + +create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \ + -master_clock [get_clocks sclk_pl] \ + -name lo_clk [get_ports LO_SPI_SCLK] +create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \ + -master_clock [get_clocks sclk_pl_wr] \ + -name lo_wr_clk [get_ports LO_SPI_SCLK] -add +create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \ + -master_clock [get_clocks sclk_pl] \ + -name lodist_clk [get_ports LODIST_Bd_SPI_SCLK] + +# Virtual clock for DSA writes for skew calculations +#create_generated_clock -source [get_pins lo_gain_table\|dsa1_le\|clk] +create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \ + -master_clock [get_clocks sclk_pl_wr] \ + -name dsa_reg_clk [get_pins lo_gain_table\|dsa1_le\|q] + +create_generated_clock -source [get_pins lo_gain_table\|dsa1_le\|q] \ + -name dsa_clk [get_ports RxLO_DSA_LE] + +# PL's pass through clock doesn't interact with internal clock +set_clock_groups -physically_exclusive \ + -group [get_clocks {sclk_pl_wr lo_wr_clk dsa_reg_clk dsa_clk}] \ + -group [get_clocks {sclk_pl lo_clk lodist_clk}] + +set_clock_groups -asynchronous \ + -group [get_clocks {sclk_ps clkdist_clk adc_clk dac_clk phdac_clk}] \ + -group [get_clocks {sclk_pl sclk_pl_wr lo_clk lodist_clk}] + +set_clock_uncertainty -to [get_clocks {sclk_ps sclk_pl sclk_pl_wr clkdist_clk + adc_clk dac_clk phdac_clk lo_clk lo_wr_clk lodist_clk dsa_reg_clk dsa_clk}] \ + $clk_uncertainty + +############################################################################### +# Timing Budget Calculations +############################################################################### +# Here we carve out some timing budget for the master's SPI interfaces. +# The master will use these values to time its SPI interface. +# The PL's write-only values are smaller because there are no external chip +# dependencies. +set setup_ps 25 +set hold_ps 30 + +# PL SPI is constrained on the master with an allowed skew value of +/- 3 ns +# relative to the launch clock +# Increase to 5 ns here for more margin +set pl_skew 5 + +# Clocks are nominally a 50% duty cycle, so difference between latch and +# launch is half a period, so subtract allowed skew from that for setup/hold +# specification. The half period is due to launch being the falling edge and +# latch being the rising edge. +set setup_pl [expr {$sclk_pl_period / 2 - $pl_skew}] +set hold_pl [expr {$sclk_pl_period / 2 - $pl_skew}] +set setup_pl_wr [expr {$sclk_pl_wr_period / 2 - $pl_skew}] +set hold_pl_wr [expr {$sclk_pl_wr_period / 2 - $pl_skew}] + +# Calculate input delays relative to falling edge (launch) +# Min is hold time after previous rising edge (previous latch) +# Max is setup time before next rising edge (next latch) +set input_delay_min_ps [expr {-$sclk_ps_period / 2 + $hold_ps}] +set input_delay_max_ps [expr {$sclk_ps_period / 2 - $setup_ps}] +set input_delay_min_pl [expr {-$sclk_pl_period / 2 + $hold_pl}] +set input_delay_max_pl [expr {$sclk_pl_period / 2 - $setup_pl}] +set input_delay_min_pl_wr [expr {-$sclk_pl_wr_period / 2 + $hold_pl_wr}] +set input_delay_max_pl_wr [expr {$sclk_pl_wr_period / 2 - $setup_pl_wr}] + +# Again, carve out timing budget for master's SPI interface +# Readback on the master will depend on clk-to-q of our slave. +# These values will need to be at least as large as the worst slave. +# Clock arrival at the slave will be delayed by propagation through the MAX 10 +# Data to the MAX 10's input port will be further delayed by slave's clk-to-q +# On top of that, we then need budget for the data to cross the MAX 10, head +# out the I/O, and propagate to the master's pin. Then the master will need +# some budget for setup time. +# +# Here is what we'll budget: +# Clk propagation to I/O: 7 ns +# Clk trace delay: 1 ns +# Worst-case chip clk-to-q: 10 ns +# Data trace delay: 1 ns +# Data propagation delay from input pin to output pin: 8 ns +# Total clk-to-q from MAX 10 sclk input to MAX 10 output: 27 ns +# +# Then master's budget is 23 ns for clock delay + data delay + setup time +set clk_q_max_ps 27.000 + +# For the PL, the worst-case chip changes to 2 ns, so there is more budget +set clk_q_max_pl 20.000 + +# clk-to-q determines one side of the data invalid window +# The maximum output delay is simply latch edge - clk-to-q +# Launch is falling edge, and latch is rising edge, so... +set output_delay_max_ps [expr {$sclk_ps_period / 2 - $clk_q_max_ps}] +set output_delay_max_pl [expr {$sclk_pl_period / 2 - $clk_q_max_pl}] + +# The minimum output delay represents the other edge of the data invalid +# window. Our clock is likely quite delayed already, but add a little more +# margin for hold time. +set output_delay_min_ps -5.000 +set output_delay_min_pl -5.000 + + +############################################################################### +# I/O groups (for reference later) +############################################################################### + +# Chip selects +set ps_csb [get_ports { + CPLD_PS_ADDR0_25 + CPLD_PS_ADDR1_25 + CPLD_PS_SPI_LE_25 + usrp_io[12] + usrp_io[13] +}] +set pl_csb [get_ports { + CPLD_PL_SPI_ADDR0_18 + CPLD_PL_SPI_ADDR1_18 + CPLD_PL_SPI_ADDR2_18 + CPLD_PL_SPI_LE_18 +}] + +# Data for internal PL SPI +set pl_src [get_ports { + CPLD_PL_SPI_SDI_18 +}] + +# Passthrough inputs (forward direction) +# CPLD_PS_SPI_CLK_25 and CPLD_PL_SPI_SCLK_18 are special +set ps_pt_src [get_ports {CPLD_PS_SPI_LE_25 + usrp_io[12] + usrp_io[13] + CPLD_PS_ADDR1_25 + CPLD_PS_SPI_SDI_25 + }] + +set pl_pt_src [get_ports {CPLD_PL_SPI_LE_18 + CPLD_PL_SPI_ADDR1_18 + CPLD_PL_SPI_ADDR2_18 + CPLD_PL_SPI_SDI_18 + }] + +# Passthrough outputs (forward direction) +# And inputs from the SPI slaves (readback direction) +set clkdist_spi_out [get_ports { + CLKDIST_SPI_CS_L + CLKDIST_SPI_SDIO +}] + +set clkdist_spi_in [get_ports { + CLKDIST_SPI_SDIO +}] + +set phdac_spi [get_ports { + PHDAC_SPI_CS_L + PHDAC_SPI_SDI +}] + +set dac_spi_out [get_ports { + DAC_SPI_CS_L_18 + DAC_SPI_SDIO_18 +}] + +set dac_spi_in [get_ports { + DAC_SPI_SDIO_18 +}] + +set adc_spi_out [get_ports { + ADC_SPI_CS_L_18 + ADC_SPI_SDIO_18 +}] + +set adc_spi_in [get_ports { + ADC_SPI_SDIO_18 +}] + +set lo_spi_out [get_ports { + LO_TX_CS_L + LO_RX_CS_L + LO_SPI_SDI +}] + +set lo_spi_in [get_ports { + LOSYNTH_RX_MUXOUT + LOSYNTH_TX_MUXOUT +}] + +set lodist_spi_out [get_ports { + LODIST_Bd_SPI_CS_L + LODIST_Bd_SPI_SDI +}] + +# Readback outputs +set ps_rb_out [get_ports CPLD_PS_SPI_SDO_25] +set pl_rb_out [get_ports CPLD_PL_SPI_SDO_18] + +############################################################################## +# Chip-selects provide async resets +############################################################################## +set_false_path -from $ps_csb -to [get_pins *|clrn] +set_false_path -from $pl_csb -to [get_pins *|clrn] + +# Also ignore setup/hold analysis for chip-selects affecting readback path +# These are available many cycles before readback begins and have +# combinatorial paths to the output +set_false_path -from $ps_csb -to $ps_rb_out +set_false_path -from $pl_csb -to $pl_rb_out + +set_input_delay -clock sclk_ps -clock_fall -max $input_delay_max_ps \ + [get_ports CPLD_PS_ADDR0_25] +set_input_delay -clock sclk_ps -clock_fall -min $input_delay_min_ps \ + [get_ports CPLD_PS_ADDR0_25] + +set_input_delay -clock sclk_pl -clock_fall -max $input_delay_max_pl \ + [get_ports CPLD_PL_SPI_ADDR0_18] +set_input_delay -clock sclk_pl -clock_fall -min $input_delay_min_pl \ + [get_ports CPLD_PL_SPI_ADDR0_18] + +set_input_delay -clock sclk_pl_wr -clock_fall -max $input_delay_max_pl_wr \ + [get_ports CPLD_PL_SPI_ADDR0_18] -add +set_input_delay -clock sclk_pl_wr -clock_fall -min $input_delay_min_pl_wr \ + [get_ports CPLD_PL_SPI_ADDR0_18] -add + + +############################################################################## +# Input delays from SPI master +############################################################################## +set_input_delay -clock sclk_ps -clock_fall -max $input_delay_max_ps $ps_pt_src +set_input_delay -clock sclk_ps -clock_fall -min $input_delay_min_ps $ps_pt_src + +set_input_delay -clock sclk_pl -clock_fall -max $input_delay_max_pl $pl_pt_src +set_input_delay -clock sclk_pl -clock_fall -min $input_delay_min_pl $pl_pt_src + +set_input_delay -clock sclk_pl_wr -clock_fall -max $input_delay_max_pl_wr $pl_src -add +set_input_delay -clock sclk_pl_wr -clock_fall -min $input_delay_min_pl_wr $pl_src -add + +############################################################################## +# Output delays to each SPI slave (uses setup/hold times from data sheet) +############################################################################## +set adc_setup 4 +set adc_hold 2 +set_output_delay -clock adc_clk -max [expr {$adc_setup + $board_delay}] \ + $adc_spi_out +set_output_delay -clock adc_clk -min [expr {-$adc_hold - $board_delay}] \ + $adc_spi_out + +set dac_setup 10 +set dac_hold 5 +set_output_delay -clock dac_clk -max [expr {$dac_setup + $board_delay}] \ + $dac_spi_out +set_output_delay -clock dac_clk -min [expr {-$dac_hold - $board_delay}] \ + $dac_spi_out + +set phdac_setup 5 +set phdac_hold 5 +set_output_delay -clock phdac_clk -max [expr {$phdac_setup + $board_delay}] \ + $phdac_spi +set_output_delay -clock phdac_clk -min [expr {-$phdac_hold - $board_delay}] \ + $phdac_spi + +set clkdist_setup 10 +set clkdist_hold 10 +set_output_delay -clock clkdist_clk -max [expr {$clkdist_setup + $board_delay}] \ + $clkdist_spi_out +set_output_delay -clock clkdist_clk -min [expr {-$clkdist_hold - $board_delay}] \ + $clkdist_spi_out + +set lo_setup 2 +set lo_hold 2 +set_output_delay -clock lo_wr_clk -max [expr {$lo_setup + $board_delay}] \ + $lo_spi_out +set_output_delay -clock lo_wr_clk -min [expr {-$lo_hold - $board_delay}] \ + $lo_spi_out + +############################################################################## +# Input delays from each SPI slave (uses clk-to-q times from data sheet) +# One board delay for clock, another for data +############################################################################## +set lo_clk_q 2 +set_input_delay -clock lo_clk -clock_fall -max [expr {$lo_clk_q + $board_delay + $board_delay}] \ + $lo_spi_in +set_input_delay -clock lo_clk -clock_fall -min 0 \ + $lo_spi_in + +set adc_clk_q 10 +set dac_clk_q 10 +set clkdist_clk_q 10 +set_input_delay -clock adc_clk -clock_fall -max [expr {$adc_clk_q + $board_delay + $board_delay}] \ + $adc_spi_in +set_input_delay -clock adc_clk -clock_fall -min 0 \ + $adc_spi_in +set_input_delay -clock dac_clk -clock_fall -max [expr {$dac_clk_q + $board_delay + $board_delay}] \ + $dac_spi_in +set_input_delay -clock dac_clk -clock_fall -min 0 \ + $dac_spi_in +set_input_delay -clock clkdist_clk -clock_fall -max [expr {$clkdist_clk_q + $board_delay + $board_delay}] \ + $clkdist_spi_in +set_input_delay -clock clkdist_clk -clock_fall -min 0 \ + $clkdist_spi_in + + +############################################################################## +# Output delays for readback path +############################################################################## +set_output_delay -clock sclk_ps -max $output_delay_max_ps $ps_rb_out +set_output_delay -clock sclk_ps -min $output_delay_min_ps $ps_rb_out + +set_output_delay -clock sclk_pl -max $output_delay_max_pl $pl_rb_out +set_output_delay -clock sclk_pl -min $output_delay_min_pl $pl_rb_out + +############################################################################## +# GPIOs and DSAs +# Outputs that aren't timing-critical +############################################################################## +set gpos [get_ports {Tx_Sw* + Rx_LO_* + Tx_LO_* + Rx_Sw* + Rx_Demod_* + Tx_HB_LB_Select + Rx_HB_LB_Select + Cal_iso_Sw_Ctrl + LODIST_Bd_IO1 + }] + +# Inputs that aren't timing-critical +set gpis [get_ports {LO_SYNC + CPLD_ATR_TX_18 + CPLD_ATR_RX_18 + DAC_Alarm_18 + CLKDIST_Status* + LODIST_Bd_IO1 + }] + +# DSAs (special skew needs) +# RxLO_DSA_LE used for skew basis +set dsas [get_ports {Tx_DSA* + Rx_DSA* + TxLO_DSA* + LO_DSA* + }] + +# Just do false paths for gpios +set_false_path -to $gpos +set_false_path -from $gpis + +# Unused +set_false_path -to $lodist_spi_out + +# DSA skew timing +# Earlier, we created a "clock" for one of the DSA latch enable signals +# Use set_output_delay to constrain skew around the latch enable +# set_multicycle_path is used to make latch clock = launch clock for setup +# Constrain skew to 8 ns -- controller nominally does 120 ns minimum between +# edges, and 100 ns is the DSA's requirement for setup/hold +set dsa_skew 8.0 +set_output_delay -clock dsa_clk -max -$dsa_skew $dsas +set_output_delay -clock dsa_clk -min $dsa_skew $dsas +set_multicycle_path -start -setup 0 -to $dsas + +set_max_delay -from [get_ports CPLD_ATR_TX_18] \ + -to [get_ports {Tx_Sw1_Ctrl_1 Tx_Sw1_Ctrl_2}] 10.0 + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v new file mode 100644 index 000000000..1d0d640da --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v @@ -0,0 +1,605 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rhodium_top +////////////////////////////////////////////////////////////////////// + +`default_nettype none + +module rhodium_top( + +input [13:0] usrp_io, // bank 1A, 1B and 6 + +input ADC_A_Over_Range_18, input ADC_B_Over_Range_18, // bank 1A + +// bank 6 +input CPLD_PS_SPI_LE_25, +input CPLD_PS_SPI_CLK_25, +input CPLD_PS_ADDR0_25, +input CPLD_PS_ADDR1_25, +input CPLD_PS_SPI_SDI_25, +output reg CPLD_PS_SPI_SDO_25, +output PHDAC_SPI_CS_L, +output PHDAC_SPI_SCLK, +output PHDAC_SPI_SDI, +input LO_SYNC, + +// bank 2 +output reg CPLD_PL_SPI_SDO_18, +input CPLD_PL_SPI_LE_18, +input CPLD_PL_SPI_SCLK_18, +input CPLD_PL_SPI_SDI_18, +input CPLD_PL_SPI_ADDR0_18, +input CPLD_PL_SPI_ADDR1_18, +input CPLD_PL_SPI_ADDR2_18, +// NOTE: TxRx front-end switches are driven direct from the motherboard, so these ATR +// lines have no function at this time. +input CPLD_ATR_TX_18, +input CPLD_ATR_RX_18, +output ADC_SPI_CS_L_18, +output ADC_SPI_SCLK_18, +inout ADC_SPI_SDIO_18, +output DAC_SPI_CS_L_18, +output DAC_SPI_SCLK_18, +inout DAC_SPI_SDIO_18, +input DAC_Alarm_18, // TODO: drive to gpio? + +// bank 3 + +output CLKDIST_SPI_CS_L, +output CLKDIST_SPI_SCLK, +inout CLKDIST_SPI_SDIO, +output Tx_DSA_C1, +output Tx_DSA_C2, +output Tx_DSA_C4, +output Tx_DSA_C8, +output Tx_DSA_C16, +output Tx_DSA1_LE, +output Tx_DSA2_LE, +output Tx_Sw1_Ctrl_1, +output Tx_Sw1_Ctrl_2, +output Tx_Sw2_Ctrl_1, +output Tx_Sw2_Ctrl_2, +output Tx_Sw3_Ctrl_1, +output Tx_Sw3_Ctrl_2, +output Tx_Sw3_Ctrl_3, +output Tx_Sw3_Ctrl_4, +output Rx_LO_Input_Select, +output Rx_LO_Filter_Sw_1, +output Rx_LO_Filter_Sw_2, +output Tx_LO_Input_Select, +output Tx_LO_Filter_Sw_1, +output Tx_LO_Filter_Sw_2, +input CLKDIST_Status_LD1, +input CLKDIST_Status_LD2, +input LOSYNTH_RX_MUXOUT, +input LOSYNTH_TX_MUXOUT, + +// bank 8 +output LO_SPI_SCLK, // fans out to both rx & tx synths +output LO_SPI_SDI, +output LO_TX_CS_L, +output LO_RX_CS_L, +output Rx_Sw1_Ctrl_1, +output Rx_Sw1_Ctrl_2, +output Rx_DSA_C1, +output Rx_DSA_C2, +output Rx_DSA_C4, +output Rx_DSA_C8, +output Rx_DSA_C16, +output Rx_DSA1_LE, +output Rx_DSA2_LE, +output Rx_Sw2_Ctrl, +output Rx_Sw3_Ctrl_1, +output Rx_Sw3_Ctrl_2, +output Rx_Sw4_Ctrl_1, +output Rx_Sw4_Ctrl_2, +output Rx_Sw4_Ctrl_3, +output Rx_Sw4_Ctrl_4, +output Rx_Demod_ADJ_1, +output Rx_Demod_ADJ_2, + +// bank 5 +output LO_DSA_C1, +output LO_DSA_C2, +output LO_DSA_C4, +output LO_DSA_C8, +output LO_DSA_C16, +output RxLO_DSA_LE, +output TxLO_DSA_LE, +output LODIST_Bd_SPI_CS_L, +output LODIST_Bd_SPI_SDI, +output LODIST_Bd_SPI_SCLK, +inout LODIST_Bd_IO1, +output Tx_Sw5_Ctrl_1, +output Tx_Sw5_Ctrl_2, +output Rx_Sw6_Ctrl_1, +output Rx_Sw6_Ctrl_2, + +output Tx_HB_LB_Select, +output Rx_HB_LB_Select, +output Cal_iso_Sw_Ctrl + + +); + +/* PS SPI */ + +localparam GIT_HASH = 36'h`GIT_HASH; +localparam PROD_SIGNATURE = 16'h0045; // Product signature (Rhodium atomic number in BCD) +localparam REVISION_MINOR = 16'h0002; +localparam REVISION_MAJOR = 16'h0004; +localparam CPLD_BUILD_LSB = GIT_HASH[15:0]; // Build code LSB +localparam CPLD_BUILD_MSB = GIT_HASH[31:16]; // Build code MSB +localparam PSADDR_SIGNATURE = 3'd0; +localparam PSADDR_REV_MINOR = 3'd1; // Minor version register +localparam PSADDR_REV_MAJOR = 3'd2; // Major version register +localparam PSADDR_BUILD_LSB = 3'd3; +localparam PSADDR_BUILD_MSB = 3'd4; +localparam PSADDR_SCRATCH = 3'd5; // scratchpad register +localparam PSADDR_GAIN_SEL = 3'd6; // band select for gain table loader +localparam PSADDR_DAC_ALARM = 3'd7; // DAC alarm pin register + +// Sub-device selection for PS SPI +localparam PS_CPLD_REGS = 2'b00; +localparam GAIN_TABLE_RX = 2'b01; +localparam GAIN_TABLE_TX = 2'b10; +localparam GAIN_TABLE_LO = 2'b11; + +// Setting to put TX SW1 in isolation mode +localparam [1:0] TX_SW1_TERM = 2'b11; + +wire clkdis_cs_b = CPLD_PS_SPI_LE_25; +wire cpld_ps_cs_b = CPLD_PS_ADDR0_25; +wire phdac_cs_b = CPLD_PS_ADDR1_25; +wire adc_cs_b = usrp_io[12]; +wire dac_cs_b = usrp_io[13]; + +// CPLD PS SPI format (left-most bit first): +// {table_sel[1:0], rsvd, reg_addr[3:0], rnw, data[15:0]} +wire [1:0] cpld_ps_table_sel; +wire [6:0] cpld_ps_spi_addr; +wire cpld_ps_spi_rnw; +reg [7:0] cpld_ps_spi_cmd; +reg [15:0] cpld_ps_spi_rdata; +reg [14:0] cpld_ps_spi_wdata; +reg cpld_ps_spi_sdo; +reg [4:0] cpld_ps_cnt; + +assign {cpld_ps_spi_addr, cpld_ps_spi_rnw} = cpld_ps_spi_cmd; + +// CPLD registers +reg [15:0] spad; +reg [15:0] gain_load_sel; + +// Double sync. the DAC ALARM pin (async). +reg dac_alarm_ms, dac_alarm = 0; +always @(posedge CPLD_PS_SPI_CLK_25) begin + {dac_alarm, dac_alarm_ms} <= {dac_alarm_ms, DAC_Alarm_18}; +end + +wire rx_gain_load_tbl_sel; +wire rx_gain_load_miso; +wire rx_gain_ctrl_tbl_sel; +wire rx_gain_ctrl_miso; +wire tx_gain_load_tbl_sel; +wire tx_gain_load_miso; +wire tx_gain_ctrl_tbl_sel; +wire tx_gain_ctrl_miso; +wire lo_gain_ctrl_miso; + +assign rx_gain_load_tbl_sel = gain_load_sel[0]; +assign tx_gain_load_tbl_sel = gain_load_sel[8]; + +always @(posedge CPLD_PS_SPI_CLK_25 or posedge cpld_ps_cs_b) +begin + if (cpld_ps_cs_b) begin + cpld_ps_cnt <= 5'd0; + end else if (!cpld_ps_cs_b) begin + if (cpld_ps_cnt < 8) begin // Address / command + cpld_ps_spi_cmd <= {cpld_ps_spi_cmd[6:0], CPLD_PS_SPI_SDI_25}; + cpld_ps_cnt <= cpld_ps_cnt + 5'd1; + end else if (cpld_ps_cnt < 23) begin // Shift in write data + cpld_ps_spi_wdata <= {cpld_ps_spi_wdata[13:0], CPLD_PS_SPI_SDI_25}; + cpld_ps_cnt <= cpld_ps_cnt + 5'd1; + end else if (!cpld_ps_spi_rnw && cpld_ps_cnt == 23 && cpld_ps_spi_addr[6:5] == PS_CPLD_REGS) begin // Write + case (cpld_ps_spi_addr[2:0]) + PSADDR_SIGNATURE: ; + PSADDR_REV_MINOR: ; + PSADDR_REV_MAJOR: ; + PSADDR_BUILD_LSB: ; + PSADDR_BUILD_MSB: ; + PSADDR_SCRATCH: spad <= {cpld_ps_spi_wdata, CPLD_PS_SPI_SDI_25}; + PSADDR_GAIN_SEL: gain_load_sel <= {cpld_ps_spi_wdata, CPLD_PS_SPI_SDI_25}; + endcase + end + if (cpld_ps_cnt == 7) begin // Set up read one cycle earlier + case (cpld_ps_spi_cmd[2:0]) + + PSADDR_SIGNATURE: cpld_ps_spi_rdata <= PROD_SIGNATURE; + PSADDR_REV_MINOR: cpld_ps_spi_rdata <= REVISION_MINOR; + PSADDR_REV_MAJOR: cpld_ps_spi_rdata <= REVISION_MAJOR; + PSADDR_BUILD_LSB: cpld_ps_spi_rdata <= CPLD_BUILD_LSB; + PSADDR_BUILD_MSB: cpld_ps_spi_rdata <= CPLD_BUILD_MSB; + PSADDR_SCRATCH: cpld_ps_spi_rdata <= spad; + PSADDR_GAIN_SEL: cpld_ps_spi_rdata <= gain_load_sel; + PSADDR_DAC_ALARM: cpld_ps_spi_rdata <= {15'b0, dac_alarm}; + endcase + end else begin + cpld_ps_spi_rdata <= {cpld_ps_spi_rdata[14:0], 1'b1}; + end + end +end + +always @(negedge CPLD_PS_SPI_CLK_25) +begin + cpld_ps_spi_sdo <= cpld_ps_spi_rdata[15]; // Shift out on negative edge +end + +// CLKDIST 3-wire to 4-wire +reg [4:0] clkdis_cnt; +reg clkdis_rd_pre, clkdis_rd, clkdis_sdio_t; + +always @(posedge CPLD_PS_SPI_CLK_25 or posedge clkdis_cs_b) +begin + if (clkdis_cs_b) begin + clkdis_cnt <= 5'd0; + clkdis_rd <= 1'b0; + clkdis_rd_pre <= 1'b0; + end else if (!clkdis_cs_b) begin + if (clkdis_cnt < 23) + clkdis_cnt <= clkdis_cnt + 5'd1; + + if (clkdis_cnt == 5'd0) // Check if read + clkdis_rd_pre <= CPLD_PS_SPI_SDI_25; + + if (clkdis_cnt == 5'd15) + clkdis_rd <= clkdis_rd_pre; + end +end + +always @(negedge CPLD_PS_SPI_CLK_25 or posedge clkdis_cs_b) +begin + if (clkdis_cs_b) begin + clkdis_sdio_t <= 1'b0; + end else begin + clkdis_sdio_t <= clkdis_rd; + end +end + +// ADC 3-wire to 4-wire +reg [4:0] adc_cnt; +reg adc_rd_pre, adc_rd, adc_sdio_t; + +always @(posedge CPLD_PS_SPI_CLK_25 or posedge adc_cs_b) +begin + if (adc_cs_b) begin + adc_cnt <= 5'd0; + adc_rd <= 1'b0; + adc_rd_pre <= 1'b0; + end else if (!adc_cs_b) begin + if (adc_cnt < 23) + adc_cnt <= adc_cnt + 5'd1; + + if (adc_cnt == 5'd0) // Check if read + adc_rd_pre <= CPLD_PS_SPI_SDI_25; + + if (adc_cnt == 5'd15) + adc_rd <= adc_rd_pre; + end +end + +always @(negedge CPLD_PS_SPI_CLK_25 or posedge adc_cs_b) +begin + if (adc_cs_b) begin + adc_sdio_t <= 1'b0; + end else begin + adc_sdio_t <= adc_rd; + end +end + +// DAC 3-wire to 4-wire +reg [4:0] dac_cnt; +reg dac_rd_pre, dac_rd, dac_sdio_t; + +always @(posedge CPLD_PS_SPI_CLK_25 or posedge dac_cs_b) +begin + if (dac_cs_b) begin + dac_cnt <= 5'd0; + dac_rd <= 1'b0; + dac_rd_pre <= 1'b0; + end else if (!dac_cs_b) begin + if (dac_cnt < 23) + dac_cnt <= dac_cnt + 5'd1; + + if (dac_cnt == 5'd0) // Check if read + dac_rd_pre <= CPLD_PS_SPI_SDI_25; + + if (dac_cnt == 5'd7) + dac_rd <= dac_rd_pre; + end +end + +always @(negedge CPLD_PS_SPI_CLK_25 or posedge dac_cs_b) +begin + if (dac_cs_b) begin + dac_sdio_t <= 1'b0; + end else begin + dac_sdio_t <= dac_rd; + end +end + +// multiplexed slave device SPI ports +wire phdac_sck, phdac_sdi; +wire clkdis_sck, adc_sck, dac_sck; +assign clkdis_sck = (clkdis_cs_b == 1'b0) ? CPLD_PS_SPI_CLK_25 : 1'b0; + +assign CLKDIST_SPI_CS_L = clkdis_cs_b; +assign CLKDIST_SPI_SCLK = clkdis_sck; + +assign adc_sck = !adc_cs_b ? CPLD_PS_SPI_CLK_25 : 1'b0; +assign dac_sck = !dac_cs_b ? CPLD_PS_SPI_CLK_25 : 1'b0; + +assign ADC_SPI_CS_L_18 = adc_cs_b; +assign ADC_SPI_SCLK_18 = adc_sck; + +assign DAC_SPI_CS_L_18 = dac_cs_b; +assign DAC_SPI_SCLK_18 = dac_sck; + +assign CLKDIST_SPI_SDIO = (!clkdis_sdio_t && !clkdis_cs_b) ? CPLD_PS_SPI_SDI_25 : 1'bz ; +assign ADC_SPI_SDIO_18 = (!adc_sdio_t && !adc_cs_b) ? CPLD_PS_SPI_SDI_25 : 1'bz ; +assign DAC_SPI_SDIO_18 = (!dac_sdio_t && !dac_cs_b) ? CPLD_PS_SPI_SDI_25 : 1'bz ; + +always @(*) +begin + CPLD_PS_SPI_SDO_25 = 1'b1; + case ({cpld_ps_cs_b, clkdis_cs_b, adc_cs_b, dac_cs_b}) + 4'b0111: begin + case (cpld_ps_spi_addr[6:5]) + PS_CPLD_REGS : CPLD_PS_SPI_SDO_25 = cpld_ps_spi_sdo; + GAIN_TABLE_RX: CPLD_PS_SPI_SDO_25 = rx_gain_load_miso; + GAIN_TABLE_TX: CPLD_PS_SPI_SDO_25 = tx_gain_load_miso; + GAIN_TABLE_LO: CPLD_PS_SPI_SDO_25 = 1'b1; + endcase + end + 4'b1011: CPLD_PS_SPI_SDO_25 = CLKDIST_SPI_SDIO; + 4'b1101: CPLD_PS_SPI_SDO_25 = ADC_SPI_SDIO_18; + 4'b1110: CPLD_PS_SPI_SDO_25 = DAC_SPI_SDIO_18; + default: ; + endcase +end + +// note: no readback from PHDAC +assign phdac_sck = (phdac_cs_b == 1'b0) ? CPLD_PS_SPI_CLK_25 : 1'b0; +assign phdac_sdi = (phdac_cs_b == 1'b0) ? CPLD_PS_SPI_SDI_25 : 1'b1; + + +assign PHDAC_SPI_SCLK = phdac_sck; +assign PHDAC_SPI_CS_L = phdac_cs_b; +assign PHDAC_SPI_SDI = phdac_sdi; + + +/* PL SPI */ +// CPLD PL SPI format (left-most bit first): +// {table_sel[1:0], reg_addr[4:0], rnw, data[15:0]} + +//TXLO, RXLO, LODIS, CPLD +localparam PLADDR_SCRATCH = 4'b0101; // scratchpad register +localparam PLADDR_RXBS = 4'b0110; +localparam PLADDR_TXBS = 4'b0111; +localparam PLADDR_RFCTRL = 4'b1000; +localparam PL_CPLD_REGS = 2'b00; + +// CPLD PL registers +reg [15:0] rxbs = 'h0; +reg [15:0] txbs = 'h0; +reg [15:0] rfctrl = 'h0; + +// register address on the falling edge of chip-select +wire txlo_cs_b = CPLD_PL_SPI_LE_18; +wire rxlo_cs_b = CPLD_PL_SPI_ADDR1_18; +wire lodis_cs_b = CPLD_PL_SPI_ADDR2_18; +wire cpld_pl_cs_b = CPLD_PL_SPI_ADDR0_18; + +wire cpld_pl_spi_rnw; +wire [6:0] cpld_pl_spi_addr; +reg [7:0] cpld_pl_spi_cmd; +reg [15:0] cpld_pl_spi_rdata; +reg [14:0] cpld_pl_spi_wdata; +reg cpld_pl_spi_sdo; +reg [4:0] cpld_pl_cnt; + +assign {cpld_pl_spi_addr, cpld_pl_spi_rnw} = cpld_pl_spi_cmd; + +reg [15:0] pl_spad; + +always @(posedge CPLD_PL_SPI_SCLK_18 or posedge cpld_pl_cs_b) +begin + if (cpld_pl_cs_b) begin + cpld_pl_cnt <= 5'd0; + end else if (!cpld_pl_cs_b) begin + if (cpld_pl_cnt < 8) begin // Address / command + cpld_pl_spi_cmd <= {cpld_pl_spi_cmd[6:0], CPLD_PL_SPI_SDI_18}; + cpld_pl_cnt <= cpld_pl_cnt + 5'd1; + end else if (cpld_pl_cnt < 23) begin // Shift in write data + cpld_pl_spi_wdata <= {cpld_pl_spi_wdata[13:0], CPLD_PL_SPI_SDI_18}; + cpld_pl_cnt <= cpld_pl_cnt + 5'd1; + end else if (!cpld_pl_spi_rnw && cpld_pl_cnt == 23 && cpld_pl_spi_addr[6:5] == PL_CPLD_REGS) begin // Write + case (cpld_pl_spi_addr[3:0]) + PLADDR_SCRATCH: pl_spad <= {cpld_pl_spi_wdata, CPLD_PL_SPI_SDI_18}; + PLADDR_RXBS: rxbs <= {cpld_pl_spi_wdata, CPLD_PL_SPI_SDI_18}; + PLADDR_TXBS: txbs <= {cpld_pl_spi_wdata, CPLD_PL_SPI_SDI_18}; + PLADDR_RFCTRL: rfctrl <= {cpld_pl_spi_wdata, CPLD_PL_SPI_SDI_18}; + endcase + end + if (cpld_pl_cnt == 7) begin // Set up read one cycle earlier + case (cpld_pl_spi_cmd[3:0]) + PLADDR_SCRATCH: cpld_pl_spi_rdata <= pl_spad; + PLADDR_RXBS: cpld_pl_spi_rdata <= rxbs; + PLADDR_TXBS: cpld_pl_spi_rdata <= txbs; + PLADDR_RFCTRL: cpld_pl_spi_rdata <= rfctrl; + endcase + end else begin + cpld_pl_spi_rdata <= {cpld_pl_spi_rdata[14:0], 1'b1}; + end + end +end + +always @(negedge CPLD_PL_SPI_SCLK_18) +begin + cpld_pl_spi_sdo <= cpld_pl_spi_rdata[15]; // Shift out on negative edge +end + +// multiplexed slave device SPI ports, names aliased to protect the innocent +wire lo_sck, lodis_sck; +wire lo_sdi, lodis_sdi; +// Note: lo_sck and lo_sdi -> fan out to both rxlo and txlo synths + +assign { LO_TX_CS_L, LO_RX_CS_L } = { txlo_cs_b, rxlo_cs_b}; +assign LO_SPI_SCLK = lo_sck; +assign LO_SPI_SDI = lo_sdi; + + +assign LODIST_Bd_SPI_CS_L = lodis_cs_b; +assign LODIST_Bd_SPI_SDI = lodis_sdi; +assign LODIST_Bd_SPI_SCLK = lodis_sck; + + +assign lodis_sck = !lodis_cs_b ? CPLD_PL_SPI_SCLK_18 : 1'b0; +assign lodis_sdi = !lodis_cs_b ? CPLD_PL_SPI_SDI_18 : 1'b1; + +assign { lo_sck, lo_sdi } = (!txlo_cs_b | !rxlo_cs_b) ? {CPLD_PL_SPI_SCLK_18,CPLD_PL_SPI_SDI_18} : 2'b01; + + +always @(*) +begin + CPLD_PL_SPI_SDO_18 = 1'bz; + case ({cpld_pl_cs_b, txlo_cs_b, rxlo_cs_b}) + 3'b110: CPLD_PL_SPI_SDO_18 = LOSYNTH_RX_MUXOUT; + 3'b101: CPLD_PL_SPI_SDO_18 = LOSYNTH_TX_MUXOUT; + 3'b011: begin + case (cpld_pl_spi_addr[6:5]) + PL_CPLD_REGS : CPLD_PL_SPI_SDO_18 = cpld_pl_spi_sdo; + GAIN_TABLE_RX: CPLD_PL_SPI_SDO_18 = rx_gain_ctrl_miso; + GAIN_TABLE_TX: CPLD_PL_SPI_SDO_18 = tx_gain_ctrl_miso; + GAIN_TABLE_LO: CPLD_PL_SPI_SDO_18 = lo_gain_ctrl_miso; + endcase + end + default: ; + endcase +end + +assign rx_gain_ctrl_tbl_sel = rxbs[12]; +assign { Rx_Sw6_Ctrl_2, + Rx_Sw6_Ctrl_1, + Rx_Sw4_Ctrl_4, + Rx_Sw4_Ctrl_3, + Rx_Sw4_Ctrl_2, + Rx_Sw4_Ctrl_1, + Rx_Sw3_Ctrl_2, + Rx_Sw3_Ctrl_1, + Rx_Sw2_Ctrl, + Rx_Sw1_Ctrl_2, + Rx_Sw1_Ctrl_1 } = { rxbs[11:1] }; + +assign tx_gain_ctrl_tbl_sel = txbs[12]; +assign { Tx_Sw5_Ctrl_2, + Tx_Sw5_Ctrl_1, + Tx_Sw3_Ctrl_4, + Tx_Sw3_Ctrl_3, + Tx_Sw3_Ctrl_2, + Tx_Sw3_Ctrl_1, + Tx_Sw2_Ctrl_2, + Tx_Sw2_Ctrl_1} = { txbs[11:4] }; + +// Terminate TX when idle +assign {Tx_Sw1_Ctrl_2, Tx_Sw1_Ctrl_1} = CPLD_ATR_TX_18 ? txbs[3:2] : TX_SW1_TERM; + +assign { Rx_LO_Filter_Sw_2, + Rx_LO_Filter_Sw_1, + Tx_LO_Filter_Sw_2, + Tx_LO_Filter_Sw_1, + Rx_Demod_ADJ_1, + Rx_Demod_ADJ_2, + Rx_LO_Input_Select } = rfctrl[15:9]; + +assign { Rx_HB_LB_Select, + Tx_LO_Input_Select } = rfctrl[7:6]; + +assign { Tx_HB_LB_Select, + Cal_iso_Sw_Ctrl } + = { rfctrl[4:3] }; + + +// RX Gain Table +wire [4:0] rx_dsa; + +rhodium_gain_ctrl #( + .TABLE_NUM(GAIN_TABLE_RX) +) rx_gain_table ( + .load_table_sel(rx_gain_load_tbl_sel), + .load_sck(CPLD_PS_SPI_CLK_25), + .load_csb(cpld_ps_cs_b), + .load_mosi(CPLD_PS_SPI_SDI_25), + .load_miso(rx_gain_load_miso), + .ctrl_table_sel(rx_gain_ctrl_tbl_sel), + .ctrl_sck(CPLD_PL_SPI_SCLK_18), + .ctrl_csb(cpld_pl_cs_b), + .ctrl_mosi(CPLD_PL_SPI_SDI_18), + .ctrl_miso(rx_gain_ctrl_miso), + .dsa(rx_dsa), + .dsa1_le(Rx_DSA1_LE), + .dsa2_le(Rx_DSA2_LE) +); + +// TX Gain Table +wire [4:0] tx_dsa; + +rhodium_gain_ctrl #( + .TABLE_NUM(GAIN_TABLE_TX) +) tx_gain_table ( + .load_table_sel(tx_gain_load_tbl_sel), + .load_sck(CPLD_PS_SPI_CLK_25), + .load_csb(cpld_ps_cs_b), + .load_mosi(CPLD_PS_SPI_SDI_25), + .load_miso(tx_gain_load_miso), + .ctrl_table_sel(tx_gain_ctrl_tbl_sel), + .ctrl_sck(CPLD_PL_SPI_SCLK_18), + .ctrl_csb(cpld_pl_cs_b), + .ctrl_mosi(CPLD_PL_SPI_SDI_18), + .ctrl_miso(tx_gain_ctrl_miso), + .dsa(tx_dsa), + .dsa1_le(Tx_DSA1_LE), + .dsa2_le(Tx_DSA2_LE) +); + +// LO Gain Table +wire [4:0] lo_dsa; + +rhodium_lo_gain #( + .TABLE_NUM(GAIN_TABLE_LO) +) lo_gain_table ( + .ctrl_sck(CPLD_PL_SPI_SCLK_18), + .ctrl_csb(cpld_pl_cs_b), + .ctrl_mosi(CPLD_PL_SPI_SDI_18), + .ctrl_miso(lo_gain_ctrl_miso), + .dsa(lo_dsa), + .dsa1_le(RxLO_DSA_LE), + .dsa2_le(TxLO_DSA_LE) +); + +// Rx data shared by DSA1, DSA2 +assign { Rx_DSA_C16, Rx_DSA_C8, Rx_DSA_C4, Rx_DSA_C2, Rx_DSA_C1 } = rx_dsa; + +// Tx data shared by DSA1, DSA2 +assign { Tx_DSA_C16, Tx_DSA_C8, Tx_DSA_C4, Tx_DSA_C2, Tx_DSA_C1 } = tx_dsa; + +// data shared by both tx and rx lo DSAs +assign { LO_DSA_C16, LO_DSA_C8, LO_DSA_C4, LO_DSA_C2, LO_DSA_C1 } = lo_dsa; + +endmodule +`default_nettype wire + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_clocks.xdc b/fpga/usrp3/top/n3xx/dboards/rh/db_clocks.xdc new file mode 100644 index 000000000..e78342849 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_clocks.xdc @@ -0,0 +1,118 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Timing analysis is performed in "usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx". +# See this spreadsheet for more details and explanations. + +#******************************************************************************* +## Daughterboard Clocks +# +# 122.88, 200, 245.76 and 250 MHz Sample Rates are allowable with 2:1/1:2 DSP and +# 2 samples/cycle arriving at the FPGA: +# +# <-- 2:1/1:2 --> +# | Supported | Sample rate | FPGA Clk | +# |sample rates | at JESD core | Frequency | +# | (MSPS) | (MSPS) | (MHz) | +# |-------------|--------------|-----------| +# | 122.88 | 491.52 | 245.76 | (uses DUC/DDC) +# | 200.00 | 400.00 | 200.00 | +# | 245.76 | 491.52 | 245.76 | +# | 250.00 | 500.00 | 250.00 | +# +# Therefore, supported sample clocks are: 122.88, 200, 245.76 and 250 MHz. +# Constrain the paths to the max rate to support all rates in a single FPGA image. +set SAMPLE_CLK_PERIOD 4.00 +create_clock -name fpga_clk_a -period $SAMPLE_CLK_PERIOD [get_ports DBA_FPGA_CLK_P] +create_clock -name fpga_clk_b -period $SAMPLE_CLK_PERIOD [get_ports DBB_FPGA_CLK_P] +create_clock -name mgt_clk_dba -period $SAMPLE_CLK_PERIOD [get_ports DBA_MGTCLK_P] +create_clock -name mgt_clk_dbb -period $SAMPLE_CLK_PERIOD [get_ports DBB_MGTCLK_P] + +# The Radio Clocks coming from the DBs are synchronized together (at the converters) to +# a typical value of less than 100ps. To give ourselves and Vivado some margin, we claim +# here that the DB-B Radio Clock can arrive 500ps before or after the DB-A clock at +# the FPGA (note that the trace lengths of the Radio Clocks coming from the DBs to the +# FPGA are about 0.5" different, thereby incurring ~80ps of additional skew at the FPGA). +# There is one spot in the FPGA where we cross domains between the DB-A and +# DB-B clock, so we must ensure that Vivado can analyze that path safely. +set FPGA_CLK_EARLY -0.5 +set FPGA_CLK_LATE 0.5 +set_clock_latency -source -early $FPGA_CLK_EARLY [get_clocks fpga_clk_b] +set_clock_latency -source -late $FPGA_CLK_LATE [get_clocks fpga_clk_b] + +# Virtual clocks for constraining I/O (used below) +create_clock -name fpga_clk_a_v -period $SAMPLE_CLK_PERIOD +create_clock -name fpga_clk_b_v -period $SAMPLE_CLK_PERIOD + +# The set_clock_latency constraints set on fpga_clk_b are problematic when used with +# I/O timing, since the analyzer gives us a double-hit on the latency. One workaround +# (used here) is to simply swap the early and late times for the virtual clock so that +# it cancels out the source latency during analysis. D. Jepson tested this by setting +# the early and late numbers to zero and then their actual value, running timing reports +# on each. The slack report matches for both cases, showing that the reversed early/late +# numbers on the virtual clock zero out the latency effects on the actual clock. +# +# Note this is not a problem for the fpga_clk_a, since no latency is added. So only apply +# it to fpga_clk_b_v. +set_clock_latency -source -early $FPGA_CLK_LATE [get_clocks fpga_clk_b_v] +set_clock_latency -source -late $FPGA_CLK_EARLY [get_clocks fpga_clk_b_v] + + + +#******************************************************************************* +## Aliases for auto-generated clocks + +create_generated_clock -name radio_clk_fb [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}] +create_generated_clock -name radio_clk [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT0}] +create_generated_clock -name radio_clk_2x [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT1}] + +create_generated_clock -name radio_clk_b_fb [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}] +create_generated_clock -name radio_clk_b [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT0}] +create_generated_clock -name radio_clk_b_2x [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT1}] + + + +#******************************************************************************* +## Generated clocks for output busses to the daughterboard +# +# These clock definitions need to come above the set_clock_groups commands below to work! + +# Define clocks on the PL SPI clock output pins for both DBs. Actual divider values are +# set by SW at run-time. Current divider value is 125 based on what radio clock +# rate is set. +# For the CPLD SPI endpoint alone, we need it to run at ~25 MHz (writes only), this means +# that at times, the PL SPI will have its divider set to 10 (radio_clock = 250 MHz) or 8 +# (radio_clock = 200 MHz). +# The readback clock is lower (~10 MHz), so create a separate clock for it. +# Use readback divide value of 24 for an even divider (and some overconstraining). +set PL_SPI_DIVIDE_VAL 10 +set PL_SPI_RB_DIVIDE_VAL 24 +set PL_SPI_CLK_A [get_ports DBA_CPLD_PL_SPI_SCLK] +create_generated_clock -name pl_spi_clk_a \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_A]/C] \ + -divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_A +create_generated_clock -name pl_spi_rb_clk_a \ + -master_clock [get_clocks radio_clk] \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_A]/C] \ + -divide_by $PL_SPI_RB_DIVIDE_VAL -add $PL_SPI_CLK_A +set PL_SPI_CLK_B [get_ports DBB_CPLD_PL_SPI_SCLK] +create_generated_clock -name pl_spi_clk_b \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_B]/C] \ + -divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_B +create_generated_clock -name pl_spi_rb_clk_b \ + -master_clock [get_clocks radio_clk] \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_B]/C] \ + -divide_by $PL_SPI_RB_DIVIDE_VAL -add $PL_SPI_CLK_B + +#******************************************************************************* +## JTAG +set DB_JTAG_DIVISOR 4 +create_generated_clock -name dba_jtag_tck -divide_by $DB_JTAG_DIVISOR \ + -source [get_pins {inst_n310_ps/jtag_0/U0/bitq_ctrl/bitq_state_reg[1]/C}] \ + [get_ports DBA_CPLD_JTAG_TCK] + +create_generated_clock -name dbb_jtag_tck -divide_by $DB_JTAG_DIVISOR \ + -source [get_pins {inst_n310_ps/jtag_1/U0/bitq_ctrl/bitq_state_reg[1]/C}] \ + [get_ports DBB_CPLD_JTAG_TCK] + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/ClockingRegs.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/ClockingRegs.vhd new file mode 100644 index 000000000..52c68ab4a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/ClockingRegs.vhd @@ -0,0 +1,345 @@ +------------------------------------------------------------------------------- +-- +-- File: ClockingRegs.vhd +-- Author: Daniel Jepson; mods by Humberto Jimenez +-- Original Project: N310; N32x +-- Date: 17 March 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Register access to the control/status bits and interfaces for the +-- RadioClocking module. +-- +-- XML register definition is included below the module. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library work; + use work.PkgClockingRegMap.all; + use work.PkgRegs.all; + + +entity ClockingRegs is + port( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + -- Register Bus Clock -- this module connects the BusClk to PsClk, so it's limited + -- to 200 MHz! + BusClk : in std_logic; + + bRegPortOut : out RegPortOut_t; + bRegPortIn : in RegPortIn_t; + + -- Phase shift interface to the RadioClkMmcm. + -- There is a reset crossing here between the MMCM reset and aReset. The outgoing + -- crossing is safe because (a) the enable signal driven to the MMCM is a strobe-only + -- signal and (b) this interface should only be used when the MMCM is not in reset + -- (SW waits for the MMCM to be out of reset and locked before using this interface). + -- The only input signal, pPsDone, is double-synced in this file before being used. + -- This is OK (even though it is a strobe signal) because there is only a reset + -- crossing and not a clock domain crossing. + pPsInc : out std_logic; + pPsEn : out std_logic; + pPsDone : in std_logic; + + -- PsClk is driven directly by BusClk, so p = b in the logic below! + PsClk : out std_logic; + + -- Sync reset strobes from the register bus to the RadioClkMmcm. + bRadioClkMmcmReset : out std_logic; + -- Status of RadioClk MMCM lock to register bus. + aRadioClksValid : in std_logic; + + bRadioClk1xEnabled : out std_logic; + bRadioClk2xEnabled : out std_logic; + bRadioClk3xEnabled : out std_logic; + + bJesdRefClkPresent : in std_logic + ); +end ClockingRegs; + + +architecture RTL of ClockingRegs is + + --vhook_sigstart + --vhook_sigend + + signal bRadioClkMmcmResetInt : std_logic := '1'; + + signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero; + + signal bPsDone, + bPsEn, + bPsInc, + pPsDoneDs_ms, + pPsDoneDs : std_logic := '0'; + + signal bRadioClk1xEnabledInt, + bRadioClk2xEnabledInt, + bRadioClk3xEnabledInt, + bRadioClksValid_ms, + bRadioClksValid : std_logic := '0'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of bRadioClksValid_ms : signal is "true"; + attribute ASYNC_REG of bRadioClksValid : signal is "true"; + attribute ASYNC_REG of pPsDoneDs_ms : signal is "true"; + attribute ASYNC_REG of pPsDoneDs : signal is "true"; + +begin + + -- Locals to outputs. + PsClk <= BusClk; + pPsInc <= bPsInc; + pPsEn <= bPsEn; + + bRadioClkMmcmReset <= bRadioClkMmcmResetInt; + + bRadioClk1xEnabled <= bRadioClk1xEnabledInt; + bRadioClk2xEnabled <= bRadioClk2xEnabledInt; + bRadioClk3xEnabled <= bRadioClk3xEnabledInt; + + + -- Write Registers : ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + WriteRegisters: process(aReset, BusClk) + begin + if aReset then + bRadioClkMmcmResetInt <= '1'; + bPsInc <= '0'; + bPsEn <= '0'; + bRadioClk1xEnabledInt <= '0'; + bRadioClk2xEnabledInt <= '0'; + bRadioClk3xEnabledInt <= '0'; + elsif rising_edge(BusClk) then + + if bReset then + bRadioClkMmcmResetInt <= '1'; + bPsInc <= '0'; + bPsEn <= '0'; + bRadioClk1xEnabledInt <= '0'; + bRadioClk2xEnabledInt <= '0'; + bRadioClk3xEnabledInt <= '0'; + else + -- Clear strobe + bPsEn <= '0'; + + if RegWrite(kPhaseShiftControl, bRegPortIn) then + if bRegPortIn.Data(kPsInc) = '1' then + bPsInc <= '1'; + bPsEn <= '1'; + elsif bRegPortIn.Data(kPsDec) = '1' then + bPsInc <= '0'; + bPsEn <= '1'; + end if; + end if; + + if RegWrite(kRadioClkMmcm, bRegPortIn) then + -- Set/Clear pair + if bRegPortIn.Data(kRadioClkMmcmResetSet) = '1' then + bRadioClkMmcmResetInt <= '1'; + elsif bRegPortIn.Data(kRadioClkMmcmResetClear) = '1' then + bRadioClkMmcmResetInt <= '0'; + end if; + end if; + + if RegWrite(kRadioClkEnables, bRegPortIn) then + bRadioClk1xEnabledInt <= bRegPortIn.Data(kRadioClk1xEnabled); + bRadioClk2xEnabledInt <= bRegPortIn.Data(kRadioClk2xEnabled); + bRadioClk3xEnabledInt <= bRegPortIn.Data(kRadioClk3xEnabled); + end if; + + end if; + end if; + end process WriteRegisters; + + + DoubleSyncs : process (aReset, BusClk) + begin + if aReset then + bRadioClksValid_ms <= '0'; + bRadioClksValid <= '0'; + pPsDoneDs_ms <= '0'; + pPsDoneDs <= '0'; + elsif rising_edge(BusClk) then + -- No sync reset on double-syncs (however there are default assignments above)! + bRadioClksValid_ms <= aRadioClksValid; + bRadioClksValid <= bRadioClksValid_ms; + pPsDoneDs_ms <= pPsDone; + pPsDoneDs <= pPsDoneDs_ms; + end if; + end process; + + + -- Read Registers : ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + ReadRegisters: process(aReset, BusClk) + begin + if aReset then + bRegPortOutLcl <= kRegPortOutZero; + bPsDone <= '0'; + elsif rising_edge(BusClk) then + + if bReset then + bRegPortOutLcl <= kRegPortOutZero; + bPsDone <= '0'; + else + -- Deassert strobes + bRegPortOutLcl.Data <= kRegPortDataZero; + + -- All of these transactions only take one clock cycle, so we do not have to + -- de-assert the Ready signal (ever). + bRegPortOutLcl.Ready <= true; + + -- Process the returned data from the phase shifter in the MMCM. Note that even + -- though the prefixes are different (p and b), we drive the PsClk from the BusClk + -- so this "crossing" is actually safe. Whenever the Done signal asserts (pPsDone - + -- pay attention to the prefix!) from the MMCM, we set a sticky bit to tell SW + -- that the shift operation is complete. + -- + -- However, if pPsDone asserts at the same time that SW tries to read the register, + -- we should accurately report that the operation is indeed complete and then NOT + -- store the sticky (since it has already been read by SW). If a read does not come + -- through at the same time pPsDone is asserted, then we store the done state as a + -- sticky, bPsDone, which is only cleared by a read to this register. + if RegRead(kPhaseShiftControl, bRegPortIn) then + -- The phase shift is always enabled for the feedback clock in RadioClocking.vhd + bRegPortOutLcl.Data(kPsEnabledForFdbClk) <= '1'; + bRegPortOutLcl.Data(kPsDone) <= bPsDone or pPsDoneDs; + bPsDone <= '0'; + elsif pPsDoneDs = '1' then + bPsDone <= '1'; + end if; + + if RegRead(kRadioClkMmcm, bRegPortIn) then + bRegPortOutLcl.Data(kRadioClkMmcmLocked) <= bRadioClksValid; + end if; + + if RegRead(kRadioClkEnables, bRegPortIn) then + bRegPortOutLcl.Data(kRadioClk1xEnabled) <= bRadioClk1xEnabledInt; + bRegPortOutLcl.Data(kRadioClk2xEnabled) <= bRadioClk2xEnabledInt; + bRegPortOutLcl.Data(kRadioClk3xEnabled) <= bRadioClk3xEnabledInt; + end if; + + if RegRead(kMgtRefClkStatus, bRegPortIn) then + bRegPortOutLcl.Data(kJesdRefClkPresent) <= bJesdRefClkPresent; + end if; + + end if; + end if; + end process ReadRegisters; + + -- Local to output + bRegPortOut <= bRegPortOutLcl; + + +end RTL; + + +--XmlParse xml_on +-- +-- +-- +-- +-- +-- +-- +-- +-- Reflects the locked status of the MMCM. '1' = locked. This bit is only valid +-- when the MMCM reset is de-asserted. Read-only. +-- +-- +-- +-- +-- Controls the reset to the Radio Clock MMCM. Strobe this bit to de-assert the +-- reset to the MMCM. Default is reset asserted. Write-only. +-- +-- +-- +-- +-- Controls the reset to the Radio Clock MMCM. Strobe this bit to assert the +-- reset to the MMCM. Default is reset asserted. Write-only. +-- +-- +-- +-- +-- +-- +-- Phase Shift for RadioClkMmcm. +-- +-- +-- +-- This bit should set after a shift operation successfully completes. +-- Reading this register will clear this bit. Read-only. +-- +-- +-- +-- +-- Strobe this bit to increment the phase. This bit is self-clearing and will +-- always return '0' when read. If PsInc and PsDec are asserted together, +-- the phase will increment. +-- +-- +-- +-- +-- Strobe this bit to decrement the phase. This bit is self-clearing and will +-- always return '0' when read. If PsInc and PsDec are asserted together, +-- the phase will increment. +-- +-- +-- +-- +-- Read-only. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- +-- +-- +-- +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- +-- +-- +-- +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Live indicator of the MGT Reference Clock toggling and within expected +-- frequency limits. If this bit is de-asserted, then the JESD204b core will +-- not function correctly! +-- +-- +-- +-- +-- +-- +-- +--XmlParse xml_off diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DaughterboardRegs.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DaughterboardRegs.vhd new file mode 100644 index 000000000..8a9c20372 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DaughterboardRegs.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------- +-- +-- File: DaughterboardRegs.vhd +-- Author: Daniel Jepson; mods by Humberto Jimenez +-- Original Project: N310; N32x +-- Date: 27 April 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Register interface to the semi-static control lines for the Mg +-- Daughterboard. +-- +-- XML register definition is included below the module. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library work; + use work.PkgDaughterboardRegMap.all; + use work.PkgRegs.all; + + +entity DaughterboardRegs is + port( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + BusClk : in std_logic; + + bRegPortOut : out RegPortOut_t; + bRegPortIn : in RegPortIn_t; + + -- Slot and DB ID values. These should be tied to constants! + kDbId : in std_logic_vector(15 downto 0); + kSlotId : in std_logic + + ); +end DaughterboardRegs; + + +architecture RTL of DaughterboardRegs is + + --vhook_sigstart + --vhook_sigend + + signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero; + +begin + + + -- Read Registers : ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + ReadRegisters: process(aReset, BusClk) + begin + if aReset then + bRegPortOutLcl <= kRegPortOutZero; + elsif rising_edge(BusClk) then + if bReset then + bRegPortOutLcl <= kRegPortOutZero; + else + -- De-assert strobes + bRegPortOutLcl.Data <= kRegPortDataZero; + + -- All of these transactions only take one clock cycle, so we do not have to + -- de-assert the Ready signal (ever). + bRegPortOutLcl.Ready <= true; + + if RegRead(kDaughterboardId, bRegPortIn) then + bRegPortOutLcl.Data(kDbIdValMsb downto kDbIdVal) <= kDbId; + bRegPortOutLcl.Data(kSlotIdVal) <= kSlotId; + end if; + + end if; + end if; + end process ReadRegisters; + + -- Local to output + bRegPortOut <= bRegPortOutLcl; + + +end RTL; + + +--XmlParse xml_on +-- +-- +-- +-- +-- +-- +-- +-- +-- ID for the DB with which this file is designed to communicate. Matches the DB +-- EEPROM ID. +-- +-- +-- +-- +-- ID for the Slot this module controls. Options are 0 and 1 for the N310 MB. +-- +-- +-- +-- +-- +-- +-- +-- +--XmlParse xml_off diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DbCore.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DbCore.vhd new file mode 100644 index 000000000..f54a976d1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DbCore.vhd @@ -0,0 +1,563 @@ +------------------------------------------------------------------------------- +-- +-- File: DbCore.vhd +-- Author: Daniel Jepson; mods by Humberto Jimenez +-- Original Project: N310; N320 +-- Date: 12 April 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2017-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Wrapper file for Daughterboard Control. This includes the semi-static control +-- and status registers, clocking, synchronization, and JESD204B cores. +-- +-- There is no version register for the plain-text files here. +-- Version control for the Sync and JESD204B cores is internal to the netlists. +-- +-- The resets for this core are almost entirely local and/or synchronous. +-- bBusReset is a Synchronous reset on the BusClk domain that resets all of the +-- registers connected to the RegPort, as well as any other stray registers +-- connected to the BusClk. All other resets are local to the modules they touch. +-- No other reset drives all modules universally. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRhPersonality.all; + use work.PkgRegs.all; + use work.PkgJesdConfig.all; + use work.PkgAdcDacInterfaceTypes.all; + + +entity DbCore is + generic( + -- Set to '1' to include the White Rabbit TDC. + kInclWhiteRabbitTdc : std_logic := '0' + ); + port( + + -- Resets -- + -- Synchronous Reset for the BusClk domain (mainly for the RegPort) + bBusReset : in std_logic; + + -- Clocks -- + -- Register Bus Clock (any frequency) + BusClk : in std_logic; + -- Always-on at 40 MHz + Clk40 : in std_logic; + -- Super secret crazy awesome measurement clock at weird frequencies. + MeasClk : in std_logic; + -- FPGA Sample Clock from DB LMK + FpgaClk_p : in std_logic; + FpgaClk_n : in std_logic; + + -- Sample Clock Sharing. The clocks generated in this module are exported out to the + -- top level so they can be shared amongst daughterboards. Therefore they must be + -- driven back into the SampleClk*x inputs at a higher level in order for this module + -- to work correctly. There are a few isolated cases where SampleClk*xOut is used + -- directly in this module, and those are documented below. + SampleClk1xOut : out std_logic; + SampleClk1x : in std_logic; + SampleClk2xOut : out std_logic; + SampleClk2x : in std_logic; + + + -- Register Ports -- + -- + -- Only synchronous resets can be used for these ports! + bRegPortInFlat : in std_logic_vector(49 downto 0); + bRegPortOutFlat : out std_logic_vector(33 downto 0); + + -- Slot ID value. This should be tied to a constant! + kSlotId : in std_logic; + + + -- SYSREF -- + -- + -- SYSREF direct from the LMK + sSysRefFpgaLvds_p, + sSysRefFpgaLvds_n : in std_logic; + -- SYNC directly to the LMK + aLmkSync : out std_logic; + + + -- JESD Signals -- + -- + -- GTX Sample Clock Reference Input. Direct connect to FPGA pins. + JesdRefClk_p, + JesdRefClk_n : in std_logic; + + -- ADC JESD PHY Interface. Direct connect to FPGA pins. + aAdcRx_p, + aAdcRx_n : in std_logic_vector(3 downto 0); + aSyncAdcOut_n : out std_logic; + + -- DAC JESD PHY Interface. Direct connect to FPGA pins. + aDacTx_p, + aDacTx_n : out std_logic_vector(3 downto 0); + aSyncDacIn_n : in std_logic; + + + -- Data Pipes to/from the DACs/ADCs -- + -- + -- - Data is presented as two samples per cycle. + -- - sAdcDataValid asserts when ADC data is valid. + -- - sDacReadyForInput asserts when DAC data is ready to be received. + -- + -- Reset Crossings: + -- The ADC data and valid outputs are synchronously cleared before the asynchronous + -- reset is asserted--preventing any reset crossing issues here between the RX + -- (internal to the core) reset and the no-reset domain of RFNoC. + -- + -- The DAC samples should be zeros on reset de-assertion due to RFI being de-asserted + -- in reset. If they are not zeros, then it is still OK because data is ignored until + -- RFI is asserted. DAC RFI is double-synchronized to protect against the reset + -- crossing. This is safe to do because it simply delays the output of RFI by two + -- cycles on the assertion edge, and as long as reset is held for more than two + -- cycles, the de-assertion edge of RFI should come long before the TX module is + -- taken out of reset. + + -- Supporting 2 samples per clk cycle. + sAdcDataValid : out std_logic; + sAdcDataSample0I : out std_logic_vector(15 downto 0); + sAdcDataSample0Q : out std_logic_vector(15 downto 0); + sAdcDataSample1I : out std_logic_vector(15 downto 0); + sAdcDataSample1Q : out std_logic_vector(15 downto 0); + -- + sDacReadyForInput : out std_logic; + sDacDataSample0I : in std_logic_vector(15 downto 0); + sDacDataSample0Q : in std_logic_vector(15 downto 0); + sDacDataSample1I : in std_logic_vector(15 downto 0); + sDacDataSample1Q : in std_logic_vector(15 downto 0); + + + -- RefClk & Timing & Sync -- + RefClk : in std_logic; + rPpsPulse : in std_logic; + rGatedPulseToPin : inout std_logic; -- straight to pin + sGatedPulseToPin : inout std_logic; -- straight to pin + sPps : out std_logic; + sPpsToIob : out std_logic; + + -- White Rabbit Timing & Sync -- + WrRefClk : in std_logic; + rWrPpsPulse : in std_logic; + rWrGatedPulseToPin : inout std_logic; -- straight to pin + sWrGatedPulseToPin : inout std_logic; -- straight to pin + aPpsSfpSel : in std_logic_vector(1 downto 0); + + -- Debug for JESD + sAdcSync : out std_logic; + sDacSync : out std_logic; + sSysRef : out std_logic; + + -- Debug for Timing & Sync + rRpTransfer : out std_logic; + sSpTransfer : out std_logic; + rWrRpTransfer : out std_logic; + sWrSpTransfer : out std_logic + ); + +end DbCore; + + +architecture RTL of DbCore is + + component Jesd204bXcvrCore + port ( + bBusReset : in STD_LOGIC; + BusClk : in STD_LOGIC; + ReliableClk40 : in STD_LOGIC; + FpgaClk1x : in STD_LOGIC; + FpgaClk2x : in STD_LOGIC; + bFpgaClksStable : in STD_LOGIC; + JesdRefClk_p : in STD_LOGIC; + JesdRefClk_n : in STD_LOGIC; + bJesdRefClkPresent : out STD_LOGIC; + aLmkSync : out STD_LOGIC; + bRegPortInFlat : in STD_LOGIC_VECTOR(49 downto 0); + bRegPortOutFlat : out STD_LOGIC_VECTOR(33 downto 0); + CaptureSysRefClk : in STD_LOGIC; + cSysRefFpgaLvds_p : in STD_LOGIC; + cSysRefFpgaLvds_n : in STD_LOGIC; + fSysRef : out STD_LOGIC; + aAdcRx_p : in STD_LOGIC_VECTOR(3 downto 0); + aAdcRx_n : in STD_LOGIC_VECTOR(3 downto 0); + aSyncAdcOut_n : out STD_LOGIC; + aDacTx_p : out STD_LOGIC_VECTOR(3 downto 0); + aDacTx_n : out STD_LOGIC_VECTOR(3 downto 0); + aSyncDacIn_n : in STD_LOGIC; + fAdcDataFlatter : out STD_LOGIC_VECTOR(63 downto 0); + fDacDataFlatter : in STD_LOGIC_VECTOR(63 downto 0); + fAdcDataValid : out STD_LOGIC; + fDacReadyForInput : out STD_LOGIC; + aDacSync : out STD_LOGIC; + aAdcSync : out STD_LOGIC); + end component; + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + --vhook_sigstart + signal aAdcSync: STD_LOGIC; + signal aDacSync: STD_LOGIC; + signal bClockingRegPortOut: RegPortOut_t; + signal bDbRegPortOut: RegPortOut_t; + signal bFpgaClksStable: STD_LOGIC; + signal bJesdCoreRegPortInFlat: STD_LOGIC_VECTOR(49 downto 0); + signal bJesdCoreRegPortOutFlat: STD_LOGIC_VECTOR(33 downto 0); + signal bJesdRefClkPresent: STD_LOGIC; + signal bRadioClk1xEnabled: std_logic; + signal bRadioClk2xEnabled: std_logic; + signal bRadioClk3xEnabled: std_logic; + signal bRadioClkMmcmReset: std_logic; + signal bRadioClksValid: std_logic; + signal pPsDone: std_logic; + signal pPsEn: std_logic; + signal pPsInc: std_logic; + signal PsClk: std_logic; + signal sAdcDataFlatter: STD_LOGIC_VECTOR(63 downto 0); + signal SampleClk1xOutLcl: std_logic; + signal sDacDataFlatter: STD_LOGIC_VECTOR(63 downto 0); + signal sDacReadyForInputAsyncReset: STD_LOGIC; + signal sRegPps: std_logic; + signal sSysRefAsyncReset: STD_LOGIC; + signal sWrPps: std_logic; + --vhook_sigend + + signal bJesdRegPortInGrp, bSyncRegPortIn, bWrSyncRegPortIn, bRegPortIn : RegPortIn_t; + signal bJesdRegPortOut, bSyncRegPortOut, bWrSyncRegPortOut, bRegPortOut : RegPortOut_t; + + signal sDacReadyForInput_ms, sDacReadyForInputLcl, + sDacSync_ms, sDacSyncLcl, + sAdcSync_ms, sAdcSyncLcl, + sSysRef_ms, sSysRefLcl : std_logic := '0'; + + signal sAdcDataAry : AdcDataAry_t; + signal sDacDataAry : DacDataAry_t; + + signal sPpsSfpSel_ms, sPpsSfpSel : std_logic_vector(1 downto 0) := (others => '0'); + signal sUseWrTdcPps : boolean := false; + signal sPpsInt, sPpsMuxed : std_logic := '0'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of sDacReadyForInput_ms : signal is "true"; + attribute ASYNC_REG of sDacReadyForInputLcl : signal is "true"; + attribute ASYNC_REG of sDacSync_ms : signal is "true"; + attribute ASYNC_REG of sDacSyncLcl : signal is "true"; + attribute ASYNC_REG of sAdcSync_ms : signal is "true"; + attribute ASYNC_REG of sAdcSyncLcl : signal is "true"; + attribute ASYNC_REG of sSysRef_ms : signal is "true"; + attribute ASYNC_REG of sSysRefLcl : signal is "true"; + attribute ASYNC_REG of sPpsSfpSel_ms : signal is "true"; + attribute ASYNC_REG of sPpsSfpSel : signal is "true"; + +begin + + bRegPortOutFlat <= Flatten(bRegPortOut); + bRegPortIn <= Unflatten(bRegPortInFlat); + + + -- Combine return RegPorts. + bRegPortOut <= bJesdRegPortOut + + bClockingRegPortOut + + bSyncRegPortOut + bWrSyncRegPortOut + + bDbRegPortOut; + + + -- Clocking : ------------------------------------------------------------------------- + -- Automatically export the Sample Clocks and only use the incoming clocks in the + -- remainder of the logic. For a single module, the clocks must be looped back + -- in at a higher level! + -- ------------------------------------------------------------------------------------ + + --vhook_e RadioClocking + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a RadioClk1x SampleClk1xOutLcl + --vhook_a RadioClk2x SampleClk2xOut + --vhook_a RadioClk3x open + RadioClockingx: entity work.RadioClocking (rtl) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRadioClkMmcmReset => bRadioClkMmcmReset, --in std_logic + bRadioClksValid => bRadioClksValid, --out std_logic + bRadioClk1xEnabled => bRadioClk1xEnabled, --in std_logic + bRadioClk2xEnabled => bRadioClk2xEnabled, --in std_logic + bRadioClk3xEnabled => bRadioClk3xEnabled, --in std_logic + pPsInc => pPsInc, --in std_logic + pPsEn => pPsEn, --in std_logic + PsClk => PsClk, --in std_logic + pPsDone => pPsDone, --out std_logic + FpgaClk_n => FpgaClk_n, --in std_logic + FpgaClk_p => FpgaClk_p, --in std_logic + RadioClk1x => SampleClk1xOutLcl, --out std_logic + RadioClk2x => SampleClk2xOut, --out std_logic + RadioClk3x => open); --out std_logic + + -- We need an internal copy of SampleClk1x for the TDC, since we don't want to try + -- and align the other DB's clock accidentally. + SampleClk1xOut <= SampleClk1xOutLcl; + + --vhook_e ClockingRegs + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a bRegPortOut bClockingRegPortOut + --vhook_a aRadioClksValid bRadioClksValid + ClockingRegsx: entity work.ClockingRegs (RTL) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRegPortOut => bClockingRegPortOut, --out RegPortOut_t + bRegPortIn => bRegPortIn, --in RegPortIn_t + pPsInc => pPsInc, --out std_logic + pPsEn => pPsEn, --out std_logic + pPsDone => pPsDone, --in std_logic + PsClk => PsClk, --out std_logic + bRadioClkMmcmReset => bRadioClkMmcmReset, --out std_logic + aRadioClksValid => bRadioClksValid, --in std_logic + bRadioClk1xEnabled => bRadioClk1xEnabled, --out std_logic + bRadioClk2xEnabled => bRadioClk2xEnabled, --out std_logic + bRadioClk3xEnabled => bRadioClk3xEnabled, --out std_logic + bJesdRefClkPresent => bJesdRefClkPresent); --in std_logic + + + + -- JESD204B : ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + bJesdRegPortInGrp <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kJesdRegGroupInDbRegs); -- 0x2000 to 0x3FFC + + -- Expand/compress the RegPort for moving through the netlist boundary. + bJesdRegPortOut <= Unflatten(bJesdCoreRegPortOutFlat); + bJesdCoreRegPortInFlat <= Flatten(bJesdRegPortInGrp); + + + --vhook Jesd204bXcvrCore + --vhook_a bRegPortInFlat bJesdCoreRegPortInFlat + --vhook_a bRegPortOutFlat bJesdCoreRegPortOutFlat + --vhook_a FpgaClk1x SampleClk1x + --vhook_a FpgaClk2x SampleClk2x + --vhook_a ReliableClk40 Clk40 + --vhook_a CaptureSysRefClk SampleClk1xOutLcl + --vhook_a cSysRefFpgaLvds_p sSysRefFpgaLvds_p + --vhook_a cSysRefFpgaLvds_n sSysRefFpgaLvds_n + --vhook_a fSysRef sSysRefAsyncReset + --vhook_a fDacReadyForInput sDacReadyForInputAsyncReset + --vhook_a {^f(.*)} s$1 + Jesd204bXcvrCorex: Jesd204bXcvrCore + port map ( + bBusReset => bBusReset, --in STD_LOGIC + BusClk => BusClk, --in STD_LOGIC + ReliableClk40 => Clk40, --in STD_LOGIC + FpgaClk1x => SampleClk1x, --in STD_LOGIC + FpgaClk2x => SampleClk2x, --in STD_LOGIC + bFpgaClksStable => bFpgaClksStable, --in STD_LOGIC + JesdRefClk_p => JesdRefClk_p, --in STD_LOGIC + JesdRefClk_n => JesdRefClk_n, --in STD_LOGIC + bJesdRefClkPresent => bJesdRefClkPresent, --out STD_LOGIC + aLmkSync => aLmkSync, --out STD_LOGIC + bRegPortInFlat => bJesdCoreRegPortInFlat, --in STD_LOGIC_VECTOR(49:0) + bRegPortOutFlat => bJesdCoreRegPortOutFlat, --out STD_LOGIC_VECTOR(33:0) + CaptureSysRefClk => SampleClk1xOutLcl, --in STD_LOGIC + cSysRefFpgaLvds_p => sSysRefFpgaLvds_p, --in STD_LOGIC + cSysRefFpgaLvds_n => sSysRefFpgaLvds_n, --in STD_LOGIC + fSysRef => sSysRefAsyncReset, --out STD_LOGIC + aAdcRx_p => aAdcRx_p, --in STD_LOGIC_VECTOR(3:0) + aAdcRx_n => aAdcRx_n, --in STD_LOGIC_VECTOR(3:0) + aSyncAdcOut_n => aSyncAdcOut_n, --out STD_LOGIC + aDacTx_p => aDacTx_p, --out STD_LOGIC_VECTOR(3:0) + aDacTx_n => aDacTx_n, --out STD_LOGIC_VECTOR(3:0) + aSyncDacIn_n => aSyncDacIn_n, --in STD_LOGIC + fAdcDataFlatter => sAdcDataFlatter, --out STD_LOGIC_VECTOR(63:0) + fDacDataFlatter => sDacDataFlatter, --in STD_LOGIC_VECTOR(63:0) + fAdcDataValid => sAdcDataValid, --out STD_LOGIC + fDacReadyForInput => sDacReadyForInputAsyncReset, --out STD_LOGIC + aDacSync => aDacSync, --out STD_LOGIC + aAdcSync => aAdcSync); --out STD_LOGIC + + + JesdDoubleSyncToNoResetSampleClk : process (SampleClk1x) + begin + if rising_edge(SampleClk1x) then + sDacReadyForInput_ms <= sDacReadyForInputAsyncReset; + sDacReadyForInputLcl <= sDacReadyForInput_ms; + -- No clock crossing here -- just reset, although the prefix declares otherwise... + sDacSync_ms <= aDacSync; + sDacSyncLcl <= sDacSync_ms; + sAdcSync_ms <= aAdcSync; + sAdcSyncLcl <= sAdcSync_ms; + sSysRef_ms <= sSysRefAsyncReset; + sSysRefLcl <= sSysRef_ms; + end if; + end process; + + -- Locals to outputs. + sDacReadyForInput <= sDacReadyForInputLcl; + sDacSync <= sDacSyncLcl; + sAdcSync <= sAdcSyncLcl; + sSysRef <= sSysRefLcl; + + -- Just combine the first two enables, since they're the ones that are used for JESD. + -- No reset crossing here, since bFpgaClksStable is only received by a no-reset domain + -- and the MGTs directly. + bFpgaClksStable <= bRadioClksValid and bRadioClk1xEnabled and bRadioClk2xEnabled; + + -- Compress/expand the flat data types from the netlist and route to top level. + sAdcDataAry <= Unflatten(sAdcDataFlatter); + sDacDataFlatter <= Flatten(sDacDataAry); + + -- Data mapping using the array types. + sAdcDataSample0I <= (sAdcDataAry(0).Data.I & sAdcDataAry(0).Over.I & sAdcDataAry(0).CBit1.I); + sAdcDataSample0Q <= (sAdcDataAry(0).Data.Q & sAdcDataAry(0).Over.Q & sAdcDataAry(0).CBit1.Q); + sAdcDataSample1I <= (sAdcDataAry(1).Data.I & sAdcDataAry(1).Over.I & sAdcDataAry(1).CBit1.I); + sAdcDataSample1Q <= (sAdcDataAry(1).Data.Q & sAdcDataAry(1).Over.Q & sAdcDataAry(1).CBit1.Q); + -- + sDacDataAry(0).Data.I <= sDacDataSample0I; + sDacDataAry(0).Data.Q <= sDacDataSample0Q; + sDacDataAry(1).Data.I <= sDacDataSample1I; + sDacDataAry(1).Data.Q <= sDacDataSample1Q; + + + -- Timing and Sync : ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + bSyncRegPortIn <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kTdc0OffsetsInEndpoint); -- 0x0200 + + --vhook_e TdcWrapper + --vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the + --vhook_# clock offset for this daughterboard, not the global SampleClock. + --vhook_a SampleClk SampleClk1xOutLcl + --vhook_a sPpsPulse sRegPps + TdcWrapperx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => RefClk, --in std_logic + SampleClk => SampleClk1xOutLcl, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rPpsPulse, --in std_logic + sPpsPulse => sRegPps, --out std_logic + rRpTransfer => rRpTransfer, --out std_logic + sSpTransfer => sSpTransfer, --out std_logic + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + WrTdcGen: if kInclWhiteRabbitTdc = '1' generate + bWrSyncRegPortIn <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kTdc1OffsetsInEndpoint); -- 0x0400 + + --vhook_e TdcWrapper WrTdcWrapperx + --vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the + --vhook_# clock offset for this daughterboard, not the global SampleClock. + --vhook_a bSyncRegPortIn bWrSyncRegPortIn + --vhook_a bSyncRegPortOut bWrSyncRegPortOut + --vhook_a SampleClk SampleClk1xOutLcl + --vhook_a RefClk WrRefClk + --vhook_a rPpsPulse rWrPpsPulse + --vhook_a sPpsPulse sWrPps + --vhook_a rRpTransfer rWrRpTransfer + --vhook_a sSpTransfer sWrSpTransfer + --vhook_a rGatedPulseToPin rWrGatedPulseToPin + --vhook_a sGatedPulseToPin sWrGatedPulseToPin + WrTdcWrapperx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => WrRefClk, --in std_logic + SampleClk => SampleClk1xOutLcl, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bWrSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bWrSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rWrPpsPulse, --in std_logic + sPpsPulse => sWrPps, --out std_logic + rRpTransfer => rWrRpTransfer, --out std_logic + sSpTransfer => sWrSpTransfer, --out std_logic + rGatedPulseToPin => rWrGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sWrGatedPulseToPin); --inout std_logic + end generate WrTdcGen; + + WrTdcNotGen: if kInclWhiteRabbitTdc = '0' generate + bWrSyncRegPortOut <= kRegPortOutZero; + sWrPps <= '0'; + rWrRpTransfer <= '0'; + sWrSpTransfer <= '0'; + rWrGatedPulseToPin <= '0'; + sWrGatedPulseToPin <= '0'; + end generate WrTdcNotGen; + + -- Mux the output PPS based on the SFP selection bits. Encoding is one-hot, with zero + -- also a valid state. Regardless of whether the user selects SFP0 or SFP1 as the time + -- source, there is only one White Rabbit TDC, so '01' and '10' are equivalent. + -- '00': Use the PPS output from the "regular" TDC. + -- '01': Use the PPS output from the "white rabbit" TDC. + -- '10': Use the PPS output from the "white rabbit" TDC. + PpsOutputMux : process (SampleClk1xOutLcl) + begin + if rising_edge(SampleClk1xOutLcl) then + -- Double-sync the control bits to the Sample Clock domain. + sPpsSfpSel_ms <= aPpsSfpSel; + sPpsSfpSel <= sPpsSfpSel_ms; + + -- OR the control bits together to produce a single override enable for the WR TDC. + sUseWrTdcPps <= to_boolean(sPpsSfpSel(0) or sPpsSfpSel(1)); + + -- Flop the outputs. One flop for the PPS output IOB, the other for use internally. + sPpsInt <= sPpsMuxed; + end if; + end process PpsOutputMux; + + sPpsMuxed <= sWrPps when sUseWrTdcPps else sRegPps; + sPps <= sPpsInt; + sPpsToIob <= sPpsMuxed; -- No added flop here since there's an IOB outside this module. + + + -- Daughterboard Control : ------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + --vhook_e DaughterboardRegs + --vhook_# Tying this low is safe because the sync reset is used inside DaughterboardRegs. + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a bRegPortOut bDbRegPortOut + --vhook_a kDbId std_logic_vector(to_unsigned(kDbId,kDbIdSize)) + DaughterboardRegsx: entity work.DaughterboardRegs (RTL) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRegPortOut => bDbRegPortOut, --out RegPortOut_t + bRegPortIn => bRegPortIn, --in RegPortIn_t + kDbId => std_logic_vector(to_unsigned(kDbId,kDbIdSize)), --in std_logic_vector(15:0) + kSlotId => kSlotId); --in std_logic + + + + +end RTL; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore.edf b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore.edf new file mode 100644 index 000000000..c9df3749b Binary files /dev/null and b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore.edf differ diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore_stub.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore_stub.vhd new file mode 100644 index 000000000..bf75e9d0d --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore_stub.vhd @@ -0,0 +1,54 @@ +-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +-- Date : Fri Nov 9 16:19:51 2018 +-- Host : hjimenez running 64-bit major release (build 9200) +-- Command : write_vhdl -mode synth_stub -force -file ./Jesd204bXcvrCore_stub.vhd +-- Design : Jesd204bXcvrCore +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Jesd204bXcvrCore is + Port ( + bBusReset : in STD_LOGIC; + BusClk : in STD_LOGIC; + ReliableClk40 : in STD_LOGIC; + FpgaClk1x : in STD_LOGIC; + FpgaClk2x : in STD_LOGIC; + bFpgaClksStable : in STD_LOGIC; + JesdRefClk_p : in STD_LOGIC; + JesdRefClk_n : in STD_LOGIC; + bJesdRefClkPresent : out STD_LOGIC; + aLmkSync : out STD_LOGIC; + bRegPortInFlat : in STD_LOGIC_VECTOR ( 49 downto 0 ); + bRegPortOutFlat : out STD_LOGIC_VECTOR ( 33 downto 0 ); + CaptureSysRefClk : in STD_LOGIC; + cSysRefFpgaLvds_p : in STD_LOGIC; + cSysRefFpgaLvds_n : in STD_LOGIC; + fSysRef : out STD_LOGIC; + aAdcRx_p : in STD_LOGIC_VECTOR ( 3 downto 0 ); + aAdcRx_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); + aSyncAdcOut_n : out STD_LOGIC; + aDacTx_p : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aDacTx_n : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aSyncDacIn_n : in STD_LOGIC; + fAdcDataFlatter : out STD_LOGIC_VECTOR ( 63 downto 0 ); + fDacDataFlatter : in STD_LOGIC_VECTOR ( 63 downto 0 ); + fAdcDataValid : out STD_LOGIC; + fDacReadyForInput : out STD_LOGIC; + aDacSync : out STD_LOGIC; + aAdcSync : out STD_LOGIC + ); + +end Jesd204bXcvrCore; + +architecture stub of Jesd204bXcvrCore is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "bBusReset,BusClk,ReliableClk40,FpgaClk1x,FpgaClk2x,bFpgaClksStable,JesdRefClk_p,JesdRefClk_n,bJesdRefClkPresent,aLmkSync,bRegPortInFlat[49:0],bRegPortOutFlat[33:0],CaptureSysRefClk,cSysRefFpgaLvds_p,cSysRefFpgaLvds_n,fSysRef,aAdcRx_p[3:0],aAdcRx_n[3:0],aSyncAdcOut_n,aDacTx_p[3:0],aDacTx_n[3:0],aSyncDacIn_n,fAdcDataFlatter[63:0],fDacDataFlatter[63:0],fAdcDataValid,fDacReadyForInput,aDacSync,aAdcSync"; +begin +end; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgAdcDacInterfaceTypes.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgAdcDacInterfaceTypes.vhd new file mode 100644 index 000000000..8512d133a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgAdcDacInterfaceTypes.vhd @@ -0,0 +1,302 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgAdcDacInterfaceTypes.vhd +-- Author: National Instruments +-- Original Project: USRP N32x +-- Date: 15 Dec 2017 +-- +------------------------------------------------------------------------------- +-- (c) 2018 Copyright National Instruments Corporation +-- All Rights Reserved +-- National Instruments Internal Information +------------------------------------------------------------------------------- +-- +-- Purpose: Contains types for ADC and DAC data so they can more easily be +-- passed through the design. +-- +-- vreview_group JesdCoreN32x +-- vreview_reviewers djepson wfife +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgJesdConfig.all; + + +package PkgAdcDacInterfaceTypes is + + -- Data type for the DACs. + type DacData_t is record + I : std_logic_vector(kDacDataWidth - 1 downto 0); + Q : std_logic_vector(kDacDataWidth - 1 downto 0); + end record; + + -- Data type for the ADCs. + type AdcData_t is record + I : std_logic_vector(kAdcDataWidth - 1 downto 0); + Q : std_logic_vector(kAdcDataWidth - 1 downto 0); + end record; + + -- Type has two bits that correspond to I and Q; example usage: overrange flags. + type IQFlags_t is record + I : std_logic; + Q : std_logic; + end record; + + -- Single data type for all information from the ADCs. + type AdcSamples_t is record + Data : AdcData_t; + Over : IQFlags_t; + CBit1 : IQFlags_t; + end record; + + -- Single data type for all information to the DACs. + type DacSamples_t is record + Data : DacData_t; + end record; + + -- To support multiple data values per clock cycle, these types + -- are arrays of the ADC and DAC data types where the size of the array + -- corresponds to the number of samples per cycle. + type AdcDataAry_t is array (kSamplesPerCycle - 1 downto 0) of AdcSamples_t; + type DacDataAry_t is array (kSamplesPerCycle - 1 downto 0) of DacSamples_t; + + -- Zero/default constant + constant kAdcDataAryZero : AdcDataAry_t := + (others => (Data => (others => (others => '0')), + Over => (others => '0'), + CBit1 => (others => '0')) + ); + + -- Zero/default constant + constant kDacDataAryZero : DacDataAry_t := + (others => (Data => (others => (others => '0'))) + ); + + -- Flattened type that converts the ADC data into std_logic_vector types. This type is + -- not suitable for use in the port maps of components that are presynthesized (into EDF + -- or NGC files) but is useful for passing data to the top level. + type AdcDataAryFlat_t is record + DataI : std_logic_vector(kSamplesPerCycle*kAdcDataWidth - 1 downto 0); + DataQ : std_logic_vector(kSamplesPerCycle*kAdcDataWidth - 1 downto 0); + OverI : std_logic_vector(kSamplesPerCycle - 1 downto 0); + OverQ : std_logic_vector(kSamplesPerCycle - 1 downto 0); + CBit1I : std_logic_vector(kSamplesPerCycle - 1 downto 0); + CBit1Q : std_logic_vector(kSamplesPerCycle - 1 downto 0); + end record; + + -- Fully flattened ADC data for passing into and out of presynthesized components. + subtype AdcDataAryFlatter_t is std_logic_vector(2*(kSamplesPerCycle*(kAdcDataWidth + 2)) - 1 downto 0); + + -- Flattened type that converts the DAC data into std_logic_vector types. This type is + -- not suitable for use in the port maps of components that are presynthesized (into EDF + -- or NGC files) but is useful for passing data from the top level. + type DacDataAryFlat_t is record + DataI : std_logic_vector(kSamplesPerCycle*kDacDataWidth - 1 downto 0); + DataQ : std_logic_vector(kSamplesPerCycle*kDacDataWidth - 1 downto 0); + end record; + + -- Fully flattened DAC data for passing into and out of presynthesized components. + subtype DacDataAryFlatter_t is std_logic_vector(2*(kSamplesPerCycle*kDacDataWidth) - 1 downto 0); + + -- Function to convert types defined above for the ADC data + function Flatten (AdcData : AdcDataAry_t) return AdcDataAryFlat_t; + function Flatten (AdcData : AdcDataAryFlat_t) return AdcDataAryFlatter_t; + function Flatten (AdcData : AdcDataAry_t) return AdcDataAryFlatter_t; + function Unflatten(AdcData : AdcDataAryFlatter_t) return AdcDataAryFlat_t; + function Unflatten(AdcData : AdcDataAryFlat_t) return AdcDataAry_t; + function Unflatten(AdcData : AdcDataAryFlatter_t) return AdcDataAry_t; + + + -- Function to convert types defined above for the DAC data + function Flatten (DacData : DacDataAry_t) return DacDataAryFlat_t; + function Flatten (DacData : DacDataAryFlat_t) return DacDataAryFlatter_t; + function Flatten (DacData : DacDataAry_t) return DacDataAryFlatter_t; + function Unflatten(DacData : DacDataAryFlatter_t) return DacDataAryFlat_t; + function UnFlatten(DacData : DacDataAryFlat_t) return DacDataAry_t; + function Unflatten(DacData : DacDataAryFlatter_t) return DacDataAry_t; + + +end package PkgAdcDacInterfaceTypes; + + +package body PkgAdcDacInterfaceTypes is + + -- Flattens AdcDataAry_t to AdcDataAryFlat_t + function Flatten(AdcData : AdcDataAry_t) return AdcDataAryFlat_t + is + variable ReturnVar : AdcDataAryFlat_t; + begin + ReturnVar := (DataI => (others => '0'), -- Note (others => (others => '0')) does not work here + DataQ => (others => '0'), -- since DataX and OverX/CBit1X are of different lengths (ModelSim error) + OverI => (others => '0'), + OverQ => (others => '0'), + CBit1I => (others => '0'), + CBit1Q => (others => '0')); + + -- The upstream logic puts the 0th element of an array in the MSBs of its data word + for i in 0 to kSamplesPerCycle - 1 loop + ReturnVar.DataI((kSamplesPerCycle - i)*kAdcDataWidth - 1 downto (kSamplesPerCycle - 1 - i)*kAdcDataWidth) := AdcData(i).Data.I; -- Input Data 0 to MSB + ReturnVar.DataQ((kSamplesPerCycle - i)*kAdcDataWidth - 1 downto (kSamplesPerCycle - 1 - i)*kAdcDataWidth) := AdcData(i).Data.Q; + ReturnVar.OverI (kSamplesPerCycle - 1 - i) := AdcData(i).Over.I; -- Input Data 0 to MSB + ReturnVar.OverQ (kSamplesPerCycle - 1 - i) := AdcData(i).Over.Q; + ReturnVar.CBit1I(kSamplesPerCycle - 1 - i) := AdcData(i).CBit1.I; + ReturnVar.CBit1Q(kSamplesPerCycle - 1 - i) := AdcData(i).CBit1.Q; + end loop; + + return ReturnVar; + end function Flatten; + + + -- UnFlattens AdcDataAryFlat_t to AdcDataAry_t + function Unflatten(AdcData : AdcDataAryFlat_t) return AdcDataAry_t + is + variable ReturnVar : AdcDataAry_t; + begin + ReturnVar := (others => (Data => (others => (others => '0')), Over => (others => '0'), CBit1 => (others => '0'))); + for i in 0 to kSamplesPerCycle - 1 loop + -- MSB of flattened word = 0th element of ADC data array - this corresponds to how TheWindow + -- expects data arrays to be transferred. + ReturnVar(kSamplesPerCycle - 1 - i).Data.I := AdcData.DataI((i+1)*kAdcDataWidth - 1 downto i*kAdcDataWidth); + ReturnVar(kSamplesPerCycle - 1 - i).Data.Q := AdcData.DataQ((i+1)*kAdcDataWidth - 1 downto i*kAdcDataWidth); + ReturnVar(kSamplesPerCycle - 1 - i).Over.I := AdcData.OverI(i); + ReturnVar(kSamplesPerCycle - 1 - i).Over.Q := AdcData.OverQ(i); + ReturnVar(kSamplesPerCycle - 1 - i).CBit1.I := AdcData.CBit1I(i); + ReturnVar(kSamplesPerCycle - 1 - i).CBit1.Q := AdcData.CBit1Q(i); + end loop; + return ReturnVar; + end function Unflatten; + + + + + -- Flattens AdcDataAryFlat_t to AdcDataAryFlatter_t + function Flatten(AdcData : AdcDataAryFlat_t) return AdcDataAryFlatter_t + is + variable ReturnVar : AdcDataAryFlatter_t; + begin + ReturnVar := AdcData.OverQ & AdcData.CBit1Q & AdcData.OverI & AdcData.CBit1I & AdcData.DataQ & AdcData.DataI; + return ReturnVar; + end function Flatten; + + -- UnFlattens AdcDataAryFlatter_t to AdcDataAryFlat_t + function Unflatten(AdcData : AdcDataAryFlatter_t) return AdcDataAryFlat_t + is + variable ReturnVar : AdcDataAryFlat_t; + begin + ReturnVar.DataI := AdcData(1*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle - 1 downto 0*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle); + ReturnVar.DataQ := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle - 1 downto 1*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle); + ReturnVar.CBit1I := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 1*kSamplesPerCycle - 1 downto 2*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle); + ReturnVar.OverI := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 2*kSamplesPerCycle - 1 downto 2*kSamplesPerCycle*kAdcDataWidth + 1*kSamplesPerCycle); + ReturnVar.CBit1Q := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 3*kSamplesPerCycle - 1 downto 2*kSamplesPerCycle*kAdcDataWidth + 2*kSamplesPerCycle); + ReturnVar.OverQ := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 4*kSamplesPerCycle - 1 downto 2*kSamplesPerCycle*kAdcDataWidth + 3*kSamplesPerCycle); + return ReturnVar; + end function Unflatten; + + + -- Flattens AdcDataAry_t to AdcDataAryFlatter_t + function Flatten(AdcData : AdcDataAry_t) return AdcDataAryFlatter_t + is + variable TempVar : AdcDataAryFlat_t; + variable ReturnVar : AdcDataAryFlatter_t; + begin + TempVar := Flatten(AdcData); + ReturnVar := Flatten(TempVar); + return ReturnVar; + end function Flatten; + + -- UnFlattens AdcDataAryFlatter_t to AdcDataAry_t + function Unflatten(AdcData : AdcDataAryFlatter_t) return AdcDataAry_t + is + variable TempVar : AdcDataAryFlat_t; + variable ReturnVar : AdcDataAry_t; + begin + TempVar := Unflatten(AdcData); + ReturnVar := Unflatten(TempVar); + return ReturnVar; + end function Unflatten; + + + + -- Flattens DacDataAry_t to DacDataAryFlat_t + function Flatten(DacData : DacDataAry_t) return DacDataAryFlat_t + is + variable ReturnVar : DacDataAryFlat_t; + begin + ReturnVar := (others => (others => '0')); + for i in 0 to kSamplesPerCycle - 1 loop + -- MSB of flattened word = 0th element of ADC data array - this corresponds to how TheWindow + -- expects data arrays to be transferred. + ReturnVar.DataI((i+1)*kDacDataWidth - 1 downto i*kDacDataWidth) := DacData(kSamplesPerCycle - 1 - i).Data.I; + ReturnVar.DataQ((i+1)*kDacDataWidth - 1 downto i*kDacDataWidth) := DacData(kSamplesPerCycle - 1 - i).Data.Q; + end loop; + return ReturnVar; + end function Flatten; + + + -- UnFlattens DacDataAryFlat_t to DacDataAry_t + function UnFlatten(DacData : DacDataAryFlat_t) return DacDataAry_t + is + variable ReturnVar : DacDataAry_t; + begin + ReturnVar := (others => (Data => (others => (others => '0')))); + + -- The upstream logic puts the 0th element of an array in the MSBs of its data word + for i in 0 to kSamplesPerCycle - 1 loop + ReturnVar(kSamplesPerCycle - 1 - i).Data.I := DacData.DataI(kDacDataWidth*(i+1) - 1 downto kDacDataWidth*i); + ReturnVar(kSamplesPerCycle - 1 - i).Data.Q := DacData.DataQ(kDacDataWidth*(i+1) - 1 downto kDacDataWidth*i); + end loop; + + return ReturnVar; + end function UnFlatten; + + + + -- Flattens DacDataAryFlat_t to DacDataAryFlatter_t + function Flatten(DacData : DacDataAryFlat_t) return DacDataAryFlatter_t + is + variable ReturnVar : DacDataAryFlatter_t; + begin + ReturnVar := DacData.DataQ & DacData.DataI; + return ReturnVar; + end function Flatten; + + + -- UnFlattens DacDataAryFlatter_t to DacDataAryFlat_t + function Unflatten(DacData : DacDataAryFlatter_t) return DacDataAryFlat_t + is + variable ReturnVar : DacDataAryFlat_t; + begin + ReturnVar.DataI := DacData(1*kSamplesPerCycle*kDacDataWidth - 1 downto 0*kSamplesPerCycle*kDacDataWidth); + ReturnVar.DataQ := DacData(2*kSamplesPerCycle*kDacDataWidth - 1 downto 1*kSamplesPerCycle*kDacDataWidth); + return ReturnVar; + end function Unflatten; + + + -- Flattens DacDataAry_t to DacDataAryFlatter_t + function Flatten(DacData : DacDataAry_t) return DacDataAryFlatter_t + is + variable TempVar : DacDataAryFlat_t; + variable ReturnVar : DacDataAryFlatter_t; + begin + TempVar := Flatten(DacData); + ReturnVar := Flatten(TempVar); + return ReturnVar; + end function Flatten; + + -- UnFlattens DacDataAryFlatter_t to DacDataAry_t + function Unflatten(DacData : DacDataAryFlatter_t) return DacDataAry_t + is + variable TempVar : DacDataAryFlat_t; + variable ReturnVar : DacDataAry_t; + begin + TempVar := Unflatten(DacData); + ReturnVar := Unflatten(TempVar); + return ReturnVar; + end function Unflatten; + + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgClockingRegMap.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgClockingRegMap.vhd new file mode 100644 index 000000000..03b95c100 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgClockingRegMap.vhd @@ -0,0 +1,107 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgClockingRegMap.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgClockingRegMap is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- RadioClkMmcm : 0x20 (ClockingRegs.vhd) + -- PhaseShiftControl : 0x24 (ClockingRegs.vhd) + -- RadioClkEnables : 0x28 (ClockingRegs.vhd) + -- MgtRefClkStatus : 0x30 (ClockingRegs.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group ClockingRegs +--=============================================================================== + + -- RadioClkMmcm Register (from ClockingRegs.vhd) + constant kRadioClkMmcm : integer := 16#20#; -- Register Offset + constant kRadioClkMmcmSize: integer := 32; -- register width in bits + constant kRadioClkMmcmMask : std_logic_vector(31 downto 0) := X"00000013"; + constant kRadioClkMmcmResetSetSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetSetMsb : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetSet : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetClearSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmResetClearMsb : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmResetClear : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmLockedSize : integer := 1; --RadioClkMmcm:RadioClkMmcmLocked + constant kRadioClkMmcmLockedMsb : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked + constant kRadioClkMmcmLocked : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked + + -- PhaseShiftControl Register (from ClockingRegs.vhd) + constant kPhaseShiftControl : integer := 16#24#; -- Register Offset + constant kPhaseShiftControlSize: integer := 32; -- register width in bits + constant kPhaseShiftControlMask : std_logic_vector(31 downto 0) := X"10010011"; + constant kPsIncSize : integer := 1; --PhaseShiftControl:PsInc + constant kPsIncMsb : integer := 0; --PhaseShiftControl:PsInc + constant kPsInc : integer := 0; --PhaseShiftControl:PsInc + constant kPsDecSize : integer := 1; --PhaseShiftControl:PsDec + constant kPsDecMsb : integer := 4; --PhaseShiftControl:PsDec + constant kPsDec : integer := 4; --PhaseShiftControl:PsDec + constant kPsEnabledForFdbClkSize : integer := 1; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsEnabledForFdbClkMsb : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsEnabledForFdbClk : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsDoneSize : integer := 1; --PhaseShiftControl:PsDone + constant kPsDoneMsb : integer := 28; --PhaseShiftControl:PsDone + constant kPsDone : integer := 28; --PhaseShiftControl:PsDone + + -- RadioClkEnables Register (from ClockingRegs.vhd) + constant kRadioClkEnables : integer := 16#28#; -- Register Offset + constant kRadioClkEnablesSize: integer := 32; -- register width in bits + constant kRadioClkEnablesMask : std_logic_vector(31 downto 0) := X"00000111"; + constant kRadioClk1xEnabledSize : integer := 1; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk1xEnabledMsb : integer := 0; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk1xEnabled : integer := 0; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk2xEnabledSize : integer := 1; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk2xEnabledMsb : integer := 4; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk2xEnabled : integer := 4; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk3xEnabledSize : integer := 1; --RadioClkEnables:RadioClk3xEnabled + constant kRadioClk3xEnabledMsb : integer := 8; --RadioClkEnables:RadioClk3xEnabled + constant kRadioClk3xEnabled : integer := 8; --RadioClkEnables:RadioClk3xEnabled + + -- MgtRefClkStatus Register (from ClockingRegs.vhd) + constant kMgtRefClkStatus : integer := 16#30#; -- Register Offset + constant kMgtRefClkStatusSize: integer := 32; -- register width in bits + constant kMgtRefClkStatusMask : std_logic_vector(31 downto 0) := X"00000001"; + constant kJesdRefClkPresentSize : integer := 1; --MgtRefClkStatus:JesdRefClkPresent + constant kJesdRefClkPresentMsb : integer := 0; --MgtRefClkStatus:JesdRefClkPresent + constant kJesdRefClkPresent : integer := 0; --MgtRefClkStatus:JesdRefClkPresent + +end package; + +package body PkgClockingRegMap is + + -- function kRadioClkMmcmRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kPhaseShiftControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRadioClkEnablesRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMgtRefClkStatusRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgDaughterboardRegMap.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgDaughterboardRegMap.vhd new file mode 100644 index 000000000..06708cde3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgDaughterboardRegMap.vhd @@ -0,0 +1,56 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgDaughterboardRegMap.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgDaughterboardRegMap is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- DaughterboardId : 0x630 (DaughterboardRegs.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group StaticControl +--=============================================================================== + + -- DaughterboardId Register (from DaughterboardRegs.vhd) + constant kDaughterboardId : integer := 16#630#; -- Register Offset + constant kDaughterboardIdSize: integer := 32; -- register width in bits + constant kDaughterboardIdMask : std_logic_vector(31 downto 0) := X"0001ffff"; + constant kDbIdValSize : integer := 16; --DaughterboardId:DbIdVal + constant kDbIdValMsb : integer := 15; --DaughterboardId:DbIdVal + constant kDbIdVal : integer := 0; --DaughterboardId:DbIdVal + constant kSlotIdValSize : integer := 1; --DaughterboardId:SlotIdVal + constant kSlotIdValMsb : integer := 16; --DaughterboardId:SlotIdVal + constant kSlotIdVal : integer := 16; --DaughterboardId:SlotIdVal + +end package; + +package body PkgDaughterboardRegMap is + + -- function kDaughterboardIdRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgJesdConfig.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgJesdConfig.vhd new file mode 100644 index 000000000..4913b03fc --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgJesdConfig.vhd @@ -0,0 +1,165 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgJesdConfig.vhd +-- Author: National Instruments +-- Original Project: N32x +-- Date: 15 Dec 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: JESD204B setup constants and functions. These constants are shared +-- between RX and TX JESD cores. +-- +-- vreview_group JesdCoreN32x +-- vreview_reviewers djepson wfife +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + + +package PkgJesdConfig is + + -- "JESD" in ASCII - with the core number 0 or 1 on the LSb. + constant kJesdSignature : std_logic_vector(31 downto 0) := x"4a455344"; + + -- Register endpoints + constant kJesdDrpRegsInEndpoint : RegOffset_t := (kOffset => 16#0800#, -- 0x2800 to + kWidth => 16#0800#); -- 0x2FFF + + -- Selects the UsrClk2 for the transceivers. For 64-bit wide transceivers, the + -- UsrClk = 2*UserClk2 frequency. For 32-bit wide transceivers, UsrClk = UserClk2 + -- frequency. This is a generalization, the clock ratio should be confirmed based on + -- the transceiver configuration. + -- The N310 transceivers use the single rate reference, hence = false. + constant kDoubleRateUsrClk : boolean := false; + + -- For the N32x, all lanes are in one quad and we use the QPLL. + constant kJesdUseQpll : boolean := true; + + constant kAdcDataWidth : integer := 14; -- ADC data width in bits + constant kDacDataWidth : integer := 16; -- DAC data width in bits + constant kSamplesPerCycle : integer := 2; -- Number of samples per SampleClk1x + + constant kGtxDrpAddrWidth : natural := 9; + constant kGtxAddrLsbPosition : natural := 2; + constant kQpllDrpAddrWidth : natural := 8; + constant kGtxDrpDataWidth : natural := 16; + + -- Max supported number of lanes + constant kMaxNumLanes : natural := 4; + -- Max supported number of quads (normally there is 1 quad per 4 lanes but disconnect + -- the definitions to allow quad sharing) + constant kMaxNumQuads : natural := 1; + + -- Rhodium: + -- JESD shared setup - LMFS = 4211, HD = 1 (Samples are split across multiple lanes). + constant kNumLanes : natural := 4; -- L + constant kNumConvs : positive := 2; -- M + constant kOctetsPerFrame : natural := 1; -- F + constant kDacJesdSamplesPerCycle : integer := 1; -- S + constant kOctetsPerLane : natural := 2; -- MGT data is kOctetsPerLane*8 = 16 bits wide + constant kNumQuads : natural := kNumLanes / 4; -- 4 lanes per quad + constant kHighDensity : boolean := true; -- HD + constant kConvResBits : positive := kDacDataWidth; -- Converter resolution in bits + constant kConvSampleBits : positive := 16; -- Sample Length in bits + constant kInitLaneAlignCnt : positive := 4; + constant kFramesPerMulti : natural := 24; -- K + + -- Rhodium: + -- The converters are running at 400/491.52/500 MSPS (DeviceClk), and the sampling + -- clock at the FPGA (UserClk) is 200/245.76/250 MHz; so UsrClk = (DeviceClk / 2). + -- The frame rate = DeviceClk, and the Multiframe rate = (frame rate / kFramesPerMulti) + -- Thus, kUserClksPerMulti = (UsrClk / Multiframe rate) + -- = (UsrClk / (DeviceClk / kFramesPerMulti)) + -- since UsrClk = DeviceClk / 2 then, + -- kUserClksPerMulti = ((DeviceClk / 2) / (DeviceClk / kFramesPerMulti)) + -- therefore, + -- kUserClksPerMulti = kFramesPerMulti / 2 + constant kUserClksPerMulti : integer := kFramesPerMulti / 2; + + + type NaturalVector is array ( natural range <>) of natural; + + -- The PCB connections are are passed trough, any swapping is handled somewhere else. + -- + -- Transceiver MGT Channel ADC Lane DAC Lane + -- *********** *********** ******** ******** + -- GT0: X0Y8 0 0 0 + -- GT1: X0Y9 1 1 1 + -- GT2: X0Y10 2 2 2 + -- GT3: X0Y11 3 3 3 + constant kRxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- MGT => ADC (in above table) + 0 => 0, + 1 => 1, + 2 => 2, + 3 => 3 + ); + + constant kTxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- MGT => DAC lane + 0 => 0, + 1 => 1, + 2 => 2, + 3 => 3 + ); + + constant kLaneToQuadMap : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- All lanes are in one quad + 0 => 0, + 1 => 0, + 2 => 0, + 3 => 0 + ); + + + -- The master transceiver channel for channel bonding. E(kMasterBondingChannel) + -- must have the highest value decrementing to b"000" for that last channels to bond. + constant kMasterBondingChannel : integer := 1; + + -- Channel bonding occurs when a master detects a K-char sequence and aligns its + -- internal FIFO to the start of this sequence. A signal is then generated to other + -- slave transceivers that cause them to bond to the sequence - this bonding signal is + -- cascaded from master to slave to slave to slave, etc where each slave must know how + -- many levels to the master there are. The last slave to bond must be at level b"000" + -- and the master is at the highest level; the number of levels in the sequence is + -- governed by the size of the transceiver FIFO (see the Xilinx user guides for more + -- information). + type BondLevels_t is array(0 to kNumLanes - 1) of std_logic_vector(2 downto 0); + constant kBondLevel : BondLevels_t := ( + 0 => b"000", -- Control from 1 + 1 => b"001", -- Master + 2 => b"000", -- Control from 1 + 3 => b"000" -- Control from 1 + ); + + + -- User Rx Data + -- ADC Word data width: 14 sample bits + 2 tails bits + constant kAdcWordWidth : integer := 16; + subtype AdcWord_t is std_logic_vector(kAdcWordWidth - 1 downto 0); + type AdcWordArray_t is array(kSamplesPerCycle*2 - 1 downto 0) of AdcWord_t; -- The *2 is because there are two samples (I and Q) per "sample" + + -- Constants to specify the contents of the AdcWord_t vector. + constant kAdcWordDataMsb : integer := 15; + constant kAdcWordDataLsb : integer := 2; + constant kAdcWordOver : integer := 1; + constant kAdcWordCBit1 : integer := 0; + + + -- Option to pipeline stages to improve timing, if needed + constant kPipelineDetectCharsStage : boolean := false; + constant kPipelineCharReplStage : boolean := false; + +end package; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgRhPersonality.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgRhPersonality.vhd new file mode 100644 index 000000000..801a46d15 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgRhPersonality.vhd @@ -0,0 +1,62 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgRhPersonality.vhd +-- Author: National Instruments +-- Original Project: N32x +-- Date: 15 Dec 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: This package contains constants and helpful functions that enable +-- the FPGA to be compiled with different features. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + + +package PkgRhPersonality is + + -- Rhodium daughterboard ID definition. + constant kDbId : integer := 16#152#; + constant kDbIdSize : integer := 16; + + + -- RegPort Address Definitions : ------------------------------------------------------ + -- + -- DB Regs ... + -- + -- Clocking Offset: 0x 000 Width: 0x 200 + -- Tdco0 Offset: 0x 200 Width: 0x 200 + -- Tdco1 Offset: 0x 400 Width: 0x 200 + -- Daughterboard Ctrl Offset: 0x 600 Width: 0x 200 + -- Total: 0x2000 + -- JESD 2x - A Offset: 0x2000 Width: 0x1000 + -- JESD 2x - B Offset: 0x3000 Width: 0x1000 + -- Total: 0x4000 + -- Total: 0x8000 for two DBs + -- ------------------------------------------------------------------------------------ + + -- A single RegPort runs to the JESD204B Core. + constant kJesdRegGroupInDbRegs : RegOffset_t := (kOffset => 16#2000#, -- 0x2000 to + kWidth => 16#1000#); -- 0x2FFF + + -- DB Regs : -------------------------------------------------------------------------- + constant kClockingOffsetInEndpoint : RegOffset_t := (kOffset => 16#0000#, -- 0x0000 to + kWidth => 16#0200#); -- 0x01FF + constant kTdc0OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0200#, -- 0x0200 to + kWidth => 16#0200#); -- 0x03FF + constant kTdc1OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0400#, -- 0x0400 to + kWidth => 16#0200#); -- 0x05FF + constant kDaughterboardOffsetInEndpoint : RegOffset_t := (kOffset => 16#0600#, -- 0x0600 to + kWidth => 16#0200#); -- 0x07FF + +end package PkgRhPersonality; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/RadioClocking.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/RadioClocking.vhd new file mode 100644 index 000000000..69a15d49a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/RadioClocking.vhd @@ -0,0 +1,305 @@ +------------------------------------------------------------------------------- +-- +-- File: RadioClocking.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 22 February 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Instantiates a MMCM to produce 1x, 2x, and 3x versions of the Radio Clock +-- coming from the FPGA input pin. Handles all the buffering for the input clock. +-- Additionally allows the clocks to be turned on and off, and phase shifted. +-- +-- NOTE: This module hard-codes the MMCM settings for a SPECIFIC clock rate! +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library unisim; + use unisim.vcomponents.all; + + +entity RadioClocking is + port ( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + + -- Should be a always-on clock + BusClk : in std_logic; + + -- Sync reset to the RadioClkMmcm. + bRadioClkMmcmReset : in std_logic; + + -- Locked indication from the RadioClkMmcm in BusClk and aReset domains. + bRadioClksValid : out std_logic; + + bRadioClk1xEnabled : in std_logic; + bRadioClk2xEnabled : in std_logic; + bRadioClk3xEnabled : in std_logic; + + -- Phase shift interface for the RadioClkMmcm. PsClk must be <= 200 MHz. + pPsInc : in std_logic; + pPsEn : in std_logic; + PsClk : in std_logic; + pPsDone : out std_logic; + + -- Straight from pins. Buffer included in here. + FpgaClk_n : in std_logic; + FpgaClk_p : in std_logic; + + RadioClk1x : out std_logic; + RadioClk2x : out std_logic; + RadioClk3x : out std_logic + + ); +end RadioClocking; + + +architecture rtl of RadioClocking is + + --vhook_sigstart + signal RadioClk1xLcl: std_logic; + signal RadioClk1xPll: std_logic; + signal RadioClk2xLcl: std_logic; + signal RadioClk2xPll: std_logic; + signal RadioClk3xLcl: std_logic; + signal RadioClk3xPll: std_logic; + --vhook_sigend + + signal RadioClkMmcmFeedbackIn, + RadioClkMmcmFeedbackOut, + FpgaClkSE, + aRadioClkMmcmLocked : std_logic; + + signal bRadioClkMmcmLocked_ms, + bRadioClkMmcmLocked, + bEnableRadioClkBufgOutputs, + bEnableRadioClk1xBufgOutput, + bEnableRadioClk2xBufgOutput, + bEnableRadioClk3xBufgOutput : std_logic := '0'; + + signal aRadioClkMmcmResetInternal : std_logic := '1'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of bRadioClkMmcmLocked_ms : signal is "true"; + attribute ASYNC_REG of bRadioClkMmcmLocked : signal is "true"; + +begin + + -- Radio Clock Buffering : ------------------------------------------------------------ + -- + -- ------------------------------------------------------------------------------------ + --vhook_i IBUFDS FpgaClkIbufg hidegeneric=true + --vhook_a I FpgaClk_p + --vhook_a IB FpgaClk_n + --vhook_a O FpgaClkSE + FpgaClkIbufg: IBUFDS + port map ( + O => FpgaClkSE, --out std_ulogic + I => FpgaClk_p, --in std_ulogic + IB => FpgaClk_n); --in std_ulogic + + + ResetDelay : process(aReset, BusClk) + begin + if aReset then + aRadioClkMmcmResetInternal <= '1'; + elsif rising_edge(BusClk) then + if bReset then + aRadioClkMmcmResetInternal <= '1'; + else + -- Delay by 1 to allow the BUFGs to turn off before the MMCM is reset. + aRadioClkMmcmResetInternal <= bRadioClkMmcmReset; + end if; + end if; + end process ResetDelay; + + + RadioClkMmcm: MMCME2_ADV + generic map( + COMPENSATION => "ZHOLD", + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 4.000, -- Feedback + CLKOUT0_DIVIDE_F => 4.000, -- Data Clock 1x, RadioClk1xPll + CLKOUT1_DIVIDE => 2, -- Data Clock 2x, RadioClk2xPll + CLKOUT2_DIVIDE => 2, -- Data Clock 3x, RadioClk3xPll + CLKOUT3_DIVIDE => 1, -- unused + CLKOUT4_DIVIDE => 1, -- unused + CLKOUT5_DIVIDE => 1, -- unused + CLKOUT6_DIVIDE => 1, -- unused + CLKFBOUT_PHASE => 0.000, -- Feedback + CLKOUT0_PHASE => 0.000, -- Data Clock 1x + CLKOUT1_PHASE => 0.000, -- Data Clock 2x + CLKOUT2_PHASE => 0.000, -- Data Clock 3x + CLKOUT3_PHASE => 0.000, -- unused + CLKOUT4_PHASE => 0.000, -- unused + CLKOUT5_PHASE => 0.000, -- unused + CLKOUT6_PHASE => 0.000, -- unused + CLKOUT0_DUTY_CYCLE => 0.500, + CLKOUT1_DUTY_CYCLE => 0.500, + CLKOUT2_DUTY_CYCLE => 0.500, + CLKOUT3_DUTY_CYCLE => 0.500, + CLKOUT4_DUTY_CYCLE => 0.500, + CLKOUT5_DUTY_CYCLE => 0.500, + CLKOUT6_DUTY_CYCLE => 0.500, + DIVCLK_DIVIDE => 1, + REF_JITTER1 => 0.010, + CLKIN1_PERIOD => 4.069, -- 245.76 MHz max + CLKFBOUT_USE_FINE_PS => true, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_USE_FINE_PS => false, + STARTUP_WAIT => false, + CLKOUT4_CASCADE => false) + port map ( + CLKINSEL => '1', + CLKIN1 => FpgaClkSE, + CLKIN2 => '0', + CLKFBIN => RadioClkMmcmFeedbackIn, + RST => aRadioClkMmcmResetInternal, + PWRDWN => '0', + DADDR => (others => '0'), + DI => (others => '0'), + DWE => '0', + DEN => '0', + DCLK => '0', + DO => open, + DRDY => open, + PSINCDEC => pPsInc, + PSEN => pPsEn, + PSCLK => PsClk, + PSDONE => pPsDone, + CLKOUT0 => RadioClk1xPll, + CLKOUT0B => open, + CLKOUT1 => RadioClk2xPll, + CLKOUT1B => open, + CLKOUT2 => RadioClk3xPll, + CLKOUT2B => open, + CLKOUT3 => open, + CLKOUT3B => open, + CLKOUT4 => open, + CLKOUT5 => open, + CLKOUT6 => open, + CLKFBOUT => RadioClkMmcmFeedbackOut, + CLKFBOUTB => open, + LOCKED => aRadioClkMmcmLocked, + CLKINSTOPPED => open, + CLKFBSTOPPED => open); + + RadioClkMmcmFeedbackBufg: BUFG + port map ( + I => RadioClkMmcmFeedbackOut, + O => RadioClkMmcmFeedbackIn + ); + + + -- Only enable the WRAPBUFGs when the MMCM is locked. If the MMCM is ever placed in + -- reset, we turn off the clocks one cycle before the asynchronous version + -- (aRadioClkMmcmResetInternal) reaches the MMCM inputs in order to prevent + -- output glitches. + CombineEnablesForBuffers : process(aReset, BusClk) + begin + if aReset then + bRadioClkMmcmLocked_ms <= '0'; + bRadioClkMmcmLocked <= '0'; + bEnableRadioClk1xBufgOutput <= '0'; + bEnableRadioClk2xBufgOutput <= '0'; + bEnableRadioClk3xBufgOutput <= '0'; + bEnableRadioClkBufgOutputs <= '0'; + elsif rising_edge(BusClk) then + if bReset then + bRadioClkMmcmLocked_ms <= '0'; + bRadioClkMmcmLocked <= '0'; + bEnableRadioClk1xBufgOutput <= '0'; + bEnableRadioClk2xBufgOutput <= '0'; + bEnableRadioClk3xBufgOutput <= '0'; + bEnableRadioClkBufgOutputs <= '0'; + else + bRadioClkMmcmLocked_ms <= aRadioClkMmcmLocked; + bRadioClkMmcmLocked <= bRadioClkMmcmLocked_ms; + + bEnableRadioClkBufgOutputs <= bRadioClkMmcmLocked and + not bRadioClkMmcmReset; + bEnableRadioClk1xBufgOutput <= bRadioClk1xEnabled and bEnableRadioClkBufgOutputs; + bEnableRadioClk2xBufgOutput <= bRadioClk2xEnabled and bEnableRadioClkBufgOutputs; + bEnableRadioClk3xBufgOutput <= bRadioClk3xEnabled and bEnableRadioClkBufgOutputs; + end if; + end if; + end process CombineEnablesForBuffers; + + bRadioClksValid <= bEnableRadioClkBufgOutputs; + + --vhook_e WrapBufg RadioClk1xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk1xPll + --vhook_a aCe bEnableRadioClk1xBufgOutput + --vhook_a ClkOut RadioClk1xLcl + RadioClk1xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk1xPll, --in std_logic + aCe => bEnableRadioClk1xBufgOutput, --in std_logic + ClkOut => RadioClk1xLcl); --out std_logic + + --vhook_e WrapBufg RadioClk2xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk2xPll + --vhook_a aCe bEnableRadioClk2xBufgOutput + --vhook_a ClkOut RadioClk2xLcl + RadioClk2xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk2xPll, --in std_logic + aCe => bEnableRadioClk2xBufgOutput, --in std_logic + ClkOut => RadioClk2xLcl); --out std_logic + + --vhook_e WrapBufg RadioClk3xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk3xPll + --vhook_a aCe bEnableRadioClk3xBufgOutput + --vhook_a ClkOut RadioClk3xLcl + RadioClk3xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk3xPll, --in std_logic + aCe => bEnableRadioClk3xBufgOutput, --in std_logic + ClkOut => RadioClk3xLcl); --out std_logic + + + -- Assign outputs from locals. + RadioClk1x <= RadioClk1xLcl; + RadioClk2x <= RadioClk2xLcl; + RadioClk3x <= RadioClk3xLcl; + + + +end rtl; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_pins.xdc b/fpga/usrp3/top/n3xx/dboards/rh/db_pins.xdc new file mode 100644 index 000000000..b67269cd9 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_pins.xdc @@ -0,0 +1,280 @@ +## TDC : ################################################################################ +## Bank 10, 2.5V (DB A) +######################################################################################### + +set_property PACKAGE_PIN AB15 [get_ports {UNUSED_PIN_TDCA_0}] +set_property PACKAGE_PIN AB14 [get_ports {UNUSED_PIN_TDCA_1}] +set_property PACKAGE_PIN AB16 [get_ports {UNUSED_PIN_TDCA_2}] +set_property PACKAGE_PIN AB17 [get_ports {UNUSED_PIN_TDCA_3}] +set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCA_*}] +set_property IOB TRUE [get_ports {UNUSED_PIN_TDCA_*}] + + +## TDC : ################################################################################ +## Bank 11, 2.5V (DB B) +######################################################################################### + +set_property PACKAGE_PIN W21 [get_ports {UNUSED_PIN_TDCB_0}] +set_property PACKAGE_PIN Y21 [get_ports {UNUSED_PIN_TDCB_1}] +set_property PACKAGE_PIN Y22 [get_ports {UNUSED_PIN_TDCB_2}] +set_property PACKAGE_PIN Y23 [get_ports {UNUSED_PIN_TDCB_3}] +set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCB_*}] +set_property IOB TRUE [get_ports {UNUSED_PIN_TDCB_*}] + + +## USRP IO A : ########################################################################## +# DBA +######################################################################################### + +set_property PACKAGE_PIN G1 [get_ports DBA_MODULE_PWR_ENABLE] +set_property PACKAGE_PIN E5 [get_ports DBA_RF_PWR_ENABLE] + +set_property PACKAGE_PIN AF14 [get_ports DBA_FPGA_CLK_P] +set_property PACKAGE_PIN AG14 [get_ports DBA_FPGA_CLK_N] + +set_property PACKAGE_PIN N8 [get_ports DBA_MGTCLK_P] +set_property PACKAGE_PIN N7 [get_ports DBA_MGTCLK_N] + +set_property PACKAGE_PIN AG17 [get_ports DBA_FPGA_SYSREF_P] +set_property PACKAGE_PIN AG16 [get_ports DBA_FPGA_SYSREF_N] +set_property IOB TRUE [get_ports DBA_FPGA_SYSREF_*] + + +# set_property PACKAGE_PIN AD10 [get_ports NET2CLK_P] +# set_property PACKAGE_PIN AD9 [get_ports NET2CLK_N] + +set_property PACKAGE_PIN C2 [get_ports DBA_CPLD_PL_SPI_SCLK] +set_property PACKAGE_PIN B1 [get_ports DBA_TXLO_SPI_CS_B]; # DBA_CPLD_PL_SPI_LE +set_property PACKAGE_PIN B2 [get_ports DBA_CPLD_PL_SPI_CS_B]; # DBA_CPLD_PL_SPI_ADDR[0] +set_property PACKAGE_PIN F4 [get_ports DBA_RXLO_SPI_CS_B]; # DBA_CPLD_PL_SPI_ADDR[1] +set_property PACKAGE_PIN F3 [get_ports DBA_LODIS_SPI_CS_B]; # DBA_CPLD_PL_SPI_ADDR[2] +set_property PACKAGE_PIN C1 [get_ports DBA_CPLD_PL_SPI_MISO] +set_property PACKAGE_PIN A3 [get_ports DBA_CPLD_PL_SPI_MOSI] + +set_property PACKAGE_PIN AC16 [get_ports DBA_CPLD_PS_SPI_SCLK]; # DBA_CPLD_PS_SPI_ADDR[0] +set_property PACKAGE_PIN AE15 [get_ports DBA_CPLD_PS_SPI_CS_B]; # DBA_CPLD_PS_SPI_ADDR[1] +set_property PACKAGE_PIN AE16 [get_ports DBA_PHDAC_SPI_CS_B]; # DBA_CPLD_PS_SPI_LE +set_property PACKAGE_PIN AF17 [get_ports DBA_CLKDIS_SPI_CS_B] +set_property PACKAGE_PIN AK16 [get_ports DBA_ADC_SPI_CS_B]; # DBA_CPLD_UNUSED[12] +set_property PACKAGE_PIN AJ16 [get_ports DBA_DAC_SPI_CS_B]; # DBA_CPLD_UNUSED[13] +set_property PACKAGE_PIN AC17 [get_ports DBA_CPLD_PS_SPI_MISO] +set_property PACKAGE_PIN AF18 [get_ports DBA_CPLD_PS_SPI_MOSI] + +set_property PACKAGE_PIN AH13 [get_ports DBA_CPLD_JTAG_TDI] +set_property PACKAGE_PIN AH14 [get_ports DBA_CPLD_JTAG_TDO] +set_property PACKAGE_PIN AE13 [get_ports DBA_CPLD_JTAG_TMS] +set_property PACKAGE_PIN AF13 [get_ports DBA_CPLD_JTAG_TCK] + +set_property PACKAGE_PIN E1 [get_ports DBA_CLKDIST_SYNC] + +set_property PACKAGE_PIN A2 [get_ports DBA_ATR_TX] +set_property PACKAGE_PIN E3 [get_ports DBA_ATR_RX] + +set_property PACKAGE_PIN E2 [get_ports DBA_TXRX_SW_CTRL_1] +set_property PACKAGE_PIN F5 [get_ports DBA_TXRX_SW_CTRL_2] + +set_property PACKAGE_PIN AE12 [get_ports DBA_ADC_SYNCB_P] +set_property PACKAGE_PIN AF12 [get_ports DBA_ADC_SYNCB_N] +set_property PACKAGE_PIN AD14 [get_ports DBA_DAC_SYNCB_P]; # Layout swapped, RTL is negated. +set_property PACKAGE_PIN AD13 [get_ports DBA_DAC_SYNCB_N]; # Layout swapped, RTL is negated. + +# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado +# places the transceivers in the correct places. The mixup in lanes is accounted for +# in the AD9695 and the DAC37J82 crossbar settings. +set_property PACKAGE_PIN V6 [get_ports DBA_RX_P[0]] +set_property PACKAGE_PIN V5 [get_ports DBA_RX_N[0]] +set_property PACKAGE_PIN U4 [get_ports DBA_RX_P[1]] +set_property PACKAGE_PIN U3 [get_ports DBA_RX_N[1]] +set_property PACKAGE_PIN T6 [get_ports DBA_RX_P[2]] +set_property PACKAGE_PIN T5 [get_ports DBA_RX_N[2]] +set_property PACKAGE_PIN P6 [get_ports DBA_RX_P[3]] +set_property PACKAGE_PIN P5 [get_ports DBA_RX_N[3]] + +set_property PACKAGE_PIN T2 [get_ports DBA_TX_P[0]] +set_property PACKAGE_PIN T1 [get_ports DBA_TX_N[0]] +set_property PACKAGE_PIN R4 [get_ports DBA_TX_P[1]] +set_property PACKAGE_PIN R3 [get_ports DBA_TX_N[1]] +set_property PACKAGE_PIN P2 [get_ports DBA_TX_P[2]] +set_property PACKAGE_PIN P1 [get_ports DBA_TX_N[2]] +set_property PACKAGE_PIN N4 [get_ports DBA_TX_P[3]] +set_property PACKAGE_PIN N3 [get_ports DBA_TX_N[3]] + +set_property PACKAGE_PIN AG12 [get_ports DBA_LED_RX] +set_property PACKAGE_PIN AH12 [get_ports DBA_LED_RX2] +set_property PACKAGE_PIN AJ13 [get_ports DBA_LED_TX] + +# Possibly need to be used. Connected to CPLD. +# set_property PACKAGE_PIN C4 [get_ports DBA_CPLD_UNUSED[0]] +# set_property PACKAGE_PIN C3 [get_ports DBA_CPLD_UNUSED[1]] +# set_property PACKAGE_PIN K1 [get_ports DBA_CPLD_UNUSED[2]] +# set_property PACKAGE_PIN L1 [get_ports DBA_CPLD_UNUSED[3]] +# set_property PACKAGE_PIN D1 [get_ports DBA_CPLD_UNUSED[4]] +# set_property PACKAGE_PIN AE17 [get_ports DBA_CPLD_UNUSED[5]] +# set_property PACKAGE_PIN AE18 [get_ports DBA_CPLD_UNUSED[6]] +# set_property PACKAGE_PIN AB12 [get_ports DBA_CPLD_UNUSED[7]] +# set_property PACKAGE_PIN AC12 [get_ports DBA_CPLD_UNUSED[8]] +# set_property PACKAGE_PIN AG17 [get_ports DBA_CPLD_UNUSED[9]] +# set_property PACKAGE_PIN AK12 [get_ports DBA_CPLD_UNUSED[10]] +# set_property PACKAGE_PIN AK13 [get_ports DBA_CPLD_UNUSED[11]] + +set UsrpIoAHpPinsSe [get_ports {DBA_MODULE_PWR_ENABLE \ + DBA_RF_PWR_ENABLE \ + DBA_CPLD_PL_SPI_* \ + DBA_TXLO_SPI_CS_B \ + DBA_RXLO_SPI_CS_B \ + DBA_LODIS_SPI_CS_B \ + DBA_CLKDIST_SYNC \ + DBA_TXRX_SW_CTRL_* \ + DBA_ATR_*}] +set_property IOSTANDARD LVCMOS18 $UsrpIoAHpPinsSe +set_property DRIVE 6 $UsrpIoAHpPinsSe +set_property SLEW SLOW $UsrpIoAHpPinsSe + +set UsrpIoAHrPinsSeDr4 [get_ports {DBA_LED_* \ + DBA_CPLD_JTAG_*}] +set_property IOSTANDARD LVCMOS25 $UsrpIoAHrPinsSeDr4 +set_property DRIVE 4 $UsrpIoAHrPinsSeDr4 +set_property SLEW SLOW $UsrpIoAHrPinsSeDr4 + +set UsrpIoAHrPinsSeDr8 [get_ports {DBA_CPLD_PS_SPI_* \ + DBA_PHDAC_SPI_CS_B \ + DBA_CLKDIS_SPI_CS_B \ + DBA_ADC_SPI_CS_B \ + DBA_DAC_SPI_CS_B}] +set_property IOSTANDARD LVCMOS25 $UsrpIoAHrPinsSeDr8 +set_property DRIVE 8 $UsrpIoAHrPinsSeDr8 +set_property SLEW SLOW $UsrpIoAHrPinsSeDr8 + +set UsrpIoAHrPinsDiff [get_ports {DBA_ADC_SYNCB_* \ + DBA_DAC_SYNCB_* \ + DBA_FPGA_CLK_* \ + DBA_FPGA_SYSREF_*}] +set_property IOSTANDARD LVDS_25 $UsrpIoAHrPinsDiff +set_property DIFF_TERM TRUE $UsrpIoAHrPinsDiff + + +## USRP IO B : ########################################################################## +# DBB +######################################################################################### + +set_property PACKAGE_PIN J4 [get_ports DBB_MODULE_PWR_ENABLE] +set_property PACKAGE_PIN G4 [get_ports DBB_RF_PWR_ENABLE] + +set_property PACKAGE_PIN AG21 [get_ports DBB_FPGA_CLK_P] +set_property PACKAGE_PIN AH21 [get_ports DBB_FPGA_CLK_N] + +set_property PACKAGE_PIN W8 [get_ports DBB_MGTCLK_P] +set_property PACKAGE_PIN W7 [get_ports DBB_MGTCLK_N] + +set_property PACKAGE_PIN AE22 [get_ports DBB_FPGA_SYSREF_P] +set_property PACKAGE_PIN AF22 [get_ports DBB_FPGA_SYSREF_N] +set_property IOB TRUE [get_ports DBB_FPGA_SYSREF_*] + +set_property PACKAGE_PIN K6 [get_ports DBB_CPLD_PL_SPI_SCLK] +set_property PACKAGE_PIN F2 [get_ports DBB_TXLO_SPI_CS_B]; # DBB_CPLD_PL_SPI_LE +set_property PACKAGE_PIN G2 [get_ports DBB_CPLD_PL_SPI_CS_B]; # DBB_CPLD_PL_SPI_ADDR[0] +set_property PACKAGE_PIN H4 [get_ports DBB_RXLO_SPI_CS_B]; # DBB_CPLD_PL_SPI_ADDR[1] +set_property PACKAGE_PIN H3 [get_ports DBB_LODIS_SPI_CS_B]; # DBB_CPLD_PL_SPI_ADDR[2] +set_property PACKAGE_PIN J6 [get_ports DBB_CPLD_PL_SPI_MISO] +set_property PACKAGE_PIN D5 [get_ports DBB_CPLD_PL_SPI_MOSI] + +set_property PACKAGE_PIN AG22 [get_ports DBB_CPLD_PS_SPI_SCLK] +set_property PACKAGE_PIN AD23 [get_ports DBB_CPLD_PS_SPI_CS_B]; # DBB_CPLD_PS_SPI_ADDR[0] +set_property PACKAGE_PIN AE23 [get_ports DBB_PHDAC_SPI_CS_B]; # DBB_CPLD_PS_SPI_ADDR[1] +set_property PACKAGE_PIN AB24 [get_ports DBB_CLKDIS_SPI_CS_B]; # DBB_CPLD_PS_SPI_LE +set_property PACKAGE_PIN AJ23 [get_ports DBB_ADC_SPI_CS_B]; # DBB_CPLD_UNUSED[12]] +set_property PACKAGE_PIN AJ24 [get_ports DBB_DAC_SPI_CS_B]; # DBB_CPLD_UNUSED[13]] +set_property PACKAGE_PIN AH22 [get_ports DBB_CPLD_PS_SPI_MISO] +set_property PACKAGE_PIN AA24 [get_ports DBB_CPLD_PS_SPI_MOSI] + +set_property PACKAGE_PIN AH19 [get_ports DBB_CPLD_JTAG_TDI] +set_property PACKAGE_PIN AJ19 [get_ports DBB_CPLD_JTAG_TDO] +set_property PACKAGE_PIN AB21 [get_ports DBB_CPLD_JTAG_TMS] +set_property PACKAGE_PIN AB22 [get_ports DBB_CPLD_JTAG_TCK] + +set_property PACKAGE_PIN D3 [get_ports DBB_CLKDIST_SYNC] + +set_property PACKAGE_PIN E6 [get_ports DBB_ATR_TX] +set_property PACKAGE_PIN J5 [get_ports DBB_ATR_RX] + +set_property PACKAGE_PIN K5 [get_ports DBB_TXRX_SW_CTRL_1] +set_property PACKAGE_PIN G5 [get_ports DBB_TXRX_SW_CTRL_2] + +set_property PACKAGE_PIN AF23 [get_ports DBB_ADC_SYNCB_P] +set_property PACKAGE_PIN AF24 [get_ports DBB_ADC_SYNCB_N] +set_property PACKAGE_PIN AD21 [get_ports DBB_DAC_SYNCB_P] +set_property PACKAGE_PIN AE21 [get_ports DBB_DAC_SYNCB_N] + +# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado +# places the transceivers in the correct places. The mixup in lanes is accounted for +# in the AD9695 and the DAC37J82 crossbar settings. +set_property PACKAGE_PIN AC4 [get_ports DBB_RX_P[0]] +set_property PACKAGE_PIN AC3 [get_ports DBB_RX_N[0]] +set_property PACKAGE_PIN AB6 [get_ports DBB_RX_P[1]] +set_property PACKAGE_PIN AB5 [get_ports DBB_RX_N[1]] +set_property PACKAGE_PIN Y6 [get_ports DBB_RX_P[2]] +set_property PACKAGE_PIN Y5 [get_ports DBB_RX_N[2]] +set_property PACKAGE_PIN AA4 [get_ports DBB_RX_P[3]] +set_property PACKAGE_PIN AA3 [get_ports DBB_RX_N[3]] + +set_property PACKAGE_PIN AB2 [get_ports DBB_TX_P[0]] +set_property PACKAGE_PIN AB1 [get_ports DBB_TX_N[0]] +set_property PACKAGE_PIN Y2 [get_ports DBB_TX_P[1]] +set_property PACKAGE_PIN Y1 [get_ports DBB_TX_N[1]] +set_property PACKAGE_PIN W4 [get_ports DBB_TX_P[2]] +set_property PACKAGE_PIN W3 [get_ports DBB_TX_N[2]] +set_property PACKAGE_PIN V2 [get_ports DBB_TX_P[3]] +set_property PACKAGE_PIN V1 [get_ports DBB_TX_N[3]] + +set_property PACKAGE_PIN AK17 [get_ports DBB_LED_RX] +set_property PACKAGE_PIN AK18 [get_ports DBB_LED_RX2] +set_property PACKAGE_PIN AK21 [get_ports DBB_LED_TX] + +# Possibly need to be used. Connected to CPLD. +# set_property PACKAGE_PIN G6 [get_ports DBB_CPLD_UNUSED[0]] +# set_property PACKAGE_PIN H6 [get_ports DBB_CPLD_UNUSED[1]] +# set_property PACKAGE_PIN L3 [get_ports DBB_CPLD_UNUSED[2]] +# set_property PACKAGE_PIN L2 [get_ports DBB_CPLD_UNUSED[3]] +# set_property PACKAGE_PIN D4 [get_ports DBB_CPLD_UNUSED[4]] +# set_property PACKAGE_PIN AC22 [get_ports DBB_CPLD_UNUSED[5]] +# set_property PACKAGE_PIN AC23 [get_ports DBB_CPLD_UNUSED[6]] +# set_property PACKAGE_PIN AC24 [get_ports DBB_CPLD_UNUSED[7]] +# set_property PACKAGE_PIN AD24 [get_ports DBB_CPLD_UNUSED[8]] +# set_property PACKAGE_PIN AE22 [get_ports DBB_CPLD_UNUSED[9]] +# set_property PACKAGE_PIN AK20 [get_ports DBB_CPLD_UNUSED[10]] +# set_property PACKAGE_PIN AJ20 [get_ports DBB_CPLD_UNUSED[11]] + +set UsrpIoBHpPinsSe [get_ports {DBB_MODULE_PWR_ENABLE \ + DBB_RF_PWR_ENABLE \ + DBB_CPLD_PL_SPI_* \ + DBB_TXLO_SPI_CS_B \ + DBB_RXLO_SPI_CS_B \ + DBB_LODIS_SPI_CS_B \ + DBB_CLKDIST_SYNC \ + DBB_TXRX_SW_CTRL_* \ + DBB_ATR_*}] +set_property IOSTANDARD LVCMOS18 $UsrpIoBHpPinsSe +set_property DRIVE 6 $UsrpIoBHpPinsSe +set_property SLEW SLOW $UsrpIoBHpPinsSe + +set UsrpIoBHrPinsSeDr4 [get_ports {DBB_LED_* \ + DBB_CPLD_JTAG_*}] +set_property IOSTANDARD LVCMOS25 $UsrpIoBHrPinsSeDr4 +set_property DRIVE 4 $UsrpIoBHrPinsSeDr4 +set_property SLEW SLOW $UsrpIoBHrPinsSeDr4 + +set UsrpIoBHrPinsSeDr8 [get_ports {DBB_CPLD_PS_SPI_* \ + DBB_PHDAC_SPI_CS_B \ + DBB_CLKDIS_SPI_CS_B \ + DBB_ADC_SPI_CS_B \ + DBB_DAC_SPI_CS_B}] +set_property IOSTANDARD LVCMOS25 $UsrpIoBHrPinsSeDr8 +set_property DRIVE 8 $UsrpIoBHrPinsSeDr8 +set_property SLEW SLOW $UsrpIoBHrPinsSeDr8 + +set UsrpIoBHrPinsDiff [get_ports {DBB_ADC_SYNCB_* \ + DBB_DAC_SYNCB_* \ + DBB_FPGA_CLK_* \ + DBB_FPGA_SYSREF_*}] +set_property IOSTANDARD LVDS_25 $UsrpIoBHrPinsDiff +set_property DIFF_TERM TRUE $UsrpIoBHrPinsDiff diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_timing.xdc b/fpga/usrp3/top/n3xx/dboards/rh/db_timing.xdc new file mode 100644 index 000000000..cffbd839a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_timing.xdc @@ -0,0 +1,264 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Timing analysis is performed in "usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx". +# See this spreadsheet for more details and explanations. + +#******************************************************************************* +## Asynchronous clock groups + +# MGT reference clocks are also async to everything. +set_clock_groups -asynchronous -group [get_clocks mgt_clk_dba -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks mgt_clk_dbb -include_generated_clocks] + +# fpga_clk_a and fpga_clk_b are related to one another after synchronization. +# However, we do need to declare that these clocks (both a and b) and their children +# are async to the remainder of the design. Use the wildcard at the end to grab the +# virtual clock as well as the real ones. +set_clock_groups -asynchronous -group [get_clocks {fpga_clk_a* fpga_clk_b*} -include_generated_clocks] + +# The SPI readback and write clocks cannot be active at the same time, as they +# originate from the same pin. +set_clock_groups -physically_exclusive \ + -group [get_clocks pl_spi_rb_clk_a] \ + -group [get_clocks pl_spi_clk_a] +set_clock_groups -physically_exclusive \ + -group [get_clocks pl_spi_rb_clk_b] \ + -group [get_clocks pl_spi_clk_b] + +#******************************************************************************* +## PS SPI: since these lines all come from the PS and I don't have access to the +# driving clock (or anything for that matter), I'm left with constraining the maximum +# and minimum delay on these lines, per a Xilinx AR: +# https://www.xilinx.com/support/answers/62122.html +set CPLD_SPI_OUTS [get_ports {DB*_CPLD_PS_SPI_SCLK \ + DB*_CPLD_PS_SPI_MOSI \ + DB*_CPLD_PS_SPI_CS_B \ + DB*_CLKDIS_SPI_CS_B \ + DB*_PHDAC_SPI_CS_B \ + DB*_ADC_SPI_CS_B \ + DB*_DAC_SPI_CS_B}] + +# The actual min and max path delays before applying constraints were (from report_timing): +# 3.332 ns (Min at Fast Process Corner) +# 10.596 ns (Max at Slow Process Corner) +# Therefore, we round those number to their immediate succesor respectively. +# After implementation, the tools were unable to meet timing when leaving a 11 ns max +# delay value, so it was incremented. +set MIN_OUT_DELAY 3.0 +set MAX_OUT_DELAY 12.0 + +set_max_delay $MAX_OUT_DELAY -to $CPLD_SPI_OUTS +set_min_delay $MIN_OUT_DELAY -to $CPLD_SPI_OUTS + +# report_timing -to $CPLD_SPI_OUTS -max_paths 20 -delay_type min_max -name CpldSpiOutTiming + +# The actual min and max path delays before applying constraints were (from report_timing): +# 2.733 ns (Min at Fast Process Corner) +# 6.071 ns (Max at Slow Process Corner) +# Therefore, we round those number to their immediate succesor respectively. +set MIN_IN_DELAY 2.0 +set MAX_IN_DELAY 10.0 + +set PS_SPI_INPUTS_0 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI0MI"}] +set PS_SPI_INPUTS_1 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI1MI"}] + +set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_0 +set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_0 +set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_1 +set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_1 + +# report_timing -to $PS_SPI_INPUTS_0 -max_paths 30 -delay_type min_max -nworst 30 -name Spi0InTiming +# report_timing -to $PS_SPI_INPUTS_1 -max_paths 30 -delay_type min_max -nworst 30 -name Spi1InTiming + + + +#******************************************************************************* +## PL SPI to the CPLD +# +# All of these lines are driven or received from flops in simple_spi_core. The CPLD +# calculations assume the FPGA has less than 6 ns of skew between the SCK and +# SDI/CS_n. Pretty easy constraint to write! See above for the clock definition. +# Do this for DBA and DBB independently. +set MAX_SKEW 6.0 +set SETUP_SKEW [expr {$MAX_SKEW / 2}] +set HOLD_SKEW [expr {$MAX_SKEW / 2}] +# Do not set the output delay constraint on the clock line! +set PORT_LIST_A [get_ports {DBA_CPLD_PL_SPI_CS_B \ + DBA_CPLD_PL_SPI_MOSI \ + DBA_TXLO_SPI_CS_B \ + DBA_RXLO_SPI_CS_B \ + DBA_LODIS_SPI_CS_B }] +set PORT_LIST_B [get_ports {DBB_CPLD_PL_SPI_CS_B \ + DBB_CPLD_PL_SPI_MOSI \ + DBB_TXLO_SPI_CS_B \ + DBB_RXLO_SPI_CS_B \ + DBB_LODIS_SPI_CS_B }] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A +set_output_delay -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A +set_output_delay -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B +set_output_delay -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -1 +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -1 + +# For SDO input timing (MISO), we need to look at the CPLD's constraints on turnaround +# time plus any board propagation delay. +# CPLD clk-to-q is 20 ns, then add 1.2 ns for board delay (once for clock, once for data) +# For hold time, assume zero delay (likely overconstraining here, due to board delays) +set MISO_INPUT_A [get_ports DBA_CPLD_PL_SPI_MISO] +set MISO_INPUT_B [get_ports DBB_CPLD_PL_SPI_MISO] +set_input_delay -clock [get_clocks pl_spi_rb_clk_a] -clock_fall -max 22.400 $MISO_INPUT_A +set_input_delay -clock [get_clocks pl_spi_rb_clk_a] -clock_fall -min 0.000 $MISO_INPUT_A +set_input_delay -clock [get_clocks pl_spi_rb_clk_b] -clock_fall -max 22.400 $MISO_INPUT_B +set_input_delay -clock [get_clocks pl_spi_rb_clk_b] -clock_fall -min 0.000 $MISO_INPUT_B + +# Since the input delay span is clearly more than a period of the radio_clk, we need to +# add a multicycle path here as well to define the clock divider ratio. The MISO data +# is driven on the falling edge of the SPI clock and captured on the rising edge, so we +# only have one half of a SPI clock cycle for our setup. Hold is left alone and is OK +# as-is due to the delays in the CPLD and board. +set SETUP_CYCLES [expr {$PL_SPI_RB_DIVIDE_VAL / 2}] +set HOLD_CYCLES 0 +set_multicycle_path -setup -from [get_clocks pl_spi_rb_clk_a] -through $MISO_INPUT_A \ + $SETUP_CYCLES +set_multicycle_path -hold -from [get_clocks pl_spi_rb_clk_a] -through $MISO_INPUT_A -end \ + [expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}] +set_multicycle_path -setup -from [get_clocks pl_spi_rb_clk_b] -through $MISO_INPUT_B \ + $SETUP_CYCLES +set_multicycle_path -hold -from [get_clocks pl_spi_rb_clk_b] -through $MISO_INPUT_B -end \ + [expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}] + +#******************************************************************************* +## SYSREF/SYNC JESD Timing +# +# SYNC is async, SYSREF is tightly timed. + +# The SYNC output (to ADC) for both DBs is governed by the JESD cores, which are solely +# driven by DB-A clock... but it is an asynchronous signal so we use the async_out_clk. +set_output_delay -clock [get_clocks async_out_clk] 0.000 [get_ports DB*_ADC_SYNCB_P] +set_max_delay -to [get_ports DB*_ADC_SYNCB_P] 50.000 +set_min_delay -to [get_ports DB*_ADC_SYNCB_P] 0.000 + +# The SYNC input (from DAC) for both DBs is received by the DB-A clock inside the JESD +# cores... but again, it is asynchronous and therefore uses the async_in_clk. +set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports DB*_DAC_SYNCB_P] +set_max_delay -from [get_ports DB*_DAC_SYNCB_P] 50.000 +set_min_delay -from [get_ports DB*_DAC_SYNCB_P] 0.000 + +# SYSREF is driven by the LMK directly to the FPGA. Timing analysis was performed once +# for the worst-case numbers across both DBs to produce one set of numbers for both DBs. +# Since we easily meet setup and hold in Vivado, then this is an acceptable approach. +# SYSREF is captured by the local clock from each DB, so we have two sets of constraints. +set_input_delay -clock fpga_clk_a_v -min -0.479 [get_ports DBA_FPGA_SYSREF_*] +set_input_delay -clock fpga_clk_a_v -max 0.661 [get_ports DBA_FPGA_SYSREF_*] + +set_input_delay -clock fpga_clk_b_v -min -0.479 [get_ports DBB_FPGA_SYSREF_*] +set_input_delay -clock fpga_clk_b_v -max 0.661 [get_ports DBB_FPGA_SYSREF_*] + + +#******************************************************************************* +## PPS Timing + +# Due to the N3xx synchronization and clocking structure, the PPS output is driven from +# the Sample Clock domain instead of the input Reference Clock. Constrain the output as +# tightly as possible to accurately mimic the internal Sample Clock timing. +set SETUP_SKEW 2.0 +set HOLD_SKEW -0.5 +set_output_delay -clock [get_clocks fpga_clk_a_v] -max -$SETUP_SKEW [get_ports REF_1PPS_OUT] +set_output_delay -clock [get_clocks fpga_clk_a_v] -min $HOLD_SKEW [get_ports REF_1PPS_OUT] +set_multicycle_path -setup -to [get_ports REF_1PPS_OUT] -start 0 +set_multicycle_path -hold -to [get_ports REF_1PPS_OUT] -1 + +#******************************************************************************* +### Async I/Os +set DB_ASYNC_OUTPUTS [get_ports { + DB*_MODULE_PWR_ENABLE + DB*_RF_PWR_ENABLE + DB*_CLKDIST_SYNC + DB*_ATR_TX + DB*_ATR_RX + DB*_TXRX_SW_CTRL_1 + DB*_TXRX_SW_CTRL_2 + DB*_LED_RX + DB*_LED_RX2 + DB*_LED_TX + QSFP_I2C_* +}] +set_output_delay -clock [get_clocks async_out_clk] 0.000 $DB_ASYNC_OUTPUTS +set_max_delay -to $DB_ASYNC_OUTPUTS 50.000 +set_min_delay -to $DB_ASYNC_OUTPUTS 0.000 + +set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports QSFP_I2C_*] +set_max_delay -from [get_ports QSFP_I2C_*] 50.000 +set_min_delay -from [get_ports QSFP_I2C_*] 0.000 + +#******************************************************************************* +## JTAG + +## MAX 10 JTAG TDI setup: 2 ns +## MAX 10 JTAG TMS setup: 3 ns +## MAX 10 JTAG hold: 10 ns +## MAX 10 JTAG clk-to-q: 18 ns +## Board delay: < 1.5 ns +## +## Setup time = Board delay + TMS setup = 3 ns + 1.5 ns = 4.5 ns +## Hold time = Board delay + TMS hold = 1.5 ns + 10 ns = 11.5 ns +## Overconstrain output delay and keep skew to +/- 8 ns +## +## Input delay = 2x Board delay + clk-to-q = 3 ns + 18 ns = 21 ns + +# Constrain outputs for skew, with same latch/launch edge: +set_output_delay -clock [get_clocks dba_jtag_tck] -max -4.0 \ + [get_ports {DBA_CPLD_JTAG_TDI DBA_CPLD_JTAG_TMS}] +set_output_delay -add_delay -clock_fall -clock [get_clocks dba_jtag_tck] -max -4.0 \ + [get_ports {DBA_CPLD_JTAG_TDI DBA_CPLD_JTAG_TMS}] +set_output_delay -clock [get_clocks dba_jtag_tck] -min 4.0 \ + [get_ports {DBA_CPLD_JTAG_TDI DBA_CPLD_JTAG_TMS}] +set_output_delay -add_delay -clock_fall -clock [get_clocks dba_jtag_tck] -min 4.0 \ + [get_ports {DBA_CPLD_JTAG_TDI DBA_CPLD_JTAG_TMS}] +set_output_delay -clock [get_clocks dbb_jtag_tck] -max -4.0 \ + [get_ports {DBB_CPLD_JTAG_TDI DBB_CPLD_JTAG_TMS}] +set_output_delay -add_delay -clock_fall -clock [get_clocks dbb_jtag_tck] -max -4.0 \ + [get_ports {DBB_CPLD_JTAG_TDI DBB_CPLD_JTAG_TMS}] +set_output_delay -clock [get_clocks dbb_jtag_tck] -min 4.0 \ + [get_ports {DBB_CPLD_JTAG_TDI DBB_CPLD_JTAG_TMS}] +set_output_delay -add_delay -clock_fall -clock [get_clocks dbb_jtag_tck] -min 4.0 \ + [get_ports {DBB_CPLD_JTAG_TDI DBB_CPLD_JTAG_TMS}] +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -from [get_clocks clk40] -to [get_clocks dba_jtag_tck] -start 0 +set_multicycle_path -hold -from [get_clocks clk40] -to [get_clocks dba_jtag_tck] -1 +set_multicycle_path -setup -from [get_clocks clk40] -to [get_clocks dbb_jtag_tck] -start 0 +set_multicycle_path -hold -from [get_clocks clk40] -to [get_clocks dbb_jtag_tck] -1 + +set_input_delay -clock [get_clocks dba_jtag_tck] -clock_fall -max 21 \ + [get_ports DBA_CPLD_JTAG_TDO] +set_input_delay -clock [get_clocks dba_jtag_tck] -clock_fall -min 0 \ + [get_ports DBA_CPLD_JTAG_TDO] +set_input_delay -clock [get_clocks dbb_jtag_tck] -clock_fall -max 21 \ + [get_ports DBB_CPLD_JTAG_TDO] +set_input_delay -clock [get_clocks dbb_jtag_tck] -clock_fall -min 0 \ + [get_ports DBB_CPLD_JTAG_TDO] +# Inputs have setup checks relative to half a period of TCK (launch on fall, +# latch on rise). Actual latch clock is faster, so push back setup and hold +# checks to match. +set_multicycle_path -setup -from [get_clocks dba_jtag_tck] \ + -through [get_ports DBA_CPLD_JTAG_TDO] \ + [expr {$DB_JTAG_DIVISOR / 2}] +set_multicycle_path -end -hold -from [get_clocks dba_jtag_tck] \ + -through [get_ports DBA_CPLD_JTAG_TDO] \ + [expr {$DB_JTAG_DIVISOR - 1}] +set_multicycle_path -setup -from [get_clocks dbb_jtag_tck] \ + -through [get_ports DBB_CPLD_JTAG_TDO] \ + [expr {$DB_JTAG_DIVISOR / 2}] +set_multicycle_path -end -hold -from [get_clocks dbb_jtag_tck] \ + -through [get_ports DBB_CPLD_JTAG_TDO] \ + [expr {$DB_JTAG_DIVISOR - 1}] diff --git a/fpga/usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx b/fpga/usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx new file mode 100755 index 000000000..7782ee33c Binary files /dev/null and b/fpga/usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx differ diff --git a/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v b/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v new file mode 100644 index 000000000..e697f00d4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v @@ -0,0 +1,3855 @@ +/////////////////////////////////////////////////////////////////// +/// +// Copyright 2018-2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx +// Description: +// Top Level for N320, N321 devices +// +////////////////////////////////////////////////////////////////////// + +module n3xx ( + inout [11:0] FPGA_GPIO, + + input FPGA_REFCLK_P, + input FPGA_REFCLK_N, + input REF_1PPS_IN, + input NETCLK_REF_P, + input NETCLK_REF_N, + //input REF_1PPS_IN_MGMT, + output REF_1PPS_OUT, + + //TDC + inout UNUSED_PIN_TDCA_0, + inout UNUSED_PIN_TDCA_1, + inout UNUSED_PIN_TDCA_2, + inout UNUSED_PIN_TDCA_3, + inout UNUSED_PIN_TDCB_0, + inout UNUSED_PIN_TDCB_1, + inout UNUSED_PIN_TDCB_2, + inout UNUSED_PIN_TDCB_3, + +`ifdef NPIO_LANES + input NPIO_RX0_P, + input NPIO_RX0_N, + output NPIO_TX0_P, + output NPIO_TX0_N, + input NPIO_RX1_P, + input NPIO_RX1_N, + output NPIO_TX1_P, + output NPIO_TX1_N, +`endif +`ifdef QSFP_LANES + input [`QSFP_LANES-1:0] QSFP_RX_P, + input [`QSFP_LANES-1:0] QSFP_RX_N, + output [`QSFP_LANES-1:0] QSFP_TX_P, + output [`QSFP_LANES-1:0] QSFP_TX_N, + output QSFP_RESET_B, + output QSFP_LED, + output QSFP_MODSEL_B, + output QSFP_LPMODE, + input QSFP_PRESENT_B, + input QSFP_INT_B, + inout QSFP_I2C_SCL, + inout QSFP_I2C_SDA, +`endif + //TODO: Uncomment when connected here + //input NPIO_0_RXSYNC_0_P, NPIO_0_RXSYNC_1_P, + //input NPIO_0_RXSYNC_0_N, NPIO_0_RXSYNC_1_N, + //output NPIO_0_TXSYNC_0_P, NPIO_0_TXSYNC_1_P, + //output NPIO_0_TXSYNC_0_N, NPIO_0_TXSYNC_1_N, + //input NPIO_1_RXSYNC_0_P, NPIO_1_RXSYNC_1_P, + //input NPIO_1_RXSYNC_0_N, NPIO_1_RXSYNC_1_N, + //output NPIO_1_TXSYNC_0_P, NPIO_1_TXSYNC_1_P, + //output NPIO_1_TXSYNC_0_N, NPIO_1_TXSYNC_1_N, + //input NPIO_2_RXSYNC_0_P, NPIO_2_RXSYNC_1_P, + //input NPIO_2_RXSYNC_0_N, NPIO_2_RXSYNC_1_N, + //output NPIO_2_TXSYNC_0_P, NPIO_2_TXSYNC_1_P, + //output NPIO_2_TXSYNC_0_N, NPIO_2_TXSYNC_1_N, + + //GPS + input GPS_1PPS, + //input GPS_1PPS_RAW, + + //Misc + input ENET0_CLK125, + //inout ENET0_PTP, + //output ENET0_PTP_DIR, + //inout ATSHA204_SDA, + input FPGA_PL_RESETN, // TODO: Add to reset logic + // output reg [1:0] FPGA_TEST, + //input PWR_CLK_FPGA, // TODO: check direction + input FPGA_PUDC_B, + + //White Rabbit + input WB_20MHZ_P, + input WB_20MHZ_N, + output WB_DAC_DIN, + output WB_DAC_NCLR, + output WB_DAC_NLDAC, + output WB_DAC_NSYNC, + output WB_DAC_SCLK, + + //LEDS + output PANEL_LED_GPS, + output PANEL_LED_LINK, + output PANEL_LED_PPS, + output PANEL_LED_REF, + + // ARM Connections (PS) + inout [53:0] MIO, + inout PS_SRSTB, + inout PS_CLK, + inout PS_PORB, + inout DDR_Clk, + inout DDR_Clk_n, + inout DDR_CKE, + inout DDR_CS_n, + inout DDR_RAS_n, + inout DDR_CAS_n, + inout DDR_WEB, + inout [2:0] DDR_BankAddr, + inout [14:0] DDR_Addr, + inout DDR_ODT, + inout DDR_DRSTB, + inout [31:0] DDR_DQ, + inout [3:0] DDR_DM, + inout [3:0] DDR_DQS, + inout [3:0] DDR_DQS_n, + inout DDR_VRP, + inout DDR_VRN, + + + /////////////////////////////////// + // + // High Speed SPF+ signals and clocking + // + /////////////////////////////////// + + // These clock inputs must always be enabled with a buffer regardless of the build + // target to avoid damage to the FPGA. + input NETCLK_P, + input NETCLK_N, + input MGT156MHZ_CLK1_P, + input MGT156MHZ_CLK1_N, + + input SFP_0_RX_P, input SFP_0_RX_N, + output SFP_0_TX_P, output SFP_0_TX_N, + input SFP_1_RX_P, input SFP_1_RX_N, + output SFP_1_TX_P, output SFP_1_TX_N, + + + /////////////////////////////////// + // + // DRAM Interface + // + /////////////////////////////////// + inout [31:0] ddr3_dq, // Data pins. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_n, // Data Strobes. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_p, + // + output [15:0] ddr3_addr, // Address + output [2:0] ddr3_ba, // Bank Address + output ddr3_ras_n, // Row Address Strobe. + output ddr3_cas_n, // Column address select + output ddr3_we_n, // Write Enable + output ddr3_reset_n, // SDRAM reset pin. + output [0:0] ddr3_ck_p, // Differential clock + output [0:0] ddr3_ck_n, + output [0:0] ddr3_cke, // Clock Enable + output [0:0] ddr3_cs_n, // Chip Select + output [3:0] ddr3_dm, // Data Mask [3] = UDM.U26, [2] = LDM.U26, ... + output [0:0] ddr3_odt, // On-Die termination enable. + // + input sys_clk_p, // Differential + input sys_clk_n, // 100MHz clock source to generate DDR3 clocking. + + + /////////////////////////////////// + // + // Supporting I/O for SPF+ interfaces + // (non high speed stuff) + // + /////////////////////////////////// + + //SFP+ 0, Slow Speed, Bank 13 3.3V + input SFP_0_I2C_NPRESENT, + output SFP_0_LED_A, + output SFP_0_LED_B, + input SFP_0_LOS, + output SFP_0_RS0, + output SFP_0_RS1, + output SFP_0_TXDISABLE, + input SFP_0_TXFAULT, + + //SFP+ 1, Slow Speed, Bank 13 3.3V + //input SFP_1_I2C_NPRESENT, + output SFP_1_LED_A, + output SFP_1_LED_B, + input SFP_1_LOS, + output SFP_1_RS0, + output SFP_1_RS1, + output SFP_1_TXDISABLE, + input SFP_1_TXFAULT, + + //USRP IO A + output DBA_MODULE_PWR_ENABLE, + output DBA_RF_PWR_ENABLE, + + output DBA_CPLD_PS_SPI_SCLK, + output DBA_CLKDIS_SPI_CS_B, + output DBA_CPLD_PS_SPI_CS_B, + output DBA_PHDAC_SPI_CS_B, + output DBA_CPLD_PS_SPI_MOSI, + input DBA_CPLD_PS_SPI_MISO, + + output DBA_ATR_RX, + output DBA_ATR_TX, + output DBA_TXRX_SW_CTRL_1, + output DBA_TXRX_SW_CTRL_2, + + output DBA_CPLD_PL_SPI_SCLK, + output DBA_ADC_SPI_CS_B, + output DBA_DAC_SPI_CS_B, + output DBA_TXLO_SPI_CS_B, + output DBA_RXLO_SPI_CS_B, + output DBA_LODIS_SPI_CS_B, + output DBA_CPLD_PL_SPI_CS_B, + output DBA_CPLD_PL_SPI_MOSI, + input DBA_CPLD_PL_SPI_MISO, + + output DBA_ADC_SYNCB_P, + output DBA_ADC_SYNCB_N, + input DBA_DAC_SYNCB_P, + input DBA_DAC_SYNCB_N, + + output DBA_CLKDIST_SYNC, + + inout DBA_CPLD_JTAG_TCK, + inout DBA_CPLD_JTAG_TMS, + inout DBA_CPLD_JTAG_TDI, + input DBA_CPLD_JTAG_TDO, + + input DBA_FPGA_CLK_P, + input DBA_FPGA_CLK_N, + + input DBA_FPGA_SYSREF_P, + input DBA_FPGA_SYSREF_N, + + input DBA_MGTCLK_P, + input DBA_MGTCLK_N, + + input [3:0] DBA_RX_P, + input [3:0] DBA_RX_N, + output [3:0] DBA_TX_P, + output [3:0] DBA_TX_N, + + output DBA_LED_RX, + output DBA_LED_RX2, + output DBA_LED_TX, + + //USRP IO B + output DBB_MODULE_PWR_ENABLE, + output DBB_RF_PWR_ENABLE, + + output DBB_CPLD_PS_SPI_SCLK, + output DBB_CLKDIS_SPI_CS_B, + output DBB_CPLD_PS_SPI_CS_B, + output DBB_PHDAC_SPI_CS_B, + output DBB_CPLD_PS_SPI_MOSI, + input DBB_CPLD_PS_SPI_MISO, + + output DBB_ATR_RX, + output DBB_ATR_TX, + output DBB_TXRX_SW_CTRL_1, + output DBB_TXRX_SW_CTRL_2, + + output DBB_CPLD_PL_SPI_SCLK, + output DBB_ADC_SPI_CS_B, + output DBB_DAC_SPI_CS_B, + output DBB_TXLO_SPI_CS_B, + output DBB_RXLO_SPI_CS_B, + output DBB_LODIS_SPI_CS_B, + output DBB_CPLD_PL_SPI_CS_B, + output DBB_CPLD_PL_SPI_MOSI, + input DBB_CPLD_PL_SPI_MISO, + + output DBB_ADC_SYNCB_P, + output DBB_ADC_SYNCB_N, + input DBB_DAC_SYNCB_P, + input DBB_DAC_SYNCB_N, + + output DBB_CLKDIST_SYNC, + + inout DBB_CPLD_JTAG_TCK, + inout DBB_CPLD_JTAG_TMS, + inout DBB_CPLD_JTAG_TDI, + input DBB_CPLD_JTAG_TDO, + + input DBB_FPGA_CLK_P, + input DBB_FPGA_CLK_N, + + input DBB_FPGA_SYSREF_P, + input DBB_FPGA_SYSREF_N, + + input DBB_MGTCLK_P, + input DBB_MGTCLK_N, + + input [3:0] DBB_RX_P, + input [3:0] DBB_RX_N, + output [3:0] DBB_TX_P, + output [3:0] DBB_TX_N, + + output DBB_LED_RX, + output DBB_LED_RX2, + output DBB_LED_TX +); + + localparam N_AXILITE_SLAVES = 4; + localparam REG_AWIDTH = 14; // log2(0x4000) + localparam QSFP_REG_AWIDTH = 17; // log2(0x20000) + localparam REG_DWIDTH = 32; + localparam FP_GPIO_OFFSET = 32; + localparam FP_GPIO_WIDTH = 12; + + localparam NUM_RADIOS = 2; + localparam NUM_CHANNELS_PER_RADIO = 1; + localparam NUM_DBOARDS = 2; + localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO; + localparam CHANNEL_WIDTH = 32; + + + // Internal connections to PS + // HP0 -- High Performance port 0, FPGA is the master + wire [5:0] S_AXI_HP0_AWID; + wire [31:0] S_AXI_HP0_AWADDR; + wire [2:0] S_AXI_HP0_AWPROT; + wire S_AXI_HP0_AWVALID; + wire S_AXI_HP0_AWREADY; + wire [63:0] S_AXI_HP0_WDATA; + wire [7:0] S_AXI_HP0_WSTRB; + wire S_AXI_HP0_WVALID; + wire S_AXI_HP0_WREADY; + wire [1:0] S_AXI_HP0_BRESP; + wire S_AXI_HP0_BVALID; + wire S_AXI_HP0_BREADY; + wire [5:0] S_AXI_HP0_ARID; + wire [31:0] S_AXI_HP0_ARADDR; + wire [2:0] S_AXI_HP0_ARPROT; + wire S_AXI_HP0_ARVALID; + wire S_AXI_HP0_ARREADY; + wire [63:0] S_AXI_HP0_RDATA; + wire [1:0] S_AXI_HP0_RRESP; + wire S_AXI_HP0_RVALID; + wire S_AXI_HP0_RREADY; + wire S_AXI_HP0_RLAST; + wire [3:0] S_AXI_HP0_ARCACHE; + wire [7:0] S_AXI_HP0_AWLEN; + wire [2:0] S_AXI_HP0_AWSIZE; + wire [1:0] S_AXI_HP0_AWBURST; + wire [3:0] S_AXI_HP0_AWCACHE; + wire S_AXI_HP0_WLAST; + wire [7:0] S_AXI_HP0_ARLEN; + wire [1:0] S_AXI_HP0_ARBURST; + wire [2:0] S_AXI_HP0_ARSIZE; + + // GP0 -- General Purpose port 0, FPGA is the master + wire [4:0] S_AXI_GP0_AWID; + wire [31:0] S_AXI_GP0_AWADDR; + wire [2:0] S_AXI_GP0_AWPROT; + wire S_AXI_GP0_AWVALID; + wire S_AXI_GP0_AWREADY; + wire [31:0] S_AXI_GP0_WDATA; + wire [3:0] S_AXI_GP0_WSTRB; + wire S_AXI_GP0_WVALID; + wire S_AXI_GP0_WREADY; + wire [1:0] S_AXI_GP0_BRESP; + wire S_AXI_GP0_BVALID; + wire S_AXI_GP0_BREADY; + wire [4:0] S_AXI_GP0_ARID; + wire [31:0] S_AXI_GP0_ARADDR; + wire [2:0] S_AXI_GP0_ARPROT; + wire S_AXI_GP0_ARVALID; + wire S_AXI_GP0_ARREADY; + wire [31:0] S_AXI_GP0_RDATA; + wire [1:0] S_AXI_GP0_RRESP; + wire S_AXI_GP0_RVALID; + wire S_AXI_GP0_RREADY; + wire S_AXI_GP0_RLAST; + wire [3:0] S_AXI_GP0_ARCACHE; + wire [7:0] S_AXI_GP0_AWLEN; + wire [2:0] S_AXI_GP0_AWSIZE; + wire [1:0] S_AXI_GP0_AWBURST; + wire [3:0] S_AXI_GP0_AWCACHE; + wire S_AXI_GP0_WLAST; + wire [7:0] S_AXI_GP0_ARLEN; + wire [1:0] S_AXI_GP0_ARBURST; + wire [2:0] S_AXI_GP0_ARSIZE; + + // HP1 -- High Performance port 1, FPGA is the master + wire [5:0] S_AXI_HP1_AWID; + wire [31:0] S_AXI_HP1_AWADDR; + wire [2:0] S_AXI_HP1_AWPROT; + wire S_AXI_HP1_AWVALID; + wire S_AXI_HP1_AWREADY; + wire [63:0] S_AXI_HP1_WDATA; + wire [7:0] S_AXI_HP1_WSTRB; + wire S_AXI_HP1_WVALID; + wire S_AXI_HP1_WREADY; + wire [1:0] S_AXI_HP1_BRESP; + wire S_AXI_HP1_BVALID; + wire S_AXI_HP1_BREADY; + wire [5:0] S_AXI_HP1_ARID; + wire [31:0] S_AXI_HP1_ARADDR; + wire [2:0] S_AXI_HP1_ARPROT; + wire S_AXI_HP1_ARVALID; + wire S_AXI_HP1_ARREADY; + wire [63:0] S_AXI_HP1_RDATA; + wire [1:0] S_AXI_HP1_RRESP; + wire S_AXI_HP1_RVALID; + wire S_AXI_HP1_RREADY; + wire S_AXI_HP1_RLAST; + wire [3:0] S_AXI_HP1_ARCACHE; + wire [7:0] S_AXI_HP1_AWLEN; + wire [2:0] S_AXI_HP1_AWSIZE; + wire [1:0] S_AXI_HP1_AWBURST; + wire [3:0] S_AXI_HP1_AWCACHE; + wire S_AXI_HP1_WLAST; + wire [7:0] S_AXI_HP1_ARLEN; + wire [1:0] S_AXI_HP1_ARBURST; + wire [2:0] S_AXI_HP1_ARSIZE; + + // GP1 -- General Purpose port 1, FPGA is the master + wire [4:0] S_AXI_GP1_AWID; + wire [31:0] S_AXI_GP1_AWADDR; + wire [2:0] S_AXI_GP1_AWPROT; + wire S_AXI_GP1_AWVALID; + wire S_AXI_GP1_AWREADY; + wire [31:0] S_AXI_GP1_WDATA; + wire [3:0] S_AXI_GP1_WSTRB; + wire S_AXI_GP1_WVALID; + wire S_AXI_GP1_WREADY; + wire [1:0] S_AXI_GP1_BRESP; + wire S_AXI_GP1_BVALID; + wire S_AXI_GP1_BREADY; + wire [4:0] S_AXI_GP1_ARID; + wire [31:0] S_AXI_GP1_ARADDR; + wire [2:0] S_AXI_GP1_ARPROT; + wire S_AXI_GP1_ARVALID; + wire S_AXI_GP1_ARREADY; + wire [31:0] S_AXI_GP1_RDATA; + wire [1:0] S_AXI_GP1_RRESP; + wire S_AXI_GP1_RVALID; + wire S_AXI_GP1_RREADY; + wire S_AXI_GP1_RLAST; + wire [3:0] S_AXI_GP1_ARCACHE; + wire [7:0] S_AXI_GP1_AWLEN; + wire [2:0] S_AXI_GP1_AWSIZE; + wire [1:0] S_AXI_GP1_AWBURST; + wire [3:0] S_AXI_GP1_AWCACHE; + wire S_AXI_GP1_WLAST; + wire [7:0] S_AXI_GP1_ARLEN; + wire [1:0] S_AXI_GP1_ARBURST; + wire [2:0] S_AXI_GP1_ARSIZE; + + // GP0 -- General Purpose port 0, FPGA is the slave + wire M_AXI_GP0_ARVALID; + wire M_AXI_GP0_AWVALID; + wire M_AXI_GP0_BREADY; + wire M_AXI_GP0_RREADY; + wire M_AXI_GP0_WVALID; + wire [11:0] M_AXI_GP0_ARID; + wire [11:0] M_AXI_GP0_AWID; + wire [11:0] M_AXI_GP0_WID; + wire [31:0] M_AXI_GP0_ARADDR; + wire [31:0] M_AXI_GP0_AWADDR; + wire [31:0] M_AXI_GP0_WDATA; + wire [3:0] M_AXI_GP0_WSTRB; + wire M_AXI_GP0_ARREADY; + wire M_AXI_GP0_AWREADY; + wire M_AXI_GP0_BVALID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RVALID; + wire M_AXI_GP0_WREADY; + wire [1:0] M_AXI_GP0_BRESP; + wire [1:0] M_AXI_GP0_RRESP; + wire [31:0] M_AXI_GP0_RDATA; + + wire M_AXI_ETH_DMA0_ARVALID; + wire M_AXI_ETH_DMA0_AWVALID; + wire M_AXI_ETH_DMA0_BREADY; + wire M_AXI_ETH_DMA0_RREADY; + wire M_AXI_ETH_DMA0_WVALID; + wire [11:0] M_AXI_ETH_DMA0_ARID; + wire [11:0] M_AXI_ETH_DMA0_AWID; + wire [11:0] M_AXI_ETH_DMA0_WID; + wire [31:0] M_AXI_ETH_DMA0_ARADDR; + wire [31:0] M_AXI_ETH_DMA0_AWADDR; + wire [31:0] M_AXI_ETH_DMA0_WDATA; + wire [3:0] M_AXI_ETH_DMA0_WSTRB; + wire M_AXI_ETH_DMA0_ARREADY; + wire M_AXI_ETH_DMA0_AWREADY; + wire M_AXI_ETH_DMA0_BVALID; + wire M_AXI_ETH_DMA0_RLAST; + wire M_AXI_ETH_DMA0_RVALID; + wire M_AXI_ETH_DMA0_WREADY; + wire [1:0] M_AXI_ETH_DMA0_BRESP; + wire [1:0] M_AXI_ETH_DMA0_RRESP; + wire [31:0] M_AXI_ETH_DMA0_RDATA; + + wire M_AXI_NET0_ARVALID; + wire M_AXI_NET0_AWVALID; + wire M_AXI_NET0_BREADY; + wire M_AXI_NET0_RREADY; + wire M_AXI_NET0_WVALID; + wire [11:0] M_AXI_NET0_ARID; + wire [11:0] M_AXI_NET0_AWID; + wire [11:0] M_AXI_NET0_WID; + wire [31:0] M_AXI_NET0_ARADDR; + wire [31:0] M_AXI_NET0_AWADDR; + wire [31:0] M_AXI_NET0_WDATA; + wire [3:0] M_AXI_NET0_WSTRB; + wire M_AXI_NET0_ARREADY; + wire M_AXI_NET0_AWREADY; + wire M_AXI_NET0_BVALID; + wire M_AXI_NET0_RLAST; + wire M_AXI_NET0_RVALID; + wire M_AXI_NET0_WREADY; + wire [1:0] M_AXI_NET0_BRESP; + wire [1:0] M_AXI_NET0_RRESP; + wire [31:0] M_AXI_NET0_RDATA; + + wire M_AXI_ETH_DMA1_ARVALID; + wire M_AXI_ETH_DMA1_AWVALID; + wire M_AXI_ETH_DMA1_BREADY; + wire M_AXI_ETH_DMA1_RREADY; + wire M_AXI_ETH_DMA1_WVALID; + wire [11:0] M_AXI_ETH_DMA1_ARID; + wire [11:0] M_AXI_ETH_DMA1_AWID; + wire [11:0] M_AXI_ETH_DMA1_WID; + wire [31:0] M_AXI_ETH_DMA1_ARADDR; + wire [31:0] M_AXI_ETH_DMA1_AWADDR; + wire [31:0] M_AXI_ETH_DMA1_WDATA; + wire [3:0] M_AXI_ETH_DMA1_WSTRB; + wire M_AXI_ETH_DMA1_ARREADY; + wire M_AXI_ETH_DMA1_AWREADY; + wire M_AXI_ETH_DMA1_BVALID; + wire M_AXI_ETH_DMA1_RLAST; + wire M_AXI_ETH_DMA1_RVALID; + wire M_AXI_ETH_DMA1_WREADY; + wire [1:0] M_AXI_ETH_DMA1_BRESP; + wire [1:0] M_AXI_ETH_DMA1_RRESP; + wire [31:0] M_AXI_ETH_DMA1_RDATA; + + wire M_AXI_NET1_ARVALID; + wire M_AXI_NET1_AWVALID; + wire M_AXI_NET1_BREADY; + wire M_AXI_NET1_RREADY; + wire M_AXI_NET1_WVALID; + wire [11:0] M_AXI_NET1_ARID; + wire [11:0] M_AXI_NET1_AWID; + wire [11:0] M_AXI_NET1_WID; + wire [31:0] M_AXI_NET1_ARADDR; + wire [31:0] M_AXI_NET1_AWADDR; + wire [31:0] M_AXI_NET1_WDATA; + wire [3:0] M_AXI_NET1_WSTRB; + wire M_AXI_NET1_ARREADY; + wire M_AXI_NET1_AWREADY; + wire M_AXI_NET1_BVALID; + wire M_AXI_NET1_RLAST; + wire M_AXI_NET1_RVALID; + wire M_AXI_NET1_WREADY; + wire [1:0] M_AXI_NET1_BRESP; + wire [1:0] M_AXI_NET1_RRESP; + wire [31:0] M_AXI_NET1_RDATA; + + wire M_AXI_NET2_ARVALID; + wire M_AXI_NET2_AWVALID; + wire M_AXI_NET2_BREADY; + wire M_AXI_NET2_RREADY; + wire M_AXI_NET2_WVALID; + wire [11:0] M_AXI_NET2_ARID; + wire [11:0] M_AXI_NET2_AWID; + wire [11:0] M_AXI_NET2_WID; + wire [31:0] M_AXI_NET2_ARADDR; + wire [31:0] M_AXI_NET2_AWADDR; + wire [31:0] M_AXI_NET2_WDATA; + wire [3:0] M_AXI_NET2_WSTRB; + wire M_AXI_NET2_ARREADY; + wire M_AXI_NET2_AWREADY; + wire M_AXI_NET2_BVALID; + wire M_AXI_NET2_RLAST; + wire M_AXI_NET2_RVALID; + wire M_AXI_NET2_WREADY; + wire [1:0] M_AXI_NET2_BRESP; + wire [1:0] M_AXI_NET2_RRESP; + wire [31:0] M_AXI_NET2_RDATA; + + wire M_AXI_XBAR_ARVALID; + wire M_AXI_XBAR_AWVALID; + wire M_AXI_XBAR_BREADY; + wire M_AXI_XBAR_RREADY; + wire M_AXI_XBAR_WVALID; + wire [11:0] M_AXI_XBAR_ARID; + wire [11:0] M_AXI_XBAR_AWID; + wire [11:0] M_AXI_XBAR_WID; + wire [31:0] M_AXI_XBAR_ARADDR; + wire [31:0] M_AXI_XBAR_AWADDR; + wire [31:0] M_AXI_XBAR_WDATA; + wire [3:0] M_AXI_XBAR_WSTRB; + wire M_AXI_XBAR_ARREADY; + wire M_AXI_XBAR_AWREADY; + wire M_AXI_XBAR_BVALID; + wire M_AXI_XBAR_RLAST; + wire M_AXI_XBAR_RVALID; + wire M_AXI_XBAR_WREADY; + wire [1:0] M_AXI_XBAR_BRESP; + wire [1:0] M_AXI_XBAR_RRESP; + wire [31:0] M_AXI_XBAR_RDATA; + + wire M_AXI_JESD0_ARVALID; + wire M_AXI_JESD0_AWVALID; + wire M_AXI_JESD0_BREADY; + wire M_AXI_JESD0_RREADY; + wire M_AXI_JESD0_WVALID; + wire [11:0] M_AXI_JESD0_ARID; + wire [11:0] M_AXI_JESD0_AWID; + wire [11:0] M_AXI_JESD0_WID; + wire [31:0] M_AXI_JESD0_ARADDR; + wire [31:0] M_AXI_JESD0_AWADDR; + wire [31:0] M_AXI_JESD0_WDATA; + wire [3:0] M_AXI_JESD0_WSTRB; + wire M_AXI_JESD0_ARREADY; + wire M_AXI_JESD0_AWREADY; + wire M_AXI_JESD0_BVALID; + wire M_AXI_JESD0_RLAST; + wire M_AXI_JESD0_RVALID; + wire M_AXI_JESD0_WREADY; + wire [1:0] M_AXI_JESD0_BRESP; + wire [1:0] M_AXI_JESD0_RRESP; + wire [31:0] M_AXI_JESD0_RDATA; + + wire M_AXI_JESD1_ARVALID; + wire M_AXI_JESD1_AWVALID; + wire M_AXI_JESD1_BREADY; + wire M_AXI_JESD1_RREADY; + wire M_AXI_JESD1_WVALID; + wire [11:0] M_AXI_JESD1_ARID; + wire [11:0] M_AXI_JESD1_AWID; + wire [11:0] M_AXI_JESD1_WID; + wire [31:0] M_AXI_JESD1_ARADDR; + wire [31:0] M_AXI_JESD1_AWADDR; + wire [31:0] M_AXI_JESD1_WDATA; + wire [3:0] M_AXI_JESD1_WSTRB; + wire M_AXI_JESD1_ARREADY; + wire M_AXI_JESD1_AWREADY; + wire M_AXI_JESD1_BVALID; + wire M_AXI_JESD1_RLAST; + wire M_AXI_JESD1_RVALID; + wire M_AXI_JESD1_WREADY; + wire [1:0] M_AXI_JESD1_BRESP; + wire [1:0] M_AXI_JESD1_RRESP; + wire [31:0] M_AXI_JESD1_RDATA; + + // White Rabbit + wire wr_uart_txd; + wire wr_uart_rxd; + wire pps_wr_refclk; + wire wr_ref_clk; + + // AXI bus from PS to WR Core + wire m_axi_wr_clk; + wire [31:0] m_axi_wr_araddr; + wire [0:0] m_axi_wr_arready; + wire [0:0] m_axi_wr_arvalid; + wire [31:0] m_axi_wr_awaddr; + wire [0:0] m_axi_wr_awready; + wire [0:0] m_axi_wr_awvalid; + wire [0:0] m_axi_wr_bready; + wire [1:0] m_axi_wr_bresp; + wire [0:0] m_axi_wr_bvalid; + wire [31:0] m_axi_wr_rdata; + wire [0:0] m_axi_wr_rready; + wire [1:0] m_axi_wr_rresp; + wire [0:0] m_axi_wr_rvalid; + wire [31:0] m_axi_wr_wdata; + wire [0:0] m_axi_wr_wready; + wire [3:0] m_axi_wr_wstrb; + wire [0:0] m_axi_wr_wvalid; + + wire [63:0] ps_gpio_out; + wire [63:0] ps_gpio_in; + wire [63:0] ps_gpio_tri; + + wire [15:0] IRQ_F2P; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + wire clk100; + wire clk40; + wire meas_clk_ref; + wire bus_clk; + wire gige_refclk; + wire gige_refclk_bufg; + wire xgige_refclk; + wire xgige_clk156; + wire xgige_dclk; + + wire global_rst; + wire radio_rst; + wire bus_rst; + wire FCLK_RESET0_N; + wire clk40_rst; + wire clk40_rstn; + + wire [1:0] USB0_PORT_INDCTL; + wire USB0_VBUS_PWRSELECT; + wire USB0_VBUS_PWRFAULT; + + wire ref_clk; + wire wr_refclk_buf; + wire netclk_buf; + wire meas_clk; + wire ddr3_dma_clk; + wire meas_clk_reset; + wire meas_clk_locked; + wire enable_ref_clk_async; + wire pps_radioclk1x_iob; + wire pps_radioclk1x; + wire [3:0] pps_select; + wire pps_out_enb; + wire [1:0] pps_select_sfp; + wire pps_refclk; + wire export_pps_radioclk; + wire radio_clk; + wire radio_clkB; + wire radio_clk_2x; + wire radio_clk_2xB; + + wire qsfp_sda_i; + wire qsfp_sda_o; + wire qsfp_sda_t; + wire qsfp_scl_i; + wire qsfp_scl_o; + wire qsfp_scl_t; + + ///////////////////////////////////////////////////////////////////// + // + // Resets + // + ////////////////////////////////////////////////////////////////////// + + // Global synchronous reset, on the bus_clk domain. De-asserts after 85 + // bus_clk cycles. Asserted by default. + por_gen por_gen(.clk(bus_clk), .reset_out(global_rst)); + + // Synchronous reset for the radio_clk domain, based on the global_rst. + reset_sync radio_reset_gen ( + .clk(radio_clk), + .reset_in(global_rst), + .reset_out(radio_rst) + ); + + // Synchronous reset for the bus_clk domain, based on the global_rst. + reset_sync bus_reset_gen ( + .clk(bus_clk), + .reset_in(global_rst), + .reset_out(bus_rst) + ); + + + // PS-based Resets // + // + // Synchronous reset for the clk40 domain. This is derived from the PS reset 0. + reset_sync clk40_reset_gen ( + .clk(clk40), + .reset_in(~FCLK_RESET0_N), + .reset_out(clk40_rst) + ); + // Invert for various modules. + assign clk40_rstn = ~clk40_rst; + + + ///////////////////////////////////////////////////////////////////// + // + // Timing + // + ////////////////////////////////////////////////////////////////////// + + // Clocks from the PS + // + // These clocks appear to have BUFGs already instantiated by the ip generator. + // Simply rename them here for clarity. + // FCLK_CLK0 : 100 MHz + // FCLK_CLK1 : 40 MHz + // FCLK_CLK2 : 166.6667 MHz + // FCLK_CLK3 : 200 MHz + assign clk100 = FCLK_CLK0; + assign clk40 = FCLK_CLK1; + assign meas_clk_ref = FCLK_CLK2; + assign bus_clk = FCLK_CLK3; + + //If bus_clk freq ever changes, update this paramter accordingly. + localparam BUS_CLK_RATE = 32'd200000000; //200 MHz bus_clk rate. + + n3xx_clocking n3xx_clocking_i ( + .enable_ref_clk_async(enable_ref_clk_async), + .FPGA_REFCLK_P(FPGA_REFCLK_P), + .FPGA_REFCLK_N(FPGA_REFCLK_N), + .ref_clk(ref_clk), + .WB_20MHz_P(WB_20MHZ_P), + .WB_20MHz_N(WB_20MHZ_N), + .wr_refclk_buf(wr_refclk_buf), + .NETCLK_REF_P(NETCLK_REF_P), + .NETCLK_REF_N(NETCLK_REF_N), + .netclk_buf(netclk_buf), + .NETCLK_P(NETCLK_P), + .NETCLK_N(NETCLK_N), + .gige_refclk_buf(gige_refclk), + .MGT156MHZ_CLK1_P(MGT156MHZ_CLK1_P), + .MGT156MHZ_CLK1_N(MGT156MHZ_CLK1_N), + .xgige_refclk_buf(xgige_refclk), + .misc_clks_ref(meas_clk_ref), + .meas_clk(meas_clk), + .ddr3_dma_clk(ddr3_dma_clk), + .misc_clks_reset(meas_clk_reset), + .misc_clks_locked(meas_clk_locked), + .ext_pps_from_pin(REF_1PPS_IN), + .gps_pps_from_pin(GPS_1PPS), + .pps_select(pps_select), + .pps_refclk(pps_refclk) + ); + + // Drive the rear panel connector with another controllable copy of the post-TDC PPS + // that SW can enable/disable. The user is free to hack this to be whatever + // they desire. Flop the PPS signal one more time in order that it can be packed into + // an IOB. This extra flop stage matches the additional flop inside DbCore to allow + // pps_radioclk1x and pps_out_radioclk to be in sync with one another. + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) pps_export_dsync ( + .clk(radio_clk), .rst(1'b0), .in(pps_out_enb), .out(export_pps_radioclk) + ); + + // The radio_clk rate is between [122.88M, 250M] for all known N3xx variants, + // resulting in approximately [8ns, 4ns] periods. To pulse-extend the PPS output, + // we create a 25 bit-wide counter, creating ~[.262s, .131s] long output high pulses, + // variable depending on our radio_clk rate. Create two of the same output signal + // in order that the PPS_OUT gets packed into an IOB for tight timing. + reg [24:0] pps_out_count = 'b0; + reg pps_out_radioclk = 1'b0; + reg pps_led_radioclk = 1'b0; + + always @(posedge radio_clk) begin + if (export_pps_radioclk) begin + if (pps_radioclk1x_iob) begin + pps_out_radioclk <= 1'b1; + pps_led_radioclk <= 1'b1; + pps_out_count <= {25{1'b1}}; + end else begin + if (pps_out_count > 0) begin + pps_out_count <= pps_out_count - 1'b1; + end else begin + pps_out_radioclk <= 1'b0; + pps_led_radioclk <= 1'b0; + end + end + end else begin + pps_out_radioclk <= 1'b0; + pps_led_radioclk <= 1'b0; + end + end + // Local to output. + assign REF_1PPS_OUT = pps_out_radioclk; + assign PANEL_LED_PPS = pps_led_radioclk; + + ///////////////////////////////////////////////////////////////////// + // + // SFP, QSFP and NPIO MGT Connections + // + ////////////////////////////////////////////////////////////////////// + wire reg_wr_req_npio; + wire [REG_AWIDTH-1:0] reg_wr_addr_npio; + wire [REG_DWIDTH-1:0] reg_wr_data_npio; + wire reg_rd_req_npio; + wire [REG_AWIDTH-1:0] reg_rd_addr_npio; + wire reg_rd_resp_npio, reg_rd_resp_npio0, reg_rd_resp_npio1; + wire [REG_DWIDTH-1:0] reg_rd_data_npio, reg_rd_data_npio0, reg_rd_data_npio1; + + localparam NPIO_REG_BASE = 14'h0200; + + regport_resp_mux #( + .WIDTH (REG_DWIDTH), + .NUM_SLAVES (2) + ) npio_resp_mux_i( + .clk(bus_clk), .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_npio0, reg_rd_resp_npio1}), + .sla_rd_data({reg_rd_data_npio0, reg_rd_data_npio1}), + .mst_rd_resp(reg_rd_resp_npio), .mst_rd_data(reg_rd_data_npio) + ); + + //-------------------------------------------------------------- + // SFP/MGT Reference Clocks + //-------------------------------------------------------------- + + // We support the HG, XG, XA, AA targets, all of which require + // the 156.25MHz reference clock. Instantiate it here. + ten_gige_phy_clk_gen xgige_clk_gen_i ( + .refclk_ibuf(xgige_refclk), + .clk156(xgige_clk156), + .dclk(xgige_dclk) + ); + + wire qpllreset; + wire qpllreset_sfp0, qpllreset_sfp1, qpllreset_npio0, qpllreset_npio1; + wire qplllock; + wire qplloutclk; + wire qplloutrefclk; + + // We reuse this GT_COMMON wrapper for both ethernet and Aurora because + // the behavior is identical + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) ten_gig_eth_pcs_pma_gt_common_block ( + .refclk(xgige_refclk), + .qpllreset(qpllreset), //from 2nd sfp + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclksel(3'b101 /*GTSOUTHREFCLK0*/) + ); + + // The quad's QPLL should reset if any of the channels request it + // This should never really happen because we are not changing the reference clock + // source for the QPLL. + assign qpllreset = qpllreset_sfp0 | qpllreset_sfp1 | qpllreset_npio0 | qpllreset_npio1; + + // Use the 156.25MHz reference clock for Aurora + wire aurora_refclk = xgige_refclk; + wire aurora_clk156 = xgige_clk156; + wire aurora_init_clk = xgige_dclk; + + // White Rabbit and 1GbE both use the same clocking +`ifdef SFP0_1GBE + `define SFP0_WR_1GBE +`endif +`ifdef SFP0_WR + `define SFP0_WR_1GBE +`endif + +`ifdef SFP0_WR_1GBE + // HG and WX targets require the 1GbE clock support + BUFG bufg_gige_refclk_i ( + .I(gige_refclk), + .O(gige_refclk_bufg) + ); + assign SFP_0_RS0 = 1'b0; + assign SFP_0_RS1 = 1'b0; +`else + assign SFP_0_RS0 = 1'b1; + assign SFP_0_RS1 = 1'b1; +`endif + + // SFP 1 is always set to run at ~10Gbps rates. + assign SFP_1_RS0 = 1'b1; + assign SFP_1_RS1 = 1'b1; + + // SFP port specific reference clocks + wire sfp0_gt_refclk, sfp1_gt_refclk; + wire sfp0_gb_refclk, sfp1_gb_refclk; + wire sfp0_misc_clk, sfp1_misc_clk; + +`ifdef SFP0_10GBE + assign sfp0_gt_refclk = xgige_refclk; + assign sfp0_gb_refclk = xgige_clk156; + assign sfp0_misc_clk = xgige_dclk; +`endif +`ifdef SFP0_WR_1GBE + assign sfp0_gt_refclk = gige_refclk; + assign sfp0_gb_refclk = gige_refclk_bufg; + assign sfp0_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP0_AURORA + assign sfp0_gt_refclk = aurora_refclk; + assign sfp0_gb_refclk = aurora_clk156; + assign sfp0_misc_clk = aurora_init_clk; +`endif + +`ifdef SFP1_10GBE + assign sfp1_gt_refclk = xgige_refclk; + assign sfp1_gb_refclk = xgige_clk156; + assign sfp1_misc_clk = xgige_dclk; +`endif +`ifdef SFP1_1GBE + assign sfp1_gt_refclk = gige_refclk; + assign sfp1_gb_refclk = gige_refclk_bufg; + assign sfp1_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP1_AURORA + assign sfp1_gt_refclk = aurora_refclk; + assign sfp1_gb_refclk = aurora_clk156; + assign sfp1_misc_clk = aurora_init_clk; +`endif + + // Instantiate Aurora MMCM if either of the SFPs + // or NPIOs are Aurora + wire au_tx_clk; + wire au_mmcm_reset; + wire au_user_clk; + wire au_sync_clk; + wire au_mmcm_locked; + wire sfp0_tx_out_clk, sfp1_tx_out_clk; + wire sfp0_gt_pll_lock, sfp1_gt_pll_lock; + wire npio0_tx_out_clk, npio1_tx_out_clk; + wire npio0_gt_pll_lock, npio1_gt_pll_lock; + + //NOTE: need to declare one of these defines in order to enable Aurora on + //any SFP or NPIO lane. +`ifdef SFP1_AURORA + `define SFP_AU_MMCM + assign au_tx_clk = sfp1_tx_out_clk; + assign au_mmcm_reset = ~sfp1_gt_pll_lock; +`elsif NPIO0 + `define SFP_AU_MMCM + assign au_tx_clk = npio0_tx_out_clk; + assign au_mmcm_reset = ~npio0_gt_pll_lock; +`elsif NPIO1 + `define SFP_AU_MMCM + assign au_tx_clk = npio1_tx_out_clk; + assign au_mmcm_reset = ~npio1_gt_pll_lock; +`endif + + +`ifdef SFP_AU_MMCM + aurora_phy_mmcm au_phy_mmcm_i ( + .aurora_tx_clk_unbuf(au_tx_clk), + .mmcm_reset(au_mmcm_reset), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .mmcm_locked(au_mmcm_locked) + ); +`else + assign au_user_clk = 1'b0; + assign au_sync_clk = 1'b0; + assign au_mmcm_locked = 1'b0; +`endif + + //-------------------------------------------------------------- + // NPIO-QSFP MGT Lanes (Example loopback config) + //-------------------------------------------------------------- + +`ifdef QSFP_LANES + localparam NUM_QSFP_LANES = `QSFP_LANES; + + // QSFP wires to the ARM core and the crossbar + // These will only be connected if QSFP is 2x10 GbE + wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_tx_tdata_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tvalid_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tlast_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tready_b; + wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_tx_tuser_b; + wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_tx_tkeep_b; + + wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_rx_tdata_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tvalid_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tlast_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tready_b; + wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_rx_tuser_b; + wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_rx_tkeep_b; + + wire [NUM_QSFP_LANES*64-1:0] v2e_qsfp_tdata; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tlast; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tvalid; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tready; + + wire [NUM_QSFP_LANES*64-1:0] e2v_qsfp_tdata; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tlast; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tvalid; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tready; + + wire [NUM_QSFP_LANES-1:0] qsfp_link_up; + + // QSFP quad's specific reference clocks + wire qsfp_gt_refclk; + wire qsfp_gb_refclk; + wire qsfp_misc_clk; + + wire qsfp_qplloutclk; + wire qsfp_qplloutrefclk; + wire qsfp_qplllock; + wire qsfp_qpllreset; + + wire qsfp_gt_tx_out_clk; + wire qsfp_gt_pll_lock; + + wire qsfp_au_user_clk; + wire qsfp_au_sync_clk; + wire qsfp_au_mmcm_locked; + + +`ifdef QSFP_10GBE + assign qsfp_gt_refclk = xgige_refclk; + assign qsfp_gb_refclk = xgige_clk156; + assign qsfp_misc_clk = xgige_dclk; +`endif +`ifdef QSFP_AURORA + assign qsfp_gt_refclk = aurora_refclk; + assign qsfp_gb_refclk = aurora_clk156; + assign qsfp_misc_clk = aurora_init_clk; +`endif + + // We reuse this GT_COMMON wrapper for both ethernet and Aurora because + // the behavior is identical + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) qsfp_gt_common_block ( + .refclk(xgige_refclk), + .qpllreset(qsfp_qpllreset), + .qplllock(qsfp_qplllock), + .qplloutclk(qsfp_qplloutclk), + .qplloutrefclk(qsfp_qplloutrefclk), + .qpllrefclksel(3'b001 /*GTREFCLK0*/) + ); + + `ifdef QSFP_AURORA + aurora_phy_mmcm aurora_phy_mmcm ( + .aurora_tx_clk_unbuf(qsfp_gt_tx_out_clk), + .mmcm_reset(~qsfp_gt_pll_lock), + .user_clk(qsfp_au_user_clk), + .sync_clk(qsfp_au_sync_clk), + .mmcm_locked(qsfp_au_mmcm_locked) + ); + `else + assign qsfp_au_user_clk = 1'b0; + assign qsfp_au_sync_clk = 1'b0; + assign qsfp_au_mmcm_locked = 1'b0; + `endif + + n3xx_mgt_channel_wrapper #( + `ifdef QSFP_10GBE + .PROTOCOL ("10GbE"), + .MDIO_EN (1'b1), + .MDIO_PHYADDR (5'd4), + `elsif QSFP_AURORA + .PROTOCOL ("Aurora"), + .MDIO_EN (1'b0), + `endif + .LANES (NUM_QSFP_LANES), + .GT_COMMON (1), + .PORTNUM_BASE (4), + .REG_DWIDTH (REG_DWIDTH), + .REG_AWIDTH (QSFP_REG_AWIDTH) + ) qsfp_wrapper_i ( + .areset (global_rst), + .gt_refclk (qsfp_gt_refclk), + .gb_refclk (qsfp_gb_refclk), + .misc_clk (qsfp_misc_clk), + .user_clk (qsfp_au_user_clk), + .sync_clk (qsfp_au_sync_clk), + .gt_tx_out_clk_unbuf(qsfp_gt_tx_out_clk), + + .bus_clk (bus_clk), + .bus_rst (bus_rst), + + // GT Common + .qpllrefclklost (), + .qplllock (qsfp_qplllock), + .qplloutclk (qsfp_qplloutclk), + .qplloutrefclk (qsfp_qplloutrefclk), + .qpllreset (qsfp_qpllreset), + + // Aurora MMCM + .mmcm_locked (qsfp_au_mmcm_locked), + .gt_pll_lock (qsfp_gt_pll_lock), + + .txp (QSFP_TX_P), + .txn (QSFP_TX_N), + .rxp (QSFP_RX_P), + .rxn (QSFP_RX_N), + + .mod_present_n (QSFP_PRESENT_B), + .mod_rxlos (1'b0), + .mod_tx_fault (1'b0), + .mod_tx_disable (), + .mod_int_n (QSFP_INT_B), + .mod_reset_n (QSFP_RESET_B), + .mod_lpmode (QSFP_LPMODE), + .mod_sel_n (QSFP_MODSEL_B), + + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_aresetn (clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr (M_AXI_NET2_AWADDR[QSFP_REG_AWIDTH-1:0]), + .s_axi_awvalid (M_AXI_NET2_AWVALID), + .s_axi_awready (M_AXI_NET2_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata (M_AXI_NET2_WDATA), + .s_axi_wstrb (M_AXI_NET2_WSTRB), + .s_axi_wvalid (M_AXI_NET2_WVALID), + .s_axi_wready (M_AXI_NET2_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp (M_AXI_NET2_BRESP), + .s_axi_bvalid (M_AXI_NET2_BVALID), + .s_axi_bready (M_AXI_NET2_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr (M_AXI_NET2_ARADDR[QSFP_REG_AWIDTH-1:0]), + .s_axi_arvalid (M_AXI_NET2_ARVALID), + .s_axi_arready (M_AXI_NET2_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_NET2_RDATA), + .s_axi_rresp (M_AXI_NET2_RRESP), + .s_axi_rvalid (M_AXI_NET2_RVALID), + .s_axi_rready (M_AXI_NET2_RREADY), + + // Ethernet to Vita + .e2v_tdata (e2v_qsfp_tdata), + .e2v_tlast (e2v_qsfp_tlast), + .e2v_tvalid (e2v_qsfp_tvalid), + .e2v_tready (e2v_qsfp_tready), + + // Vita to Ethernet + .v2e_tdata (v2e_qsfp_tdata), + .v2e_tlast (v2e_qsfp_tlast), + .v2e_tvalid (v2e_qsfp_tvalid), + .v2e_tready (v2e_qsfp_tready), + + // Ethernet to CPU + .e2c_tdata (arm_eth_qsfp_rx_tdata_b), + .e2c_tkeep (arm_eth_qsfp_rx_tkeep_b), + .e2c_tlast (arm_eth_qsfp_rx_tlast_b), + .e2c_tvalid (arm_eth_qsfp_rx_tvalid_b), + .e2c_tready (arm_eth_qsfp_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata (arm_eth_qsfp_tx_tdata_b), + .c2e_tkeep (arm_eth_qsfp_tx_tkeep_b), + .c2e_tlast (arm_eth_qsfp_tx_tlast_b), + .c2e_tvalid (arm_eth_qsfp_tx_tvalid_b), + .c2e_tready (arm_eth_qsfp_tx_tready_b), + + // Sideband White Rabbit Control + .wr_reset_n (1'b1), + .wr_refclk (1'b0), + + .wr_dac_sclk (), + .wr_dac_din (), + .wr_dac_clr_n (), + .wr_dac_cs_n (), + .wr_dac_ldac_n (), + + .wr_eeprom_scl_o(), + .wr_eeprom_scl_i(1'b0), + .wr_eeprom_sda_o(), + .wr_eeprom_sda_i(1'b0), + + .wr_uart_rx (1'b0), + .wr_uart_tx (), + + .mod_pps (), + .mod_refclk (), + + // WR AXI Control + .wr_axi_aclk (), + .wr_axi_aresetn (1'b1), + .wr_axi_awaddr (), + .wr_axi_awvalid (), + .wr_axi_awready (), + .wr_axi_wdata (), + .wr_axi_wstrb (), + .wr_axi_wvalid (), + .wr_axi_wready (), + .wr_axi_bresp (), + .wr_axi_bvalid (), + .wr_axi_bready (), + .wr_axi_araddr (), + .wr_axi_arvalid (), + .wr_axi_arready (), + .wr_axi_rdata (), + .wr_axi_rresp (), + .wr_axi_rvalid (), + .wr_axi_rready (), + .wr_axi_rlast (), + + .port_info (), + .device_id (device_id), + + .link_up (qsfp_link_up), + .activity () + ); + + assign QSFP_I2C_SCL = qsfp_scl_t ? 1'bz : qsfp_scl_o; + assign qsfp_scl_i = QSFP_I2C_SCL; + assign QSFP_I2C_SDA = qsfp_sda_t ? 1'bz : qsfp_sda_o; + assign qsfp_sda_i = QSFP_I2C_SDA; + + assign QSFP_LED = |qsfp_link_up; +`else + + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_qsfp ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_NET2_AWADDR), + .s_axi_awvalid(M_AXI_NET2_AWVALID), + .s_axi_awready(M_AXI_NET2_AWREADY), + + .s_axi_wdata(M_AXI_NET2_WDATA), + .s_axi_wvalid(M_AXI_NET2_WVALID), + .s_axi_wready(M_AXI_NET2_WREADY), + + .s_axi_bresp(M_AXI_NET2_BRESP), + .s_axi_bvalid(M_AXI_NET2_BVALID), + .s_axi_bready(M_AXI_NET2_BREADY), + + .s_axi_araddr(M_AXI_NET2_ARADDR), + .s_axi_arvalid(M_AXI_NET2_ARVALID), + .s_axi_arready(M_AXI_NET2_ARREADY), + + .s_axi_rdata(M_AXI_NET2_RDATA), + .s_axi_rresp(M_AXI_NET2_RRESP), + .s_axi_rvalid(M_AXI_NET2_RVALID), + .s_axi_rready(M_AXI_NET2_RREADY) + + ); + + assign qsfp_scl_i = qsfp_scl_t ? 1'b1 : qsfp_scl_o; + assign qsfp_sda_i = qsfp_sda_t ? 1'b1 : qsfp_sda_o; + +`endif + + //-------------------------------------------------------------- + // NPIO MGT Lanes (Example loopback config) + //-------------------------------------------------------------- + +`ifdef NPIO_LANES + + wire [127:0] npio_loopback_tdata; + wire [1:0] npio_loopback_tvalid; + wire [1:0] npio_loopback_tready; + wire [1:0] npio_loopback_tlast; + + n3xx_mgt_io_core #( + .PROTOCOL ("Aurora"), + .REG_BASE (NPIO_REG_BASE + 14'h00), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .PORTNUM (8'd2), + .MDIO_EN (0) + ) npio_ln_0_i ( + .areset (global_rst), + .gt_refclk (aurora_refclk), + .gb_refclk (aurora_clk156), + .misc_clk (aurora_init_clk), + .user_clk (au_user_clk), + .sync_clk (au_sync_clk), + .gt_tx_out_clk_unbuf(npio0_tx_out_clk), + + .bus_clk (bus_clk),//clk for status reg reads to mdio interface + .bus_rst (bus_rst), + .qpllreset (qpllreset_npio0), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qplllock (qplllock), + .qpllrefclklost (), + + .rxp (NPIO_RX0_P), + .rxn (NPIO_RX0_N), + .txp (NPIO_TX0_P), + .txn (NPIO_TX0_N), + + .sfpp_rxlos (1'b0), + .sfpp_tx_fault (1'b0), + + //RegPort + .reg_wr_req (reg_wr_req_npio), + .reg_wr_addr (reg_wr_addr_npio), + .reg_wr_data (reg_wr_data_npio), + .reg_rd_req (reg_rd_req_npio), + .reg_rd_addr (reg_rd_addr_npio), + .reg_rd_resp (reg_rd_resp_npio0), + .reg_rd_data (reg_rd_data_npio0), + + //DATA (loopback mode) + .s_axis_tdata (npio_loopback_tdata[63:0]), //Data to aurora core + .s_axis_tuser (4'b0), + .s_axis_tvalid (npio_loopback_tvalid[0]), + .s_axis_tlast (npio_loopback_tlast[0]), + .s_axis_tready (npio_loopback_tready[0]), + .m_axis_tdata (npio_loopback_tdata[63:0]), //Data from aurora core + .m_axis_tuser (), + .m_axis_tvalid (npio_loopback_tvalid[0]), + .m_axis_tlast (npio_loopback_tlast[0]), + .m_axis_tready (npio_loopback_tready[0]), + + .mmcm_locked (au_mmcm_locked), + .gt_pll_lock (npio0_gt_pll_lock) + ); + + n3xx_mgt_io_core #( + .PROTOCOL ("Aurora"), + .REG_BASE (NPIO_REG_BASE + 14'h40), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .PORTNUM (8'd3), + .MDIO_EN (0) + ) npio_ln_1_i ( + .areset (global_rst), + .gt_refclk (aurora_refclk), + .gb_refclk (aurora_clk156), + .misc_clk (aurora_init_clk), + .user_clk (au_user_clk), + .sync_clk (au_sync_clk), + .gt_tx_out_clk_unbuf(npio1_tx_out_clk), + + .bus_clk (bus_clk),//clk for status reg reads to mdio interface + .bus_rst (bus_rst), + .qpllreset (qpllreset_npio1), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qplllock (qplllock), + .qpllrefclklost (), + + .rxp (NPIO_RX1_P), + .rxn (NPIO_RX1_N), + .txp (NPIO_TX1_P), + .txn (NPIO_TX1_N), + + .sfpp_rxlos (1'b0), + .sfpp_tx_fault (1'b0), + + //RegPort + .reg_wr_req (reg_wr_req_npio), + .reg_wr_addr (reg_wr_addr_npio), + .reg_wr_data (reg_wr_data_npio), + .reg_rd_req (reg_rd_req_npio), + .reg_rd_addr (reg_rd_addr_npio), + .reg_rd_resp (reg_rd_resp_npio1), + .reg_rd_data (reg_rd_data_npio1), + + //DATA (loopback mode) + .s_axis_tdata (npio_loopback_tdata[127:64]), //Data to aurora core + .s_axis_tuser (4'b0), + .s_axis_tvalid (npio_loopback_tvalid[1]), + .s_axis_tlast (npio_loopback_tlast[1]), + .s_axis_tready (npio_loopback_tready[1]), + .m_axis_tdata (npio_loopback_tdata[127:64]), //Data from aurora core + .m_axis_tuser (), + .m_axis_tvalid (npio_loopback_tvalid[1]), + .m_axis_tlast (npio_loopback_tlast[1]), + .m_axis_tready (npio_loopback_tready[1]), + + .mmcm_locked (au_mmcm_locked), + .gt_pll_lock (npio1_gt_pll_lock) + ); + +`else + + assign reg_rd_resp_npio0 = 1'b0; + assign reg_rd_data_npio0 = 'h0; + assign reg_rd_resp_npio1 = 1'b0; + assign reg_rd_data_npio1 = 'h0; + assign npio0_gt_pll_lock = 1'b1; + assign npio1_gt_pll_lock = 1'b1; + assign qpllreset_npio0 = 1'b0; + assign qpllreset_npio1 = 1'b0; + +`endif + + + // ARM ethernet 0 bridge signals + wire [63:0] arm_eth0_tx_tdata; + wire arm_eth0_tx_tvalid; + wire arm_eth0_tx_tlast; + wire arm_eth0_tx_tready; + wire [3:0] arm_eth0_tx_tuser; + wire [7:0] arm_eth0_tx_tkeep; + + wire [63:0] arm_eth0_tx_tdata_b; + wire arm_eth0_tx_tvalid_b; + wire arm_eth0_tx_tlast_b; + wire arm_eth0_tx_tready_b; + wire [3:0] arm_eth0_tx_tuser_b; + wire [7:0] arm_eth0_tx_tkeep_b; + + wire [63:0] arm_eth_sfp0_tx_tdata_b; + wire arm_eth_sfp0_tx_tvalid_b; + wire arm_eth_sfp0_tx_tlast_b; + wire arm_eth_sfp0_tx_tready_b; + wire [3:0] arm_eth_sfp0_tx_tuser_b; + wire [7:0] arm_eth_sfp0_tx_tkeep_b; + + wire [63:0] arm_eth0_rx_tdata; + wire arm_eth0_rx_tvalid; + wire arm_eth0_rx_tlast; + wire arm_eth0_rx_tready; + wire [3:0] arm_eth0_rx_tuser; + wire [7:0] arm_eth0_rx_tkeep; + + wire [63:0] arm_eth0_rx_tdata_b; + wire arm_eth0_rx_tvalid_b; + wire arm_eth0_rx_tlast_b; + wire arm_eth0_rx_tready_b; + wire [3:0] arm_eth0_rx_tuser_b; + wire [7:0] arm_eth0_rx_tkeep_b; + + wire [63:0] arm_eth_sfp0_rx_tdata_b; + wire arm_eth_sfp0_rx_tvalid_b; + wire arm_eth_sfp0_rx_tlast_b; + wire arm_eth_sfp0_rx_tready_b; + wire [3:0] arm_eth_sfp0_rx_tuser_b; + wire [7:0] arm_eth_sfp0_rx_tkeep_b; + + wire arm_eth0_rx_irq; + wire arm_eth0_tx_irq; + + // ARM ethernet 1 bridge signals + wire [63:0] arm_eth1_tx_tdata; + wire arm_eth1_tx_tvalid; + wire arm_eth1_tx_tlast; + wire arm_eth1_tx_tready; + wire [3:0] arm_eth1_tx_tuser; + wire [7:0] arm_eth1_tx_tkeep; + + wire [63:0] arm_eth1_tx_tdata_b; + wire arm_eth1_tx_tvalid_b; + wire arm_eth1_tx_tlast_b; + wire arm_eth1_tx_tready_b; + wire [3:0] arm_eth1_tx_tuser_b; + wire [7:0] arm_eth1_tx_tkeep_b; + + wire [63:0] arm_eth_sfp1_tx_tdata_b; + wire arm_eth_sfp1_tx_tvalid_b; + wire arm_eth_sfp1_tx_tlast_b; + wire arm_eth_sfp1_tx_tready_b; + wire [3:0] arm_eth_sfp1_tx_tuser_b; + wire [7:0] arm_eth_sfp1_tx_tkeep_b; + + wire [63:0] arm_eth1_rx_tdata; + wire arm_eth1_rx_tvalid; + wire arm_eth1_rx_tlast; + wire arm_eth1_rx_tready; + wire [3:0] arm_eth1_rx_tuser; + wire [7:0] arm_eth1_rx_tkeep; + + wire [63:0] arm_eth1_rx_tdata_b; + wire arm_eth1_rx_tvalid_b; + wire arm_eth1_rx_tlast_b; + wire arm_eth1_rx_tready_b; + wire [3:0] arm_eth1_rx_tuser_b; + wire [7:0] arm_eth1_rx_tkeep_b; + + wire [63:0] arm_eth_sfp1_rx_tdata_b; + wire arm_eth_sfp1_rx_tvalid_b; + wire arm_eth_sfp1_rx_tlast_b; + wire arm_eth_sfp1_rx_tready_b; + wire [3:0] arm_eth_sfp1_rx_tuser_b; + wire [7:0] arm_eth_sfp1_rx_tkeep_b; + + wire arm_eth1_tx_irq; + wire arm_eth1_rx_irq; + + // Vita to Ethernet + wire [63:0] v2e0_tdata; + wire v2e0_tlast; + wire v2e0_tvalid; + wire v2e0_tready; + + wire [63:0] v2e1_tdata; + wire v2e1_tlast; + wire v2e1_tvalid; + wire v2e1_tready; + + wire [63:0] v2e_sfp0_tdata; + wire v2e_sfp0_tlast; + wire v2e_sfp0_tvalid; + wire v2e_sfp0_tready; + + wire [63:0] v2e_sfp1_tdata; + wire v2e_sfp1_tlast; + wire v2e_sfp1_tvalid; + wire v2e_sfp1_tready; + + // Ethernet to Vita + wire [63:0] e2v0_tdata; + wire e2v0_tlast; + wire e2v0_tvalid; + wire e2v0_tready; + + wire [63:0] e2v1_tdata; + wire e2v1_tlast; + wire e2v1_tvalid; + wire e2v1_tready; + + wire [63:0] e2v_sfp0_tdata; + wire e2v_sfp0_tlast; + wire e2v_sfp0_tvalid; + wire e2v_sfp0_tready; + + wire [63:0] e2v_sfp1_tdata; + wire e2v_sfp1_tlast; + wire e2v_sfp1_tvalid; + wire e2v_sfp1_tready; + + // Ethernet crossover + wire [63:0] e01_tdata, e10_tdata; + wire [3:0] e01_tuser, e10_tuser; + wire e01_tlast, e01_tvalid, e01_tready; + wire e10_tlast, e10_tvalid, e10_tready; + + + // DMA xport adapter to PS + wire [63:0] m_axis_dma_tdata; + wire [3:0] m_axis_dma_tuser; + wire m_axis_dma_tlast; + wire m_axis_dma_tready; + wire m_axis_dma_tvalid; + + wire [63:0] s_axis_dma_tdata; + wire [3:0] s_axis_dma_tdest; + wire s_axis_dma_tlast; + wire s_axis_dma_tready; + wire s_axis_dma_tvalid; + + // Misc + wire [31:0] sfp_port0_info; + wire [31:0] sfp_port1_info; + wire sfp0_link_up, sfp1_link_up; + wire [15:0] device_id; + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper 0: Network Interface (1/10G or Aurora) + // + ////////////////////////////////////////////////////////////////////// + + n3xx_mgt_channel_wrapper #( + .LANES(1), + `ifdef SFP0_10GBE + .PROTOCOL("10GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP0_AURORA + .PROTOCOL("Aurora"), + .MDIO_EN(1'b0), + `elsif SFP0_1GBE + .PROTOCOL("1GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP0_WR + .PROTOCOL("WhiteRabbit"), + .MDIO_EN(1'b0), + `endif + .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH(REG_AWIDTH), // Width of the address bus + .GT_COMMON(1), + .PORTNUM_BASE(8'd0) + ) sfp_wrapper_0 ( + .areset(global_rst), + .gt_refclk(sfp0_gt_refclk), + .gb_refclk(sfp0_gb_refclk), + .misc_clk(sfp0_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp0_tx_out_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + + .qpllreset(qpllreset_sfp0), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), + + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp0_gt_pll_lock), + + .txp(SFP_0_TX_P), + .txn(SFP_0_TX_N), + .rxp(SFP_0_RX_P), + .rxn(SFP_0_RX_N), + + .mod_present_n(SFP_0_I2C_NPRESENT), + .mod_rxlos(SFP_0_LOS), + .mod_tx_fault(SFP_0_TXFAULT), + .mod_tx_disable(SFP_0_TXDISABLE), + + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET0_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET0_AWVALID), + .s_axi_awready(M_AXI_NET0_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET0_WDATA), + .s_axi_wstrb(M_AXI_NET0_WSTRB), + .s_axi_wvalid(M_AXI_NET0_WVALID), + .s_axi_wready(M_AXI_NET0_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET0_BRESP), + .s_axi_bvalid(M_AXI_NET0_BVALID), + .s_axi_bready(M_AXI_NET0_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET0_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET0_ARVALID), + .s_axi_arready(M_AXI_NET0_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET0_RDATA), + .s_axi_rresp(M_AXI_NET0_RRESP), + .s_axi_rvalid(M_AXI_NET0_RVALID), + .s_axi_rready(M_AXI_NET0_RREADY), + + // Ethernet to Vita + .e2v_tdata(e2v_sfp0_tdata), + .e2v_tlast(e2v_sfp0_tlast), + .e2v_tvalid(e2v_sfp0_tvalid), + .e2v_tready(e2v_sfp0_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_sfp0_tdata), + .v2e_tlast(v2e_sfp0_tlast), + .v2e_tvalid(v2e_sfp0_tvalid), + .v2e_tready(v2e_sfp0_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp0_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp0_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp0_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp0_rx_tvalid_b), + .e2c_tready(arm_eth_sfp0_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp0_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp0_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp0_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp0_tx_tvalid_b), + .c2e_tready(arm_eth_sfp0_tx_tready_b), + + // White Rabbit Specific +`ifdef SFP0_WR + .wr_reset_n (~ps_gpio_out[48]), // reset for WR only + .wr_refclk (wr_refclk_buf), + .wr_dac_sclk (WB_DAC_SCLK), + .wr_dac_din (WB_DAC_DIN), + .wr_dac_clr_n (WB_DAC_NCLR), + .wr_dac_cs_n (WB_DAC_NSYNC), + .wr_dac_ldac_n(WB_DAC_NLDAC), + .wr_eeprom_scl_o(), // storage for delay characterization + .wr_eeprom_scl_i(1'b0), // temp + .wr_eeprom_sda_o(), + .wr_eeprom_sda_i(1'b0), // temp + .wr_uart_rx(wr_uart_rxd), // to/from PS + .wr_uart_tx(wr_uart_txd), + .mod_pps(pps_wr_refclk), // out, reference clock and pps + .mod_refclk(wr_ref_clk), + // WR Slave Port to PS + .wr_axi_aclk(m_axi_wr_clk), // out to PS + .wr_axi_aresetn(1'b1), // in + .wr_axi_awaddr(m_axi_wr_awaddr), + .wr_axi_awvalid(m_axi_wr_awvalid), + .wr_axi_awready(m_axi_wr_awready), + .wr_axi_wdata(m_axi_wr_wdata), + .wr_axi_wstrb(m_axi_wr_wstrb), + .wr_axi_wvalid(m_axi_wr_wvalid), + .wr_axi_wready(m_axi_wr_wready), + .wr_axi_bresp(m_axi_wr_bresp), + .wr_axi_bvalid(m_axi_wr_bvalid), + .wr_axi_bready(m_axi_wr_bready), + .wr_axi_araddr(m_axi_wr_araddr), + .wr_axi_arvalid(m_axi_wr_arvalid), + .wr_axi_arready(m_axi_wr_arready), + .wr_axi_rdata(m_axi_wr_rdata), + .wr_axi_rresp(m_axi_wr_rresp), + .wr_axi_rvalid(m_axi_wr_rvalid), + .wr_axi_rready(m_axi_wr_rready), + .wr_axi_rlast(), +`else + .wr_reset_n(1'b1), + .wr_refclk(1'b0), + .wr_eeprom_scl_i(1'b0), + .wr_eeprom_sda_i(1'b0), + .wr_uart_rx(1'b0), +`endif + + // Misc + .port_info(sfp_port0_info), + .device_id(device_id), + + // LED + .link_up(sfp0_link_up), + .activity(SFP_0_LED_A) + ); + + assign ps_gpio_in[60] = ps_gpio_tri[60] ? sfp0_link_up : ps_gpio_out[60]; + assign SFP_0_LED_B = sfp0_link_up; + +`ifndef SFP0_WR + assign WB_DAC_SCLK = 1'b0; + assign WB_DAC_DIN = 1'b0; + assign WB_DAC_NCLR = 1'b1; + assign WB_DAC_NSYNC = 1'b1; + assign WB_DAC_NLDAC = 1'b1; + assign pps_wr_refclk = 1'b0; + assign wr_ref_clk = 1'b0; +`endif + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper 1: Network Interface (1/10G or Aurora) + // + ////////////////////////////////////////////////////////////////////// + + n3xx_mgt_channel_wrapper #( + .LANES(1), + `ifdef SFP1_10GBE + .PROTOCOL("10GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP1_AURORA + .PROTOCOL("Aurora"), + .MDIO_EN(1'b0), + `endif + .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH(REG_AWIDTH), // Width of the address bus + .GT_COMMON(1), + .PORTNUM_BASE(8'd1) + ) sfp_wrapper_1 ( + .areset(global_rst), + + .gt_refclk(sfp1_gt_refclk), + .gb_refclk(sfp1_gb_refclk), + .misc_clk(sfp1_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp1_tx_out_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + + .qpllreset(qpllreset_sfp1), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), + + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp1_gt_pll_lock), + + .txp(SFP_1_TX_P), + .txn(SFP_1_TX_N), + .rxp(SFP_1_RX_P), + .rxn(SFP_1_RX_N), + + .mod_rxlos(SFP_1_LOS), + .mod_tx_fault(SFP_1_TXFAULT), + .mod_tx_disable(SFP_1_TXDISABLE), + + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET1_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET1_AWVALID), + .s_axi_awready(M_AXI_NET1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET1_WDATA), + .s_axi_wstrb(M_AXI_NET1_WSTRB), + .s_axi_wvalid(M_AXI_NET1_WVALID), + .s_axi_wready(M_AXI_NET1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET1_BRESP), + .s_axi_bvalid(M_AXI_NET1_BVALID), + .s_axi_bready(M_AXI_NET1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET1_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET1_ARVALID), + .s_axi_arready(M_AXI_NET1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET1_RDATA), + .s_axi_rresp(M_AXI_NET1_RRESP), + .s_axi_rvalid(M_AXI_NET1_RVALID), + .s_axi_rready(M_AXI_NET1_RREADY), + + // Ethernet to Vita + .e2v_tdata(e2v_sfp1_tdata), + .e2v_tlast(e2v_sfp1_tlast), + .e2v_tvalid(e2v_sfp1_tvalid), + .e2v_tready(e2v_sfp1_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_sfp1_tdata), + .v2e_tlast(v2e_sfp1_tlast), + .v2e_tvalid(v2e_sfp1_tvalid), + .v2e_tready(v2e_sfp1_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp1_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp1_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp1_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp1_rx_tvalid_b), + .e2c_tready(arm_eth_sfp1_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp1_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp1_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp1_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp1_tx_tvalid_b), + .c2e_tready(arm_eth_sfp1_tx_tready_b), + + // Misc + .port_info(sfp_port1_info), + .device_id(device_id), + + // LED + .link_up(sfp1_link_up), + .activity(SFP_1_LED_A) + ); + + assign ps_gpio_in[61] = ps_gpio_tri[61] ? sfp1_link_up : ps_gpio_out[61]; + assign SFP_1_LED_B = sfp1_link_up; + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA 0 + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[0] = arm_eth0_rx_irq; + assign IRQ_F2P[1] = arm_eth0_tx_irq; + + assign {S_AXI_HP0_AWID, S_AXI_HP0_ARID} = 12'd0; + assign {S_AXI_GP0_AWID, S_AXI_GP0_ARID} = 10'd0; + +`ifdef QSFP_10GBE + // QSFP+ lanes connect to DMA engines and crossbar + // Connect first QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_qsfp_tx_tdata_b[0*64 +: 64] = arm_eth0_tx_tdata_b; + assign arm_eth_qsfp_tx_tvalid_b[0] = arm_eth0_tx_tvalid_b; + assign arm_eth_qsfp_tx_tlast_b[0] = arm_eth0_tx_tlast_b; + assign arm_eth0_tx_tready_b = arm_eth_qsfp_tx_tready_b[0]; + assign arm_eth_qsfp_tx_tuser_b[0*4 +: 4] = arm_eth0_tx_tuser_b; + assign arm_eth_qsfp_tx_tkeep_b[0*8 +: 8] = arm_eth0_tx_tkeep_b; + + assign arm_eth0_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[0*64 +: 64]; + assign arm_eth0_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[0]; + assign arm_eth0_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[0]; + assign arm_eth_qsfp_rx_tready_b[0] = arm_eth0_rx_tready_b; + assign arm_eth0_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[0*4 +: 4]; + assign arm_eth0_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[0*8 +: 8]; + + // Connect first QSFP+ 10 GbE port to the crossbar + assign v2e_qsfp_tdata[0*64 +: 64] = v2e0_tdata; + assign v2e_qsfp_tlast[0] = v2e0_tlast; + assign v2e_qsfp_tvalid[0] = v2e0_tvalid; + assign v2e0_tready = v2e_qsfp_tready[0]; + + assign e2v0_tdata = e2v_qsfp_tdata[0*64 +: 64]; + assign e2v0_tlast = e2v_qsfp_tlast[0]; + assign e2v0_tvalid = e2v_qsfp_tvalid[0]; + assign e2v_qsfp_tready[0] = e2v0_tready; + + // Connect second QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_qsfp_tx_tdata_b[1*64 +: 64] = arm_eth1_tx_tdata_b; + assign arm_eth_qsfp_tx_tvalid_b[1] = arm_eth1_tx_tvalid_b; + assign arm_eth_qsfp_tx_tlast_b[1] = arm_eth1_tx_tlast_b; + assign arm_eth1_tx_tready_b = arm_eth_qsfp_tx_tready_b[1]; + assign arm_eth_qsfp_tx_tuser_b[1*4 +: 4] = arm_eth1_tx_tuser_b; + assign arm_eth_qsfp_tx_tkeep_b[1*8 +: 8] = arm_eth1_tx_tkeep_b; + + assign arm_eth1_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[1*64 +: 64]; + assign arm_eth1_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[1]; + assign arm_eth1_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[1]; + assign arm_eth_qsfp_rx_tready_b[1] = arm_eth1_rx_tready_b; + assign arm_eth1_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[1*4 +: 4]; + assign arm_eth1_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[1*8 +: 8]; + + // Connect second QSFP+ 10 GbE port to the crossbar + assign v2e_qsfp_tdata[1*64 +: 64] = v2e1_tdata; + assign v2e_qsfp_tlast[1] = v2e1_tlast; + assign v2e_qsfp_tvalid[1] = v2e1_tvalid; + assign v2e1_tready = v2e_qsfp_tready[1]; + + assign e2v1_tdata = e2v_qsfp_tdata[1*64 +: 64]; + assign e2v1_tlast = e2v_qsfp_tlast[1]; + assign e2v1_tvalid = e2v_qsfp_tvalid[1]; + assign e2v_qsfp_tready[1] = e2v1_tready; +`else + // SFP+ ports connects to DMA engines and crossbar + // Connect first SFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_sfp0_tx_tdata_b = arm_eth0_tx_tdata_b; + assign arm_eth_sfp0_tx_tvalid_b = arm_eth0_tx_tvalid_b; + assign arm_eth_sfp0_tx_tlast_b = arm_eth0_tx_tlast_b; + assign arm_eth0_tx_tready_b = arm_eth_sfp0_tx_tready_b; + assign arm_eth_sfp0_tx_tuser_b = arm_eth0_tx_tuser_b; + assign arm_eth_sfp0_tx_tkeep_b = arm_eth0_tx_tkeep_b; + + assign arm_eth0_rx_tdata_b = arm_eth_sfp0_rx_tdata_b; + assign arm_eth0_rx_tvalid_b = arm_eth_sfp0_rx_tvalid_b; + assign arm_eth0_rx_tlast_b = arm_eth_sfp0_rx_tlast_b; + assign arm_eth_sfp0_rx_tready_b = arm_eth0_rx_tready_b; + assign arm_eth0_rx_tuser_b = arm_eth_sfp0_rx_tuser_b; + assign arm_eth0_rx_tkeep_b = arm_eth_sfp0_rx_tkeep_b; + + // Connect first SFP+ 10 GbE port to the crossbar + assign v2e_sfp0_tdata = v2e0_tdata; + assign v2e_sfp0_tlast = v2e0_tlast; + assign v2e_sfp0_tvalid = v2e0_tvalid; + assign v2e0_tready = v2e_sfp0_tready; + + assign e2v0_tdata = e2v_sfp0_tdata; + assign e2v0_tlast = e2v_sfp0_tlast; + assign e2v0_tvalid = e2v_sfp0_tvalid; + assign e2v_sfp0_tready = e2v0_tready; + + // Connect second SFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_sfp1_tx_tdata_b = arm_eth1_tx_tdata_b; + assign arm_eth_sfp1_tx_tvalid_b = arm_eth1_tx_tvalid_b; + assign arm_eth_sfp1_tx_tlast_b = arm_eth1_tx_tlast_b; + assign arm_eth1_tx_tready_b = arm_eth_sfp1_tx_tready_b; + assign arm_eth_sfp1_tx_tuser_b = arm_eth1_tx_tuser_b; + assign arm_eth_sfp1_tx_tkeep_b = arm_eth1_tx_tkeep_b; + + assign arm_eth1_rx_tdata_b = arm_eth_sfp1_rx_tdata_b; + assign arm_eth1_rx_tvalid_b = arm_eth_sfp1_rx_tvalid_b; + assign arm_eth1_rx_tlast_b = arm_eth_sfp1_rx_tlast_b; + assign arm_eth_sfp1_rx_tready_b = arm_eth1_rx_tready_b; + assign arm_eth1_rx_tuser_b = arm_eth_sfp1_rx_tuser_b; + assign arm_eth1_rx_tkeep_b = arm_eth_sfp1_rx_tkeep_b; + + // Connect first SFP+ 10 GbE port to the crossbar + assign v2e_sfp1_tdata = v2e1_tdata; + assign v2e_sfp1_tlast = v2e1_tlast; + assign v2e_sfp1_tvalid = v2e1_tvalid; + assign v2e1_tready = v2e_sfp1_tready; + + assign e2v1_tdata = e2v_sfp1_tdata; + assign e2v1_tlast = e2v_sfp1_tlast; + assign e2v1_tvalid = e2v_sfp1_tvalid; + assign e2v_sfp1_tready = e2v1_tready; + + // Don't actually instantiate DMA engines if protocols can't use them + `ifdef SFP0_AURORA + `define NO_ETH_DMA_0 + `elsif SFP0_WR + `define NO_ETH_DMA_0 + `endif + + `ifdef SFP1_AURORA + `define NO_ETH_DMA_1 + `endif +`endif + +`ifdef NO_ETH_DMA_0 + //If inst Aurora, tie off each axi/axi-lite interface + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_sfp0_eth_dma ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_ETH_DMA0_AWADDR), + .s_axi_awvalid(M_AXI_ETH_DMA0_AWVALID), + .s_axi_awready(M_AXI_ETH_DMA0_AWREADY), + + .s_axi_wdata(M_AXI_ETH_DMA0_WDATA), + .s_axi_wvalid(M_AXI_ETH_DMA0_WVALID), + .s_axi_wready(M_AXI_ETH_DMA0_WREADY), + + .s_axi_bresp(M_AXI_ETH_DMA0_BRESP), + .s_axi_bvalid(M_AXI_ETH_DMA0_BVALID), + .s_axi_bready(M_AXI_ETH_DMA0_BREADY), + + .s_axi_araddr(M_AXI_ETH_DMA0_ARADDR), + .s_axi_arvalid(M_AXI_ETH_DMA0_ARVALID), + .s_axi_arready(M_AXI_ETH_DMA0_ARREADY), + + .s_axi_rdata(M_AXI_ETH_DMA0_RDATA), + .s_axi_rresp(M_AXI_ETH_DMA0_RRESP), + .s_axi_rvalid(M_AXI_ETH_DMA0_RVALID), + .s_axi_rready(M_AXI_ETH_DMA0_RREADY) + + ); + //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off + assign S_AXI_GP0_AWADDR = 32'h0; + assign S_AXI_GP0_AWLEN = 8'h0; + assign S_AXI_GP0_AWSIZE = 4'h0; + assign S_AXI_GP0_AWBURST = 3'h0; + assign S_AXI_GP0_AWPROT = 3'h0; + assign S_AXI_GP0_AWCACHE = 4'h0; + assign S_AXI_GP0_AWVALID = 1'b0; + //S_AXI_GP0_AWREADY output from PS + assign S_AXI_GP0_WDATA = 32'h0; + assign S_AXI_GP0_WSTRB = 4'h0; + assign S_AXI_GP0_WLAST = 1'b0; + assign S_AXI_GP0_WVALID = 1'b0; + //S_AXI_GP0_WREADY output from PS + //S_AXI_GP0_BRESP + //S_AXI_GP0_BVALID + assign S_AXI_GP0_BREADY = 1'b1; + assign S_AXI_GP0_ARADDR = 32'h0; + assign S_AXI_GP0_ARLEN = 8'h0; + assign S_AXI_GP0_ARSIZE = 3'h0; + assign S_AXI_GP0_ARBURST = 2'h0; + assign S_AXI_GP0_ARPROT = 3'h0; + assign S_AXI_GP0_ARCACHE = 4'h0; + assign S_AXI_GP0_ARVALID = 1'b0; + //S_AXI_GP0_ARREADY + //S_AXI_GP0_RDATA + //S_AXI_GP0_RRESP + //S_AXI_GP0_RLAST + //S_AXI_GP0_RVALID + assign S_AXI_GP0_RREADY = 1'b1; + + //S_AXI_HP0 from axi_eth_dma + assign S_AXI_HP0_ARADDR = 32'h0; + assign S_AXI_HP0_ARLEN = 8'h0; + assign S_AXI_HP0_ARSIZE = 3'h0; + assign S_AXI_HP0_ARBURST = 2'h0; + assign S_AXI_HP0_ARPROT = 3'h0; + assign S_AXI_HP0_ARCACHE = 4'h0; + assign S_AXI_HP0_ARVALID = 1'b0; + //S_AXI_HP0_ARREADY + //S_AXI_HP0_RDATA + //S_AXI_HP0_RRESP + //S_AXI_HP0_RLAST + //S_AXI_HP0_RVALID + assign S_AXI_HP0_RREADY = 1'b1; + assign S_AXI_HP0_AWADDR = 32'h0; + assign S_AXI_HP0_AWLEN = 8'h0; + assign S_AXI_HP0_AWSIZE = 3'h0; + assign S_AXI_HP0_AWBURST = 2'h0; + assign S_AXI_HP0_AWPROT = 3'h0; + assign S_AXI_HP0_AWCACHE = 4'h0; + assign S_AXI_HP0_AWVALID = 1'b0; + //S_AXI_HP0_AWREADY + assign S_AXI_HP0_WDATA = 64'h0; + assign S_AXI_HP0_WSTRB = 8'h0; + assign S_AXI_HP0_WLAST = 1'b0; + assign S_AXI_HP0_WVALID = 1'b0; + //S_AXI_HP0_WREADY + //S_AXI_HP0_BRESP + //S_AXI_HP0_BVALID + assign S_AXI_HP0_BREADY = 1'b1; + +`else + + axi_eth_dma inst_axi_eth_dma0 ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(M_AXI_ETH_DMA0_AWADDR), + .s_axi_lite_awvalid(M_AXI_ETH_DMA0_AWVALID), + .s_axi_lite_awready(M_AXI_ETH_DMA0_AWREADY), + + .s_axi_lite_wdata(M_AXI_ETH_DMA0_WDATA), + .s_axi_lite_wvalid(M_AXI_ETH_DMA0_WVALID), + .s_axi_lite_wready(M_AXI_ETH_DMA0_WREADY), + + .s_axi_lite_bresp(M_AXI_ETH_DMA0_BRESP), + .s_axi_lite_bvalid(M_AXI_ETH_DMA0_BVALID), + .s_axi_lite_bready(M_AXI_ETH_DMA0_BREADY), + + .s_axi_lite_araddr(M_AXI_ETH_DMA0_ARADDR), + .s_axi_lite_arvalid(M_AXI_ETH_DMA0_ARVALID), + .s_axi_lite_arready(M_AXI_ETH_DMA0_ARREADY), + + .s_axi_lite_rdata(M_AXI_ETH_DMA0_RDATA), + .s_axi_lite_rresp(M_AXI_ETH_DMA0_RRESP), + .s_axi_lite_rvalid(M_AXI_ETH_DMA0_RVALID), + .s_axi_lite_rready(M_AXI_ETH_DMA0_RREADY), + + .m_axi_sg_awaddr(S_AXI_GP0_AWADDR), + .m_axi_sg_awlen(S_AXI_GP0_AWLEN), + .m_axi_sg_awsize(S_AXI_GP0_AWSIZE), + .m_axi_sg_awburst(S_AXI_GP0_AWBURST), + .m_axi_sg_awprot(S_AXI_GP0_AWPROT), + .m_axi_sg_awcache(S_AXI_GP0_AWCACHE), + .m_axi_sg_awvalid(S_AXI_GP0_AWVALID), + .m_axi_sg_awready(S_AXI_GP0_AWREADY), + .m_axi_sg_wdata(S_AXI_GP0_WDATA), + .m_axi_sg_wstrb(S_AXI_GP0_WSTRB), + .m_axi_sg_wlast(S_AXI_GP0_WLAST), + .m_axi_sg_wvalid(S_AXI_GP0_WVALID), + .m_axi_sg_wready(S_AXI_GP0_WREADY), + .m_axi_sg_bresp(S_AXI_GP0_BRESP), + .m_axi_sg_bvalid(S_AXI_GP0_BVALID), + .m_axi_sg_bready(S_AXI_GP0_BREADY), + .m_axi_sg_araddr(S_AXI_GP0_ARADDR), + .m_axi_sg_arlen(S_AXI_GP0_ARLEN), + .m_axi_sg_arsize(S_AXI_GP0_ARSIZE), + .m_axi_sg_arburst(S_AXI_GP0_ARBURST), + .m_axi_sg_arprot(S_AXI_GP0_ARPROT), + .m_axi_sg_arcache(S_AXI_GP0_ARCACHE), + .m_axi_sg_arvalid(S_AXI_GP0_ARVALID), + .m_axi_sg_arready(S_AXI_GP0_ARREADY), + .m_axi_sg_rdata(S_AXI_GP0_RDATA), + .m_axi_sg_rresp(S_AXI_GP0_RRESP), + .m_axi_sg_rlast(S_AXI_GP0_RLAST), + .m_axi_sg_rvalid(S_AXI_GP0_RVALID), + .m_axi_sg_rready(S_AXI_GP0_RREADY), + + .m_axi_mm2s_araddr(S_AXI_HP0_ARADDR), + .m_axi_mm2s_arlen(S_AXI_HP0_ARLEN), + .m_axi_mm2s_arsize(S_AXI_HP0_ARSIZE), + .m_axi_mm2s_arburst(S_AXI_HP0_ARBURST), + .m_axi_mm2s_arprot(S_AXI_HP0_ARPROT), + .m_axi_mm2s_arcache(S_AXI_HP0_ARCACHE), + .m_axi_mm2s_arvalid(S_AXI_HP0_ARVALID), + .m_axi_mm2s_arready(S_AXI_HP0_ARREADY), + .m_axi_mm2s_rdata(S_AXI_HP0_RDATA), + .m_axi_mm2s_rresp(S_AXI_HP0_RRESP), + .m_axi_mm2s_rlast(S_AXI_HP0_RLAST), + .m_axi_mm2s_rvalid(S_AXI_HP0_RVALID), + .m_axi_mm2s_rready(S_AXI_HP0_RREADY), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth0_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth0_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth0_tx_tvalid), + .m_axis_mm2s_tready(arm_eth0_tx_tready), + .m_axis_mm2s_tlast(arm_eth0_tx_tlast), + + .m_axi_s2mm_awaddr(S_AXI_HP0_AWADDR), + .m_axi_s2mm_awlen(S_AXI_HP0_AWLEN), + .m_axi_s2mm_awsize(S_AXI_HP0_AWSIZE), + .m_axi_s2mm_awburst(S_AXI_HP0_AWBURST), + .m_axi_s2mm_awprot(S_AXI_HP0_AWPROT), + .m_axi_s2mm_awcache(S_AXI_HP0_AWCACHE), + .m_axi_s2mm_awvalid(S_AXI_HP0_AWVALID), + .m_axi_s2mm_awready(S_AXI_HP0_AWREADY), + .m_axi_s2mm_wdata(S_AXI_HP0_WDATA), + .m_axi_s2mm_wstrb(S_AXI_HP0_WSTRB), + .m_axi_s2mm_wlast(S_AXI_HP0_WLAST), + .m_axi_s2mm_wvalid(S_AXI_HP0_WVALID), + .m_axi_s2mm_wready(S_AXI_HP0_WREADY), + .m_axi_s2mm_bresp(S_AXI_HP0_BRESP), + .m_axi_s2mm_bvalid(S_AXI_HP0_BVALID), + .m_axi_s2mm_bready(S_AXI_HP0_BREADY), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth0_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth0_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth0_rx_tvalid), + .s_axis_s2mm_tready(arm_eth0_rx_tready), + .s_axis_s2mm_tlast(arm_eth0_rx_tlast), + + .mm2s_introut(arm_eth0_tx_irq), + .s2mm_introut(arm_eth0_rx_irq), + .axi_dma_tstvec() + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_tx_0_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth0_tx_tlast, arm_eth0_tx_tkeep, arm_eth0_tx_tdata}), + .i_tvalid(arm_eth0_tx_tvalid), + .i_tready(arm_eth0_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth0_tx_tlast_b, arm_eth0_tx_tkeep_b, arm_eth0_tx_tdata_b}), + .o_tvalid(arm_eth0_tx_tvalid_b), + .o_tready(arm_eth0_tx_tready_b) + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_rx_0_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth0_rx_tlast_b, arm_eth0_rx_tkeep_b, arm_eth0_rx_tdata_b}), + .i_tvalid(arm_eth0_rx_tvalid_b), + .i_tready(arm_eth0_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth0_rx_tlast, arm_eth0_rx_tkeep, arm_eth0_rx_tdata}), + .o_tvalid(arm_eth0_rx_tvalid), + .o_tready(arm_eth0_rx_tready) + ); + +`endif + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA 1 + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[2] = arm_eth1_rx_irq; + assign IRQ_F2P[3] = arm_eth1_tx_irq; + + assign {S_AXI_HP1_AWID, S_AXI_HP1_ARID} = 12'd0; + assign {S_AXI_GP1_AWID, S_AXI_GP1_ARID} = 10'd0; + +`ifdef NO_ETH_DMA_1 + //If inst Aurora, tie off each axi/axi-lite interface + axi_dummy #(.DEC_ERR(1'b0)) inst_axi_dummy_sfp1_eth_dma + ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_ETH_DMA1_AWADDR), + .s_axi_awvalid(M_AXI_ETH_DMA1_AWVALID), + .s_axi_awready(M_AXI_ETH_DMA1_AWREADY), + + .s_axi_wdata(M_AXI_ETH_DMA1_WDATA), + .s_axi_wvalid(M_AXI_ETH_DMA1_WVALID), + .s_axi_wready(M_AXI_ETH_DMA1_WREADY), + + .s_axi_bresp(M_AXI_ETH_DMA1_BRESP), + .s_axi_bvalid(M_AXI_ETH_DMA1_BVALID), + .s_axi_bready(M_AXI_ETH_DMA1_BREADY), + + .s_axi_araddr(M_AXI_ETH_DMA1_ARADDR), + .s_axi_arvalid(M_AXI_ETH_DMA1_ARVALID), + .s_axi_arready(M_AXI_ETH_DMA1_ARREADY), + + .s_axi_rdata(M_AXI_ETH_DMA1_RDATA), + .s_axi_rresp(M_AXI_ETH_DMA1_RRESP), + .s_axi_rvalid(M_AXI_ETH_DMA1_RVALID), + .s_axi_rready(M_AXI_ETH_DMA1_RREADY) + + ); + //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off + assign S_AXI_GP1_AWADDR = 32'h0; + assign S_AXI_GP1_AWLEN = 8'h0; + assign S_AXI_GP1_AWSIZE = 4'h0; + assign S_AXI_GP1_AWBURST = 3'h0; + assign S_AXI_GP1_AWPROT = 3'h0; + assign S_AXI_GP1_AWCACHE = 4'h0; + assign S_AXI_GP1_AWVALID = 1'b0; + //S_AXI_GP1_AWREADY output from PS + assign S_AXI_GP1_WDATA = 32'h0; + assign S_AXI_GP1_WSTRB = 4'h0; + assign S_AXI_GP1_WLAST = 1'b0; + assign S_AXI_GP1_WVALID = 1'b0; + //S_AXI_GP1_WREADY output from PS + //S_AXI_GP1_BRESP + //S_AXI_GP1_BVALID + assign S_AXI_GP1_BREADY = 1'b1; + assign S_AXI_GP1_ARADDR = 32'h0; + assign S_AXI_GP1_ARLEN = 8'h0; + assign S_AXI_GP1_ARSIZE = 3'h0; + assign S_AXI_GP1_ARBURST = 2'h0; + assign S_AXI_GP1_ARPROT = 3'h0; + assign S_AXI_GP1_ARCACHE = 4'h0; + assign S_AXI_GP1_ARVALID = 1'b0; + //S_AXI_GP1_ARREADY + //S_AXI_GP1_RDATA + //S_AXI_GP1_RRESP + //S_AXI_GP1_RLAST + //S_AXI_GP1_RVALID + assign S_AXI_GP1_RREADY = 1'b1; + + //S_AXI_HP0 from axi_eth_dma + assign S_AXI_HP1_ARADDR = 32'h0; + assign S_AXI_HP1_ARLEN = 8'h0; + assign S_AXI_HP1_ARSIZE = 3'h0; + assign S_AXI_HP1_ARBURST = 2'h0; + assign S_AXI_HP1_ARPROT = 3'h0; + assign S_AXI_HP1_ARCACHE = 4'h0; + assign S_AXI_HP1_ARVALID = 1'b0; + //S_AXI_HP1_ARREADY + //S_AXI_HP1_RDATA + //S_AXI_HP1_RRESP + //S_AXI_HP1_RLAST + //S_AXI_HP1_RVALID + assign S_AXI_HP1_RREADY = 1'b1; + assign S_AXI_HP1_AWADDR = 32'h0; + assign S_AXI_HP1_AWLEN = 8'h0; + assign S_AXI_HP1_AWSIZE = 3'h0; + assign S_AXI_HP1_AWBURST = 2'h0; + assign S_AXI_HP1_AWPROT = 3'h0; + assign S_AXI_HP1_AWCACHE = 4'h0; + assign S_AXI_HP1_AWVALID = 1'b0; + //S_AXI_HP1_AWREADY + assign S_AXI_HP1_WDATA = 64'h0; + assign S_AXI_HP1_WSTRB = 8'h0; + assign S_AXI_HP1_WLAST = 1'b0; + assign S_AXI_HP1_WVALID = 1'b0; + //S_AXI_HP1_WREADY + //S_AXI_HP1_BRESP + //S_AXI_HP1_BVALID + assign S_AXI_HP1_BREADY = 1'b1; + +`else + + axi_eth_dma inst_axi_eth_dma1 ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(M_AXI_ETH_DMA1_AWADDR), + .s_axi_lite_awvalid(M_AXI_ETH_DMA1_AWVALID), + .s_axi_lite_awready(M_AXI_ETH_DMA1_AWREADY), + + .s_axi_lite_wdata(M_AXI_ETH_DMA1_WDATA), + .s_axi_lite_wvalid(M_AXI_ETH_DMA1_WVALID), + .s_axi_lite_wready(M_AXI_ETH_DMA1_WREADY), + + .s_axi_lite_bresp(M_AXI_ETH_DMA1_BRESP), + .s_axi_lite_bvalid(M_AXI_ETH_DMA1_BVALID), + .s_axi_lite_bready(M_AXI_ETH_DMA1_BREADY), + + .s_axi_lite_araddr(M_AXI_ETH_DMA1_ARADDR), + .s_axi_lite_arvalid(M_AXI_ETH_DMA1_ARVALID), + .s_axi_lite_arready(M_AXI_ETH_DMA1_ARREADY), + + .s_axi_lite_rdata(M_AXI_ETH_DMA1_RDATA), + .s_axi_lite_rresp(M_AXI_ETH_DMA1_RRESP), + .s_axi_lite_rvalid(M_AXI_ETH_DMA1_RVALID), + .s_axi_lite_rready(M_AXI_ETH_DMA1_RREADY), + + .m_axi_sg_awaddr(S_AXI_GP1_AWADDR), + .m_axi_sg_awlen(S_AXI_GP1_AWLEN), + .m_axi_sg_awsize(S_AXI_GP1_AWSIZE), + .m_axi_sg_awburst(S_AXI_GP1_AWBURST), + .m_axi_sg_awprot(S_AXI_GP1_AWPROT), + .m_axi_sg_awcache(S_AXI_GP1_AWCACHE), + .m_axi_sg_awvalid(S_AXI_GP1_AWVALID), + .m_axi_sg_awready(S_AXI_GP1_AWREADY), + .m_axi_sg_wdata(S_AXI_GP1_WDATA), + .m_axi_sg_wstrb(S_AXI_GP1_WSTRB), + .m_axi_sg_wlast(S_AXI_GP1_WLAST), + .m_axi_sg_wvalid(S_AXI_GP1_WVALID), + .m_axi_sg_wready(S_AXI_GP1_WREADY), + .m_axi_sg_bresp(S_AXI_GP1_BRESP), + .m_axi_sg_bvalid(S_AXI_GP1_BVALID), + .m_axi_sg_bready(S_AXI_GP1_BREADY), + .m_axi_sg_araddr(S_AXI_GP1_ARADDR), + .m_axi_sg_arlen(S_AXI_GP1_ARLEN), + .m_axi_sg_arsize(S_AXI_GP1_ARSIZE), + .m_axi_sg_arburst(S_AXI_GP1_ARBURST), + .m_axi_sg_arprot(S_AXI_GP1_ARPROT), + .m_axi_sg_arcache(S_AXI_GP1_ARCACHE), + .m_axi_sg_arvalid(S_AXI_GP1_ARVALID), + .m_axi_sg_arready(S_AXI_GP1_ARREADY), + .m_axi_sg_rdata(S_AXI_GP1_RDATA), + .m_axi_sg_rresp(S_AXI_GP1_RRESP), + .m_axi_sg_rlast(S_AXI_GP1_RLAST), + .m_axi_sg_rvalid(S_AXI_GP1_RVALID), + .m_axi_sg_rready(S_AXI_GP1_RREADY), + + .m_axi_mm2s_araddr(S_AXI_HP1_ARADDR), + .m_axi_mm2s_arlen(S_AXI_HP1_ARLEN), + .m_axi_mm2s_arsize(S_AXI_HP1_ARSIZE), + .m_axi_mm2s_arburst(S_AXI_HP1_ARBURST), + .m_axi_mm2s_arprot(S_AXI_HP1_ARPROT), + .m_axi_mm2s_arcache(S_AXI_HP1_ARCACHE), + .m_axi_mm2s_arvalid(S_AXI_HP1_ARVALID), + .m_axi_mm2s_arready(S_AXI_HP1_ARREADY), + .m_axi_mm2s_rdata(S_AXI_HP1_RDATA), + .m_axi_mm2s_rresp(S_AXI_HP1_RRESP), + .m_axi_mm2s_rlast(S_AXI_HP1_RLAST), + .m_axi_mm2s_rvalid(S_AXI_HP1_RVALID), + .m_axi_mm2s_rready(S_AXI_HP1_RREADY), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth1_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth1_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth1_tx_tvalid), + .m_axis_mm2s_tready(arm_eth1_tx_tready), + .m_axis_mm2s_tlast(arm_eth1_tx_tlast), + + .m_axi_s2mm_awaddr(S_AXI_HP1_AWADDR), + .m_axi_s2mm_awlen(S_AXI_HP1_AWLEN), + .m_axi_s2mm_awsize(S_AXI_HP1_AWSIZE), + .m_axi_s2mm_awburst(S_AXI_HP1_AWBURST), + .m_axi_s2mm_awprot(S_AXI_HP1_AWPROT), + .m_axi_s2mm_awcache(S_AXI_HP1_AWCACHE), + .m_axi_s2mm_awvalid(S_AXI_HP1_AWVALID), + .m_axi_s2mm_awready(S_AXI_HP1_AWREADY), + .m_axi_s2mm_wdata(S_AXI_HP1_WDATA), + .m_axi_s2mm_wstrb(S_AXI_HP1_WSTRB), + .m_axi_s2mm_wlast(S_AXI_HP1_WLAST), + .m_axi_s2mm_wvalid(S_AXI_HP1_WVALID), + .m_axi_s2mm_wready(S_AXI_HP1_WREADY), + .m_axi_s2mm_bresp(S_AXI_HP1_BRESP), + .m_axi_s2mm_bvalid(S_AXI_HP1_BVALID), + .m_axi_s2mm_bready(S_AXI_HP1_BREADY), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth1_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth1_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth1_rx_tvalid), + .s_axis_s2mm_tready(arm_eth1_rx_tready), + .s_axis_s2mm_tlast(arm_eth1_rx_tlast), + + .mm2s_introut(arm_eth1_tx_irq), + .s2mm_introut(arm_eth1_rx_irq), + .axi_dma_tstvec() + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_tx_1_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth1_tx_tlast, arm_eth1_tx_tkeep, arm_eth1_tx_tdata}), + .i_tvalid(arm_eth1_tx_tvalid), + .i_tready(arm_eth1_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth1_tx_tlast_b, arm_eth1_tx_tkeep_b, arm_eth1_tx_tdata_b}), + .o_tvalid(arm_eth1_tx_tvalid_b), + .o_tready(arm_eth1_tx_tready_b) + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_rx_1_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth1_rx_tlast_b, arm_eth1_rx_tkeep_b, arm_eth1_rx_tdata_b}), + .i_tvalid(arm_eth1_rx_tvalid_b), + .i_tready(arm_eth1_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth1_rx_tlast, arm_eth1_rx_tkeep, arm_eth1_rx_tdata}), + .o_tvalid(arm_eth1_rx_tvalid), + .o_tready(arm_eth1_rx_tready) + ); +`endif + + ///////////////////////////////////////////////////////////////////// + // + // Processing System + // + ////////////////////////////////////////////////////////////////////// + + wire spi0_sclk; + wire spi0_mosi; + wire spi0_miso; + wire spi0_ss0; + wire spi0_ss1; + wire spi0_ss2; + wire spi1_sclk; + wire spi1_mosi; + wire spi1_miso; + wire spi1_ss0; + wire spi1_ss1; + wire spi1_ss2; + + assign DBA_MODULE_PWR_ENABLE = ps_gpio_out[8]; + assign DBA_RF_PWR_ENABLE = ps_gpio_out[9]; + assign DBB_MODULE_PWR_ENABLE = ps_gpio_out[10]; + assign DBB_RF_PWR_ENABLE = ps_gpio_out[11]; + assign ps_gpio_in[8] = DBA_MODULE_PWR_ENABLE; + assign ps_gpio_in[9] = DBA_RF_PWR_ENABLE; + assign ps_gpio_in[10] = DBB_MODULE_PWR_ENABLE; + assign ps_gpio_in[11] = DBB_RF_PWR_ENABLE; + + // Processing System + n310_ps_bd inst_n310_ps ( + .SPI0_SCLK_I(1'b0), + .SPI0_SCLK_O(spi0_sclk), + .SPI0_SCLK_T(), + .SPI0_MOSI_I(1'b0), + .SPI0_MOSI_O(spi0_mosi), + .SPI0_MOSI_T(), + .SPI0_MISO_I(spi0_miso), + .SPI0_MISO_O(), + .SPI0_MISO_T(), + .SPI0_SS_I(1'b1), + .SPI0_SS_O(spi0_ss0), + .SPI0_SS1_O(spi0_ss1), + .SPI0_SS2_O(spi0_ss2), + .SPI0_SS_T(), + + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(spi1_sclk), + .SPI1_SCLK_T(), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(spi1_mosi), + .SPI1_MOSI_T(), + .SPI1_MISO_I(spi1_miso), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_SS_I(1'b1), + .SPI1_SS_O(spi1_ss0), + .SPI1_SS1_O(spi1_ss1), + .SPI1_SS2_O(spi1_ss2), + .SPI1_SS_T(), + + .bus_clk(bus_clk), + .bus_rstn(~bus_rst), + .clk40(clk40), + .clk40_rstn(clk40_rstn), + + .M_AXI_ETH_DMA0_araddr(M_AXI_ETH_DMA0_ARADDR), + .M_AXI_ETH_DMA0_arprot(), + .M_AXI_ETH_DMA0_arready(M_AXI_ETH_DMA0_ARREADY), + .M_AXI_ETH_DMA0_arvalid(M_AXI_ETH_DMA0_ARVALID), + + .M_AXI_ETH_DMA0_awaddr(M_AXI_ETH_DMA0_AWADDR), + .M_AXI_ETH_DMA0_awprot(), + .M_AXI_ETH_DMA0_awready(M_AXI_ETH_DMA0_AWREADY), + .M_AXI_ETH_DMA0_awvalid(M_AXI_ETH_DMA0_AWVALID), + + .M_AXI_ETH_DMA0_wdata(M_AXI_ETH_DMA0_WDATA), + .M_AXI_ETH_DMA0_wready(M_AXI_ETH_DMA0_WREADY), + .M_AXI_ETH_DMA0_wstrb(M_AXI_ETH_DMA0_WSTRB), + .M_AXI_ETH_DMA0_wvalid(M_AXI_ETH_DMA0_WVALID), + + .M_AXI_ETH_DMA0_rdata(M_AXI_ETH_DMA0_RDATA), + .M_AXI_ETH_DMA0_rready(M_AXI_ETH_DMA0_RREADY), + .M_AXI_ETH_DMA0_rresp(M_AXI_ETH_DMA0_RRESP), + .M_AXI_ETH_DMA0_rvalid(M_AXI_ETH_DMA0_RVALID), + + .M_AXI_ETH_DMA0_bready(M_AXI_ETH_DMA0_BREADY), + .M_AXI_ETH_DMA0_bresp(M_AXI_ETH_DMA0_BRESP), + .M_AXI_ETH_DMA0_bvalid(M_AXI_ETH_DMA0_BVALID), + + .M_AXI_ETH_DMA1_araddr(M_AXI_ETH_DMA1_ARADDR), + .M_AXI_ETH_DMA1_arprot(), + .M_AXI_ETH_DMA1_arready(M_AXI_ETH_DMA1_ARREADY), + .M_AXI_ETH_DMA1_arvalid(M_AXI_ETH_DMA1_ARVALID), + + .M_AXI_ETH_DMA1_awaddr(M_AXI_ETH_DMA1_AWADDR), + .M_AXI_ETH_DMA1_awprot(), + .M_AXI_ETH_DMA1_awready(M_AXI_ETH_DMA1_AWREADY), + .M_AXI_ETH_DMA1_awvalid(M_AXI_ETH_DMA1_AWVALID), + + .M_AXI_ETH_DMA1_bready(M_AXI_ETH_DMA1_BREADY), + .M_AXI_ETH_DMA1_bresp(M_AXI_ETH_DMA1_BRESP), + .M_AXI_ETH_DMA1_bvalid(M_AXI_ETH_DMA1_BVALID), + + .M_AXI_ETH_DMA1_rdata(M_AXI_ETH_DMA1_RDATA), + .M_AXI_ETH_DMA1_rready(M_AXI_ETH_DMA1_RREADY), + .M_AXI_ETH_DMA1_rresp(M_AXI_ETH_DMA1_RRESP), + .M_AXI_ETH_DMA1_rvalid(M_AXI_ETH_DMA1_RVALID), + + .M_AXI_ETH_DMA1_wdata(M_AXI_ETH_DMA1_WDATA), + .M_AXI_ETH_DMA1_wready(M_AXI_ETH_DMA1_WREADY), + .M_AXI_ETH_DMA1_wstrb(M_AXI_ETH_DMA1_WSTRB), + .M_AXI_ETH_DMA1_wvalid(M_AXI_ETH_DMA1_WVALID), + + .M_AXI_JESD0_araddr(M_AXI_JESD0_ARADDR), + .M_AXI_JESD0_arprot(), + .M_AXI_JESD0_arready(M_AXI_JESD0_ARREADY), + .M_AXI_JESD0_arvalid(M_AXI_JESD0_ARVALID), + + .M_AXI_JESD0_awaddr(M_AXI_JESD0_AWADDR), + .M_AXI_JESD0_awprot(), + .M_AXI_JESD0_awready(M_AXI_JESD0_AWREADY), + .M_AXI_JESD0_awvalid(M_AXI_JESD0_AWVALID), + + .M_AXI_JESD0_bready(M_AXI_JESD0_BREADY), + .M_AXI_JESD0_bresp(M_AXI_JESD0_BRESP), + .M_AXI_JESD0_bvalid(M_AXI_JESD0_BVALID), + + .M_AXI_JESD0_rdata(M_AXI_JESD0_RDATA), + .M_AXI_JESD0_rready(M_AXI_JESD0_RREADY), + .M_AXI_JESD0_rresp(M_AXI_JESD0_RRESP), + .M_AXI_JESD0_rvalid(M_AXI_JESD0_RVALID), + + .M_AXI_JESD0_wdata(M_AXI_JESD0_WDATA), + .M_AXI_JESD0_wready(M_AXI_JESD0_WREADY), + .M_AXI_JESD0_wstrb(M_AXI_JESD0_WSTRB), + .M_AXI_JESD0_wvalid(M_AXI_JESD0_WVALID), + + .M_AXI_JESD1_araddr(M_AXI_JESD1_ARADDR), + .M_AXI_JESD1_arprot(), + .M_AXI_JESD1_arready(M_AXI_JESD1_ARREADY), + .M_AXI_JESD1_arvalid(M_AXI_JESD1_ARVALID), + + .M_AXI_JESD1_awaddr(M_AXI_JESD1_AWADDR), + .M_AXI_JESD1_awprot(), + .M_AXI_JESD1_awready(M_AXI_JESD1_AWREADY), + .M_AXI_JESD1_awvalid(M_AXI_JESD1_AWVALID), + + .M_AXI_JESD1_bready(M_AXI_JESD1_BREADY), + .M_AXI_JESD1_bresp(M_AXI_JESD1_BRESP), + .M_AXI_JESD1_bvalid(M_AXI_JESD1_BVALID), + + .M_AXI_JESD1_rdata(M_AXI_JESD1_RDATA), + .M_AXI_JESD1_rready(M_AXI_JESD1_RREADY), + .M_AXI_JESD1_rresp(M_AXI_JESD1_RRESP), + .M_AXI_JESD1_rvalid(M_AXI_JESD1_RVALID), + + .M_AXI_JESD1_wdata(M_AXI_JESD1_WDATA), + .M_AXI_JESD1_wready(M_AXI_JESD1_WREADY), + .M_AXI_JESD1_wstrb(M_AXI_JESD1_WSTRB), + .M_AXI_JESD1_wvalid(M_AXI_JESD1_WVALID), + + .M_AXI_NET0_araddr(M_AXI_NET0_ARADDR), + .M_AXI_NET0_arprot(), + .M_AXI_NET0_arready(M_AXI_NET0_ARREADY), + .M_AXI_NET0_arvalid(M_AXI_NET0_ARVALID), + + .M_AXI_NET0_awaddr(M_AXI_NET0_AWADDR), + .M_AXI_NET0_awprot(), + .M_AXI_NET0_awready(M_AXI_NET0_AWREADY), + .M_AXI_NET0_awvalid(M_AXI_NET0_AWVALID), + + .M_AXI_NET0_bready(M_AXI_NET0_BREADY), + .M_AXI_NET0_bresp(M_AXI_NET0_BRESP), + .M_AXI_NET0_bvalid(M_AXI_NET0_BVALID), + + .M_AXI_NET0_rdata(M_AXI_NET0_RDATA), + .M_AXI_NET0_rready(M_AXI_NET0_RREADY), + .M_AXI_NET0_rresp(M_AXI_NET0_RRESP), + .M_AXI_NET0_rvalid(M_AXI_NET0_RVALID), + + .M_AXI_NET0_wdata(M_AXI_NET0_WDATA), + .M_AXI_NET0_wready(M_AXI_NET0_WREADY), + .M_AXI_NET0_wstrb(M_AXI_NET0_WSTRB), + .M_AXI_NET0_wvalid(M_AXI_NET0_WVALID), + + .M_AXI_NET1_araddr(M_AXI_NET1_ARADDR), + .M_AXI_NET1_arprot(), + .M_AXI_NET1_arready(M_AXI_NET1_ARREADY), + .M_AXI_NET1_arvalid(M_AXI_NET1_ARVALID), + + .M_AXI_NET1_awaddr(M_AXI_NET1_AWADDR), + .M_AXI_NET1_awprot(), + .M_AXI_NET1_awready(M_AXI_NET1_AWREADY), + .M_AXI_NET1_awvalid(M_AXI_NET1_AWVALID), + + .M_AXI_NET1_bready(M_AXI_NET1_BREADY), + .M_AXI_NET1_bresp(M_AXI_NET1_BRESP), + .M_AXI_NET1_bvalid(M_AXI_NET1_BVALID), + + .M_AXI_NET1_rdata(M_AXI_NET1_RDATA), + .M_AXI_NET1_rready(M_AXI_NET1_RREADY), + .M_AXI_NET1_rresp(M_AXI_NET1_RRESP), + .M_AXI_NET1_rvalid(M_AXI_NET1_RVALID), + + .M_AXI_NET1_wdata(M_AXI_NET1_WDATA), + .M_AXI_NET1_wready(M_AXI_NET1_WREADY), + .M_AXI_NET1_wstrb(M_AXI_NET1_WSTRB), + .M_AXI_NET1_wvalid(M_AXI_NET1_WVALID), + + .M_AXI_NET2_araddr(M_AXI_NET2_ARADDR), + .M_AXI_NET2_arprot(), + .M_AXI_NET2_arready(M_AXI_NET2_ARREADY), + .M_AXI_NET2_arvalid(M_AXI_NET2_ARVALID), + + .M_AXI_NET2_awaddr(M_AXI_NET2_AWADDR), + .M_AXI_NET2_awprot(), + .M_AXI_NET2_awready(M_AXI_NET2_AWREADY), + .M_AXI_NET2_awvalid(M_AXI_NET2_AWVALID), + + .M_AXI_NET2_bready(M_AXI_NET2_BREADY), + .M_AXI_NET2_bresp(M_AXI_NET2_BRESP), + .M_AXI_NET2_bvalid(M_AXI_NET2_BVALID), + + .M_AXI_NET2_rdata(M_AXI_NET2_RDATA), + .M_AXI_NET2_rready(M_AXI_NET2_RREADY), + .M_AXI_NET2_rresp(M_AXI_NET2_RRESP), + .M_AXI_NET2_rvalid(M_AXI_NET2_RVALID), + + .M_AXI_NET2_wdata(M_AXI_NET2_WDATA), + .M_AXI_NET2_wready(M_AXI_NET2_WREADY), + .M_AXI_NET2_wstrb(M_AXI_NET2_WSTRB), + .M_AXI_NET2_wvalid(M_AXI_NET2_WVALID), + + .M_AXI_WR_CLK(m_axi_wr_clk), + .M_AXI_WR_RSTn(1'b1), + .M_AXI_WR_araddr(m_axi_wr_araddr), + .M_AXI_WR_arready(m_axi_wr_arready), + .M_AXI_WR_arvalid(m_axi_wr_arvalid), + .M_AXI_WR_arprot(), + .M_AXI_WR_awaddr(m_axi_wr_awaddr), + .M_AXI_WR_awready(m_axi_wr_awready), + .M_AXI_WR_awvalid(m_axi_wr_awvalid), + .M_AXI_WR_awprot(), + .M_AXI_WR_bready(m_axi_wr_bready), + .M_AXI_WR_bresp(m_axi_wr_bresp), + .M_AXI_WR_bvalid(m_axi_wr_bvalid), + .M_AXI_WR_rdata(m_axi_wr_rdata), + .M_AXI_WR_rready(m_axi_wr_rready), + .M_AXI_WR_rresp(m_axi_wr_rresp), + .M_AXI_WR_rvalid(m_axi_wr_rvalid), + .M_AXI_WR_wdata(m_axi_wr_wdata), + .M_AXI_WR_wready(m_axi_wr_wready), + .M_AXI_WR_wstrb(m_axi_wr_wstrb), + .M_AXI_WR_wvalid(m_axi_wr_wvalid), + + .M_AXI_XBAR_araddr(M_AXI_XBAR_ARADDR), + .M_AXI_XBAR_arprot(), + .M_AXI_XBAR_arready(M_AXI_XBAR_ARREADY), + .M_AXI_XBAR_arvalid(M_AXI_XBAR_ARVALID), + + .M_AXI_XBAR_awaddr(M_AXI_XBAR_AWADDR), + .M_AXI_XBAR_awprot(), + .M_AXI_XBAR_awready(M_AXI_XBAR_AWREADY), + .M_AXI_XBAR_awvalid(M_AXI_XBAR_AWVALID), + + .M_AXI_XBAR_bready(M_AXI_XBAR_BREADY), + .M_AXI_XBAR_bresp(M_AXI_XBAR_BRESP), + .M_AXI_XBAR_bvalid(M_AXI_XBAR_BVALID), + + .M_AXI_XBAR_rdata(M_AXI_XBAR_RDATA), + .M_AXI_XBAR_rready(M_AXI_XBAR_RREADY), + .M_AXI_XBAR_rresp(M_AXI_XBAR_RRESP), + .M_AXI_XBAR_rvalid(M_AXI_XBAR_RVALID), + + .M_AXI_XBAR_wdata(M_AXI_XBAR_WDATA), + .M_AXI_XBAR_wready(M_AXI_XBAR_WREADY), + .M_AXI_XBAR_wstrb(M_AXI_XBAR_WSTRB), + .M_AXI_XBAR_wvalid(M_AXI_XBAR_WVALID), + + .S_AXI_GP0_ACLK(clk40), + .S_AXI_GP0_ARESETN(clk40_rstn), + .S_AXI_GP0_araddr(S_AXI_GP0_ARADDR), + .S_AXI_GP0_arburst(S_AXI_GP0_ARBURST), + .S_AXI_GP0_arcache(S_AXI_GP0_ARCACHE), + .S_AXI_GP0_arid(S_AXI_GP0_ARID), + .S_AXI_GP0_arlen(S_AXI_GP0_ARLEN), + .S_AXI_GP0_arlock(1'b0), + .S_AXI_GP0_arprot(S_AXI_GP0_ARPROT), + .S_AXI_GP0_arqos(4'b0000), + .S_AXI_GP0_arready(S_AXI_GP0_ARREADY), + .S_AXI_GP0_arregion(4'b0000), + .S_AXI_GP0_arsize(S_AXI_GP0_ARSIZE), + .S_AXI_GP0_arvalid(S_AXI_GP0_ARVALID), + .S_AXI_GP0_awaddr(S_AXI_GP0_AWADDR), + .S_AXI_GP0_awburst(S_AXI_GP0_AWBURST), + .S_AXI_GP0_awcache(S_AXI_GP0_AWCACHE), + .S_AXI_GP0_awid(S_AXI_GP0_AWID), + .S_AXI_GP0_awlen(S_AXI_GP0_AWLEN), + .S_AXI_GP0_awlock(1'b0), + .S_AXI_GP0_awprot(S_AXI_GP0_AWPROT), + .S_AXI_GP0_awqos(4'b0000), + .S_AXI_GP0_awregion(4'b0000), + .S_AXI_GP0_awready(S_AXI_GP0_AWREADY), + .S_AXI_GP0_awsize(S_AXI_GP0_AWSIZE), + .S_AXI_GP0_awvalid(S_AXI_GP0_AWVALID), + .S_AXI_GP0_bid(), + .S_AXI_GP0_bready(S_AXI_GP0_BREADY), + .S_AXI_GP0_bresp(S_AXI_GP0_BRESP), + .S_AXI_GP0_bvalid(S_AXI_GP0_BVALID), + .S_AXI_GP0_rdata(S_AXI_GP0_RDATA), + .S_AXI_GP0_rid(), + .S_AXI_GP0_rlast(S_AXI_GP0_RLAST), + .S_AXI_GP0_rready(S_AXI_GP0_RREADY), + .S_AXI_GP0_rresp(S_AXI_GP0_RRESP), + .S_AXI_GP0_rvalid(S_AXI_GP0_RVALID), + .S_AXI_GP0_wdata(S_AXI_GP0_WDATA), + .S_AXI_GP0_wlast(S_AXI_GP0_WLAST), + .S_AXI_GP0_wready(S_AXI_GP0_WREADY), + .S_AXI_GP0_wstrb(S_AXI_GP0_WSTRB), + .S_AXI_GP0_wvalid(S_AXI_GP0_WVALID), + + .S_AXI_GP1_ACLK(clk40), + .S_AXI_GP1_ARESETN(clk40_rstn), + .S_AXI_GP1_araddr(S_AXI_GP1_ARADDR), + .S_AXI_GP1_arburst(S_AXI_GP1_ARBURST), + .S_AXI_GP1_arcache(S_AXI_GP1_ARCACHE), + .S_AXI_GP1_arid(S_AXI_GP1_ARID), + .S_AXI_GP1_arlen(S_AXI_GP1_ARLEN), + .S_AXI_GP1_arlock(1'b0), + .S_AXI_GP1_arprot(S_AXI_GP1_ARPROT), + .S_AXI_GP1_arqos(4'b000), + .S_AXI_GP1_arregion(4'b0000), + .S_AXI_GP1_arready(S_AXI_GP1_ARREADY), + .S_AXI_GP1_arsize(S_AXI_GP1_ARSIZE), + .S_AXI_GP1_arvalid(S_AXI_GP1_ARVALID), + .S_AXI_GP1_awaddr(S_AXI_GP1_AWADDR), + .S_AXI_GP1_awburst(S_AXI_GP1_AWBURST), + .S_AXI_GP1_awcache(S_AXI_GP1_AWCACHE), + .S_AXI_GP1_awid(S_AXI_GP1_AWID), + .S_AXI_GP1_awlen(S_AXI_GP1_AWLEN), + .S_AXI_GP1_awlock(1'b0), + .S_AXI_GP1_awprot(S_AXI_GP1_AWPROT), + .S_AXI_GP1_awqos(4'b0000), + .S_AXI_GP1_awregion(4'b0000), + .S_AXI_GP1_awready(S_AXI_GP1_AWREADY), + .S_AXI_GP1_awsize(S_AXI_GP1_AWSIZE), + .S_AXI_GP1_awvalid(S_AXI_GP1_AWVALID), + .S_AXI_GP1_bid(), + .S_AXI_GP1_bready(S_AXI_GP1_BREADY), + .S_AXI_GP1_bresp(S_AXI_GP1_BRESP), + .S_AXI_GP1_bvalid(S_AXI_GP1_BVALID), + .S_AXI_GP1_rdata(S_AXI_GP1_RDATA), + .S_AXI_GP1_rid(), + .S_AXI_GP1_rlast(S_AXI_GP1_RLAST), + .S_AXI_GP1_rready(S_AXI_GP1_RREADY), + .S_AXI_GP1_rresp(S_AXI_GP1_RRESP), + .S_AXI_GP1_rvalid(S_AXI_GP1_RVALID), + .S_AXI_GP1_wdata(S_AXI_GP1_WDATA), + .S_AXI_GP1_wlast(S_AXI_GP1_WLAST), + .S_AXI_GP1_wready(S_AXI_GP1_WREADY), + .S_AXI_GP1_wstrb(S_AXI_GP1_WSTRB), + .S_AXI_GP1_wvalid(S_AXI_GP1_WVALID), + + .S_AXI_HP0_ACLK(clk40), + .S_AXI_HP0_ARESETN(clk40_rstn), + .S_AXI_HP0_araddr(S_AXI_HP0_ARADDR), + .S_AXI_HP0_arburst(S_AXI_HP0_ARBURST), + .S_AXI_HP0_arcache(S_AXI_HP0_ARCACHE), + .S_AXI_HP0_arid(S_AXI_HP0_ARID), + .S_AXI_HP0_arlen(S_AXI_HP0_ARLEN), + .S_AXI_HP0_arlock(1'b0), + .S_AXI_HP0_arprot(S_AXI_HP0_ARPROT), + .S_AXI_HP0_arqos(4'b0000), + .S_AXI_HP0_arready(S_AXI_HP0_ARREADY), + .S_AXI_HP0_arsize(S_AXI_HP0_ARSIZE), + .S_AXI_HP0_arvalid(S_AXI_HP0_ARVALID), + .S_AXI_HP0_awaddr(S_AXI_HP0_AWADDR), + .S_AXI_HP0_awburst(S_AXI_HP0_AWBURST), + .S_AXI_HP0_awcache(S_AXI_HP0_AWCACHE), + .S_AXI_HP0_awid(S_AXI_HP0_AWID), + .S_AXI_HP0_awlen(S_AXI_HP0_AWLEN), + .S_AXI_HP0_awlock(1'b0), + .S_AXI_HP0_awprot(S_AXI_HP0_AWPROT), + .S_AXI_HP0_awqos(4'b0000), + .S_AXI_HP0_awready(S_AXI_HP0_AWREADY), + .S_AXI_HP0_awsize(S_AXI_HP0_AWSIZE), + .S_AXI_HP0_awvalid(S_AXI_HP0_AWVALID), + .S_AXI_HP0_bid(), + .S_AXI_HP0_bready(S_AXI_HP0_BREADY), + .S_AXI_HP0_bresp(S_AXI_HP0_BRESP), + .S_AXI_HP0_bvalid(S_AXI_HP0_BVALID), + .S_AXI_HP0_rdata(S_AXI_HP0_RDATA), + .S_AXI_HP0_rid(), + .S_AXI_HP0_rlast(S_AXI_HP0_RLAST), + .S_AXI_HP0_rready(S_AXI_HP0_RREADY), + .S_AXI_HP0_rresp(S_AXI_HP0_RRESP), + .S_AXI_HP0_rvalid(S_AXI_HP0_RVALID), + .S_AXI_HP0_wdata(S_AXI_HP0_WDATA), + .S_AXI_HP0_wlast(S_AXI_HP0_WLAST), + .S_AXI_HP0_wready(S_AXI_HP0_WREADY), + .S_AXI_HP0_wstrb(S_AXI_HP0_WSTRB), + .S_AXI_HP0_wvalid(S_AXI_HP0_WVALID), + + .S_AXI_HP1_ACLK(clk40), + .S_AXI_HP1_ARESETN(clk40_rstn), + .S_AXI_HP1_araddr(S_AXI_HP1_ARADDR), + .S_AXI_HP1_arburst(S_AXI_HP1_ARBURST), + .S_AXI_HP1_arcache(S_AXI_HP1_ARCACHE), + .S_AXI_HP1_arid(S_AXI_HP1_ARID), + .S_AXI_HP1_arlen(S_AXI_HP1_ARLEN), + .S_AXI_HP1_arlock(1'b0), + .S_AXI_HP1_arprot(S_AXI_HP1_ARPROT), + .S_AXI_HP1_arqos(4'b0000), + .S_AXI_HP1_arready(S_AXI_HP1_ARREADY), + .S_AXI_HP1_arsize(S_AXI_HP1_ARSIZE), + .S_AXI_HP1_arvalid(S_AXI_HP1_ARVALID), + .S_AXI_HP1_awaddr(S_AXI_HP1_AWADDR), + .S_AXI_HP1_awburst(S_AXI_HP1_AWBURST), + .S_AXI_HP1_awcache(S_AXI_HP1_AWCACHE), + .S_AXI_HP1_awid(S_AXI_HP1_AWID), + .S_AXI_HP1_awlen(S_AXI_HP1_AWLEN), + .S_AXI_HP1_awlock(1'b0), + .S_AXI_HP1_awprot(S_AXI_HP1_AWPROT), + .S_AXI_HP1_awqos(4'b0000), + .S_AXI_HP1_awready(S_AXI_HP1_AWREADY), + .S_AXI_HP1_awsize(S_AXI_HP1_AWSIZE), + .S_AXI_HP1_awvalid(S_AXI_HP1_AWVALID), + .S_AXI_HP1_bid(), + .S_AXI_HP1_bready(S_AXI_HP1_BREADY), + .S_AXI_HP1_bresp(S_AXI_HP1_BRESP), + .S_AXI_HP1_bvalid(S_AXI_HP1_BVALID), + .S_AXI_HP1_rdata(S_AXI_HP1_RDATA), + .S_AXI_HP1_rid(), + .S_AXI_HP1_rlast(S_AXI_HP1_RLAST), + .S_AXI_HP1_rready(S_AXI_HP1_RREADY), + .S_AXI_HP1_rresp(S_AXI_HP1_RRESP), + .S_AXI_HP1_rvalid(S_AXI_HP1_RVALID), + .S_AXI_HP1_wdata(S_AXI_HP1_WDATA), + .S_AXI_HP1_wlast(S_AXI_HP1_WLAST), + .S_AXI_HP1_wready(S_AXI_HP1_WREADY), + .S_AXI_HP1_wstrb(S_AXI_HP1_WSTRB), + .S_AXI_HP1_wvalid(S_AXI_HP1_WVALID), + + // ARM DMA + .s_axis_dma_tdata(s_axis_dma_tdata), + .s_axis_dma_tdest(s_axis_dma_tdest), + .s_axis_dma_tlast(s_axis_dma_tlast), + .s_axis_dma_tready(s_axis_dma_tready), + .s_axis_dma_tvalid(s_axis_dma_tvalid), + .m_axis_dma_tdata(m_axis_dma_tdata), + .m_axis_dma_tuser(m_axis_dma_tuser), + .m_axis_dma_tlast(m_axis_dma_tlast), + .m_axis_dma_tready(m_axis_dma_tready), + .m_axis_dma_tvalid(m_axis_dma_tvalid), + + // Misc Interrupts, GPIO, clk + .IRQ_F2P(IRQ_F2P), + + .GPIO_0_tri_i(ps_gpio_in), + .GPIO_0_tri_o(ps_gpio_out), + .GPIO_0_tri_t(ps_gpio_tri), + + .JTAG0_TCK(DBA_CPLD_JTAG_TCK), + .JTAG0_TMS(DBA_CPLD_JTAG_TMS), + .JTAG0_TDI(DBA_CPLD_JTAG_TDI), + .JTAG0_TDO(DBA_CPLD_JTAG_TDO), + + .JTAG1_TCK(DBB_CPLD_JTAG_TCK), + .JTAG1_TMS(DBB_CPLD_JTAG_TMS), + .JTAG1_TDI(DBB_CPLD_JTAG_TDI), + .JTAG1_TDO(DBB_CPLD_JTAG_TDO), + + .FCLK_CLK0(FCLK_CLK0), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_RESET1_N(), + .FCLK_CLK2(FCLK_CLK2), + .FCLK_RESET2_N(), + .FCLK_CLK3(FCLK_CLK3), + .FCLK_RESET3_N(), + + .WR_UART_txd(wr_uart_rxd), // rx <-> tx + .WR_UART_rxd(wr_uart_txd), // rx <-> tx + + .qsfp_sda_i(qsfp_sda_i), + .qsfp_sda_o(qsfp_sda_o), + .qsfp_sda_t(qsfp_sda_t), + .qsfp_scl_i(qsfp_scl_i), + .qsfp_scl_o(qsfp_scl_o), + .qsfp_scl_t(qsfp_scl_t), + + .USBIND_0_port_indctl(), + .USBIND_0_vbus_pwrfault(), + .USBIND_0_vbus_pwrselect(), + + // Outward connections to the pins + .MIO(MIO), + .DDR_cas_n(DDR_CAS_n), + .DDR_cke(DDR_CKE), + .DDR_ck_n(DDR_Clk_n), + .DDR_ck_p(DDR_Clk), + .DDR_cs_n(DDR_CS_n), + .DDR_reset_n(DDR_DRSTB), + .DDR_odt(DDR_ODT), + .DDR_ras_n(DDR_RAS_n), + .DDR_we_n(DDR_WEB), + .DDR_ba(DDR_BankAddr), + .DDR_addr(DDR_Addr), + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_dm(DDR_DM), + .DDR_dq(DDR_DQ), + .DDR_dqs_n(DDR_DQS_n), + .DDR_dqs_p(DDR_DQS), + .PS_SRSTB(PS_SRSTB), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB) + ); + + /////////////////////////////////////////////////////////////////////////////////// + // + // Xilinx DDR3 Controller and PHY. + // + /////////////////////////////////////////////////////////////////////////////////// + + wire ddr3_axi_clk; // 1/4 DDR external clock rate (200MHz) + wire ddr3_axi_rst; // Synchronized to ddr_sys_clk + wire ddr3_running; // DRAM calibration complete. + wire [11:0] device_temp; + + // Slave Interface Write Address Ports + wire [3:0] ddr3_axi_awid; + wire [31:0] ddr3_axi_awaddr; + wire [7:0] ddr3_axi_awlen; + wire [2:0] ddr3_axi_awsize; + wire [1:0] ddr3_axi_awburst; + wire [0:0] ddr3_axi_awlock; + wire [3:0] ddr3_axi_awcache; + wire [2:0] ddr3_axi_awprot; + wire [3:0] ddr3_axi_awqos; + wire ddr3_axi_awvalid; + wire ddr3_axi_awready; + // Slave Interface Write Data Ports + wire [255:0] ddr3_axi_wdata; + wire [31:0] ddr3_axi_wstrb; + wire ddr3_axi_wlast; + wire ddr3_axi_wvalid; + wire ddr3_axi_wready; + // Slave Interface Write Response Ports + wire ddr3_axi_bready; + wire [3:0] ddr3_axi_bid; + wire [1:0] ddr3_axi_bresp; + wire ddr3_axi_bvalid; + // Slave Interface Read Address Ports + wire [3:0] ddr3_axi_arid; + wire [31:0] ddr3_axi_araddr; + wire [7:0] ddr3_axi_arlen; + wire [2:0] ddr3_axi_arsize; + wire [1:0] ddr3_axi_arburst; + wire [0:0] ddr3_axi_arlock; + wire [3:0] ddr3_axi_arcache; + wire [2:0] ddr3_axi_arprot; + wire [3:0] ddr3_axi_arqos; + wire ddr3_axi_arvalid; + wire ddr3_axi_arready; + // Slave Interface Read Data Ports + wire ddr3_axi_rready; + wire [3:0] ddr3_axi_rid; + wire [255:0] ddr3_axi_rdata; + wire [1:0] ddr3_axi_rresp; + wire ddr3_axi_rlast; + wire ddr3_axi_rvalid; + + reg ddr3_axi_rst_reg_n; + + // Copied this reset circuit from example design. + always @(posedge ddr3_axi_clk) + ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; + + + // Instantiate the DDR3 MIG core + // + // The top-level IP block has no parameters defined for some reason. + // Most of configurable parameters are hard-coded in the mig so get + // some additional knobs we pull those out into verilog headers. + // + // Synthesis params: ip/ddr3_32bit/ddr3_32bit_mig_parameters.vh + // Simulation params: ip/ddr3_32bit/ddr3_32bit_mig_sim_parameters.vh + + ddr3_32bit u_ddr3_32bit ( + // Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .init_calib_complete (ddr3_running), + .device_temp_i (device_temp), + + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + // Application interface ports + .ui_clk (ddr3_axi_clk), // 200Hz clock out + .ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 200 MHz. + .aresetn (ddr3_axi_rst_reg_n), + .app_sr_req (1'b0), + .app_sr_active (), + .app_ref_req (1'b0), + .app_ref_ack (), + .app_zq_req (1'b0), + .app_zq_ack (), + // Slave Interface Write Address Ports + .s_axi_awid (ddr3_axi_awid), + .s_axi_awaddr (ddr3_axi_awaddr), + .s_axi_awlen (ddr3_axi_awlen), + .s_axi_awsize (ddr3_axi_awsize), + .s_axi_awburst (ddr3_axi_awburst), + .s_axi_awlock (ddr3_axi_awlock), + .s_axi_awcache (ddr3_axi_awcache), + .s_axi_awprot (ddr3_axi_awprot), + .s_axi_awqos (ddr3_axi_awqos), + .s_axi_awvalid (ddr3_axi_awvalid), + .s_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .s_axi_wdata (ddr3_axi_wdata), + .s_axi_wstrb (ddr3_axi_wstrb), + .s_axi_wlast (ddr3_axi_wlast), + .s_axi_wvalid (ddr3_axi_wvalid), + .s_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .s_axi_bid (ddr3_axi_bid), + .s_axi_bresp (ddr3_axi_bresp), + .s_axi_bvalid (ddr3_axi_bvalid), + .s_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .s_axi_arid (ddr3_axi_arid), + .s_axi_araddr (ddr3_axi_araddr), + .s_axi_arlen (ddr3_axi_arlen), + .s_axi_arsize (ddr3_axi_arsize), + .s_axi_arburst (ddr3_axi_arburst), + .s_axi_arlock (ddr3_axi_arlock), + .s_axi_arcache (ddr3_axi_arcache), + .s_axi_arprot (ddr3_axi_arprot), + .s_axi_arqos (ddr3_axi_arqos), + .s_axi_arvalid (ddr3_axi_arvalid), + .s_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .s_axi_rid (ddr3_axi_rid), + .s_axi_rdata (ddr3_axi_rdata), + .s_axi_rresp (ddr3_axi_rresp), + .s_axi_rlast (ddr3_axi_rlast), + .s_axi_rvalid (ddr3_axi_rvalid), + .s_axi_rready (ddr3_axi_rready), + // System Clock Ports + .sys_clk_p (sys_clk_p), + .sys_clk_n (sys_clk_n), + .clk_ref_i (bus_clk), + + .sys_rst (~global_rst) // IJB. Poorly named active low. Should change RST_ACT_LOW. + ); + + // Temperature monitor module + mig_7series_v4_2_tempmon #( + .TEMP_MON_CONTROL("INTERNAL"), + .XADC_CLK_PERIOD(5000 /* 200MHz clock period in ps */) + ) tempmon_i ( + .clk(bus_clk), .xadc_clk(bus_clk), .rst(bus_rst), + .device_temp_i(12'd0 /* ignored */), .device_temp(device_temp) + ); + + /////////////////////////////////////////////////////// + // + // DB PS SPI Connections + // + /////////////////////////////////////////////////////// + wire [NUM_CHANNELS-1:0] rx_atr; + wire [NUM_CHANNELS-1:0] tx_atr; + (* IOB = "true" *) reg [NUM_CHANNELS-1:0] rx_atr_reg; + (* IOB = "true" *) reg [NUM_CHANNELS-1:0] tx_atr_reg; + + // Radio GPIO control for DSA + wire [16*NUM_CHANNELS-1:0] db_gpio_out; + wire [16*NUM_CHANNELS-1:0] db_gpio_ddr; + wire [16*NUM_CHANNELS-1:0] db_gpio_in; + wire [16*NUM_CHANNELS-1:0] db_gpio_fab; + + // DB A SPI Connections + assign DBA_CPLD_PS_SPI_SCLK = spi0_sclk; + assign DBA_CPLD_PS_SPI_MOSI = spi0_mosi; + + // Assign individual chip selects from PS SPI MASTER 0. + assign DBA_CPLD_PS_SPI_CS_B = spi0_ss0; + assign DBA_CLKDIS_SPI_CS_B = spi0_ss1; + assign DBA_PHDAC_SPI_CS_B = spi0_ss2; + assign DBA_ADC_SPI_CS_B = ps_gpio_out[13]; + assign DBA_DAC_SPI_CS_B = ps_gpio_out[14]; + + // Returned data mux from the SPI interfaces. + assign spi0_miso = DBA_CPLD_PS_SPI_MISO; + + // TODO: How to control? + assign DBA_ATR_RX = rx_atr_reg[0]; + assign DBA_ATR_TX = tx_atr_reg[0]; + assign DBA_TXRX_SW_CTRL_1 = db_gpio_out[16*0+0]; + assign DBA_TXRX_SW_CTRL_2 = db_gpio_out[16*0+1]; + assign DBA_LED_RX = db_gpio_out[16*0+2]; + assign DBA_LED_RX2 = db_gpio_out[16*0+3]; + assign DBA_LED_TX = db_gpio_out[16*0+4]; + + // DB B SPI Connections + assign DBB_CPLD_PS_SPI_SCLK = spi1_sclk; + assign DBB_CPLD_PS_SPI_MOSI = spi1_mosi; + + // Assign individual chip selects from PS SPI MASTER 1. + assign DBB_CPLD_PS_SPI_CS_B = spi1_ss0; + assign DBB_CLKDIS_SPI_CS_B = spi1_ss1; + assign DBB_PHDAC_SPI_CS_B = spi1_ss2; + assign DBB_ADC_SPI_CS_B = ps_gpio_out[15]; + assign DBB_DAC_SPI_CS_B = ps_gpio_out[16]; + + // Returned data mux from the SPI interfaces. + assign spi1_miso = DBB_CPLD_PS_SPI_MISO; + + + // TODO: How to control? + assign DBB_ATR_RX = rx_atr_reg[1]; + assign DBB_ATR_TX = tx_atr_reg[1]; + assign DBB_TXRX_SW_CTRL_1 = db_gpio_out[16*1+0]; + assign DBB_TXRX_SW_CTRL_2 = db_gpio_out[16*1+1]; + assign DBB_LED_RX = db_gpio_out[16*1+2]; + assign DBB_LED_RX2 = db_gpio_out[16*1+3]; + assign DBB_LED_TX = db_gpio_out[16*1+4]; + + + /////////////////////////////////////////////////////// + // + // N320 CORE + // + /////////////////////////////////////////////////////// + + wire [CHANNEL_WIDTH-1:0] rx_db[2*NUM_CHANNELS-1:0]; + wire [CHANNEL_WIDTH-1:0] tx_db[2*NUM_CHANNELS-1:0]; + wire [CHANNEL_WIDTH-1:0] rx[NUM_CHANNELS-1:0]; + wire [CHANNEL_WIDTH-1:0] tx[NUM_CHANNELS-1:0]; + wire [CHANNEL_WIDTH*NUM_CHANNELS-1:0] rx_flat; + wire [CHANNEL_WIDTH*NUM_CHANNELS-1:0] tx_flat; + wire [47:0] rx_hb[NUM_CHANNELS-1:0]; + wire [95:0] tx_hb[NUM_CHANNELS-1:0]; + + wire [NUM_CHANNELS-1:0] rx_stb; + wire [NUM_CHANNELS-1:0] tx_stb; + + wire [31:0] build_datestamp; + + /* 2:1 and 1:2 filters to bring sample rates down + */ + genvar i; + generate for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + hb47_1to2 tx_1to2 ( + .aresetn(!radio_rst), + .aclk(radio_clk), + .s_axis_data_tvalid(tx_stb[i]), + .s_axis_data_tready(), + .s_axis_data_tdata(tx[i]), + .m_axis_data_tvalid(), + .m_axis_data_tready(tx_stb[i]), + .m_axis_data_tdata(tx_hb[i]) + ); + + assign tx_db[2*i] = {tx_hb[i][39:24], tx_hb[i][15:0]}; + assign tx_db[2*i+1] = {tx_hb[i][87:72], tx_hb[i][63:48]}; + + hb47_2to1 rx_2to1 ( + .aresetn(!radio_rst), + .aclk(radio_clk), + .s_axis_data_tvalid(rx_stb[i]), + .s_axis_data_tready(), + .s_axis_data_tdata({rx_db[2*i+1], rx_db[2*i]}), + .m_axis_data_tvalid(), + .m_axis_data_tdata(rx_hb[i]) + ); + + assign rx[i] = {rx_hb[i][39:24], rx_hb[i][15:0]}; + end endgenerate + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + // Radio Data + assign rx_flat[CHANNEL_WIDTH*i +: CHANNEL_WIDTH] = rx[i]; + assign tx[i] = tx_flat[CHANNEL_WIDTH*i +: CHANNEL_WIDTH]; + end + endgenerate + + USR_ACCESSE2 usr_access_i ( + .DATA(build_datestamp), .CFGCLK(), .DATAVALID() + ); + + n3xx_core #( + .REG_AWIDTH(14), + .BUS_CLK_RATE(BUS_CLK_RATE), + .FP_GPIO_WIDTH(FP_GPIO_WIDTH), + .CHANNEL_WIDTH(CHANNEL_WIDTH), + .NUM_CHANNELS_PER_RADIO(NUM_CHANNELS_PER_RADIO), + .NUM_CHANNELS(NUM_CHANNELS), + .NUM_DBOARDS(NUM_DBOARDS), + .NUM_SPI_PER_DBOARD(4), + .USE_CORRECTION(1), + `ifdef USE_REPLAY + .USE_REPLAY(1) + `else + .USE_REPLAY(0) + `endif + ) n3xx_core( + // Clocks and resets +`ifdef NO_DB + .radio_clk(bus_clk), + .radio_rst(bus_rst), +`else + .radio_clk(radio_clk), + .radio_rst(radio_rst), +`endif + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .ddr3_dma_clk(ddr3_dma_clk), + .clk40(clk40), + + // Clocking and PPS Controls/Indicators + .pps(pps_radioclk1x), + .pps_select(pps_select), + .pps_out_enb(pps_out_enb), + .pps_select_sfp(pps_select_sfp), + .ref_clk_reset(), + .meas_clk_reset(meas_clk_reset), + .ref_clk_locked(1'b1), + .meas_clk_locked(meas_clk_locked), + .enable_ref_clk_async(enable_ref_clk_async), + + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_XBAR_AWADDR), + .s_axi_awvalid(M_AXI_XBAR_AWVALID), + .s_axi_awready(M_AXI_XBAR_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_XBAR_WDATA), + .s_axi_wstrb(M_AXI_XBAR_WSTRB), + .s_axi_wvalid(M_AXI_XBAR_WVALID), + .s_axi_wready(M_AXI_XBAR_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_XBAR_BRESP), + .s_axi_bvalid(M_AXI_XBAR_BVALID), + .s_axi_bready(M_AXI_XBAR_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_XBAR_ARADDR), + .s_axi_arvalid(M_AXI_XBAR_ARVALID), + .s_axi_arready(M_AXI_XBAR_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_XBAR_RDATA), + .s_axi_rresp(M_AXI_XBAR_RRESP), + .s_axi_rvalid(M_AXI_XBAR_RVALID), + .s_axi_rready(M_AXI_XBAR_RREADY), + // ps gpio source + .ps_gpio_tri(ps_gpio_tri[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + .ps_gpio_out(ps_gpio_out[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + .ps_gpio_in(ps_gpio_in[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + // FP_GPIO + .fp_gpio_inout(FPGA_GPIO), + // Radio ATR + .rx_atr(rx_atr), + .tx_atr(tx_atr), + // Radio GPIO DSA + .db_gpio_out_flat(db_gpio_out), + .db_gpio_in_flat(db_gpio_in), + .db_gpio_ddr_flat(db_gpio_ddr), + .db_gpio_fab_flat(db_gpio_fab), + // Radio Strobes + .rx_stb(rx_stb), + .tx_stb(tx_stb), + // Radio Data + .rx(rx_flat), + .tx(tx_flat), + //cpld rx_lo tx_lo spi + .sclk_flat({DBB_CPLD_PL_SPI_SCLK, + DBA_CPLD_PL_SPI_SCLK}), + .sen_flat({DBB_CPLD_PL_SPI_CS_B,DBB_LODIS_SPI_CS_B,DBB_RXLO_SPI_CS_B,DBB_TXLO_SPI_CS_B, + DBA_CPLD_PL_SPI_CS_B,DBA_LODIS_SPI_CS_B,DBA_RXLO_SPI_CS_B,DBA_TXLO_SPI_CS_B}), + .mosi_flat({DBB_CPLD_PL_SPI_MOSI, + DBA_CPLD_PL_SPI_MOSI}), + .miso_flat({DBB_CPLD_PL_SPI_MISO, + DBA_CPLD_PL_SPI_MISO}), + // DRAM signals. + .ddr3_axi_clk (ddr3_axi_clk), + .ddr3_axi_rst (ddr3_axi_rst), + .ddr3_running (ddr3_running), + // Slave Interface Write Address Ports + .ddr3_axi_awid (ddr3_axi_awid), + .ddr3_axi_awaddr (ddr3_axi_awaddr), + .ddr3_axi_awlen (ddr3_axi_awlen), + .ddr3_axi_awsize (ddr3_axi_awsize), + .ddr3_axi_awburst (ddr3_axi_awburst), + .ddr3_axi_awlock (ddr3_axi_awlock), + .ddr3_axi_awcache (ddr3_axi_awcache), + .ddr3_axi_awprot (ddr3_axi_awprot), + .ddr3_axi_awqos (ddr3_axi_awqos), + .ddr3_axi_awvalid (ddr3_axi_awvalid), + .ddr3_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .ddr3_axi_wdata (ddr3_axi_wdata), + .ddr3_axi_wstrb (ddr3_axi_wstrb), + .ddr3_axi_wlast (ddr3_axi_wlast), + .ddr3_axi_wvalid (ddr3_axi_wvalid), + .ddr3_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .ddr3_axi_bid (ddr3_axi_bid), + .ddr3_axi_bresp (ddr3_axi_bresp), + .ddr3_axi_bvalid (ddr3_axi_bvalid), + .ddr3_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .ddr3_axi_arid (ddr3_axi_arid), + .ddr3_axi_araddr (ddr3_axi_araddr), + .ddr3_axi_arlen (ddr3_axi_arlen), + .ddr3_axi_arsize (ddr3_axi_arsize), + .ddr3_axi_arburst (ddr3_axi_arburst), + .ddr3_axi_arlock (ddr3_axi_arlock), + .ddr3_axi_arcache (ddr3_axi_arcache), + .ddr3_axi_arprot (ddr3_axi_arprot), + .ddr3_axi_arqos (ddr3_axi_arqos), + .ddr3_axi_arvalid (ddr3_axi_arvalid), + .ddr3_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .ddr3_axi_rid (ddr3_axi_rid), + .ddr3_axi_rdata (ddr3_axi_rdata), + .ddr3_axi_rresp (ddr3_axi_rresp), + .ddr3_axi_rlast (ddr3_axi_rlast), + .ddr3_axi_rvalid (ddr3_axi_rvalid), + .ddr3_axi_rready (ddr3_axi_rready), + + // DMA to PS + .m_dma_tdata(s_axis_dma_tdata), + .m_dma_tdest(s_axis_dma_tdest), + .m_dma_tlast(s_axis_dma_tlast), + .m_dma_tready(s_axis_dma_tready), + .m_dma_tvalid(s_axis_dma_tvalid), + + .s_dma_tdata(m_axis_dma_tdata), + .s_dma_tuser(m_axis_dma_tuser), + .s_dma_tlast(m_axis_dma_tlast), + .s_dma_tready(m_axis_dma_tready), + .s_dma_tvalid(m_axis_dma_tvalid), + + // VITA to Ethernet + .v2e0_tdata(v2e0_tdata), + .v2e0_tvalid(v2e0_tvalid), + .v2e0_tlast(v2e0_tlast), + .v2e0_tready(v2e0_tready), + + .v2e1_tdata(v2e1_tdata), + .v2e1_tlast(v2e1_tlast), + .v2e1_tvalid(v2e1_tvalid), + .v2e1_tready(v2e1_tready), + + // Ethernet to VITA + .e2v0_tdata(e2v0_tdata), + .e2v0_tlast(e2v0_tlast), + .e2v0_tvalid(e2v0_tvalid), + .e2v0_tready(e2v0_tready), + + .e2v1_tdata(e2v1_tdata), + .e2v1_tlast(e2v1_tlast), + .e2v1_tvalid(e2v1_tvalid), + .e2v1_tready(e2v1_tready), + + //regport interface to npio + .reg_wr_req_npio(reg_wr_req_npio), + .reg_wr_addr_npio(reg_wr_addr_npio), + .reg_wr_data_npio(reg_wr_data_npio), + .reg_rd_req_npio(reg_rd_req_npio), + .reg_rd_addr_npio(reg_rd_addr_npio), + .reg_rd_resp_npio(reg_rd_resp_npio), + .reg_rd_data_npio(reg_rd_data_npio), + + .build_datestamp(build_datestamp), + .xadc_readback({20'h0, device_temp}), + .sfp_ports_info({sfp_port1_info, sfp_port0_info}), + .device_id(device_id) + ); + + // Register the ATR bits once between sending them out to the CPLD to avoid + // glitches on the outputs! + always @(posedge radio_clk) begin + rx_atr_reg <= rx_atr; + tx_atr_reg <= tx_atr; + end + + // ////////////////////////////////////////////////////////////////////// + // + // Daughterboard Cores + // + // ////////////////////////////////////////////////////////////////////// + + wire sAdcSyncUnusedA; + wire sAdcSyncUnusedB; + wire sDacSyncUnusedA; + wire sDacSyncUnusedB; + wire sSysrefUnusedA; + wire sSysrefUnusedB; + wire rRpTransferUnusedA; + wire rRpTransferUnusedB; + wire sSpTransferUnusedA; + wire sSpTransferUnusedB; + wire rWrRpTransferUnusedA; + wire rWrRpTransferUnusedB; + wire sWrSpTransferUnusedA; + wire sWrSpTransferUnusedB; + wire sPpsUnusedB; + wire sPpsToIobUnusedB; + + wire dba_adc_sync_b; + wire dba_dac_sync_b; + wire dba_dac_sync_b_n; // This is the swapped version coming from the IBUFDS. + wire dbb_adc_sync_b; + wire dbb_dac_sync_b; + + wire [49:0] bRegPortInFlatA; + wire [49:0] bRegPortInFlatB; + wire [33:0] bRegPortOutFlatA; + wire [33:0] bRegPortOutFlatB; + + wire rx_a_valid; + wire rx_b_valid; + wire tx_a_rfi; + wire tx_b_rfi; + +`ifdef BUILD_WR + localparam INCL_WR_TDC = 1'b1; +`else + localparam INCL_WR_TDC = 1'b0; +`endif + + wire reg_portA_rd; + wire reg_portA_wr; + wire [14-1:0] reg_portA_addr; + wire [32-1:0] reg_portA_wr_data; + wire [32-1:0] reg_portA_rd_data; + wire reg_portA_ready; + wire validA_unused; + + OBUFDS dba_adc_sync_buf( + .O(DBA_ADC_SYNCB_P), + .OB(DBA_ADC_SYNCB_N), + .I(dba_adc_sync_b) + ); + + IBUFDS dba_dac_sync_buf( + .I(DBA_DAC_SYNCB_P), + .IB(DBA_DAC_SYNCB_N), + .O(dba_dac_sync_b_n) + ); + + // The differential signals are swapped in the pins, so the SYNC signal + // must be negated after the IBUFDS. + assign dba_dac_sync_b = ~ dba_dac_sync_b_n; + + OBUFDS dbb_adc_sync_buf( + .O(DBB_ADC_SYNCB_P), + .OB(DBB_ADC_SYNCB_N), + .I(dbb_adc_sync_b) + ); + + IBUFDS dbb_dac_sync_buf( + .I(DBB_DAC_SYNCB_P), + .IB(DBB_DAC_SYNCB_N), + .O(dbb_dac_sync_b) + ); + + + assign bRegPortInFlatA = {2'b0, reg_portA_addr, reg_portA_wr_data, reg_portA_rd, reg_portA_wr}; + assign {reg_portA_rd_data, validA_unused, reg_portA_ready} = bRegPortOutFlatA; + + DbCore + # (.kInclWhiteRabbitTdc(INCL_WR_TDC)) //std_logic:='0' + dba_core ( + .bBusReset(clk40_rst), //in std_logic + .BusClk(clk40), //in std_logic + .Clk40(clk40), //in std_logic + .MeasClk(meas_clk), //in std_logic + .FpgaClk_p(DBA_FPGA_CLK_P), //in std_logic + .FpgaClk_n(DBA_FPGA_CLK_N), //in std_logic + .SampleClk1xOut(radio_clk), //out std_logic + .SampleClk1x(radio_clk), //in std_logic + .SampleClk2xOut(radio_clk_2x), //out std_logic + .SampleClk2x(radio_clk_2x), //in std_logic + .bRegPortInFlat(bRegPortInFlatA), //in std_logic_vector(49:0) + .bRegPortOutFlat(bRegPortOutFlatA), //out std_logic_vector(33:0) + .kSlotId(1'b0), //in std_logic + .sSysRefFpgaLvds_p(DBA_FPGA_SYSREF_P), //in std_logic + .sSysRefFpgaLvds_n(DBA_FPGA_SYSREF_N), //in std_logic + .aLmkSync(DBA_CLKDIST_SYNC), //out std_logic + .JesdRefClk_p(DBA_MGTCLK_P), //in std_logic + .JesdRefClk_n(DBA_MGTCLK_N), //in std_logic + .aAdcRx_p(DBA_RX_P), //in std_logic_vector(3:0) + .aAdcRx_n(DBA_RX_N), //in std_logic_vector(3:0) + .aSyncAdcOut_n(dba_adc_sync_b), //out std_logic + .aDacTx_p(DBA_TX_P), //out std_logic_vector(3:0) + .aDacTx_n(DBA_TX_N), //out std_logic_vector(3:0) + .aSyncDacIn_n(dba_dac_sync_b), //in std_logic + .sAdcDataValid(rx_a_valid), //out std_logic + .sAdcDataSample0I(rx_db[0][31:16]), //out std_logic_vector(15:0) + .sAdcDataSample0Q(rx_db[0][15: 0]), //out std_logic_vector(15:0) + .sAdcDataSample1I(rx_db[1][31:16]), //out std_logic_vector(15:0) + .sAdcDataSample1Q(rx_db[1][15: 0]), //out std_logic_vector(15:0) + .sDacReadyForInput(tx_a_rfi), //out std_logic + .sDacDataSample0I(tx_db[0][31:16]), //in std_logic_vector(15:0) + .sDacDataSample0Q(tx_db[0][15: 0]), //in std_logic_vector(15:0) + .sDacDataSample1I(tx_db[1][31:16]), //in std_logic_vector(15:0) + .sDacDataSample1Q(tx_db[1][15: 0]), //in std_logic_vector(15:0) + .RefClk(ref_clk), //in std_logic + .rPpsPulse(pps_refclk), //in std_logic + .rGatedPulseToPin(UNUSED_PIN_TDCA_0), //inout std_logic + .sGatedPulseToPin(UNUSED_PIN_TDCA_1), //inout std_logic + .sPps(pps_radioclk1x), //out std_logic + .sPpsToIob(pps_radioclk1x_iob), //out std_logic + .WrRefClk(wr_ref_clk), //in std_logic + .rWrPpsPulse(pps_wr_refclk), //in std_logic + .rWrGatedPulseToPin(UNUSED_PIN_TDCA_2), //inout std_logic + .sWrGatedPulseToPin(UNUSED_PIN_TDCA_3), //inout std_logic + .aPpsSfpSel(pps_select_sfp), //in std_logic_vector(1:0) + .sAdcSync(sAdcSyncUnusedA), //out std_logic + .sDacSync(sDacSyncUnusedA), //out std_logic + .sSysRef(sSysrefUnusedA), //out std_logic + .rRpTransfer(rRpTransferUnusedA), //out std_logic + .sSpTransfer(sSpTransferUnusedA), //out std_logic + .rWrRpTransfer(rWrRpTransferUnusedA), //out std_logic + .sWrSpTransfer(sWrSpTransferUnusedA)); //out std_logic + + + + assign rx_stb[0] = rx_a_valid; + assign tx_stb[0] = tx_a_rfi; + + axil_to_ni_regport #( + .RP_DWIDTH (32), + .RP_AWIDTH (14), + .TIMEOUT (512) + ) ni_regportA_inst ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD0_AWADDR), + .s_axi_awvalid(M_AXI_JESD0_AWVALID), + .s_axi_awready(M_AXI_JESD0_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD0_WDATA), + .s_axi_wstrb(M_AXI_JESD0_WSTRB), + .s_axi_wvalid(M_AXI_JESD0_WVALID), + .s_axi_wready(M_AXI_JESD0_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD0_BRESP), + .s_axi_bvalid(M_AXI_JESD0_BVALID), + .s_axi_bready(M_AXI_JESD0_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD0_ARADDR), + .s_axi_arvalid(M_AXI_JESD0_ARVALID), + .s_axi_arready(M_AXI_JESD0_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_JESD0_RDATA), + .s_axi_rresp(M_AXI_JESD0_RRESP), + .s_axi_rvalid(M_AXI_JESD0_RVALID), + .s_axi_rready(M_AXI_JESD0_RREADY), + // Register port + .reg_port_in_rd (reg_portA_rd), + .reg_port_in_wt (reg_portA_wr), + .reg_port_in_addr (reg_portA_addr), + .reg_port_in_data (reg_portA_wr_data), + .reg_port_out_data (reg_portA_rd_data), + .reg_port_out_ready(reg_portA_ready) + ); + + wire reg_portB_rd; + wire reg_portB_wr; + wire [14-1:0] reg_portB_addr; + wire [32-1:0] reg_portB_wr_data; + wire [32-1:0] reg_portB_rd_data; + wire reg_portB_ready; + wire validB_unused; + + assign bRegPortInFlatB = {2'b0, reg_portB_addr, reg_portB_wr_data, reg_portB_rd, reg_portB_wr}; + assign {reg_portB_rd_data, validB_unused, reg_portB_ready} = bRegPortOutFlatB; + + DbCore + # (.kInclWhiteRabbitTdc(INCL_WR_TDC)) //std_logic:='0' + dbb_core ( + .bBusReset(clk40_rst), //in std_logic + .BusClk(clk40), //in std_logic + .Clk40(clk40), //in std_logic + .MeasClk(meas_clk), //in std_logic + .FpgaClk_p(DBB_FPGA_CLK_P), //in std_logic + .FpgaClk_n(DBB_FPGA_CLK_N), //in std_logic + .SampleClk1xOut(radio_clkB), //out std_logic + .SampleClk1x(radio_clk), //in std_logic + .SampleClk2xOut(radio_clk_2xB), //out std_logic + .SampleClk2x(radio_clk_2x), //in std_logic + .bRegPortInFlat(bRegPortInFlatB), //in std_logic_vector(49:0) + .bRegPortOutFlat(bRegPortOutFlatB), //out std_logic_vector(33:0) + .kSlotId(1'b1), //in std_logic + .sSysRefFpgaLvds_p(DBB_FPGA_SYSREF_P), //in std_logic + .sSysRefFpgaLvds_n(DBB_FPGA_SYSREF_N), //in std_logic + .aLmkSync(DBB_CLKDIST_SYNC), //out std_logic + .JesdRefClk_p(DBB_MGTCLK_P), //in std_logic + .JesdRefClk_n(DBB_MGTCLK_N), //in std_logic + .aAdcRx_p(DBB_RX_P), //in std_logic_vector(3:0) + .aAdcRx_n(DBB_RX_N), //in std_logic_vector(3:0) + .aSyncAdcOut_n(dbb_adc_sync_b), //out std_logic + .aDacTx_p(DBB_TX_P), //out std_logic_vector(3:0) + .aDacTx_n(DBB_TX_N), //out std_logic_vector(3:0) + .aSyncDacIn_n(dbb_dac_sync_b), //in std_logic + .sAdcDataValid(rx_b_valid), //out std_logic + .sAdcDataSample0I(rx_db[2][31:16]), //out std_logic_vector(15:0) + .sAdcDataSample0Q(rx_db[2][15: 0]), //out std_logic_vector(15:0) + .sAdcDataSample1I(rx_db[3][31:16]), //out std_logic_vector(15:0) + .sAdcDataSample1Q(rx_db[3][15: 0]), //out std_logic_vector(15:0) + .sDacReadyForInput(tx_b_rfi), //out std_logic + .sDacDataSample0I(tx_db[2][31:16]), //in std_logic_vector(15:0) + .sDacDataSample0Q(tx_db[2][15: 0]), //in std_logic_vector(15:0) + .sDacDataSample1I(tx_db[3][31:16]), //in std_logic_vector(15:0) + .sDacDataSample1Q(tx_db[3][15: 0]), //in std_logic_vector(15:0) + .RefClk(ref_clk), //in std_logic + .rPpsPulse(pps_refclk), //in std_logic + .rGatedPulseToPin(UNUSED_PIN_TDCB_0), //inout std_logic + .sGatedPulseToPin(UNUSED_PIN_TDCB_1), //inout std_logic + .sPps(sPpsUnusedB), //out std_logic + .sPpsToIob(sPpsToIobUnusedB), //out std_logic + .WrRefClk(wr_ref_clk), //in std_logic + .rWrPpsPulse(pps_wr_refclk), //in std_logic + .rWrGatedPulseToPin(UNUSED_PIN_TDCB_2), //inout std_logic + .sWrGatedPulseToPin(UNUSED_PIN_TDCB_3), //inout std_logic + .aPpsSfpSel(2'd0), //in std_logic_vector(1:0) + .sAdcSync(sAdcSyncUnusedB), //out std_logic + .sDacSync(sDacSyncUnusedB), //out std_logic + .sSysRef(sSysrefUnusedB), //out std_logic + .rRpTransfer(rRpTransferUnusedB), //out std_logic + .sSpTransfer(sSpTransferUnusedB), //out std_logic + .rWrRpTransfer(rWrRpTransferUnusedB), //out std_logic + .sWrSpTransfer(sWrSpTransferUnusedB)); //out std_logic + + + + assign rx_stb[1] = rx_b_valid; + assign tx_stb[1] = tx_b_rfi; + + axil_to_ni_regport #( + .RP_DWIDTH (32), + .RP_AWIDTH (14), + .TIMEOUT (512) + ) ni_regportB_inst ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD1_AWADDR), + .s_axi_awvalid(M_AXI_JESD1_AWVALID), + .s_axi_awready(M_AXI_JESD1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD1_WDATA), + .s_axi_wstrb(M_AXI_JESD1_WSTRB), + .s_axi_wvalid(M_AXI_JESD1_WVALID), + .s_axi_wready(M_AXI_JESD1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD1_BRESP), + .s_axi_bvalid(M_AXI_JESD1_BVALID), + .s_axi_bready(M_AXI_JESD1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD1_ARADDR), + .s_axi_arvalid(M_AXI_JESD1_ARVALID), + .s_axi_arready(M_AXI_JESD1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_JESD1_RDATA), + .s_axi_rresp (M_AXI_JESD1_RRESP), + .s_axi_rvalid (M_AXI_JESD1_RVALID), + .s_axi_rready (M_AXI_JESD1_RREADY), + // Register port + .reg_port_in_rd (reg_portB_rd), + .reg_port_in_wt (reg_portB_wr), + .reg_port_in_addr (reg_portB_addr), + .reg_port_in_data (reg_portB_wr_data), + .reg_port_out_data (reg_portB_rd_data), + .reg_port_out_ready(reg_portB_ready) + ); + + + // ////////////////////////////////////////////////////////////////////// + // + // LEDS + // + // ////////////////////////////////////////////////////////////////////// + + assign PANEL_LED_LINK = ps_gpio_out[45]; + assign PANEL_LED_REF = ps_gpio_out[46]; + assign PANEL_LED_GPS = ps_gpio_out[47]; + + + ///////////////////////////////////////////////////////////////////// + // + // PUDC Workaround + // + ////////////////////////////////////////////////////////////////////// + // This is a workaround for a silicon bug in Series 7 FPGA where a + // race condition with the reading of PUDC during the erase of the FPGA + // image cause glitches on output IO pins. + // + // Workaround: + // - Define the PUDC pin in the XDC file with a pullup. + // - Implements an IBUF on the PUDC input and make sure that it does + // not get optimized out. + (* dont_touch = "true" *) wire fpga_pudc_b_buf; + IBUF pudc_ibuf_i ( + .I(FPGA_PUDC_B), + .O(fpga_pudc_b_buf)); + +endmodule diff --git a/fpga/usrp3/top/n3xx/dev_config.json b/fpga/usrp3/top/n3xx/dev_config.json new file mode 100644 index 000000000..eb6ce9dc0 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dev_config.json @@ -0,0 +1,3 @@ +{ + "warning": { "ignore": ["."]} +} diff --git a/fpga/usrp3/top/n3xx/doc/mb_timing.xlsx b/fpga/usrp3/top/n3xx/doc/mb_timing.xlsx new file mode 100644 index 000000000..ec3849d59 Binary files /dev/null and b/fpga/usrp3/top/n3xx/doc/mb_timing.xlsx differ diff --git a/fpga/usrp3/top/n3xx/dts/dma-common.dtsi b/fpga/usrp3/top/n3xx/dts/dma-common.dtsi new file mode 100644 index 000000000..65d33cb76 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/dma-common.dtsi @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2017 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +&fpga_full { + tx_dma0: dma@43CA0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CA0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma1: dma@43CB0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CB0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma2: dma@43CC0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CC0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma3: dma@43CD0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CD0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma4: dma@43CE0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CE0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma5: dma@43CF0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CF0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma6: dma@43D00000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43D00000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma7: dma@43D10000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43D10000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma8: dma@43D20000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43D20000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma9: dma@43D30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43D30000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma0: dma@43C00000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C00000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma1: dma@43C10000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C10000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma2: dma@43C20000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C20000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma3: dma@43C30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C30000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma4: dma@43C40000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C40000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma5: dma@43C50000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C50000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma6: dma@43C60000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C60000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma7: dma@43C70000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C70000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma8: dma@43C80000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C80000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma9: dma@43C90000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C90000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + + + usrp_rx_dma0: usrp-rx-dma@43c00000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma0 0>; + dma-names = "dma"; + port-id = <0>; + status = "okay"; + + regmap = <&dma_conf0>; + offset = <0x0>; + }; + + usrp_rx_dma1: usrp-rx-dma@43c10000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma1 0>; + dma-names = "dma"; + port-id = <1>; + + regmap = <&dma_conf0>; + offset = <0x4>; + }; + + usrp_rx_dma2: usrp-rx-dma@43c20000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma2 0>; + dma-names = "dma"; + port-id = <2>; + + regmap = <&dma_conf0>; + offset = <0x8>; + }; + + usrp_rx_dma3: usrp-rx-dma@43c30000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma3 0>; + dma-names = "dma"; + port-id = <3>; + + regmap = <&dma_conf0>; + offset = <0xc>; + }; + + usrp_rx_dma4: usrp-rx-dma@43c40000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma4 0>; + dma-names = "dma"; + port-id = <4>; + + regmap = <&dma_conf0>; + offset = <0x10>; + }; + + usrp_rx_dma5: usrp-rx-dma@43c50000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma5 0>; + dma-names = "dma"; + port-id = <5>; + + regmap = <&dma_conf0>; + offset = <0x14>; + }; + + usrp_rx_dma6: usrp-rx-dma@43c60000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma6 0>; + dma-names = "dma"; + port-id = <6>; + + regmap = <&dma_conf0>; + offset = <0x18>; + }; + + usrp_rx_dma7: usrp-rx-dma@43c70000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma7 0>; + dma-names = "dma"; + port-id = <7>; + + regmap = <&dma_conf0>; + offset = <0x1c>; + }; + + usrp_rx_dma8: usrp-rx-dma@43c80000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma8 0>; + dma-names = "dma"; + port-id = <8>; + + regmap = <&dma_conf0>; + offset = <0x20>; + }; + + usrp_rx_dma9: usrp-rx-dma@43c90000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma9 0>; + dma-names = "dma"; + port-id = <9>; + + regmap = <&dma_conf0>; + offset = <0x24>; + }; + + usrp_tx_dma0: usrp-tx-dma@43ca0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma0 0>; + dma-names = "dma"; + port-id = <0>; + }; + + usrp_tx_dma1: usrp-tx-dma@43cb0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma1 0>; + dma-names = "dma"; + port-id = <1>; + }; + + usrp_tx_dma2: usrp-tx-dma@43cc0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma2 0>; + dma-names = "dma"; + port-id = <2>; + status = "okay"; + }; + + usrp_tx_dma3: usrp-tx-dma@43cd0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma3 0>; + dma-names = "dma"; + port-id = <3>; + }; + + usrp_tx_dma4: usrp-tx-dma@43ce0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma4 0>; + dma-names = "dma"; + port-id = <4>; + status = "okay"; + }; + + usrp_tx_dma5: usrp-tx-dma@43cf0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma5 0>; + dma-names = "dma"; + port-id = <5>; + }; + + usrp_tx_dma6: usrp-tx-dma@43d00000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma6 0>; + dma-names = "dma"; + port-id = <6>; + }; + + usrp_tx_dma7: usrp-tx-dma@43d10000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma7 0>; + dma-names = "dma"; + port-id = <7>; + }; + + usrp_tx_dma8: usrp-tx-dma@43d20000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma8 0>; + dma-names = "dma"; + port-id = <8>; + }; + + usrp_tx_dma9: usrp-tx-dma@43d30000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma9 0>; + dma-names = "dma"; + port-id = <9>; + }; + + dma_conf0: dma_conf0@42080000 { + compatible = "syscon"; + reg = <0x42080000 0x1000>; + status = "okay"; + }; +}; diff --git a/fpga/usrp3/top/n3xx/dts/n300-common.dtsi b/fpga/usrp3/top/n3xx/dts/n300-common.dtsi new file mode 100644 index 000000000..1042d9531 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/n300-common.dtsi @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2017 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +&fpga_full { + uio@40010000 { + compatible = "usrp-uio"; + reg = <0x40010000 0x2000>; + reg-names = "mboard-regs"; + status = "okay"; + }; + + uio@40014000 { + compatible = "usrp-uio"; + reg = <0x40014000 0x4000>; + reg-names = "dboard-regs-0"; + status = "okay"; + }; + + uio@42100000 { + compatible = "usrp-uio"; + reg = <0x42100000 0x1000>; + reg-names = "dboard-jtag-0"; + status = "okay"; + }; +}; + +&spi0 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 62 0>; + + spidev0: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev1: spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <1>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev2: spidev@2 { + compatible = "rohm,dh2228fv"; + reg = <2>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev3: spidev@3 { + compatible = "rohm,dh2228fv"; + reg = <3>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; diff --git a/fpga/usrp3/top/n3xx/dts/n300-fpga.dtsi b/fpga/usrp3/top/n3xx/dts/n300-fpga.dtsi new file mode 100644 index 000000000..d6bbee1a3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/n300-fpga.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +&fpga_full { + firmware-name = "n300.bin"; +}; diff --git a/fpga/usrp3/top/n3xx/dts/n310-common.dtsi b/fpga/usrp3/top/n3xx/dts/n310-common.dtsi new file mode 100644 index 000000000..14be62eaf --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/n310-common.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +&fpga_full { + uio@40010000 { + compatible = "usrp-uio"; + reg = <0x40010000 0x2000>; + reg-names = "mboard-regs"; + status = "okay"; + }; + + uio@40014000 { + compatible = "usrp-uio"; + reg = <0x40014000 0x4000>; + reg-names = "dboard-regs-0"; + status = "okay"; + }; + + uio@40018000 { + compatible = "usrp-uio"; + reg = <0x40018000 0x4000>; + reg-names = "dboard-regs-1"; + status = "okay"; + }; + + uio@42100000 { + compatible = "usrp-uio"; + reg = <0x42100000 0x1000>; + reg-names = "dboard-jtag-0"; + status = "okay"; + }; + + uio@42200000 { + compatible = "usrp-uio"; + reg = <0x42200000 0x1000>; + reg-names = "dboard-jtag-1"; + status = "okay"; + }; + +}; + +&spi0 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 62 0>; + + spidev0: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev1: spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <1>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev2: spidev@2 { + compatible = "rohm,dh2228fv"; + reg = <2>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev3: spidev@3 { + compatible = "rohm,dh2228fv"; + reg = <3>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; + +&spi1 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 63 0>; + + spidev4: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev5: spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <1>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev6: spidev@2 { + compatible = "rohm,dh2228fv"; + reg = <2>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev7: spidev@3 { + compatible = "rohm,dh2228fv"; + reg = <3>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; diff --git a/fpga/usrp3/top/n3xx/dts/n310-fpga.dtsi b/fpga/usrp3/top/n3xx/dts/n310-fpga.dtsi new file mode 100644 index 000000000..3859c84f0 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/n310-fpga.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +&fpga_full { + firmware-name = "n310.bin"; +}; diff --git a/fpga/usrp3/top/n3xx/dts/n320-common.dtsi b/fpga/usrp3/top/n3xx/dts/n320-common.dtsi new file mode 100644 index 000000000..e7fd557b3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/n320-common.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +&fpga_full { + uio@40010000 { + compatible = "usrp-uio"; + reg = <0x40010000 0x2000>; + reg-names = "mboard-regs"; + status = "okay"; + }; + + uio@40014000 { + compatible = "usrp-uio"; + reg = <0x40014000 0x4000>; + reg-names = "dboard-regs-0"; + status = "okay"; + }; + + uio@40018000 { + compatible = "usrp-uio"; + reg = <0x40018000 0x4000>; + reg-names = "dboard-regs-1"; + status = "okay"; + }; + + uio@42100000 { + compatible = "usrp-uio"; + reg = <0x42100000 0x1000>; + reg-names = "dboard-jtag-0"; + status = "okay"; + }; + + uio@42200000 { + compatible = "usrp-uio"; + reg = <0x42200000 0x1000>; + reg-names = "dboard-jtag-1"; + status = "okay"; + }; +}; + +&spi0 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 67 0>, <&gpio0 68 0>; + + spidev0: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev1: spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <1>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev2: spidev@2 { + compatible = "rohm,dh2228fv"; + reg = <2>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev3: spidev@3 { + compatible = "rohm,dh2228fv"; + reg = <3>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev4: spidev@4 { + compatible = "rohm,dh2228fv"; + reg = <4>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; + +&spi1 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 69 0>, <&gpio0 70 0>; + + spidev5: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev6: spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <1>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev7: spidev@2 { + compatible = "rohm,dh2228fv"; + reg = <2>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev8: spidev@3 { + compatible = "rohm,dh2228fv"; + reg = <3>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev9: spidev@4 { + compatible = "rohm,dh2228fv"; + reg = <4>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; + +&usrpio_i2c0 { + rhodium_lodist_gpio: rhodium-lodist-gpio@22 { + compatible = "nxp,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/fpga/usrp3/top/n3xx/dts/n320-fpga.dtsi b/fpga/usrp3/top/n3xx/dts/n320-fpga.dtsi new file mode 100644 index 000000000..5934138a9 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/n320-fpga.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +&fpga_full { + firmware-name = "n320.bin"; +}; diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_AA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_AA.dts new file mode 100644 index 000000000..f0099f08b --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_AA.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n300-fpga.dtsi" + +&fpga_full { + uio@40004000 { + compatible = "usrp-uio"; + reg = <0x40004000 0x1000>; + reg-names = "misc-auro-regs0"; + status = "okay"; + }; + + + uio@4000c000 { + compatible = "usrp-uio"; + reg = <0x4000c000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; +}; + +#include "n300-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HA.dts new file mode 100644 index 000000000..6cdce8022 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HA.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n300-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + /* 114 = 54 (MIOs) + 60 (EMIO 60) */ + link-gpios = <&gpio0 114 0>; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + uio@4000c000 { + compatible = "usrp-uio"; + reg = <0x4000c000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; +}; + +#include "n300-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HG.dts new file mode 100644 index 000000000..7f94f1126 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HG.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n300-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + /* 114 = 54 (MIOs) + 60 (EMIO 60) */ + link-gpios = <&gpio0 114 0>; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; +}; + +#include "n300-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_WX.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_WX.dts new file mode 100644 index 000000000..904149270 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_WX.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n300-fpga.dtsi" + +&fpga_full { + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; + + uio@43d40000 { + compatible = "usrp-uio"; + reg = <0x43d40000 0x40000>; + reg-names = "wr-regs"; + status = "okay"; + }; + + uart2@42c00000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x42c00000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 54 4>; + }; +}; + +#include "n300-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XA.dts new file mode 100644 index 000000000..984591d08 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XA.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n300-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + uio@4000c000 { + compatible = "usrp-uio"; + reg = <0x4000c000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; +}; + +#include "n300-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XG.dts new file mode 100644 index 000000000..3f01d18b1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XG.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n300-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; +}; + +#include "n300-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_AA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_AA.dts new file mode 100644 index 000000000..637e6371d --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_AA.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n310-fpga.dtsi" + +&fpga_full { + uio@40004000 { + compatible = "usrp-uio"; + reg = <0x40004000 0x1000>; + reg-names = "misc-auro-regs0"; + status = "okay"; + }; + + + uio@4000c000 { + compatible = "usrp-uio"; + reg = <0x4000c000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; +}; + +#include "n310-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HA.dts new file mode 100644 index 000000000..bc03736e3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HA.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n310-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + /* 114 = 54 (MIOs) + 60 (EMIO 60) */ + link-gpios = <&gpio0 114 0>; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + uio@4000c000 { + compatible = "usrp-uio"; + reg = <0x4000c000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; +}; + +#include "n310-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HG.dts new file mode 100644 index 000000000..0039d3b0a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HG.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n310-fpga.dtsi" + +&fpga_full{ + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + /* 114 = 54 (MIOs) + 60 (EMIO 60) */ + link-gpios = <&gpio0 114 0>; + }; + + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; +}; + +#include "n310-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_WX.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_WX.dts new file mode 100644 index 000000000..41ee3c0a8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_WX.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n310-fpga.dtsi" + +&fpga_full { + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; + + uio@43d40000 { + compatible = "usrp-uio"; + reg = <0x43d40000 0x40000>; + reg-names = "wr-regs"; + status = "okay"; + }; + + uart2@42c00000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x42c00000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 54 4>; + }; +}; + +#include "n310-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XA.dts new file mode 100644 index 000000000..0838595dd --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XA.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n310-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + uio@4000c000 { + compatible = "usrp-uio"; + reg = <0x4000c000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; +}; + +#include "n310-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XG.dts new file mode 100644 index 000000000..204f91515 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XG.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n310-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; +}; + +#include "n310-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AQ.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AQ.dts new file mode 100644 index 000000000..6382192b8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AQ.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; + + uio@40020000 { + compatible = "usrp-uio"; + reg = <0x40020000 0x1000>; + reg-names = "misc-auro-regs0"; + status = "okay"; + }; + + uio@40024000 { + compatible = "usrp-uio"; + reg = <0x40024000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; + + uio@40028000 { + compatible = "usrp-uio"; + reg = <0x40028000 0x1000>; + reg-names = "misc-auro-regs2"; + status = "okay"; + }; + + + uio@4002c000 { + compatible = "usrp-uio"; + reg = <0x4002c000 0x1000>; + reg-names = "misc-auro-regs3"; + status = "okay"; + }; + + qsfp_i2c: qsfp-i2c@43D80000 { + compatible = "xlnx,xps-iic-2.00.a"; + clocks = <&clkc 15>; + interrupt-parent = <&intc>; + interrupts = <0 55 4>; + reg = <0x43D80000 0x10000>; + }; +}; + +#include "n320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_HG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_HG.dts new file mode 100644 index 000000000..d08aeb87b --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_HG.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + /* 114 = 54 (MIOs) + 60 (EMIO 60) */ + link-gpios = <&gpio0 114 0>; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; +}; + +#include "n320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_WX.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_WX.dts new file mode 100644 index 000000000..8b133ce98 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_WX.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n320-fpga.dtsi" + +&fpga_full { + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; + + uio@43d40000 { + compatible = "usrp-uio"; + reg = <0x43d40000 0x40000>; + reg-names = "wr-regs"; + status = "okay"; + }; + + uart2@42c00000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x42c00000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 54 4>; + }; +}; + +#include "n320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XG.dts new file mode 100644 index 000000000..f585dbddb --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XG.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; +}; + +#include "n320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XQ.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XQ.dts new file mode 100644 index 000000000..037447932 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XQ.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ni,xge-enet-3.00"; + reg = <0x40000000 0x4000 + 0x40020000 0x2000>; + reg-names = "dma", "ctrl"; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40022000 { + compatible = "usrp-uio"; + reg = <0x40022000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ni,xge-enet-3.00"; + reg = <0x40008000 0x4000 + 0x40024000 0x2000>; + reg-names = "dma", "ctrl"; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40026000 { + compatible = "usrp-uio"; + reg = <0x40026000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs2"; + status = "okay"; + }; + + uio@43d40000 { + compatible = "usrp-uio"; + reg = <0x43d40000 0x40000>; + reg-names = "wr-regs"; + status = "okay"; + }; + + uart2@42c00000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x42c00000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 54 4>; + }; + + qsfp_i2c: qsfp-i2c@43D80000 { + compatible = "xlnx,xps-iic-2.00.a"; + clocks = <&clkc 15>; + interrupt-parent = <&intc>; + interrupts = <0 55 4>; + reg = <0x43D80000 0x10000>; + }; +}; + +#include "n320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/ip/Makefile.inc b/fpga/usrp3/top/n3xx/ip/Makefile.inc new file mode 100644 index 000000000..98021fcc7 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/Makefile.inc @@ -0,0 +1,90 @@ +# +# Copyright 2017-2018 Ettus Research, a National Instruments Company +# + +#include $(IP_DIR)/axi4_dualport_sram/Makefile.inc +include $(IP_DIR)/hb47_1to2/Makefile.inc +include $(IP_DIR)/hb47_2to1/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi_intercon_2x64_256_bd/Makefile.inc +include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc +include $(IP_DIR)/ddr3_32bit/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +#include $(IP_DIR)/input_sample_fifo/Makefile.inc +include $(IP_DIR)/one_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/misc_clock_gen/Makefile.inc +include $(IP_DIR)/ten_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/aurora_64b66b_pcs_pma/Makefile.inc +include $(IP_DIR)/axi3_to_axi4lite_protocol_converter/Makefile.inc +include $(IP_DIR)/axis_fifo_to_axi4lite/Makefile.inc +include $(IP_DIR)/axi_eth_dma/Makefile.inc +include $(IP_DIR)/axi4_to_axi3_protocol_converter_32/Makefile.inc +include $(IP_DIR)/axi4_to_axi3_protocol_converter_64/Makefile.inc +include $(IP_DIR)/n310_ps_bd/Makefile.inc + +BD_SRCS = \ +$(IP_AXI_INTERCON_2X64_256_BD_SRCS) \ +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \ +$(IP_N310_PS_BD_SRCS) + +IP_XCI_SRCS = \ +$(IP_HB47_1TO2_SRCS) \ +$(IP_HB47_2TO1_SRCS) \ +$(IP_AXI4_BRAM_SRCS) \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(IP_AXI64_8K_2CLK_FIFO_SRCS) \ +$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS) \ +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS) \ +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS) \ +$(IP_AXIS_FIFO_TO_AXI4LITE_SRCS) \ +$(IP_MISC_CLOCK_GEN_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +$(IP_AXI_ETH_DMA_SRCS) \ +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_AURORA_64B66B_PCS_PMA_SRCS) + +IP_DRAM_XCI_SRCS = \ +$(IP_DDR3_32BIT_SRCS) + +# Currently unused +# $(IP_INPUT_SAMPLE_FIFO_SRCS) \ + +IP_CODEGEN_SRCS = \ +$(ONE_GIGE_PHY_SRCS) \ +$(TEN_GIGE_PHY_SRCS) + +IP_SYNTH_OUTPUTS = \ +$(IP_HB47_1TO2_OUTS) \ +$(IP_HB47_2TO1_OUTS) \ +$(IP_AXI4_BRAM_OUTS) \ +$(IP_AXI64_4K_2CLK_FIFO_OUTS) \ +$(IP_AXI64_8K_2CLK_FIFO_OUTS) \ +$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS) \ +$(IP_AXI_INTERCONNECT_OUTS) \ +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS) \ +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS) \ +$(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) \ +$(IP_FIFO_4K_2CLK_OUTS) \ +$(IP_FIFO_SHORT_2CLK_OUTS) \ +$(IP_ONE_GIG_ETH_PCS_PMA_OUTS) \ +$(IP_AXI_ETH_DMA_OUTS) \ +$(IP_TEN_GIG_ETH_PCS_PMA_OUTS) \ +$(IP_AURORA_64B66B_PCS_PMA_OUTS) + +BD_OUTPUTS = \ +$(IP_AXI_INTERCON_2X64_256_BD_OUTS) \ +$(IP_AXI_INTERCON_4X64_256_BD_OUTS) \ +$(IP_N310_PS_BD_OUTS) + +# Currently unused +# $(IP_INPUT_SAMPLE_FIFO_OUTS) \ +# $(IP_AXI_INTERCON_4X64_128_OUTS) \ + +ip: $(IP_SYNTH_OUTPUTS) $(IP_CODEGEN_SRCS) $(BD_OUTPUTS) + +.PHONY: ip + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/Makefile.inc b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/Makefile.inc new file mode 100644 index 000000000..270f4e92e --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/Makefile.inc @@ -0,0 +1,32 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +AURORA_PHY_SRCS = \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_x1.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_mmcm.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_axis_mac.v \ +$(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS) + +IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma_ex/, \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_clock_module.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_gt_common_wrapper.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support_reset_logic.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support.v \ +imports/aurora_64b66b_pcs_pma_cdc_sync_exdes.v \ +imports/aurora_64b66b_pcs_pma_example_axi_to_ll.v \ +imports/aurora_64b66b_pcs_pma_example_ll_to_axi.v \ +) + +IP_AURORA_64B66B_PCS_PMA_SRCS = $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + +IP_AURORA_64B66B_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/, \ +aurora_64b66b_pcs_pma.xci.out \ +) + +$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + $(call BUILD_VIVADO_IP,aurora_64b66b_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci new file mode 100644 index 000000000..aaba9d9c1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci @@ -0,0 +1,1780 @@ + + + xilinx.com + xci + unknown + 1.0 + + + aurora_64b66b_pcs_pma + + + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 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+ 78.125 + 20 + AC + AUTO + 0 + PROGRAMMABLE + 800 + false + false + 0 + false + false + Duplex + AXI4_LITE + None + Streaming + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v new file mode 100644 index 000000000..39ed52f8c --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v @@ -0,0 +1,329 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_axis_mac #( + parameter PHY_ENDIANNESS = "LITTLE", //{"LITTLE, "BIG"} + parameter PACKET_MODE = 0, + parameter MAX_PACKET_SIZE = 512, + parameter BIST_ENABLED = 1 +) ( + // Clocks and resets + input phy_clk, + input phy_rst, + input sys_clk, + input sys_rst, + input clear, + // PHY TX Interface (Synchronous to phy_clk) + output [63:0] phy_m_axis_tdata, + output phy_m_axis_tvalid, + input phy_m_axis_tready, + // PHY RX Interface (Synchronous to phy_clk) + input [63:0] phy_s_axis_tdata, + input phy_s_axis_tvalid, + // User TX Interface (Synchronous to sys_clk) + input [63:0] s_axis_tdata, + input s_axis_tlast, + input s_axis_tvalid, + output s_axis_tready, + // User RX Interface (Synchronous to sys_clk) + output [63:0] m_axis_tdata, + output m_axis_tlast, + output m_axis_tvalid, + input m_axis_tready, + // PHY Status Inputs (Synchronous to phy_clk) + input channel_up, + input hard_err, + input soft_err, + // Status and Error Outputs (Synchronous to sys_clk) + output [31:0] overruns, + output [31:0] soft_errors, + output reg [31:0] checksum_errors, + output critical_err, + // BIST Interface (Synchronous to sys_clk) + input bist_gen_en, + input [5:0] bist_gen_rate, + input bist_checker_en, + input bist_loopback_en, + output reg bist_checker_locked, + output reg [47:0] bist_checker_samps, + output reg [47:0] bist_checker_errors +); + + // ---------------------------------------------- + // Resets, Clears, Clock crossings + // ---------------------------------------------- + + wire phy_s_axis_tready; // Internal only. The PHY has no backpressure signal. + + // Stay idle if the PHY is not up or if it experiences a fatal error + wire clear_sysclk, clear_phyclk; + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_phyclk_i ( + .clk(phy_clk), .rst(1'b0 /* no reset */), .in((~channel_up) | hard_err | clear), .out(clear_phyclk)); + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_sysclk_i ( + .clk(sys_clk), .rst(1'b0 /* no reset */), .in(clear_phyclk), .out(clear_sysclk)); + + // ---------------------------------------------- + // Counters + // ---------------------------------------------- + + reg [31:0] overruns_reg; + reg [31:0] soft_errors_reg; + + // Counter for recoverable errors. For reporting only. + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + soft_errors_reg <= 32'd0; + else if (soft_err) + soft_errors_reg <= soft_errors_reg + 32'd1; + + // Tag an overrun if the FIFO is full. Samples will get dropped + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + overruns_reg <= 32'd0; + else if (phy_s_axis_tvalid & ~phy_s_axis_tready) + overruns_reg <= overruns_reg + 32'd1; + + wire [7:0] dummy0; + fifo_short_2clk status_counters_2clk_i ( + .rst(phy_rst), + .wr_clk(phy_clk), .din({8'h00, soft_errors_reg, overruns_reg}), .wr_en(1'b1), .full(), .wr_data_count(), + .rd_clk(sys_clk), .dout({dummy0, soft_errors, overruns}), .rd_en(1'b1), .empty(), .rd_data_count() + ); + + // ---------------------------------------------- + // BIST Wires + // ---------------------------------------------- + + wire [63:0] bist_o_tdata; + wire bist_o_tvalid, bist_o_tready; + wire [63:0] bist_i_tdata; + wire bist_i_tvalid, bist_i_tready; + wire [63:0] loopback_tdata; + wire loopback_tvalid, loopback_tready; + reg bist_gen_en_reg = 1'b0, bist_checker_en_reg = 1'b0, bist_loopback_en_reg = 1'b0; + reg [5:0] bist_gen_rate_reg = 'd0; + + generate if (BIST_ENABLED == 1) begin + // Pipeline control signals + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) begin + bist_gen_en_reg <= 1'b0; + bist_checker_en_reg <= 1'b0; + bist_loopback_en_reg <= 1'b0; + bist_gen_rate_reg <= 'd0; + end else begin + bist_gen_en_reg <= bist_gen_en; + bist_checker_en_reg <= bist_checker_en; + bist_loopback_en_reg <= bist_loopback_en; + bist_gen_rate_reg <= bist_gen_rate; + end + end + end endgenerate + // ---------------------------------------------- + // RX Data Path + // ---------------------------------------------- + + wire [63:0] i_raw_tdata; + wire i_raw_tvalid, i_raw_tready; + + wire [63:0] i_pip_tdata; + wire i_pip_tvalid, i_pip_tready; + + wire [63:0] i_pkt_tdata; + wire i_pkt_tlast, i_pkt_tvalid, i_pkt_tready; + + wire [63:0] i_gt_tdata; + wire i_gt_tlast, i_gt_tvalid, i_gt_tready; + + wire checksum_err; + + wire [63:0] phy_s_axis_tdata_endian, phy_m_axis_tdata_endian; + + generate if (PHY_ENDIANNESS == "BIG") begin + assign phy_s_axis_tdata_endian = { + phy_s_axis_tdata[7:0], phy_s_axis_tdata[15:8], phy_s_axis_tdata[23:16], phy_s_axis_tdata[31:24], + phy_s_axis_tdata[39:32], phy_s_axis_tdata[47:40], phy_s_axis_tdata[55:48], phy_s_axis_tdata[63:56] + }; + assign phy_m_axis_tdata = { + phy_m_axis_tdata_endian[7:0], phy_m_axis_tdata_endian[15:8], phy_m_axis_tdata_endian[23:16], phy_m_axis_tdata_endian[31:24], + phy_m_axis_tdata_endian[39:32], phy_m_axis_tdata_endian[47:40], phy_m_axis_tdata_endian[55:48], phy_m_axis_tdata_endian[63:56] + }; + end else begin + assign phy_s_axis_tdata_endian = phy_s_axis_tdata; + assign phy_m_axis_tdata = phy_m_axis_tdata_endian; + end endgenerate + + // Large FIFO must be able to run input side at 64b@156MHz to sustain 10Gb Rx. + axi64_4k_2clk_fifo ingress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(phy_clk), + .s_axis_tdata(phy_s_axis_tdata_endian), .s_axis_tlast(phy_s_axis_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(phy_s_axis_tvalid), .s_axis_tready(phy_s_axis_tready), .axis_wr_data_count(), + .m_aclk(sys_clk), + .m_axis_tdata(i_raw_tdata), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(i_raw_tvalid), .m_axis_tready(i_raw_tready), .axis_rd_data_count() + ); + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(64)) input_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_raw_tdata), .i_tvalid(i_raw_tvalid), .i_tready(i_raw_tready), + .o_tdata(i_pip_tdata), .o_tvalid(i_pip_tvalid), + .o_tready(bist_checker_en_reg ? bist_i_tready : (bist_loopback_en_reg ? loopback_tready : i_pip_tready)), + .space(), .occupied() + ); + + assign bist_i_tdata = i_pip_tdata; + assign bist_i_tvalid = i_pip_tvalid & bist_checker_en_reg; + + assign loopback_tdata = i_pip_tdata; + assign loopback_tvalid = i_pip_tvalid & bist_loopback_en_reg; + + axi_strip_preamble #(.WIDTH(64), .MAX_PKT_SIZE(MAX_PACKET_SIZE)) axi_strip_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_pip_tdata), .i_tvalid(i_pip_tvalid & ~bist_checker_en_reg & ~bist_loopback_en_reg), .i_tready(i_pip_tready), + .o_tdata(i_gt_tdata), .o_tlast(i_gt_tlast), .o_tvalid(i_gt_tvalid), .o_tready(i_gt_tready), + .crc_err(checksum_err), .pkt_dropped(), .crit_error(critical_err) + ); + + axi_fifo_flop #(.WIDTH(65)) input_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({i_gt_tlast, i_gt_tdata}), .i_tvalid(i_gt_tvalid), .i_tready(i_gt_tready), + .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready), + .space(), .occupied() + ); + + always @(posedge sys_clk) + if (sys_rst | clear_sysclk) + checksum_errors <= 32'd0; + else if (checksum_err) + checksum_errors <= checksum_errors + 32'd1; + + // ---------------------------------------------- + // TX Data Path + // ---------------------------------------------- + + wire [63:0] o_pkt_tdata; + wire o_pkt_tlast, o_pkt_tvalid, o_pkt_tready; + + wire [63:0] o_pip_tdata; + wire o_pip_tvalid, o_pip_tready; + + wire [63:0] o_raw_tdata; + wire o_raw_tvalid, o_raw_tready; + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(65)) output_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({s_axis_tlast, s_axis_tdata}), .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready), + .o_tdata({o_pkt_tlast, o_pkt_tdata}), .o_tvalid(o_pkt_tvalid), .o_tready(o_pkt_tready), + .space(), .occupied() + ); + + // Insert preamble and EOP + axi_add_preamble #(.WIDTH(64)) axi_add_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(o_pkt_tdata), .i_tlast(o_pkt_tlast), .i_tvalid(o_pkt_tvalid), .i_tready(o_pkt_tready), + .o_tdata(o_pip_tdata), .o_tvalid(o_pip_tvalid), .o_tready(o_pip_tready & ~bist_gen_en_reg & ~bist_loopback_en_reg) + ); + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(64)) output_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(bist_gen_en_reg ? bist_o_tdata : (bist_loopback_en_reg ? loopback_tdata : o_pip_tdata)), + .i_tvalid(bist_gen_en_reg ? bist_o_tvalid : (bist_loopback_en_reg ? loopback_tvalid : o_pip_tvalid)), + .i_tready(o_pip_tready), + .o_tdata(o_raw_tdata), .o_tvalid(o_raw_tvalid), .o_tready(o_raw_tready), + .space(), .occupied() + ); + + assign bist_o_tready = o_pip_tready; + assign loopback_tready = o_pip_tready; + + // Egress FIFO + axi64_4k_2clk_fifo egress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(sys_clk), + .s_axis_tdata(o_raw_tdata), .s_axis_tlast(o_raw_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(o_raw_tvalid), .s_axis_tready(o_raw_tready), .axis_wr_data_count(), + .m_aclk(phy_clk), + .m_axis_tdata(phy_m_axis_tdata_endian), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(phy_m_axis_tvalid), .m_axis_tready(phy_m_axis_tready), .axis_rd_data_count() + ); + + // ------------------------------------------------- + // BIST: Generator and checker for a LFSR polynomial + // ------------------------------------------------- + localparam LFSR_LEN = 32; + localparam LFSR_SEED = {LFSR_LEN{1'b1}}; + + function [LFSR_LEN-1:0] compute_lfsr_next; + input [LFSR_LEN-1:0] current; + // Maximal length polynomial: x^32 + x^22 + x^2 + x^1 + 1 + compute_lfsr_next = {current[30:0], current[31]^current[21]^current[1]^current[0]}; + endfunction + + function [63:0] lfsr_to_axis; + input [LFSR_LEN-1:0] lfsr; + lfsr_to_axis = {~lfsr, lfsr}; + endfunction + + function [LFSR_LEN-1:0] axis_to_lfsr; + input [63:0] axis; + axis_to_lfsr = axis[LFSR_LEN-1:0]; + endfunction + + generate if (BIST_ENABLED == 1) begin + // Throttle outgoing LFSR to based on the specified rate + // BIST Throughput = sys_clk BW * (bist_gen_rate+1)/64 + reg [5:0] throttle_cnt; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) + throttle_cnt <= 6'd0; + else if (bist_gen_en_reg) + throttle_cnt <= throttle_cnt + 6'd1; + end + // NOTE: This techinically violates AXIS spec (valid revocation) + assign bist_o_tvalid = bist_gen_en_reg && (throttle_cnt <= bist_gen_rate_reg); + + // Unsynchronized LFSR generator (for BIST output) + reg [LFSR_LEN-1:0] lfsr_gen = LFSR_SEED, lfsr_check = LFSR_SEED; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_gen_en_reg) + lfsr_gen <= LFSR_SEED; + else if (bist_o_tready & bist_o_tvalid) + lfsr_gen <= compute_lfsr_next(lfsr_gen); + end + assign bist_o_tdata = lfsr_to_axis(lfsr_gen); + + // Synchronized LFSR checker (for BIST input) + wire [LFSR_LEN-1:0] lfsr_next = compute_lfsr_next(lfsr_check);; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_checker_en_reg) begin + bist_checker_locked <= 1'b0; + lfsr_check <= LFSR_SEED; + end else if (bist_i_tvalid && bist_i_tready) begin + lfsr_check <= axis_to_lfsr(bist_i_tdata); + if (bist_i_tdata == lfsr_to_axis(LFSR_SEED)) + bist_checker_locked <= 1'b1; + end + end + + // LFSR checker + always @(posedge sys_clk) begin + if (bist_checker_locked) begin + if (bist_i_tvalid & bist_i_tready) begin + bist_checker_samps <= bist_checker_samps + 48'd1; + if (bist_i_tdata != lfsr_to_axis(lfsr_next)) begin + bist_checker_errors <= bist_checker_errors + 48'd1; + end + end + end else begin + bist_checker_samps <= 48'd0; + bist_checker_errors <= 48'd0; + end + end + assign bist_i_tready = 1'b1; + end endgenerate + +endmodule + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v new file mode 100644 index 000000000..9e98990c1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v @@ -0,0 +1,37 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_phy_clk_gen +( + input refclk_ibuf, + output clk156, + output init_clk +); + + wire init_clk_buf; + + BUFG clk156_bufg_inst ( + .I (refclk_ibuf), + .O (clk156) + ); + + // Divding independent clock by 2 as source for DRP clock + BUFR # ( + .BUFR_DIVIDE ("2") + ) dclk_divide_by_2_buf ( + .I (clk156), + .O (init_clk_buf), + .CE (1'b1), + .CLR (1'b0) + ); + + BUFG dclk_bufg_i ( + .I (init_clk_buf), + .O (init_clk) + ); + +endmodule + + + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_mmcm.v b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_mmcm.v new file mode 100644 index 000000000..c2107f8b1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_mmcm.v @@ -0,0 +1,108 @@ +// +// Copyright 2017 Ettus Research LLC +// + +module aurora_phy_mmcm +( + input aurora_tx_clk_unbuf, + input mmcm_reset, + output user_clk, + output sync_clk, + output mmcm_locked +); + + wire mmcm_fb_clk; + wire user_clk_i; + wire sync_clk_i; + wire aurora_tx_clk; + + BUFG txout_clock_net_i ( + .I(aurora_tx_clk_unbuf), + .O(aurora_tx_clk) + ); + + localparam MULT = 10; + localparam DIVIDE = 5; + localparam CLK_PERIOD = 3.103; + localparam OUT0_DIVIDE = 4; + localparam OUT1_DIVIDE = 2; + localparam OUT2_DIVIDE = 6; + localparam OUT3_DIVIDE = 8; + + MMCME2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (DIVIDE), + .CLKFBOUT_MULT_F (MULT), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (OUT0_DIVIDE), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (CLK_PERIOD), + .CLKOUT1_DIVIDE (OUT1_DIVIDE), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (OUT2_DIVIDE), + .CLKOUT2_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKOUT3_DIVIDE (OUT3_DIVIDE), + .CLKOUT3_PHASE (0.000), + .CLKOUT3_DUTY_CYCLE (0.500), + .CLKOUT3_USE_FINE_PS ("FALSE"), + .REF_JITTER1 (0.010) + ) mmcm_adv_inst ( + .CLKFBOUT (mmcm_fb_clk), + .CLKFBOUTB (), + .CLKOUT0 (user_clk_i), + .CLKOUT0B (), + .CLKOUT1 (sync_clk_i), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (mmcm_fb_clk), + .CLKIN1 (aurora_tx_clk), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (mmcm_locked), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (mmcm_reset) + ); + + BUFG user_clk_net_i ( + .I(user_clk_i), + .O(user_clk) + ); + BUFG sync_clock_net_i ( + .I(sync_clk_i), + .O(sync_clk) + ); +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v new file mode 100644 index 000000000..6b768bfcf --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v @@ -0,0 +1,258 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_phy_x1 #( + parameter SIMULATION = 0 +)( + // Clocks and Resets + input areset, + input refclk, + input user_clk, + input sync_clk, + input init_clk, + input qpllclk, + input qpllrefclk, + output user_rst, + // GTX Serial I/O + input rx_p, + input rx_n, + output tx_p, + output tx_n, + // AXI4-Stream TX Interface + input [63:0] s_axis_tdata, + input s_axis_tvalid, + output s_axis_tready, + // AXI4-Stream RX Interface + output [63:0] m_axis_tdata, + output m_axis_tvalid, + // AXI4-Lite Config Interface + input [31:0] s_axi_awaddr, + input [31:0] s_axi_araddr, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + input s_axi_awvalid, + input s_axi_rready, + output [31:0] s_axi_rdata, + output s_axi_awready, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + output [1:0] s_axi_rresp, + input s_axi_bready, + output s_axi_arready, + output s_axi_rvalid, + input s_axi_arvalid, + input s_axi_wvalid, + // Status and Error Reporting Interface + output reg channel_up, + output reg hard_err, + output reg soft_err, + input qplllock, + input qpllrefclklost, + output qpllreset, + output tx_out_clk, + input mmcm_locked, + output gt_pll_lock +); + + //-------------------------------------------------------------- + // Status and Error Signals + //-------------------------------------------------------------- + wire hard_err_i, soft_err_i, channel_up_i, lane_up_i; + always @(posedge user_clk) begin + hard_err <= hard_err_i; + soft_err <= soft_err_i; + channel_up <= channel_up_i && lane_up_i; + end + + //-------------------------------------------------------------- + // Reset and PMA Init Sequence + //-------------------------------------------------------------- + // Requirements from PG074: + // - It is expected that user_clock is stable when the reset_pb signal is applied. + // - During the board power-on sequence, both the pma_init and reset_pb signals are + // expected to be High. INIT_CLK and GT_REFCLK are expected to be stable during + // power-on for the proper functioning of the Aurora 64B/66B core. When both clocks are + // stable, pma_init is deasserted followed by the deassertion of reset_pb. + // - Normal Operation Reset Sequence: + // 1. Assert reset. Wait for a minimum time equal to 128*user_clk's time-period. + // 2. Assert pma_init. Keep pma_init and reset asserted for at least one second to prevent + // the transmission of CC characters and ensure that the remote agent detects a hot plug event. + // 3. Deassert pma_init. + // 4. Deassert reset_pb. + + localparam PWRON_PMA_INIT_CYC = 32'd1024; + localparam SYSRST_ASSERT_CYC = 32'd128; + localparam PMA_INIT_ASSERT_CYC_LOG2 = (SIMULATION == 1) ? 4 : 26; + localparam SYSRST_DEASSERT_CYC = 32'd20; + + wire reset_iclk, pma_init, reset_pb; + wire gt_pll_lock_iclk, mmcm_locked_iclk; + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b1) ) input_rst_sync_i ( + .clk(init_clk), .rst(1'b0), .in(areset), .out(reset_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) gt_pll_lock_sync_i ( + .clk(init_clk), .rst(1'b0), .in(gt_pll_lock), .out(gt_pll_lock_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) mmcm_locked_sync_i ( + .clk(init_clk), .rst(1'b0), .in(mmcm_locked), .out(mmcm_locked_iclk) + ); + + localparam [2:0] RST_ST_PWRON_PMA_INIT = 3'd0; + localparam [2:0] RST_ST_PWRON_PMA_SYSRST = 3'd1; + localparam [2:0] RST_ST_IDLE = 3'd2; + localparam [2:0] RST_ST_SYSRST_PRE = 3'd3; + localparam [2:0] RST_ST_PMA_INIT = 3'd4; + localparam [2:0] RST_ST_SYSRST_POST = 3'd5; + + reg [2:0] rst_state = RST_ST_PWRON_PMA_INIT; + reg [31:0] rst_counter = PWRON_PMA_INIT_CYC; + + always @(posedge init_clk) begin + case (rst_state) + RST_ST_PWRON_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PWRON_PMA_SYSRST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PWRON_PMA_SYSRST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_IDLE: begin + if (reset_iclk) begin + rst_state <= RST_ST_SYSRST_PRE; + rst_counter <= SYSRST_ASSERT_CYC; + end + end + RST_ST_SYSRST_PRE: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PMA_INIT; + rst_counter <= {{(32-PMA_INIT_ASSERT_CYC_LOG2){1'b0}}, {PMA_INIT_ASSERT_CYC_LOG2{1'b1}}}; + end else if (mmcm_locked_iclk) begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_SYSRST_POST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_SYSRST_POST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + endcase + end + + assign reset_pb = (rst_state != RST_ST_IDLE); + assign pma_init = (rst_state == RST_ST_PMA_INIT || rst_state == RST_ST_PWRON_PMA_INIT); + + //-------------------------------------------------------------- + // GT Common + //-------------------------------------------------------------- + wire gt_qpllclk_quad1_i; + wire gt_qpllrefclk_quad1_i; + wire gt_qpllclk_quad2_i; + wire gt_qpllrefclk_quad2_i; + wire gt_to_common_qpllreset_i; + wire gt_qpllrefclklost_i; + wire gt_qplllock_i; + + assign gt_qpllclk_quad1_i = qpllclk; + assign gt_qpllrefclk_quad1_i = qpllrefclk; + assign gt_qpllclk_quad2_i = qpllclk; + assign gt_qpllrefclk_quad2_i = qpllrefclk; + assign gt_qplllock_i = qplllock; + assign gt_qpllrefclklost_i = qpllrefclklost; + assign qpllreset = gt_to_common_qpllreset_i; + + //-------------------------------------------------------------- + // IP Instantiation + //-------------------------------------------------------------- + + wire gt_rxcdrovrden_i = 1'b0; + wire [2:0] loopback_i = 3'b000; + wire power_down_i = 1'b0; +aurora_64b66b_pcs_pma aurora_64b66b_pcs_pma_i ( + .refclk1_in (refclk), + // TX AXI4-S Interface + .s_axi_tx_tdata (s_axis_tdata), + .s_axi_tx_tvalid (s_axis_tvalid), + .s_axi_tx_tready (s_axis_tready), + // RX AXI4-S Interface + .m_axi_rx_tdata (m_axis_tdata), + .m_axi_rx_tvalid (m_axis_tvalid), + // GTX Serial I/O + .rxp (rx_p), + .rxn (rx_n), + .txp (tx_p), + .txn (tx_n), + // Status and Error + .hard_err (hard_err_i), + .soft_err (soft_err_i), + .channel_up (channel_up_i), + .lane_up (lane_up_i), + // System Interface + .mmcm_not_locked (!mmcm_locked), + .user_clk (user_clk), + .sync_clk (sync_clk), + .reset_pb (reset_pb), + .gt_rxcdrovrden_in (gt_rxcdrovrden_i), + .power_down (power_down_i), + .loopback (loopback_i), + .pma_init (pma_init), + .gt_pll_lock (gt_pll_lock), + .drp_clk_in (init_clk), + .gt_qpllclk_quad1_in (gt_qpllclk_quad1_i), + .gt_qpllrefclk_quad1_in (gt_qpllrefclk_quad1_i), + .gt_to_common_qpllreset_out(gt_to_common_qpllreset_i), + .gt_qplllock_in (gt_qplllock_i), + .gt_qpllrefclklost_in (gt_qpllrefclklost_i), + // AXI4-Lite config + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bready (s_axi_bready), + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_rdata (s_axi_rdata), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rresp (s_axi_rresp), + .s_axi_rready (s_axi_rready), + // GTXE2 COMMON DRP Ports + .qpll_drpaddr_in (qpll_drpaddr_in_i), + .qpll_drpdi_in (qpll_drpdi_in_i), + .qpll_drpdo_out (), + .qpll_drprdy_out (), + .qpll_drpen_in (qpll_drpen_in_i), + .qpll_drpwe_in (qpll_drpwe_in_i), + .init_clk (init_clk), + .link_reset_out (), + .sys_reset_out (user_rst), + .tx_out_clk (tx_out_clk) + ); +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/Makefile.inc new file mode 100644 index 000000000..34dacff4f --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2015 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS = $(IP_BUILD_DIR)/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci + +IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS = $(addprefix $(IP_BUILD_DIR)/axi3_to_axi4lite_protocol_converter/, \ +axi3_to_axi4lite_protocol_converter.xci.out \ +synth/axi3_to_axi4lite_protocol_converter.v \ +) + +$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS) $(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS) : $(IP_DIR)/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci + $(call BUILD_VIVADO_IP,axi3_to_axi4lite_protocol_converter,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci b/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci new file mode 100644 index 000000000..344851bf8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi3_to_axi4lite_protocol_converter + + + + + + 10000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + ACTIVE_LOW + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 12 + 0 + 16 + 2 + 1 + 2 + 1 + 0.000 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 1 + 1 + 1 + 32 + 12 + 1 + 1 + 0 + 1 + 1 + zynq + 0 + 2 + 1 + 2 + 32 + 0 + 0 + 0 + axi3_to_axi4lite_protocol_converter + 32 + 12 + AXI4LITE + READ_WRITE + 0 + AXI3 + 2 + 0 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 19 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/Makefile.inc new file mode 100644 index 000000000..b7f92cf6f --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2015 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS = $(IP_BUILD_DIR)/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci + +IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS = $(addprefix $(IP_BUILD_DIR)/axi4_to_axi3_protocol_converter_32/, \ +axi4_to_axi3_protocol_converter_32.xci.out \ +synth/axi4_to_axi3_protocol_converter_32.v \ +) + +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS) $(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS) : $(IP_DIR)/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci + $(call BUILD_VIVADO_IP,axi4_to_axi3_protocol_converter_32,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci new file mode 100644 index 000000000..2fa5f4cac --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci @@ -0,0 +1,149 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi4_to_axi3_protocol_converter_32 + + + + + + 10000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.000 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0 + ACTIVE_LOW + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 6 + 0 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 1 + 1 + 1 + 32 + 6 + 1 + 1 + 0 + 1 + 1 + zynq + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + axi4_to_axi3_protocol_converter_32 + 32 + 6 + AXI3 + READ_WRITE + 0 + AXI4 + 0 + 0 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 19 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/Makefile.inc new file mode 100644 index 000000000..0c68b7a3a --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2015 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS = $(IP_BUILD_DIR)/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci + +IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS = $(addprefix $(IP_BUILD_DIR)/axi4_to_axi3_protocol_converter_64/, \ +axi4_to_axi3_protocol_converter_64.xci.out \ +synth/axi4_to_axi3_protocol_converter_64.v \ +) + +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS) $(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS) : $(IP_DIR)/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci + $(call BUILD_VIVADO_IP,axi4_to_axi3_protocol_converter_64,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci new file mode 100644 index 000000000..fc8b9e67e --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci @@ -0,0 +1,151 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi4_to_axi3_protocol_converter_64 + + + + + + 10000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.000 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0 + ACTIVE_LOW + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 6 + 0 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 1 + 1 + 1 + 64 + 6 + 1 + 1 + 0 + 1 + 1 + zynq + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + axi4_to_axi3_protocol_converter_64 + 64 + 6 + AXI3 + READ_WRITE + 0 + AXI4 + 0 + 0 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 19 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..75bdf99c3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + +IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \ +axi64_4k_2clk_fifo.xci.out \ +synth/axi64_4k_2clk_fifo.vhd \ +) + +$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci b/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci new file mode 100644 index 000000000..26d706087 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci @@ -0,0 +1,584 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi64_4k_2clk_fifo + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 64 + 1 + 1 + 8 + 8 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 10 + BlankString + 18 + 69 + 32 + 64 + 32 + 64 + 2 + 0 + 18 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 12 + 11 + 12 + 11 + 12 + 0 + 1 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 4kx4 + 512x72 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 509 + 13 + 1021 + 13 + 1021 + 13 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 511 + 15 + 1023 + 15 + 1023 + 15 + 1021 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 512 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 9 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Independent_Clock + axi64_4k_2clk_fifo + 64 + false + 10 + false + false + 0 + 2 + 509 + 13 + 1021 + 13 + 1021 + 13 + 3 + false + false + true + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + true + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Common_Clock_Block_RAM + 1 + 1022 + 511 + 15 + 1023 + 15 + 1023 + 15 + 1021 + false + false + false + 0 + AXI_STREAM + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 18 + 1024 + 512 + 16 + 1024 + 16 + 1024 + 16 + false + 18 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 8 + 0 + 0 + 8 + 8 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..647ca003b --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_8K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci + +IP_AXI64_8K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/, \ +axi64_8k_2clk_fifo.xci.out \ +synth/axi64_8k_2clk_fifo.vhd \ +) + +$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_8k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci b/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci new file mode 100644 index 000000000..2f6ec0d88 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci @@ -0,0 +1,582 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi64_8k_2clk_fifo + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 64 + 1 + 1 + 8 + 8 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 10 + BlankString + 18 + 69 + 32 + 64 + 32 + 64 + 2 + 0 + 18 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 12 + 11 + 12 + 11 + 12 + 0 + 1 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 4kx4 + 1kx36 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 1021 + 13 + 1021 + 13 + 1021 + 13 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 1023 + 15 + 1023 + 15 + 1023 + 15 + 1021 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Independent_Clock + axi64_8k_2clk_fifo + 64 + false + 10 + false + false + 0 + 2 + 1021 + 13 + 1021 + 13 + 1021 + 13 + 3 + false + false + true + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + true + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Common_Clock_Block_RAM + 1 + 1022 + 1023 + 15 + 1023 + 15 + 1023 + 15 + 1021 + false + false + false + 0 + AXI_STREAM + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 18 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 18 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 8 + 0 + 0 + 8 + 8 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi_eth_dma/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi_eth_dma/Makefile.inc new file mode 100644 index 000000000..658891469 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_eth_dma/Makefile.inc @@ -0,0 +1,14 @@ +# +# Copyright 2017 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_ETH_DMA_SRCS = $(IP_BUILD_DIR)/axi_eth_dma/axi_eth_dma.xci + +IP_AXI_ETH_DMA_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma/, \ +axi_eth_dma.xci.out \ +) + +$(IP_AXI_ETH_DMA_SRCS) $(IP_AXI_ETH_DMA_OUTS) : $(IP_DIR)/axi_eth_dma/axi_eth_dma.xci + $(call BUILD_VIVADO_IP,axi_eth_dma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi_eth_dma/axi_eth_dma.xci b/fpga/usrp3/top/n3xx/ip/axi_eth_dma/axi_eth_dma.xci new file mode 100644 index 000000000..ec1df69ec --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_eth_dma/axi_eth_dma.xci @@ -0,0 +1,412 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_eth_dma + + + 0 + 0 + 1 + 0 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 256 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 256 + 1 + 2 + 1 + 0.000 + AXI4 + READ_ONLY + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 256 + 2 + 1 + 1 + 0.000 + AXI4 + WRITE_ONLY + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 10 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0.000 + 125 + 0 + zynq + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 16 + 32 + 64 + 32 + 64 + 32 + 64 + 32 + 1 + 1 + 0 + 16 + 0 + 23 + 0 + 32 + 64 + axi_eth_dma + 32 + 125 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 64 + 64 + 64 + 0 + 16 + 1 + 1 + 0 + 16 + 64 + 0 + 23 + 0 + 0 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 20 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/Makefile.inc new file mode 100644 index 000000000..02b27ee68 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCON_2X64_256_BD_SRCS = $(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd \ +$(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml \ +$(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_wrapper.v + +BD_AXI_INTERCON_2X64_256_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/, \ +axi_intercon_2x64_256_bd.bd.out \ +axi_intercon_2x64_256_bd_ooc.xdc \ +) + +$(IP_AXI_INTERCON_2X64_256_BD_SRCS) $(IP_AXI_INTERCON_2X64_256_BD_OUTS) : $(IP_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd + $(call BUILD_VIVADO_BD,axi_intercon_2x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd new file mode 100644 index 000000000..121829558 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd @@ -0,0 +1,715 @@ + + + + + xilinx.com + BlockDiagram + axi_intercon_2x64_256_bd + 1.00.a + + + isTop + true + + + + + M00_AXI + + + + + + DATA_WIDTH + 256 + + + PROTOCOL + AXI4 + + + FREQ_HZ + 200000000 + + + ADDR_WIDTH + 32 + + + NUM_READ_OUTSTANDING + 2 + + + NUM_WRITE_OUTSTANDING + 2 + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_M00_ACLK + + + + + S00_AXI + + + + + + DATA_WIDTH + 64 + + + PROTOCOL + AXI4 + + + FREQ_HZ + 350000000 + + + ID_WIDTH + 1 + + + ADDR_WIDTH + 32 + + + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + BUSER_WIDTH + 0 + + + READ_WRITE_MODE + READ_WRITE + + + HAS_BURST + 1 + + + HAS_LOCK + 1 + + + HAS_PROT + 1 + + + HAS_CACHE + 1 + + + HAS_QOS + 1 + + + HAS_REGION + 1 + + + HAS_WSTRB + 1 + + + HAS_BRESP + 1 + + + HAS_RRESP + 1 + + + SUPPORTS_NARROW_BURST + 1 + + + NUM_READ_OUTSTANDING + 2 + + + NUM_WRITE_OUTSTANDING + 2 + + + MAX_BURST_LENGTH + 256 + + + PHASE + 0.000 + + + + + S01_AXI + + + + + + DATA_WIDTH + 64 + + + PROTOCOL + AXI4 + + + FREQ_HZ + 350000000 + + + ID_WIDTH + 1 + + + ADDR_WIDTH + 32 + + + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + BUSER_WIDTH + 0 + + + READ_WRITE_MODE + READ_WRITE + + + HAS_BURST + 1 + + + HAS_LOCK + 1 + + + HAS_PROT + 1 + + + HAS_CACHE + 1 + + + HAS_QOS + 1 + + + HAS_REGION + 1 + + + HAS_WSTRB + 1 + + + HAS_BRESP + 1 + + + HAS_RRESP + 1 + + + SUPPORTS_NARROW_BURST + 1 + + + NUM_READ_OUTSTANDING + 2 + + + NUM_WRITE_OUTSTANDING + 2 + + + MAX_BURST_LENGTH + 256 + + + PHASE + 0.000 + + + + + CLK.M00_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + M00_AXI_ACLK + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_M00_ACLK + + + ASSOCIATED_RESET + M00_AXI_ARESETN + + + + + RST.M00_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + M00_AXI_ARESETN + + + + + + + CLK.S00_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S00_AXI_ACLK + + + + + + FREQ_HZ + 1000000000 + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_S00_ACLK + + + ASSOCIATED_RESET + S00_AXI_ARESETN + + + + + RST.S00_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S00_AXI_ARESETN + + + + + + + CLK.S01_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S01_AXI_ACLK + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_S01_ACLK + + + ASSOCIATED_RESET + S01_AXI_ARESETN + + + + + RST.S01_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S01_AXI_ARESETN + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + M00_AXI_ACLK + + in + + + + M00_AXI_ARESETN + + in + + + + S00_AXI_ACLK + + in + + + + S00_AXI_ARESETN + + in + + + + S01_AXI_ACLK + + in + + + + S01_AXI_ARESETN + + in + + + + + + + S00_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 32M + + + + + S01_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x02000000 + 32M + + + + + + + M00_AXI + + Reg + 0 + 64K + 32 + register + + + + + + + xilinx.com + BlockDiagram + axi_intercon_2x64_256_bd_imp + 1.00.a + + + m00_rs + + + axi_intercon_2x64_256_bd_m00_rs_0 + 1 + 1 + 1 + + + + s00_rs + + + axi_intercon_2x64_256_bd_s00_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_width_conv + + + axi_intercon_2x64_256_bd_s00_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + s01_rs + + + axi_intercon_2x64_256_bd_s01_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s01_width_conv + + + axi_intercon_2x64_256_bd_s01_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + xbar + + + axi_intercon_2x64_256_bd_xbar_0 + 2 + 1 + 2 + 256 + 1 + 0x00000001 + 0x00000002 + 0x00000003 + 0x00000004 + 0x00000005 + 0x00000006 + 0x00000007 + 0x00000008 + 0x00000009 + 0x0000000a + 0x0000000b + 0x0000000c + 0x0000000d + 0x0000000e + 0x0000000f + + + + s01_rs_256 + + + axi_intercon_2x64_256_bd_s01_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_rs_256 + + + axi_intercon_2x64_256_bd_s00_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + + + s00_rs_M_AXI + + + + + s01_rs_M_AXI + + + + + xbar_M00_AXI + + + + + s00_rs_256_M_AXI + + + + + s01_rs_256_M_AXI + + + + + s00_width_conv_M_AXI + + + + + s01_width_conv_M_AXI + + + + + + + M00_AXI_ACLK_1 + + + + + + + + + + M00_AXI_ARESETN_1 + + + + + + + + + + S00_AXI_ACLK_1 + + + + + + S00_AXI_ARESETN_1 + + + + + + S01_AXI_ACLK_1 + + + + + + S01_AXI_ARESETN_1 + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml new file mode 100644 index 000000000..5e3a0c83e --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml @@ -0,0 +1,89 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_wrapper.v b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_wrapper.v new file mode 100644 index 000000000..06a471d59 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_wrapper.v @@ -0,0 +1,500 @@ +//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +`timescale 1 ps / 1 ps + +module axi_intercon_2x64_256_bd_wrapper + (M00_AXI_ACLK, + M00_AXI_ARESETN, + M00_AXI_ARADDR, + M00_AXI_ARBURST, + M00_AXI_ARCACHE, + M00_AXI_ARID, + M00_AXI_ARLEN, + M00_AXI_ARLOCK, + M00_AXI_ARPROT, + M00_AXI_ARQOS, + M00_AXI_ARREADY, + M00_AXI_ARREGION, + M00_AXI_ARSIZE, + M00_AXI_ARVALID, + M00_AXI_AWADDR, + M00_AXI_AWBURST, + M00_AXI_AWCACHE, + M00_AXI_AWID, + M00_AXI_AWLEN, + M00_AXI_AWLOCK, + M00_AXI_AWPROT, + M00_AXI_AWQOS, + M00_AXI_AWREADY, + M00_AXI_AWREGION, + M00_AXI_AWSIZE, + M00_AXI_AWVALID, + M00_AXI_BID, + M00_AXI_BREADY, + M00_AXI_BRESP, + M00_AXI_BVALID, + M00_AXI_RDATA, + M00_AXI_RID, + M00_AXI_RLAST, + M00_AXI_RREADY, + M00_AXI_RRESP, + M00_AXI_RVALID, + M00_AXI_WDATA, + M00_AXI_WLAST, + M00_AXI_WREADY, + M00_AXI_WSTRB, + M00_AXI_WVALID, + S00_AXI_ACLK, + S00_AXI_ARESETN, + S00_AXI_ARADDR, + S00_AXI_ARBURST, + S00_AXI_ARCACHE, + S00_AXI_ARID, + S00_AXI_ARLEN, + S00_AXI_ARLOCK, + S00_AXI_ARPROT, + S00_AXI_ARQOS, + S00_AXI_ARREADY, + S00_AXI_ARREGION, + S00_AXI_ARSIZE, + S00_AXI_ARVALID, + S00_AXI_AWADDR, + S00_AXI_AWBURST, + S00_AXI_AWCACHE, + S00_AXI_AWID, + S00_AXI_AWLEN, + S00_AXI_AWLOCK, + S00_AXI_AWPROT, + S00_AXI_AWQOS, + S00_AXI_AWREADY, + S00_AXI_AWREGION, + S00_AXI_AWSIZE, + S00_AXI_AWVALID, + S00_AXI_BID, + S00_AXI_BREADY, + S00_AXI_BRESP, + S00_AXI_BVALID, + S00_AXI_RDATA, + S00_AXI_RID, + S00_AXI_RLAST, + S00_AXI_RREADY, + S00_AXI_RRESP, + S00_AXI_RVALID, + S00_AXI_WDATA, + S00_AXI_WLAST, + S00_AXI_WREADY, + S00_AXI_WSTRB, + S00_AXI_WVALID, + S01_AXI_ACLK, + S01_AXI_ARESETN, + S01_AXI_ARADDR, + S01_AXI_ARBURST, + S01_AXI_ARCACHE, + S01_AXI_ARID, + S01_AXI_ARLEN, + S01_AXI_ARLOCK, + S01_AXI_ARPROT, + S01_AXI_ARQOS, + S01_AXI_ARREADY, + S01_AXI_ARREGION, + S01_AXI_ARSIZE, + S01_AXI_ARVALID, + S01_AXI_AWADDR, + S01_AXI_AWBURST, + S01_AXI_AWCACHE, + S01_AXI_AWID, + S01_AXI_AWLEN, + S01_AXI_AWLOCK, + S01_AXI_AWPROT, + S01_AXI_AWQOS, + S01_AXI_AWREADY, + S01_AXI_AWREGION, + S01_AXI_AWSIZE, + S01_AXI_AWVALID, + S01_AXI_BID, + S01_AXI_BREADY, + S01_AXI_BRESP, + S01_AXI_BVALID, + S01_AXI_RDATA, + S01_AXI_RID, + S01_AXI_RLAST, + S01_AXI_RREADY, + S01_AXI_RRESP, + S01_AXI_RVALID, + S01_AXI_WDATA, + S01_AXI_WLAST, + S01_AXI_WREADY, + S01_AXI_WSTRB, + S01_AXI_WVALID); + input M00_AXI_ACLK; + input M00_AXI_ARESETN; + output [31:0]M00_AXI_ARADDR; + output [1:0]M00_AXI_ARBURST; + output [3:0]M00_AXI_ARCACHE; + output [0:0]M00_AXI_ARID; + output [7:0]M00_AXI_ARLEN; + output [0:0]M00_AXI_ARLOCK; + output [2:0]M00_AXI_ARPROT; + output [3:0]M00_AXI_ARQOS; + input M00_AXI_ARREADY; + output [3:0]M00_AXI_ARREGION; + output [2:0]M00_AXI_ARSIZE; + output M00_AXI_ARVALID; + output [31:0]M00_AXI_AWADDR; + output [1:0]M00_AXI_AWBURST; + output [3:0]M00_AXI_AWCACHE; + output [0:0]M00_AXI_AWID; + output [7:0]M00_AXI_AWLEN; + output [0:0]M00_AXI_AWLOCK; + output [2:0]M00_AXI_AWPROT; + output [3:0]M00_AXI_AWQOS; + input M00_AXI_AWREADY; + output [3:0]M00_AXI_AWREGION; + output [2:0]M00_AXI_AWSIZE; + output M00_AXI_AWVALID; + input [0:0]M00_AXI_BID; + output M00_AXI_BREADY; + input [1:0]M00_AXI_BRESP; + input M00_AXI_BVALID; + input [255:0]M00_AXI_RDATA; + input [0:0]M00_AXI_RID; + input M00_AXI_RLAST; + output M00_AXI_RREADY; + input [1:0]M00_AXI_RRESP; + input M00_AXI_RVALID; + output [255:0]M00_AXI_WDATA; + output M00_AXI_WLAST; + input M00_AXI_WREADY; + output [31:0]M00_AXI_WSTRB; + output M00_AXI_WVALID; + input S00_AXI_ACLK; + input S00_AXI_ARESETN; + input [31:0]S00_AXI_ARADDR; + input [1:0]S00_AXI_ARBURST; + input [3:0]S00_AXI_ARCACHE; + input [0:0]S00_AXI_ARID; + input [7:0]S00_AXI_ARLEN; + input [0:0]S00_AXI_ARLOCK; + input [2:0]S00_AXI_ARPROT; + input [3:0]S00_AXI_ARQOS; + output S00_AXI_ARREADY; + input [3:0]S00_AXI_ARREGION; + input [2:0]S00_AXI_ARSIZE; + input S00_AXI_ARVALID; + input [31:0]S00_AXI_AWADDR; + input [1:0]S00_AXI_AWBURST; + input [3:0]S00_AXI_AWCACHE; + input [0:0]S00_AXI_AWID; + input [7:0]S00_AXI_AWLEN; + input [0:0]S00_AXI_AWLOCK; + input [2:0]S00_AXI_AWPROT; + input [3:0]S00_AXI_AWQOS; + output S00_AXI_AWREADY; + input [3:0]S00_AXI_AWREGION; + input [2:0]S00_AXI_AWSIZE; + input S00_AXI_AWVALID; + output [0:0]S00_AXI_BID; + input S00_AXI_BREADY; + output [1:0]S00_AXI_BRESP; + output S00_AXI_BVALID; + output [63:0]S00_AXI_RDATA; + output [0:0]S00_AXI_RID; + output S00_AXI_RLAST; + input S00_AXI_RREADY; + output [1:0]S00_AXI_RRESP; + output S00_AXI_RVALID; + input [63:0]S00_AXI_WDATA; + input S00_AXI_WLAST; + output S00_AXI_WREADY; + input [7:0]S00_AXI_WSTRB; + input S00_AXI_WVALID; + input S01_AXI_ACLK; + input S01_AXI_ARESETN; + input [31:0]S01_AXI_ARADDR; + input [1:0]S01_AXI_ARBURST; + input [3:0]S01_AXI_ARCACHE; + input [0:0]S01_AXI_ARID; + input [7:0]S01_AXI_ARLEN; + input [0:0]S01_AXI_ARLOCK; + input [2:0]S01_AXI_ARPROT; + input [3:0]S01_AXI_ARQOS; + output S01_AXI_ARREADY; + input [3:0]S01_AXI_ARREGION; + input [2:0]S01_AXI_ARSIZE; + input S01_AXI_ARVALID; + input [31:0]S01_AXI_AWADDR; + input [1:0]S01_AXI_AWBURST; + input [3:0]S01_AXI_AWCACHE; + input [0:0]S01_AXI_AWID; + input [7:0]S01_AXI_AWLEN; + input [0:0]S01_AXI_AWLOCK; + input [2:0]S01_AXI_AWPROT; + input [3:0]S01_AXI_AWQOS; + output S01_AXI_AWREADY; + input [3:0]S01_AXI_AWREGION; + input [2:0]S01_AXI_AWSIZE; + input S01_AXI_AWVALID; + output [0:0]S01_AXI_BID; + input S01_AXI_BREADY; + output [1:0]S01_AXI_BRESP; + output S01_AXI_BVALID; + output [63:0]S01_AXI_RDATA; + output [0:0]S01_AXI_RID; + output S01_AXI_RLAST; + input S01_AXI_RREADY; + output [1:0]S01_AXI_RRESP; + output S01_AXI_RVALID; + input [63:0]S01_AXI_WDATA; + input S01_AXI_WLAST; + output S01_AXI_WREADY; + input [7:0]S01_AXI_WSTRB; + input S01_AXI_WVALID; + + wire M00_AXI_ACLK; + wire M00_AXI_ARESETN; + wire [31:0]M00_AXI_ARADDR; + wire [1:0]M00_AXI_ARBURST; + wire [3:0]M00_AXI_ARCACHE; + wire [0:0]M00_AXI_ARID; + wire [7:0]M00_AXI_ARLEN; + wire [0:0]M00_AXI_ARLOCK; + wire [2:0]M00_AXI_ARPROT; + wire [3:0]M00_AXI_ARQOS; + wire M00_AXI_ARREADY; + wire [3:0]M00_AXI_ARREGION; + wire [2:0]M00_AXI_ARSIZE; + wire M00_AXI_ARVALID; + wire [31:0]M00_AXI_AWADDR; + wire [1:0]M00_AXI_AWBURST; + wire [3:0]M00_AXI_AWCACHE; + wire [0:0]M00_AXI_AWID; + wire [7:0]M00_AXI_AWLEN; + wire [0:0]M00_AXI_AWLOCK; + wire [2:0]M00_AXI_AWPROT; + wire [3:0]M00_AXI_AWQOS; + wire M00_AXI_AWREADY; + wire [3:0]M00_AXI_AWREGION; + wire [2:0]M00_AXI_AWSIZE; + wire M00_AXI_AWVALID; + wire [0:0]M00_AXI_BID; + wire M00_AXI_BREADY; + wire [1:0]M00_AXI_BRESP; + wire M00_AXI_BVALID; + wire [255:0]M00_AXI_RDATA; + wire [0:0]M00_AXI_RID; + wire M00_AXI_RLAST; + wire M00_AXI_RREADY; + wire [1:0]M00_AXI_RRESP; + wire M00_AXI_RVALID; + wire [255:0]M00_AXI_WDATA; + wire M00_AXI_WLAST; + wire M00_AXI_WREADY; + wire [31:0]M00_AXI_WSTRB; + wire M00_AXI_WVALID; + wire S00_AXI_ACLK; + wire S00_AXI_ARESETN; + wire [31:0]S00_AXI_ARADDR; + wire [1:0]S00_AXI_ARBURST; + wire [3:0]S00_AXI_ARCACHE; + wire [0:0]S00_AXI_ARID; + wire [7:0]S00_AXI_ARLEN; + wire [0:0]S00_AXI_ARLOCK; + wire [2:0]S00_AXI_ARPROT; + wire [3:0]S00_AXI_ARQOS; + wire S00_AXI_ARREADY; + wire [3:0]S00_AXI_ARREGION; + wire [2:0]S00_AXI_ARSIZE; + wire S00_AXI_ARVALID; + wire [31:0]S00_AXI_AWADDR; + wire [1:0]S00_AXI_AWBURST; + wire [3:0]S00_AXI_AWCACHE; + wire [0:0]S00_AXI_AWID; + wire [7:0]S00_AXI_AWLEN; + wire [0:0]S00_AXI_AWLOCK; + wire [2:0]S00_AXI_AWPROT; + wire [3:0]S00_AXI_AWQOS; + wire S00_AXI_AWREADY; + wire [3:0]S00_AXI_AWREGION; + wire [2:0]S00_AXI_AWSIZE; + wire S00_AXI_AWVALID; + wire [0:0]S00_AXI_BID; + wire S00_AXI_BREADY; + wire [1:0]S00_AXI_BRESP; + wire S00_AXI_BVALID; + wire [63:0]S00_AXI_RDATA; + wire [0:0]S00_AXI_RID; + wire S00_AXI_RLAST; + wire S00_AXI_RREADY; + wire [1:0]S00_AXI_RRESP; + wire S00_AXI_RVALID; + wire [63:0]S00_AXI_WDATA; + wire S00_AXI_WLAST; + wire S00_AXI_WREADY; + wire [7:0]S00_AXI_WSTRB; + wire S00_AXI_WVALID; + wire S01_AXI_ACLK; + wire S01_AXI_ARESETN; + wire [31:0]S01_AXI_ARADDR; + wire [1:0]S01_AXI_ARBURST; + wire [3:0]S01_AXI_ARCACHE; + wire [0:0]S01_AXI_ARID; + wire [7:0]S01_AXI_ARLEN; + wire [0:0]S01_AXI_ARLOCK; + wire [2:0]S01_AXI_ARPROT; + wire [3:0]S01_AXI_ARQOS; + wire S01_AXI_ARREADY; + wire [3:0]S01_AXI_ARREGION; + wire [2:0]S01_AXI_ARSIZE; + wire S01_AXI_ARVALID; + wire [31:0]S01_AXI_AWADDR; + wire [1:0]S01_AXI_AWBURST; + wire [3:0]S01_AXI_AWCACHE; + wire [0:0]S01_AXI_AWID; + wire [7:0]S01_AXI_AWLEN; + wire [0:0]S01_AXI_AWLOCK; + wire [2:0]S01_AXI_AWPROT; + wire [3:0]S01_AXI_AWQOS; + wire S01_AXI_AWREADY; + wire [3:0]S01_AXI_AWREGION; + wire [2:0]S01_AXI_AWSIZE; + wire S01_AXI_AWVALID; + wire [0:0]S01_AXI_BID; + wire S01_AXI_BREADY; + wire [1:0]S01_AXI_BRESP; + wire S01_AXI_BVALID; + wire [63:0]S01_AXI_RDATA; + wire [0:0]S01_AXI_RID; + wire S01_AXI_RLAST; + wire S01_AXI_RREADY; + wire [1:0]S01_AXI_RRESP; + wire S01_AXI_RVALID; + wire [63:0]S01_AXI_WDATA; + wire S01_AXI_WLAST; + wire S01_AXI_WREADY; + wire [7:0]S01_AXI_WSTRB; + wire S01_AXI_WVALID; + + axi_intercon_2x64_256_bd axi_intercon_2x64_256_bd_i ( + .M00_AXI_ACLK(M00_AXI_ACLK), + .M00_AXI_ARESETN(M00_AXI_ARESETN), + .M00_AXI_araddr(M00_AXI_ARADDR), + .M00_AXI_arburst(M00_AXI_ARBURST), + .M00_AXI_arcache(M00_AXI_ARCACHE), + .M00_AXI_arid(M00_AXI_ARID), + .M00_AXI_arlen(M00_AXI_ARLEN), + .M00_AXI_arlock(M00_AXI_ARLOCK), + .M00_AXI_arprot(M00_AXI_ARPROT), + .M00_AXI_arqos(M00_AXI_ARQOS), + .M00_AXI_arready(M00_AXI_ARREADY), + .M00_AXI_arregion(M00_AXI_ARREGION), + .M00_AXI_arsize(M00_AXI_ARSIZE), + .M00_AXI_arvalid(M00_AXI_ARVALID), + .M00_AXI_awaddr(M00_AXI_AWADDR), + .M00_AXI_awburst(M00_AXI_AWBURST), + .M00_AXI_awcache(M00_AXI_AWCACHE), + .M00_AXI_awid(M00_AXI_AWID), + .M00_AXI_awlen(M00_AXI_AWLEN), + .M00_AXI_awlock(M00_AXI_AWLOCK), + .M00_AXI_awprot(M00_AXI_AWPROT), + .M00_AXI_awqos(M00_AXI_AWQOS), + .M00_AXI_awready(M00_AXI_AWREADY), + .M00_AXI_awregion(M00_AXI_AWREGION), + .M00_AXI_awsize(M00_AXI_AWSIZE), + .M00_AXI_awvalid(M00_AXI_AWVALID), + .M00_AXI_bid(M00_AXI_BID), + .M00_AXI_bready(M00_AXI_BREADY), + .M00_AXI_bresp(M00_AXI_BRESP), + .M00_AXI_bvalid(M00_AXI_BVALID), + .M00_AXI_rdata(M00_AXI_RDATA), + .M00_AXI_rid(M00_AXI_RID), + .M00_AXI_rlast(M00_AXI_RLAST), + .M00_AXI_rready(M00_AXI_RREADY), + .M00_AXI_rresp(M00_AXI_RRESP), + .M00_AXI_rvalid(M00_AXI_RVALID), + .M00_AXI_wdata(M00_AXI_WDATA), + .M00_AXI_wlast(M00_AXI_WLAST), + .M00_AXI_wready(M00_AXI_WREADY), + .M00_AXI_wstrb(M00_AXI_WSTRB), + .M00_AXI_wvalid(M00_AXI_WVALID), + .S00_AXI_ACLK(S00_AXI_ACLK), + .S00_AXI_ARESETN(S00_AXI_ARESETN), + .S00_AXI_araddr(S00_AXI_ARADDR), + .S00_AXI_arburst(S00_AXI_ARBURST), + .S00_AXI_arcache(S00_AXI_ARCACHE), + .S00_AXI_arid(S00_AXI_ARID), + .S00_AXI_arlen(S00_AXI_ARLEN), + .S00_AXI_arlock(S00_AXI_ARLOCK), + .S00_AXI_arprot(S00_AXI_ARPROT), + .S00_AXI_arqos(S00_AXI_ARQOS), + .S00_AXI_arready(S00_AXI_ARREADY), + .S00_AXI_arregion(S00_AXI_ARREGION), + .S00_AXI_arsize(S00_AXI_ARSIZE), + .S00_AXI_arvalid(S00_AXI_ARVALID), + .S00_AXI_awaddr(S00_AXI_AWADDR), + .S00_AXI_awburst(S00_AXI_AWBURST), + .S00_AXI_awcache(S00_AXI_AWCACHE), + .S00_AXI_awid(S00_AXI_AWID), + .S00_AXI_awlen(S00_AXI_AWLEN), + .S00_AXI_awlock(S00_AXI_AWLOCK), + .S00_AXI_awprot(S00_AXI_AWPROT), + .S00_AXI_awqos(S00_AXI_AWQOS), + .S00_AXI_awready(S00_AXI_AWREADY), + .S00_AXI_awregion(S00_AXI_AWREGION), + .S00_AXI_awsize(S00_AXI_AWSIZE), + .S00_AXI_awvalid(S00_AXI_AWVALID), + .S00_AXI_bid(S00_AXI_BID), + .S00_AXI_bready(S00_AXI_BREADY), + .S00_AXI_bresp(S00_AXI_BRESP), + .S00_AXI_bvalid(S00_AXI_BVALID), + .S00_AXI_rdata(S00_AXI_RDATA), + .S00_AXI_rid(S00_AXI_RID), + .S00_AXI_rlast(S00_AXI_RLAST), + .S00_AXI_rready(S00_AXI_RREADY), + .S00_AXI_rresp(S00_AXI_RRESP), + .S00_AXI_rvalid(S00_AXI_RVALID), + .S00_AXI_wdata(S00_AXI_WDATA), + .S00_AXI_wlast(S00_AXI_WLAST), + .S00_AXI_wready(S00_AXI_WREADY), + .S00_AXI_wstrb(S00_AXI_WSTRB), + .S00_AXI_wvalid(S00_AXI_WVALID), + .S01_AXI_ACLK(S01_AXI_ACLK), + .S01_AXI_ARESETN(S01_AXI_ARESETN), + .S01_AXI_araddr(S01_AXI_ARADDR), + .S01_AXI_arburst(S01_AXI_ARBURST), + .S01_AXI_arcache(S01_AXI_ARCACHE), + .S01_AXI_arid(S01_AXI_ARID), + .S01_AXI_arlen(S01_AXI_ARLEN), + .S01_AXI_arlock(S01_AXI_ARLOCK), + .S01_AXI_arprot(S01_AXI_ARPROT), + .S01_AXI_arqos(S01_AXI_ARQOS), + .S01_AXI_arready(S01_AXI_ARREADY), + .S01_AXI_arregion(S01_AXI_ARREGION), + .S01_AXI_arsize(S01_AXI_ARSIZE), + .S01_AXI_arvalid(S01_AXI_ARVALID), + .S01_AXI_awaddr(S01_AXI_AWADDR), + .S01_AXI_awburst(S01_AXI_AWBURST), + .S01_AXI_awcache(S01_AXI_AWCACHE), + .S01_AXI_awid(S01_AXI_AWID), + .S01_AXI_awlen(S01_AXI_AWLEN), + .S01_AXI_awlock(S01_AXI_AWLOCK), + .S01_AXI_awprot(S01_AXI_AWPROT), + .S01_AXI_awqos(S01_AXI_AWQOS), + .S01_AXI_awready(S01_AXI_AWREADY), + .S01_AXI_awregion(S01_AXI_AWREGION), + .S01_AXI_awsize(S01_AXI_AWSIZE), + .S01_AXI_awvalid(S01_AXI_AWVALID), + .S01_AXI_bid(S01_AXI_BID), + .S01_AXI_bready(S01_AXI_BREADY), + .S01_AXI_bresp(S01_AXI_BRESP), + .S01_AXI_bvalid(S01_AXI_BVALID), + .S01_AXI_rdata(S01_AXI_RDATA), + .S01_AXI_rid(S01_AXI_RID), + .S01_AXI_rlast(S01_AXI_RLAST), + .S01_AXI_rready(S01_AXI_RREADY), + .S01_AXI_rresp(S01_AXI_RRESP), + .S01_AXI_rvalid(S01_AXI_RVALID), + .S01_AXI_wdata(S01_AXI_WDATA), + .S01_AXI_wlast(S01_AXI_WLAST), + .S01_AXI_wready(S01_AXI_WREADY), + .S01_AXI_wstrb(S01_AXI_WSTRB), + .S01_AXI_wvalid(S01_AXI_WVALID)); +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc new file mode 100644 index 000000000..2f5ba57c6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCON_4X64_256_BD_SRCS = $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v + +BD_AXI_INTERCON_4X64_256_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/, \ +axi_intercon_4x64_256_bd.bd.out \ +axi_intercon_4x64_256_bd_ooc.xdc \ +) + +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) $(IP_AXI_INTERCON_4X64_256_BD_OUTS) : $(IP_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd + $(call BUILD_VIVADO_BD,axi_intercon_4x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd new file mode 100644 index 000000000..eb6c30100 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd @@ -0,0 +1,2191 @@ + + + + + xilinx.com + BlockDiagram + axi_intercon_4x64_256_bd + 1.00.a + + + isTop + true + + + + + M00_AXI + + + + + + DATA_WIDTH + 256 + + + + + + + + PROTOCOL + AXI4 + + + + + + + + FREQ_HZ + 200000000 + + + + + + + + ID_WIDTH + 4 + + + + + + + + ADDR_WIDTH + 32 + + + + + + + + AWUSER_WIDTH + 0 + + + + + + + + ARUSER_WIDTH + 0 + + + + + + + + WUSER_WIDTH + 0 + + + + + + + + RUSER_WIDTH + 0 + + + + + + + + BUSER_WIDTH + 0 + + + + + + + + READ_WRITE_MODE + READ_WRITE + + + + + + + + HAS_BURST + 1 + + + + + + + + HAS_LOCK + 1 + + + + + + + + HAS_PROT + 1 + + + + + + + + HAS_CACHE + 1 + + + + + + + + HAS_QOS + 1 + + + + + + + + HAS_REGION + 1 + + + + + + + + HAS_WSTRB + 1 + + + + + + + + HAS_BRESP + 1 + + + + + + + + HAS_RRESP + 1 + + + + + + + + SUPPORTS_NARROW_BURST + 1 + + + + + + + + NUM_READ_OUTSTANDING + 2 + + + + + + + + NUM_WRITE_OUTSTANDING + 2 + + + + + + + + MAX_BURST_LENGTH + 256 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_M00_ACLK + + + + + + + + + + S00_AXI + + + + + + DATA_WIDTH + 64 + + + + + + + + PROTOCOL + AXI4 + + + + + + + + FREQ_HZ + 350000000 + + + + + + + + ID_WIDTH + 1 + + + + + + + + ADDR_WIDTH + 32 + + + + + + + + AWUSER_WIDTH + 0 + + + + + + + + ARUSER_WIDTH + 0 + + + + + + + + WUSER_WIDTH + 0 + + + + + + + + RUSER_WIDTH + 0 + + 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+ + + + ASSOCIATED_BUSIF + S00_AXI + + + + + + + + ASSOCIATED_RESET + S00_AXI_ARESETN + + + + + + + + + + RST.S00_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S00_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + CLK.S01_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S01_AXI_ACLK + + + + + + FREQ_HZ + 350000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_S01_ACLK + + + + + + + + ASSOCIATED_BUSIF + S01_AXI + + + + + + + + ASSOCIATED_RESET + S01_AXI_ARESETN + + + + + + + + + + RST.S01_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S01_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + CLK.S02_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S02_AXI_ACLK + + + + + + FREQ_HZ + 350000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_S00_ACLK + + + + + + + + ASSOCIATED_BUSIF + S02_AXI + + + + + + + + ASSOCIATED_RESET + S00_AXI_ARESETN:S02_AXI_ARESETN + + + + + + + + + + RST.S02_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S02_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + CLK.S03_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S03_AXI_ACLK + + + + + + FREQ_HZ + 350000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_S00_ACLK + + + + + + + + ASSOCIATED_BUSIF + S02_AXI:S03_AXI + + + + + + + + ASSOCIATED_RESET + S00_AXI_ARESETN:S02_AXI_ARESETN:S03_AXI_ARESETN + + + + + + + + + + RST.S03_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S03_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + M00_AXI_ACLK + + in + + + + M00_AXI_ARESETN + + in + + + + S00_AXI_ACLK + + in + + + + S00_AXI_ARESETN + + in + + + + S01_AXI_ACLK + + in + + + + S01_AXI_ARESETN + + in + + + + S02_AXI_ACLK + + in + + + + S02_AXI_ARESETN + + in + + + + S03_AXI_ACLK + + in + + + + S03_AXI_ARESETN + + in + + + + + + + S00_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 1G + + + + + S01_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 1G + + + + + S02_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 1G + + + + + S03_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 1G + + + + + + + M00_AXI + + Reg + 0 + 64K + 32 + register + + + + + + + xilinx.com + BlockDiagram + axi_intercon_4x64_256_bd_imp + 1.00.a + + + m00_rs + + + axi_intercon_4x64_256_bd_m00_rs_0 + 4 + 1 + 1 + 1 + + + + s00_rs + + + axi_intercon_4x64_256_bd_s00_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_width_conv + + + axi_intercon_4x64_256_bd_s00_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + s01_rs + + + axi_intercon_4x64_256_bd_s01_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s01_width_conv + + + axi_intercon_4x64_256_bd_s01_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + xbar + + + axi_intercon_4x64_256_bd_xbar_0 + 4 + 1 + 2 + 256 + SAMD + 4 + 0 + 0x00000004 + 0x00000008 + 0x0000000c + 0x00000010 + 0x00000014 + 0x00000018 + 0x0000001c + 0x00000020 + 0x00000024 + 0x00000028 + 0x0000002c + 0x00000030 + 0x00000034 + 0x00000038 + 0x0000003c + + + + s01_rs_256 + + + axi_intercon_4x64_256_bd_s01_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_rs_256 + + + axi_intercon_4x64_256_bd_s00_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + s02_rs + + + axi_intercon_4x64_256_bd_s02_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s03_rs + + + axi_intercon_4x64_256_bd_s03_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s02_width_conv + + + axi_intercon_4x64_256_bd_s02_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + s03_width_conv + + + axi_intercon_4x64_256_bd_s03_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + s03_rs_256 + + + axi_intercon_4x64_256_bd_s03_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + s02_rs_256 + + + axi_intercon_4x64_256_bd_s02_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + + + s00_rs_M_AXI + + + + + s01_rs_M_AXI + + + + + xbar_M00_AXI + + + + + s00_rs_256_M_AXI + + + + + s01_rs_256_M_AXI + + + + + s00_width_conv_M_AXI + + + + + s01_width_conv_M_AXI + + + + + s02_rs_M_AXI + + + + + s03_rs_M_AXI + + + + + s02_width_conv_M_AXI + + + + + s03_width_conv_M_AXI + + + + + s02_rs_256_M_AXI + + + + + s03_rs_256_M_AXI + + + + + + + M00_AXI_ACLK_1 + + + + + + + + + + + + + + M00_AXI_ARESETN_1 + + + + + + + + + + + + + + S00_AXI_ACLK_1 + + + + + + S00_AXI_ARESETN_1 + + + + + + S01_AXI_ACLK_1 + + + + + + S01_AXI_ARESETN_1 + + + + + + S02_AXI_ACLK_1 + + + + + + S02_AXI_ARESETN_1 + + + + + + S03_AXI_ACLK_1 + + + + + + S03_AXI_ARESETN_1 + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml new file mode 100644 index 000000000..217597784 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml @@ -0,0 +1,123 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v new file mode 100644 index 000000000..71e446f92 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v @@ -0,0 +1,419 @@ +//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +`timescale 1 ps / 1 ps + +module axi_intercon_4x64_256_bd_wrapper ( + input M00_AXI_ACLK, + input M00_AXI_ARESETN, + output [31:0]M00_AXI_ARADDR, + output [1:0]M00_AXI_ARBURST, + output [3:0]M00_AXI_ARCACHE, + output [3:0]M00_AXI_ARID, + output [7:0]M00_AXI_ARLEN, + output [0:0]M00_AXI_ARLOCK, + output [2:0]M00_AXI_ARPROT, + output [3:0]M00_AXI_ARQOS, + input M00_AXI_ARREADY, + output [3:0]M00_AXI_ARREGION, + output [2:0]M00_AXI_ARSIZE, + output M00_AXI_ARVALID, + output [31:0]M00_AXI_AWADDR, + output [1:0]M00_AXI_AWBURST, + output [3:0]M00_AXI_AWCACHE, + output [3:0]M00_AXI_AWID, + output [7:0]M00_AXI_AWLEN, + output [0:0]M00_AXI_AWLOCK, + output [2:0]M00_AXI_AWPROT, + output [3:0]M00_AXI_AWQOS, + input M00_AXI_AWREADY, + output [3:0]M00_AXI_AWREGION, + output [2:0]M00_AXI_AWSIZE, + output M00_AXI_AWVALID, + input [3:0]M00_AXI_BID, + output M00_AXI_BREADY, + input [1:0]M00_AXI_BRESP, + input M00_AXI_BVALID, + input [255:0]M00_AXI_RDATA, + input [3:0]M00_AXI_RID, + input M00_AXI_RLAST, + output M00_AXI_RREADY, + input [1:0]M00_AXI_RRESP, + input M00_AXI_RVALID, + output [255:0]M00_AXI_WDATA, + output M00_AXI_WLAST, + input M00_AXI_WREADY, + output [31:0]M00_AXI_WSTRB, + output M00_AXI_WVALID, + input S00_AXI_ACLK, + input S00_AXI_ARESETN, + input [31:0]S00_AXI_ARADDR, + input [1:0]S00_AXI_ARBURST, + input [3:0]S00_AXI_ARCACHE, + input [0:0]S00_AXI_ARID, + input [7:0]S00_AXI_ARLEN, + input [0:0]S00_AXI_ARLOCK, + input [2:0]S00_AXI_ARPROT, + input [3:0]S00_AXI_ARQOS, + output S00_AXI_ARREADY, + input [3:0]S00_AXI_ARREGION, + input [2:0]S00_AXI_ARSIZE, + input S00_AXI_ARVALID, + input [31:0]S00_AXI_AWADDR, + input [1:0]S00_AXI_AWBURST, + input [3:0]S00_AXI_AWCACHE, + input [0:0]S00_AXI_AWID, + input [7:0]S00_AXI_AWLEN, + input [0:0]S00_AXI_AWLOCK, + input [2:0]S00_AXI_AWPROT, + input [3:0]S00_AXI_AWQOS, + output S00_AXI_AWREADY, + input [3:0]S00_AXI_AWREGION, + input [2:0]S00_AXI_AWSIZE, + input S00_AXI_AWVALID, + output [0:0]S00_AXI_BID, + input S00_AXI_BREADY, + output [1:0]S00_AXI_BRESP, + output S00_AXI_BVALID, + output [63:0]S00_AXI_RDATA, + output [0:0]S00_AXI_RID, + output S00_AXI_RLAST, + input S00_AXI_RREADY, + output [1:0]S00_AXI_RRESP, + output S00_AXI_RVALID, + input [63:0]S00_AXI_WDATA, + input S00_AXI_WLAST, + output S00_AXI_WREADY, + input [7:0]S00_AXI_WSTRB, + input S00_AXI_WVALID, + input S01_AXI_ACLK, + input S01_AXI_ARESETN, + input [31:0]S01_AXI_ARADDR, + input [1:0]S01_AXI_ARBURST, + input [3:0]S01_AXI_ARCACHE, + input [0:0]S01_AXI_ARID, + input [7:0]S01_AXI_ARLEN, + input [0:0]S01_AXI_ARLOCK, + input [2:0]S01_AXI_ARPROT, + input [3:0]S01_AXI_ARQOS, + output S01_AXI_ARREADY, + input [3:0]S01_AXI_ARREGION, + input [2:0]S01_AXI_ARSIZE, + input S01_AXI_ARVALID, + input [31:0]S01_AXI_AWADDR, + input [1:0]S01_AXI_AWBURST, + input [3:0]S01_AXI_AWCACHE, + input [0:0]S01_AXI_AWID, + input [7:0]S01_AXI_AWLEN, + input [0:0]S01_AXI_AWLOCK, + input [2:0]S01_AXI_AWPROT, + input [3:0]S01_AXI_AWQOS, + output S01_AXI_AWREADY, + input [3:0]S01_AXI_AWREGION, + input [2:0]S01_AXI_AWSIZE, + input S01_AXI_AWVALID, + output [0:0]S01_AXI_BID, + input S01_AXI_BREADY, + output [1:0]S01_AXI_BRESP, + output S01_AXI_BVALID, + output [63:0]S01_AXI_RDATA, + output [0:0]S01_AXI_RID, + output S01_AXI_RLAST, + input S01_AXI_RREADY, + output [1:0]S01_AXI_RRESP, + output S01_AXI_RVALID, + input [63:0]S01_AXI_WDATA, + input S01_AXI_WLAST, + output S01_AXI_WREADY, + input [7:0]S01_AXI_WSTRB, + input S01_AXI_WVALID, + input S02_AXI_ACLK, + input S02_AXI_ARESETN, + input [31:0]S02_AXI_ARADDR, + input [1:0]S02_AXI_ARBURST, + input [3:0]S02_AXI_ARCACHE, + input [0:0]S02_AXI_ARID, + input [7:0]S02_AXI_ARLEN, + input [0:0]S02_AXI_ARLOCK, + input [2:0]S02_AXI_ARPROT, + input [3:0]S02_AXI_ARQOS, + output S02_AXI_ARREADY, + input [3:0]S02_AXI_ARREGION, + input [2:0]S02_AXI_ARSIZE, + input S02_AXI_ARVALID, + input [31:0]S02_AXI_AWADDR, + input [1:0]S02_AXI_AWBURST, + input [3:0]S02_AXI_AWCACHE, + input [0:0]S02_AXI_AWID, + input [7:0]S02_AXI_AWLEN, + input [0:0]S02_AXI_AWLOCK, + input [2:0]S02_AXI_AWPROT, + input [3:0]S02_AXI_AWQOS, + output S02_AXI_AWREADY, + input [3:0]S02_AXI_AWREGION, + input [2:0]S02_AXI_AWSIZE, + input S02_AXI_AWVALID, + output [0:0]S02_AXI_BID, + input S02_AXI_BREADY, + output [1:0]S02_AXI_BRESP, + output S02_AXI_BVALID, + output [63:0]S02_AXI_RDATA, + output [0:0]S02_AXI_RID, + output S02_AXI_RLAST, + input S02_AXI_RREADY, + output [1:0]S02_AXI_RRESP, + output S02_AXI_RVALID, + input [63:0]S02_AXI_WDATA, + input S02_AXI_WLAST, + output S02_AXI_WREADY, + input [7:0]S02_AXI_WSTRB, + input S02_AXI_WVALID, + input S03_AXI_ACLK, + input S03_AXI_ARESETN, + input [31:0]S03_AXI_ARADDR, + input [1:0]S03_AXI_ARBURST, + input [3:0]S03_AXI_ARCACHE, + input [0:0]S03_AXI_ARID, + input [7:0]S03_AXI_ARLEN, + input [0:0]S03_AXI_ARLOCK, + input [2:0]S03_AXI_ARPROT, + input [3:0]S03_AXI_ARQOS, + output S03_AXI_ARREADY, + input [3:0]S03_AXI_ARREGION, + input [2:0]S03_AXI_ARSIZE, + input S03_AXI_ARVALID, + input [31:0]S03_AXI_AWADDR, + input [1:0]S03_AXI_AWBURST, + input [3:0]S03_AXI_AWCACHE, + input [0:0]S03_AXI_AWID, + input [7:0]S03_AXI_AWLEN, + input [0:0]S03_AXI_AWLOCK, + input [2:0]S03_AXI_AWPROT, + input [3:0]S03_AXI_AWQOS, + output S03_AXI_AWREADY, + input [3:0]S03_AXI_AWREGION, + input [2:0]S03_AXI_AWSIZE, + input S03_AXI_AWVALID, + output [0:0]S03_AXI_BID, + input S03_AXI_BREADY, + output [1:0]S03_AXI_BRESP, + output S03_AXI_BVALID, + output [63:0]S03_AXI_RDATA, + output [0:0]S03_AXI_RID, + output S03_AXI_RLAST, + input S03_AXI_RREADY, + output [1:0]S03_AXI_RRESP, + output S03_AXI_RVALID, + input [63:0]S03_AXI_WDATA, + input S03_AXI_WLAST, + output S03_AXI_WREADY, + input [7:0]S03_AXI_WSTRB, + input S03_AXI_WVALID +); + + axi_intercon_4x64_256_bd axi_intercon_4x64_256_bd_i ( + .M00_AXI_ACLK(M00_AXI_ACLK), + .M00_AXI_ARESETN(M00_AXI_ARESETN), + .M00_AXI_araddr(M00_AXI_ARADDR), + .M00_AXI_arburst(M00_AXI_ARBURST), + .M00_AXI_arcache(M00_AXI_ARCACHE), + .M00_AXI_arid(M00_AXI_ARID), + .M00_AXI_arlen(M00_AXI_ARLEN), + .M00_AXI_arlock(M00_AXI_ARLOCK), + .M00_AXI_arprot(M00_AXI_ARPROT), + .M00_AXI_arqos(M00_AXI_ARQOS), + .M00_AXI_arready(M00_AXI_ARREADY), + .M00_AXI_arregion(M00_AXI_ARREGION), + .M00_AXI_arsize(M00_AXI_ARSIZE), + .M00_AXI_arvalid(M00_AXI_ARVALID), + .M00_AXI_awaddr(M00_AXI_AWADDR), + .M00_AXI_awburst(M00_AXI_AWBURST), + .M00_AXI_awcache(M00_AXI_AWCACHE), + .M00_AXI_awid(M00_AXI_AWID), + .M00_AXI_awlen(M00_AXI_AWLEN), + .M00_AXI_awlock(M00_AXI_AWLOCK), + .M00_AXI_awprot(M00_AXI_AWPROT), + .M00_AXI_awqos(M00_AXI_AWQOS), + .M00_AXI_awready(M00_AXI_AWREADY), + .M00_AXI_awregion(M00_AXI_AWREGION), + .M00_AXI_awsize(M00_AXI_AWSIZE), + .M00_AXI_awvalid(M00_AXI_AWVALID), + .M00_AXI_bid(M00_AXI_BID), + .M00_AXI_bready(M00_AXI_BREADY), + .M00_AXI_bresp(M00_AXI_BRESP), + .M00_AXI_bvalid(M00_AXI_BVALID), + .M00_AXI_rdata(M00_AXI_RDATA), + .M00_AXI_rid(M00_AXI_RID), + .M00_AXI_rlast(M00_AXI_RLAST), + .M00_AXI_rready(M00_AXI_RREADY), + .M00_AXI_rresp(M00_AXI_RRESP), + .M00_AXI_rvalid(M00_AXI_RVALID), + .M00_AXI_wdata(M00_AXI_WDATA), + .M00_AXI_wlast(M00_AXI_WLAST), + .M00_AXI_wready(M00_AXI_WREADY), + .M00_AXI_wstrb(M00_AXI_WSTRB), + .M00_AXI_wvalid(M00_AXI_WVALID), + .S00_AXI_ACLK(S00_AXI_ACLK), + .S00_AXI_ARESETN(S00_AXI_ARESETN), + .S00_AXI_araddr(S00_AXI_ARADDR), + .S00_AXI_arburst(S00_AXI_ARBURST), + .S00_AXI_arcache(S00_AXI_ARCACHE), + .S00_AXI_arid(S00_AXI_ARID), + .S00_AXI_arlen(S00_AXI_ARLEN), + .S00_AXI_arlock(S00_AXI_ARLOCK), + .S00_AXI_arprot(S00_AXI_ARPROT), + .S00_AXI_arqos(S00_AXI_ARQOS), + .S00_AXI_arready(S00_AXI_ARREADY), + .S00_AXI_arregion(S00_AXI_ARREGION), + .S00_AXI_arsize(S00_AXI_ARSIZE), + .S00_AXI_arvalid(S00_AXI_ARVALID), + .S00_AXI_awaddr(S00_AXI_AWADDR), + .S00_AXI_awburst(S00_AXI_AWBURST), + .S00_AXI_awcache(S00_AXI_AWCACHE), + .S00_AXI_awid(S00_AXI_AWID), + .S00_AXI_awlen(S00_AXI_AWLEN), + .S00_AXI_awlock(S00_AXI_AWLOCK), + .S00_AXI_awprot(S00_AXI_AWPROT), + .S00_AXI_awqos(S00_AXI_AWQOS), + .S00_AXI_awready(S00_AXI_AWREADY), + .S00_AXI_awregion(S00_AXI_AWREGION), + .S00_AXI_awsize(S00_AXI_AWSIZE), + .S00_AXI_awvalid(S00_AXI_AWVALID), + .S00_AXI_bid(S00_AXI_BID), + .S00_AXI_bready(S00_AXI_BREADY), + .S00_AXI_bresp(S00_AXI_BRESP), + .S00_AXI_bvalid(S00_AXI_BVALID), + .S00_AXI_rdata(S00_AXI_RDATA), + .S00_AXI_rid(S00_AXI_RID), + .S00_AXI_rlast(S00_AXI_RLAST), + .S00_AXI_rready(S00_AXI_RREADY), + .S00_AXI_rresp(S00_AXI_RRESP), + .S00_AXI_rvalid(S00_AXI_RVALID), + .S00_AXI_wdata(S00_AXI_WDATA), + .S00_AXI_wlast(S00_AXI_WLAST), + .S00_AXI_wready(S00_AXI_WREADY), + .S00_AXI_wstrb(S00_AXI_WSTRB), + .S00_AXI_wvalid(S00_AXI_WVALID), + .S01_AXI_ACLK(S01_AXI_ACLK), + .S01_AXI_ARESETN(S01_AXI_ARESETN), + .S01_AXI_araddr(S01_AXI_ARADDR), + .S01_AXI_arburst(S01_AXI_ARBURST), + .S01_AXI_arcache(S01_AXI_ARCACHE), + .S01_AXI_arid(S01_AXI_ARID), + .S01_AXI_arlen(S01_AXI_ARLEN), + .S01_AXI_arlock(S01_AXI_ARLOCK), + .S01_AXI_arprot(S01_AXI_ARPROT), + .S01_AXI_arqos(S01_AXI_ARQOS), + .S01_AXI_arready(S01_AXI_ARREADY), + .S01_AXI_arregion(S01_AXI_ARREGION), + .S01_AXI_arsize(S01_AXI_ARSIZE), + .S01_AXI_arvalid(S01_AXI_ARVALID), + .S01_AXI_awaddr(S01_AXI_AWADDR), + .S01_AXI_awburst(S01_AXI_AWBURST), + .S01_AXI_awcache(S01_AXI_AWCACHE), + .S01_AXI_awid(S01_AXI_AWID), + .S01_AXI_awlen(S01_AXI_AWLEN), + .S01_AXI_awlock(S01_AXI_AWLOCK), + .S01_AXI_awprot(S01_AXI_AWPROT), + .S01_AXI_awqos(S01_AXI_AWQOS), + .S01_AXI_awready(S01_AXI_AWREADY), + .S01_AXI_awregion(S01_AXI_AWREGION), + .S01_AXI_awsize(S01_AXI_AWSIZE), + .S01_AXI_awvalid(S01_AXI_AWVALID), + .S01_AXI_bid(S01_AXI_BID), + .S01_AXI_bready(S01_AXI_BREADY), + .S01_AXI_bresp(S01_AXI_BRESP), + .S01_AXI_bvalid(S01_AXI_BVALID), + .S01_AXI_rdata(S01_AXI_RDATA), + .S01_AXI_rid(S01_AXI_RID), + .S01_AXI_rlast(S01_AXI_RLAST), + .S01_AXI_rready(S01_AXI_RREADY), + .S01_AXI_rresp(S01_AXI_RRESP), + .S01_AXI_rvalid(S01_AXI_RVALID), + .S01_AXI_wdata(S01_AXI_WDATA), + .S01_AXI_wlast(S01_AXI_WLAST), + .S01_AXI_wready(S01_AXI_WREADY), + .S01_AXI_wstrb(S01_AXI_WSTRB), + .S01_AXI_wvalid(S01_AXI_WVALID), + .S02_AXI_ACLK(S02_AXI_ACLK), + .S02_AXI_ARESETN(S02_AXI_ARESETN), + .S02_AXI_araddr(S02_AXI_ARADDR), + .S02_AXI_arburst(S02_AXI_ARBURST), + .S02_AXI_arcache(S02_AXI_ARCACHE), + .S02_AXI_arid(S02_AXI_ARID), + .S02_AXI_arlen(S02_AXI_ARLEN), + .S02_AXI_arlock(S02_AXI_ARLOCK), + .S02_AXI_arprot(S02_AXI_ARPROT), + .S02_AXI_arqos(S02_AXI_ARQOS), + .S02_AXI_arready(S02_AXI_ARREADY), + .S02_AXI_arregion(S02_AXI_ARREGION), + .S02_AXI_arsize(S02_AXI_ARSIZE), + .S02_AXI_arvalid(S02_AXI_ARVALID), + .S02_AXI_awaddr(S02_AXI_AWADDR), + .S02_AXI_awburst(S02_AXI_AWBURST), + .S02_AXI_awcache(S02_AXI_AWCACHE), + .S02_AXI_awid(S02_AXI_AWID), + .S02_AXI_awlen(S02_AXI_AWLEN), + .S02_AXI_awlock(S02_AXI_AWLOCK), + .S02_AXI_awprot(S02_AXI_AWPROT), + .S02_AXI_awqos(S02_AXI_AWQOS), + .S02_AXI_awready(S02_AXI_AWREADY), + .S02_AXI_awregion(S02_AXI_AWREGION), + .S02_AXI_awsize(S02_AXI_AWSIZE), + .S02_AXI_awvalid(S02_AXI_AWVALID), + .S02_AXI_bid(S02_AXI_BID), + .S02_AXI_bready(S02_AXI_BREADY), + .S02_AXI_bresp(S02_AXI_BRESP), + .S02_AXI_bvalid(S02_AXI_BVALID), + .S02_AXI_rdata(S02_AXI_RDATA), + .S02_AXI_rid(S02_AXI_RID), + .S02_AXI_rlast(S02_AXI_RLAST), + .S02_AXI_rready(S02_AXI_RREADY), + .S02_AXI_rresp(S02_AXI_RRESP), + .S02_AXI_rvalid(S02_AXI_RVALID), + .S02_AXI_wdata(S02_AXI_WDATA), + .S02_AXI_wlast(S02_AXI_WLAST), + .S02_AXI_wready(S02_AXI_WREADY), + .S02_AXI_wstrb(S02_AXI_WSTRB), + .S02_AXI_wvalid(S02_AXI_WVALID), + .S03_AXI_ACLK(S03_AXI_ACLK), + .S03_AXI_ARESETN(S03_AXI_ARESETN), + .S03_AXI_araddr(S03_AXI_ARADDR), + .S03_AXI_arburst(S03_AXI_ARBURST), + .S03_AXI_arcache(S03_AXI_ARCACHE), + .S03_AXI_arid(S03_AXI_ARID), + .S03_AXI_arlen(S03_AXI_ARLEN), + .S03_AXI_arlock(S03_AXI_ARLOCK), + .S03_AXI_arprot(S03_AXI_ARPROT), + .S03_AXI_arqos(S03_AXI_ARQOS), + .S03_AXI_arready(S03_AXI_ARREADY), + .S03_AXI_arregion(S03_AXI_ARREGION), + .S03_AXI_arsize(S03_AXI_ARSIZE), + .S03_AXI_arvalid(S03_AXI_ARVALID), + .S03_AXI_awaddr(S03_AXI_AWADDR), + .S03_AXI_awburst(S03_AXI_AWBURST), + .S03_AXI_awcache(S03_AXI_AWCACHE), + .S03_AXI_awid(S03_AXI_AWID), + .S03_AXI_awlen(S03_AXI_AWLEN), + .S03_AXI_awlock(S03_AXI_AWLOCK), + .S03_AXI_awprot(S03_AXI_AWPROT), + .S03_AXI_awqos(S03_AXI_AWQOS), + .S03_AXI_awready(S03_AXI_AWREADY), + .S03_AXI_awregion(S03_AXI_AWREGION), + .S03_AXI_awsize(S03_AXI_AWSIZE), + .S03_AXI_awvalid(S03_AXI_AWVALID), + .S03_AXI_bid(S03_AXI_BID), + .S03_AXI_bready(S03_AXI_BREADY), + .S03_AXI_bresp(S03_AXI_BRESP), + .S03_AXI_bvalid(S03_AXI_BVALID), + .S03_AXI_rdata(S03_AXI_RDATA), + .S03_AXI_rid(S03_AXI_RID), + .S03_AXI_rlast(S03_AXI_RLAST), + .S03_AXI_rready(S03_AXI_RREADY), + .S03_AXI_rresp(S03_AXI_RRESP), + .S03_AXI_rvalid(S03_AXI_RVALID), + .S03_AXI_wdata(S03_AXI_WDATA), + .S03_AXI_wlast(S03_AXI_WLAST), + .S03_AXI_wready(S03_AXI_WREADY), + .S03_AXI_wstrb(S03_AXI_WSTRB), + .S03_AXI_wvalid(S03_AXI_WVALID) + ); +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/axi_interconnect/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi_interconnect/Makefile.inc new file mode 100644 index 000000000..a169c12bf --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_interconnect/Makefile.inc @@ -0,0 +1,16 @@ +# +# Copyright 2015 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCONNECT_SRCS = $(IP_BUILD_DIR)/axi_interconnect/axi_interconnect.xci + +IP_AXI_INTERCONNECT = $(addprefix $(IP_BUILD_DIR)/axi_interconnect/, \ +axi_interconnect.xci.out \ +synth/axi_interconnect.v \ +) + +$(IP_AXI_INTERCONNECT_SRCS) $(IP_AXI_INTERCONNECT_OUTS) : $(IP_DIR)/axi_interconnect/axi_interconnect.xci + $(call BUILD_VIVADO_IP,axi_interconnect,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + diff --git a/fpga/usrp3/top/n3xx/ip/axi_interconnect/axi_interconnect.xci b/fpga/usrp3/top/n3xx/ip/axi_interconnect/axi_interconnect.xci new file mode 100644 index 000000000..8af91b716 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_interconnect/axi_interconnect.xci @@ -0,0 +1,2674 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_interconnect + + + + + + 10000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 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1 + 0 + 0x0000000e + 1 + 0 + 0 + 1 + 0 + 0x0000000f + 1 + 0 + 0 + 1 + 0 + 0 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 20 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/Makefile.inc new file mode 100644 index 000000000..a78954885 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/Makefile.inc @@ -0,0 +1,14 @@ +# +# Copyright 2017 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXIS_FIFO_TO_AXI4LITE_SRCS = $(IP_BUILD_DIR)/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci + +IP_AXIS_FIFO_TO_AXI4LITE_OUTS = $(addprefix $(IP_BUILD_DIR)/axis_fifo_to_axi4lite/, \ +axis_fifo_to_axi4lite.xci.out \ +) + +$(IP_AXIS_FIFO_TO_AXI4LITE_SRCS) $(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) : $(IP_DIR)/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci + $(call BUILD_VIVADO_IP,axis_fifo_to_axi4lite,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci b/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci new file mode 100644 index 000000000..80d8104d5 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci @@ -0,0 +1,267 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axis_fifo_to_axi4lite + + + 4096 + 4096 + + 100000000 + 0 + 0.000 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0x80001000 + 0x80002FFF + 4 + 4 + 4 + 0x80000000 + 0 + zynq + 0 + 0 + 1 + 0 + 0 + 0x80000FFF + 32768 + 5 + 4091 + 32 + 32 + 32 + 4 + 2048 + 5 + 2043 + 0 + 1 + 0 + 0 + 1 + 0x80001000 + 0x80002FFF + 4 + 4 + 4 + XIL_AXI_STREAM_ETH_DATA + 32 + XIL_AXI_STREAM_ETH_CTRL + 32 + XIL_AXI_STREAM_ETH_DATA + 32 + 0x80000000 + 0 + false + false + true + false + false + 0x80000FFF + 32768 + 5 + 4091 + 0 + 32 + 32 + 32 + 4 + AXI4LITE + 2048 + 5 + 2043 + false + 1 + 0 + 0 + 1 + axis_fifo_to_axi4lite + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/ddr3_32bit/Makefile.inc b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/Makefile.inc new file mode 100644 index 000000000..e96eaf838 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/Makefile.inc @@ -0,0 +1,26 @@ +# +# Copyright 2017 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR3_32BIT_SRCS = \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit.xci \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v + +IP_DDR3_32BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit.xci.out \ +ddr3_32bit/user_design/rtl/ddr3_32bit.v \ +ddr3_32bit/user_design/rtl/ddr3_32bit_mig.v \ +) + +IP_DDR3_32BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit/example_design/sim/ddr3_model.sv \ +ddr3_32bit/example_design/sim/ddr3_model_parameters.vh \ +) + + +$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS) : $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_xc7z*.prj + cp -f $(IP_DIR)/ddr3_32bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_32bit/mig_a.prj # Note: This won't allow parallel IP builds + $(call BUILD_VIVADO_IP,ddr3_32bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + rm -f $(IP_DIR)/ddr3_32bit/mig_a.prj diff --git a/fpga/usrp3/top/n3xx/ip/ddr3_32bit/ddr3_32bit.xci b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/ddr3_32bit.xci new file mode 100644 index 000000000..f72f56759 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/ddr3_32bit.xci @@ -0,0 +1,2648 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ddr3_32bit + + + 0 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z035ffg900-2.prj b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z035ffg900-2.prj new file mode 100644 index 000000000..495ca2a8b --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z035ffg900-2.prj @@ -0,0 +1,164 @@ + + + + ddr3_32bit + 1 + 1 + OFF + 1024 + ON + Disabled + xc7z035-ffg900/-2 + 4.0 + Differential + No Buffer + ACTIVE LOW + FALSE + 0 + 50 Ohms + 0 + + 7z/xc7z035-ffg900 + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 1538 + 1.8V + 4:1 + 100.03 + 0 + 650 + 1.000 + 1 + 1 + 1 + 1 + 32 + 1 + 1 + Disabled + Normal + 4 + TRUE + MT41K512M16XX-125 + 16 + 10 + 3 + 1.5V + ROW_BANK_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 9 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 7 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 31 + 256 + 4 + 1 + + + + diff --git a/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z100ffg900-2.prj b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z100ffg900-2.prj new file mode 100644 index 000000000..ffad2f7f8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z100ffg900-2.prj @@ -0,0 +1,164 @@ + + + + ddr3_32bit + 1 + 1 + OFF + 1024 + ON + Disabled + xc7z100-ffg900/-2 + 4.0 + Differential + No Buffer + ACTIVE LOW + FALSE + 0 + 50 Ohms + 0 + + 7z/xc7z035-ffg900 + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 1538 + 1.8V + 4:1 + 100.03 + 0 + 650 + 1.000 + 1 + 1 + 1 + 1 + 32 + 1 + 1 + Disabled + Normal + 4 + TRUE + MT41K512M16XX-125 + 16 + 10 + 3 + 1.5V + ROW_BANK_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 9 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 7 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 31 + 256 + 4 + 1 + + + + diff --git a/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/Makefile.inc b/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/Makefile.inc new file mode 100644 index 000000000..e022d9a1c --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + +IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ +fifo_4k_2clk.xci.out \ +synth/fifo_4k_2clk.vhd \ +) + +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/fifo_4k_2clk.xci new file mode 100644 index 000000000..888840273 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/fifo_4k_2clk.xci @@ -0,0 +1,576 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_4k_2clk + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 9 + BlankString + 72 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 72 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 0 + 0 + 0 + 0 + 0 + 1 + 512x72 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 511 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 510 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 512 + 1 + 9 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 9 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_4k_2clk + 64 + false + 9 + true + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 1 + 511 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 510 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 72 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 72 + 512 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + true + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + true + false + Active_High + 0 + false + Active_High + 1 + true + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/Makefile.inc b/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/Makefile.inc new file mode 100644 index 000000000..8c5c54213 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci + +IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ +fifo_short_2clk.xci.out \ +synth/fifo_short_2clk.vhd \ +) + +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci + $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/fifo_short_2clk.xci b/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/fifo_short_2clk.xci new file mode 100644 index 000000000..cc0f896b8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/fifo_short_2clk.xci @@ -0,0 +1,578 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_short_2clk + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 5 + BlankString + 72 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 72 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 2 + BlankString + 1 + 0 + 0 + 0 + 0 + 1 + 512x72 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 31 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 30 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 32 + 1 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 32 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 5 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_short_2clk + 64 + false + 5 + false + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Distributed_RAM + 1 + 31 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 30 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 72 + 32 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 72 + 32 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + true + 6 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + true + false + Active_High + 0 + false + Active_High + 1 + true + 6 + false + FIFO + false + false + false + false + FIFO + FIFO + 3 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/hb47_1to2/Makefile.inc b/fpga/usrp3/top/n3xx/ip/hb47_1to2/Makefile.inc new file mode 100644 index 000000000..14b705d1d --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_1to2/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_HB47_1TO2_SRCS = $(IP_BUILD_DIR)/hb47_1to2/hb47_1to2.xci + +IP_HB47_1TO2_OUTS = $(addprefix $(IP_BUILD_DIR)/hb47_1to2/, \ +hb47_1to2.xci.out \ +synth/hb47_1to2.vhd \ +) + +$(IP_HB47_1TO2_SRCS) $(IP_HB47_1TO2_OUTS) : $(IP_DIR)/hb47_1to2/hb47_1to2.xci + $(call BUILD_VIVADO_IP,hb47_1to2,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/hb47_1to2/hb47_1to2.xci b/fpga/usrp3/top/n3xx/ip/hb47_1to2/hb47_1to2.xci new file mode 100644 index 000000000..a192027fb --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_1to2/hb47_1to2.xci @@ -0,0 +1,294 @@ + + + xilinx.com + xci + unknown + 1.0 + + + hb47_1to2 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 12 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 35,35,35,35 + 35,35,35,35 + fixed + hb47_1to2.mif + 48 + 2 + 0 + 0,0,0,0 + 0,0,2,2 + 18,18,18,18 + 0 + 18 + 24 + 1 + 4 + hb47_1to2 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + -0;-1;-0;-1 + 0,0,0,0 + 0,1,0,1 + 16,16,16,16 + 16,16 + 16 + 1 + ./ + none + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 0 + 29 + 2 + 1 + 0 + 96 + 1 + 1 + 1 + 24 + 1 + 47 + 0 + 0 + none;none + -0;-1;-0;-1 + 18,18,18,18 + 1 + 18 + 1 + 0,1,2,3 + 1 + 7 + 0 + 1 + 0 + 32 + 1 + zynq + 1 + false + false + Basic + 300.0 + Vector + -62, 0, 194, 0, -440, 0, 855, 0, -1505, 0, 2478, 0, -3900, 0, 5990, 0, -9187, 0, 14632, 0, -26536, 0, 83009, 131071, 83009, 0, -26536, 0, 14632, 0, -9187, 0, 5990, 0, -3900, 0, 2478, 0, -1505, 0, 855, 0, -440, 0, 194, 0, -62 + Automatic + no_coe_file_loaded + 0 + false + 1 + Signed + Inferred + 18 + 24 + hb47_1to2 + Not_Required + 1 + Automatic + 0 + Signed + 16 + 1 + false + Systolic_Multiply_Accumulate + 1 + Interpolation + Coregen + false + false + false + 1 + false + true + Automatic + 4 + 2 + true + Not_Required + Automatic + 1 + 1 + 2 + Area + None + None + Automatic + Non_Symmetric_Rounding_Up + 18 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + Automatic + Integer_Coefficients + Output_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 0.5 + 0.001 + All + 1.0 + 0.5 + 1 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 12 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/hb47_2to1/Makefile.inc b/fpga/usrp3/top/n3xx/ip/hb47_2to1/Makefile.inc new file mode 100644 index 000000000..293f64d3a --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_2to1/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_HB47_2TO1_SRCS = $(IP_BUILD_DIR)/hb47_2to1/hb47_2to1.xci + +IP_HB47_2TO1_OUTS = $(addprefix $(IP_BUILD_DIR)/hb47_2to1/, \ +hb47_2to1.xci.out \ +synth/hb47_2to1.vhd \ +) + +$(IP_HB47_2TO1_SRCS) $(IP_HB47_2TO1_OUTS) : $(IP_DIR)/hb47_2to1/hb47_2to1.xci $(IP_DIR)/hb47_2to1/hb47.coe + $(call BUILD_VIVADO_IP,hb47_2to1,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47.coe b/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47.coe new file mode 100644 index 000000000..4c9a6c406 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47.coe @@ -0,0 +1,51 @@ +; Generated with round((2^18-2)*halfgen_test(.21,12,1)) +; 83% effective BW, 64dB to 85dB rolloff +Radix=10; +CoefData = +-62, + 0, + 194, + 0, +-440, + 0, + 855, + 0, +-1505, + 0, + 2478, + 0, +-3900, + 0, + 5990, + 0, +-9187, + 0, + 14632, + 0, +-26536, + 0, + 83009, + 131071, + 83009, + 0, +-26536, + 0, + 14632, + 0, +-9187, + 0, + 5990, + 0, +-3900, + 0, + 2478, + 0, +-1505, + 0, + 855, + 0, +-440, + 0 + 194, + 0, +-62; diff --git a/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47_2to1.xci b/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47_2to1.xci new file mode 100644 index 000000000..7a8522f9c --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47_2to1.xci @@ -0,0 +1,310 @@ + + + xilinx.com + xci + unknown + 1.0 + + + hb47_2to1 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 6 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 35,35 + 35,35,35,35 + fixed + hb47_2to1.mif + 47 + 2 + 0 + 0,0,0,0 + 0,0,0,0 + 18,18,18,18 + 0 + 18 + 47 + 1 + 4 + hb47_2to1 + 0 + 0 + 1 + 2 + 0 + 16,16,16,16 + 0 + 0 + -0,2;-1,3;0,-2;1,-3 + 0,0,0,0 + 0,1,2,3 + 16,16,16,16 + 16,16,16,16 + 16 + 1 + ./ + none + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 2 + 52 + 2 + 0 + 0 + 48 + 1 + 1 + 1 + 47 + 1 + 47 + 0 + 0 + none + 0,-2;1,-3 + 17,17 + 1 + 17 + 1 + 2,3,2,3 + 1 + 7 + 0 + 0 + 0 + 64 + 1 + zynq + 1 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + hb47.coe + 0 + false + 1 + Signed + Inferred + 18 + 47 + hb47_2to1 + Not_Required + 1 + Automatic + 0 + Signed + 16 + 2 + false + Systolic_Multiply_Accumulate + 1 + Decimation + Coregen + false + false + false + 1 + false + true + Automatic + 4 + 1 + false + Not_Required + Automatic + 1 + 1 + 2 + Area + None + None + Automatic + Non_Symmetric_Rounding_Up + 17 + 0.4 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + false + Not_Required + 0.5 + 0.001 + All + 1.0 + 0.59 + 1 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 12 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/misc_clock_gen/Makefile.inc b/fpga/usrp3/top/n3xx/ip/misc_clock_gen/Makefile.inc new file mode 100644 index 000000000..2caa3384b --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/misc_clock_gen/Makefile.inc @@ -0,0 +1,18 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_MISC_CLOCK_GEN_SRCS = $(IP_BUILD_DIR)/misc_clock_gen/misc_clock_gen.xci + +IP_MISC_CLOCK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/misc_clock_gen/, \ +misc_clock_gen.xci.out \ +misc_clock_gen.v \ +) + +# We have to patch the XDC file to remove constraints on the source clock for the module +# All timing constraints are handled in one place (timing.xdc) +$(IP_MISC_CLOCK_GEN_SRCS) $(IP_MISC_CLOCK_GEN_OUTS) : $(IP_DIR)/misc_clock_gen/misc_clock_gen.xci + $(call BUILD_VIVADO_IP,misc_clock_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + diff --git a/fpga/usrp3/top/n3xx/ip/misc_clock_gen/misc_clock_gen.xci b/fpga/usrp3/top/n3xx/ip/misc_clock_gen/misc_clock_gen.xci new file mode 100644 index 000000000..2a2cc31ef --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/misc_clock_gen/misc_clock_gen.xci @@ -0,0 +1,739 @@ + + + xilinx.com + xci + unknown + 1.0 + + + misc_clock_gen + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 59.989999999999995 + 100.0 + 0000 + 0000 + 198.413 + 0000 + 0000 + 303.819 + BUFGCE + 50.0 + false + 198.413 + 0.000 + 50.0 + 198.412704761 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFGCE + 50.0 + false + 303.819 + 0.000 + 50.0 + 305.55555 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFGCE + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFGCE + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFGCE + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFGCE + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFGCE + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + meas_clk + ddr3_dma_clk + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.6493506819332852 + 1.98412704761 + 1.98412704761 + 1.98412704761 + 1.98412704761 + 1.98412704761 + dout + drdy + dwe + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary________166.666667____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 21.875 + 0.000 + FALSE + 6.000 + 10.000 + 6.125 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 3 + None + 0.010 + 0.010 + FALSE + 2 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + meas_clk___198.413______0.000______50.0______113.755____141.292 + ddr3_dma_clk___303.819______0.000______50.0______105.705____141.292 + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in + MMCM + AUTO + 166.666667 + 0.010 + 10.000 + No_buffer + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + misc_clock_gen + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 59.989999999999995 + 0.010 + 100.0 + 0.010 + BUFGCE + 113.755 + false + 141.292 + 50.0 + 198.412704761 + 0.000 + 1 + true + BUFGCE + 105.705 + false + 141.292 + 50.0 + 305.55555 + 0.000 + 1 + true + BUFGCE + 81.390 + false + 326.622 + 50.000 + 100.000 + 0.000 + 1 + false + BUFGCE + 81.390 + false + 326.622 + 50.000 + 100.000 + 0.000 + 1 + false + BUFGCE + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFGCE + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFGCE + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + meas_clk + false + ddr3_dma_clk + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + misc_clock_gen + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 21.875 + 0.000 + false + 6.000 + 10.000 + 6.125 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 3 + None + 0.010 + 0.010 + false + 2 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in + MMCM + mmcm_adv + 166.666667 + 0.010 + 10.000 + No_buffer + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + false + false + true + true + false + false + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/Makefile.inc b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/Makefile.inc new file mode 100644 index 000000000..26f994676 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/Makefile.inc @@ -0,0 +1,35 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak +include $(LIB_DIR)/rfnoc/utils/Makefile.srcs + +IP_N310_PS_ORIG_SRCS = $(addprefix $(IP_DIR)/n310_ps_bd/, \ +n310_ps_bd.tcl \ +chdr_dma_rx.tcl \ +chdr_dma_tx.tcl \ +chdr_dma_frame_size.tcl \ +chdr_dma_top.tcl \ +) + +IP_N310_PS_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/n310_ps_bd/, \ +n310_ps_bd.tcl \ +chdr_dma_rx.tcl \ +chdr_dma_tx.tcl \ +chdr_dma_frame_size.tcl \ +chdr_dma_top.tcl \ +) + +IP_N310_PS_HDL_SRCS = $(RFNOC_UTIL_SRCS) + +IP_N310_PS_BD_SRCS = $(IP_BUILD_DIR)/n310_ps_bd/n310_ps_bd/n310_ps_bd.bd + +BD_N310_PS_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/n310_ps_bd/, \ +n310_ps_bd.bd.out \ +n310_ps_bd/n310_ps_bd_ooc.xdc \ +) + +$(IP_N310_PS_BD_SRCS) $(BD_N310_PS_BD_OUTS) $(IP_N310_PS_BDTCL_SRCS): $(IP_N310_PS_ORIG_SRCS) $(IP_N310_PS_HDL_SRCS) + $(call BUILD_VIVADO_BDTCL,n310_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_N310_PS_HDL_SRCS)) + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_frame_size.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_frame_size.tcl new file mode 100644 index 000000000..387f67d9c --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_frame_size.tcl @@ -0,0 +1,59 @@ +# Hierarchical cell: mtu +proc create_hier_cell_mtu { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" } { + puts "ERROR: create_hier_cell_mtu() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create cells and wire everything up + create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs + connect_bd_net -net mtu_regs_1 [get_bd_pins mtu_regs] + # BUG: Vivado 2015.4 does not connect nets the first time with just the driver + connect_bd_net -quiet -net mtu_regs_1 [get_bd_pins mtu_regs] + + for {set i 0} {$i < $numPorts} {incr i} { + # Create instance: xlslice_0, and set properties + set xlslice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_$i ] + set_property -dict [ list \ + CONFIG.DIN_FROM [expr $i * 32 + 15] \ + CONFIG.DIN_TO [expr $i * 32] \ + CONFIG.DIN_WIDTH [expr $numPorts * 32] \ + CONFIG.DOUT_WIDTH {16} \ + ] $xlslice + + connect_bd_net -net mtu_regs_1 [get_bd_pins $xlslice/Din] + + create_bd_pin -dir O -from 15 -to 0 mtu$i + connect_bd_net [get_bd_pins mtu$i] [get_bd_pins $xlslice/Dout] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_rx.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_rx.tcl new file mode 100644 index 000000000..500771071 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_rx.tcl @@ -0,0 +1,339 @@ +set scriptDir [file dirname [info script]] + +source "$scriptDir/chdr_dma_frame_size.tcl" + +proc create_hier_cell_rx_dma_channel { parentCell nameHier } { + + if { $parentCell eq "" || $nameHier eq "" } { + puts "ERROR: create_hier_cell_dma() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_dest_axi + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_pin -dir I -from 15 -to 0 frame_size + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type rst m_dest_axi_aresetn + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + + ######################### + # Instantiate IPs + ######################### + set reset_inv [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 reset_inv ] + set_property -dict [ list \ + CONFIG.C_SIZE {1} \ + CONFIG.C_OPERATION {not} \ + ] $reset_inv + + set chdr_padder [ create_bd_cell -type module -reference chdr_pad_packet chdr_padder ] + set_property -dict [ list \ + CONFIG.CHDR_W {64} \ + ] $chdr_padder + set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_pins chdr_padder/rst] + + set axi_rx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_rx_dmac ] + set_property -dict [ list \ + CONFIG.ASYNC_CLK_DEST_REQ {true} \ + CONFIG.ASYNC_CLK_REQ_SRC {true} \ + CONFIG.ASYNC_CLK_SRC_DEST {false} \ + CONFIG.DMA_AXI_PROTOCOL_DEST {1} \ + CONFIG.DMA_TYPE_SRC {1} \ + CONFIG.SYNC_TRANSFER_START {false} \ + ] $axi_rx_dmac + + ######################### + # Wiring + ######################### + + # Top-level connections + connect_bd_net -net aclk_1 \ + [get_bd_pins s_axis_aclk] \ + [get_bd_pins chdr_padder/clk] \ + [get_bd_pins axi_rx_dmac/m_dest_axi_aclk] \ + [get_bd_pins axi_rx_dmac/s_axis_aclk] + connect_bd_net -net aresetn_1 \ + [get_bd_pins m_dest_axi_aresetn] \ + [get_bd_pins reset_inv/Op1] \ + [get_bd_pins axi_rx_dmac/m_dest_axi_aresetn] + connect_bd_net -net areset_1 \ + [get_bd_pins reset_inv/Res] \ + [get_bd_pins chdr_padder/rst] + connect_bd_net -net s_axi_aclk_1 \ + [get_bd_pins s_axi_aclk] \ + [get_bd_pins axi_rx_dmac/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 \ + [get_bd_pins s_axi_aresetn] \ + [get_bd_pins axi_rx_dmac/s_axi_aresetn] + connect_bd_net -net axi_rx_dmac_irq \ + [get_bd_pins irq] \ + [get_bd_pins axi_rx_dmac/irq] + connect_bd_net -net mtu \ + [get_bd_pins frame_size] \ + [get_bd_pins chdr_padder/len] + + # Control and DMA ports + connect_bd_intf_net -intf_net axi_rx_dmac_s_axi \ + [get_bd_intf_pins s_axi] \ + [get_bd_intf_pins axi_rx_dmac/s_axi] + connect_bd_intf_net -intf_net axi_rx_dmac_m_dest_axi \ + [get_bd_intf_pins m_dest_axi] \ + [get_bd_intf_pins axi_rx_dmac/m_dest_axi] + + # AXI-Stream ports + connect_bd_intf_net -intf_net s_axis_dma \ + [get_bd_intf_pins S_AXIS] \ + [get_bd_intf_pins chdr_padder/s_axis] + connect_bd_intf_net -intf_net s_axis_dma_padded \ + [get_bd_intf_pins chdr_padder/m_axis] \ + [get_bd_intf_pins axi_rx_dmac/s_axis] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: rx +proc create_hier_cell_rx_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_rx() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 1 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq + create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs + ######################### + # Instantiate IPs + ######################### + # For sharing one S_AXI_HP port across all RX DMA engines + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.CONNECTIVITY_MODE {SASD} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts \ + CONFIG.R_REGISTER {1} \ + ] $axi_crossbar_0 + + # For fanning out AXI-Lite bus to all RX DMA engines + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI $numPorts \ + ] $axi_interconnect_0 + + # Routes AXI-Stream to appropriate RX DMA engine + set axis_switch_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_0 ] + set_property -dict [ list \ + CONFIG.DECODER_REG {1} \ + CONFIG.NUM_MI $numPorts \ + CONFIG.NUM_SI {1} \ + ] $axis_switch_0 + + # Cross domains from incoming AXI-Stream to RX DMA engines domain + # Note that the fifo_generator_0 is hard-coded to have 4 TDEST bits, so we + # are limited to 16 RX DMA channels + set fifo_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 fifo_generator_0 ] + set_property -dict [ list \ + CONFIG.Clock_Type_AXI {Independent_Clock} \ + CONFIG.Empty_Threshold_Assert_Value_axis {1021} \ + CONFIG.Empty_Threshold_Assert_Value_rach {13} \ + CONFIG.Empty_Threshold_Assert_Value_rdch {1021} \ + CONFIG.Empty_Threshold_Assert_Value_wach {13} \ + CONFIG.Empty_Threshold_Assert_Value_wdch {1021} \ + CONFIG.Empty_Threshold_Assert_Value_wrch {13} \ + CONFIG.Enable_TLAST {true} \ + CONFIG.FIFO_Implementation_axis {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_rach {Independent_Clocks_Distributed_RAM} \ + CONFIG.FIFO_Implementation_rdch {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_wach {Independent_Clocks_Distributed_RAM} \ + CONFIG.FIFO_Implementation_wdch {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_wrch {Independent_Clocks_Distributed_RAM} \ + CONFIG.Full_Flags_Reset_Value {1} \ + CONFIG.Full_Threshold_Assert_Value_axis {1023} \ + CONFIG.Full_Threshold_Assert_Value_rach {15} \ + CONFIG.Full_Threshold_Assert_Value_wach {15} \ + CONFIG.Full_Threshold_Assert_Value_wrch {15} \ + CONFIG.HAS_TKEEP {false} \ + CONFIG.INTERFACE_TYPE {AXI_STREAM} \ + CONFIG.Input_Depth_axis {1024} \ + CONFIG.Reset_Type {Asynchronous_Reset} \ + CONFIG.TDATA_NUM_BYTES {8} \ + CONFIG.TDEST_WIDTH {4} \ + CONFIG.TKEEP_WIDTH {0} \ + CONFIG.TSTRB_WIDTH {8} \ + CONFIG.TUSER_WIDTH {0} \ + ] $fifo_generator_0 + + set rx_dmac_irq_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rx_dmac_irq_concat ] + set_property -dict [ list \ + CONFIG.NUM_PORTS $numPorts \ + ] $rx_dmac_irq_concat + + create_hier_cell_mtu $hier_obj mtu $numPorts + + ######################### + # Wiring + ######################### + connect_bd_intf_net -intf_net S00_AXIS_1 \ + [get_bd_intf_pins S_AXIS_DMA] \ + [get_bd_intf_pins fifo_generator_0/S_AXIS] + + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \ + [get_bd_intf_pins M_AXI_RX_DMA] \ + [get_bd_intf_pins axi_crossbar_0/M00_AXI] + + connect_bd_intf_net -intf_net fifo_generator_0_M_AXIS \ + [get_bd_intf_pins axis_switch_0/S00_AXIS] \ + [get_bd_intf_pins fifo_generator_0/M_AXIS] + + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \ + [get_bd_intf_pins s_axi_rx_dmac] \ + [get_bd_intf_pins axi_interconnect_0/S00_AXI] + + connect_bd_net -net aresetn_1 \ + [get_bd_pins bus_rstn] \ + [get_bd_pins fifo_generator_0/s_aresetn] + connect_bd_net -net bus_clk \ + [get_bd_pins bus_clk] \ + [get_bd_pins fifo_generator_0/s_aclk] + + connect_bd_net -net clk40 \ + [get_bd_pins clk40] \ + [get_bd_pins axi_crossbar_0/aclk] \ + [get_bd_pins axi_interconnect_0/ACLK] \ + [get_bd_pins axi_interconnect_0/S00_ACLK] \ + [get_bd_pins axis_switch_0/aclk] \ + [get_bd_pins fifo_generator_0/m_aclk] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_crossbar_0/aresetn] \ + [get_bd_pins axi_interconnect_0/ARESETN] \ + [get_bd_pins axi_interconnect_0/S00_ARESETN] \ + [get_bd_pins axis_switch_0/aresetn] + + connect_bd_net -net mtu_regs_1 \ + [get_bd_pins mtu_regs] \ + [get_bd_pins mtu/mtu_regs] + + connect_bd_net -net rx_dmac_irq_concat_dout \ + [get_bd_pins irq] \ + [get_bd_pins rx_dmac_irq_concat/dout] + + ######################### + # Per-port Section + ######################### + for {set i 0} {$i < $numPorts} {incr i} { + puts "Instantiating rx_dma port ${i}" + create_hier_cell_rx_dma_channel $hier_obj dma$i + + set_property -dict [ list \ + [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} \ + ] $axi_crossbar_0 + + connect_bd_intf_net -intf_net [format "axis_switch_0_M%02d_AXIS" ${i}] \ + [get_bd_intf_pins [format "axis_switch_0/M%02d_AXIS" ${i}]] \ + [get_bd_intf_pins dma${i}/S_AXIS] + + connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \ + [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \ + [get_bd_intf_pins dma${i}/s_axi] + + connect_bd_intf_net -intf_net dma${i}_m_dest_axi \ + [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \ + [get_bd_intf_pins dma${i}/m_dest_axi] + + connect_bd_net -net clk40 \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]] \ + [get_bd_pins dma${i}/s_axi_aclk] \ + [get_bd_pins dma${i}/s_axis_aclk] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \ + [get_bd_pins dma${i}/m_dest_axi_aresetn] \ + [get_bd_pins dma${i}/s_axi_aresetn] + + connect_bd_net -net dma${i}_irq \ + [get_bd_pins dma${i}/irq] \ + [get_bd_pins rx_dmac_irq_concat/In${i}] + + connect_bd_net -net frame_size_${i} \ + [get_bd_pins dma${i}/frame_size] \ + [get_bd_pins mtu/mtu${i}] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_top.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_top.tcl new file mode 100644 index 000000000..9a4e832aa --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_top.tcl @@ -0,0 +1,159 @@ +set scriptDir [file dirname [info script]] + +source "$scriptDir/chdr_dma_rx.tcl" +source "$scriptDir/chdr_dma_tx.tcl" + +# Hierarchical cell: dma +proc create_hier_cell_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_dma() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 2 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_regfile + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O rx_irq + create_bd_pin -dir O tx_irq + + ######################### + # Instantiate IPs + ######################### + # Create instance: rx + create_hier_cell_rx_dma $hier_obj rx $numPorts + + # Create instance: tx + create_hier_cell_tx_dma $hier_obj tx $numPorts + + # Used to set frame size of RX DMA engines + set axi_regfile_0 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_regfile:1.0 axi_regfile_0 ] + set_property -dict [ list \ +CONFIG.NUM_REGS $numPorts \ + ] $axi_regfile_0 + + set util_reduced_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_0 ] + set_property -dict [ list \ +CONFIG.C_OPERATION {or} \ +CONFIG.C_SIZE $numPorts \ + ] $util_reduced_logic_0 + + set util_reduced_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_1 ] + set_property -dict [ list \ +CONFIG.C_OPERATION {or} \ +CONFIG.C_SIZE $numPorts \ + ] $util_reduced_logic_1 + + ######################### + # Wiring + ######################### + # Clocks and resets + connect_bd_net -net bus_clk_1 \ + [get_bd_pins bus_clk] \ + [get_bd_pins rx/bus_clk] \ + [get_bd_pins tx/bus_clk] + connect_bd_net -net bus_rstn_1 \ + [get_bd_pins bus_rstn] \ + [get_bd_pins rx/bus_rstn] \ + [get_bd_pins tx/bus_rstn] + connect_bd_net -net clk40_1 \ + [get_bd_pins clk40] \ + [get_bd_pins rx/clk40] \ + [get_bd_pins tx/clk40] \ + [get_bd_pins axi_regfile_0/S_AXI_ACLK] + connect_bd_net -net clk40_rstn_1 \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_regfile_0/S_AXI_ARESETN] \ + [get_bd_pins rx/clk40_rstn] \ + [get_bd_pins tx/clk40_rstn] + + # AXI buses + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \ + [get_bd_intf_pins s_axi_rx_dmac] \ + [get_bd_intf_pins rx/s_axi_rx_dmac] + connect_bd_intf_net -intf_net rx_dma_M_AXI_RX_DMA \ + [get_bd_intf_pins M_AXI_RX_DMA] \ + [get_bd_intf_pins rx/M_AXI_RX_DMA] + connect_bd_intf_net -intf_net s_axi_tx_dmac_1 \ + [get_bd_intf_pins s_axi_tx_dmac] \ + [get_bd_intf_pins tx/s_axi_tx_dmac] + connect_bd_intf_net -intf_net tx_M_AXI_TX_DMA \ + [get_bd_intf_pins M_AXI_TX_DMA] \ + [get_bd_intf_pins tx/M_AXI_TX_DMA] + connect_bd_intf_net -intf_net s_axi_regfile_1 \ + [get_bd_intf_pins s_axi_regfile] \ + [get_bd_intf_pins axi_regfile_0/S_AXI] + + # RX CHDR + connect_bd_intf_net -intf_net s_axis_dma_1 \ + [get_bd_intf_pins s_axis_dma] \ + [get_bd_intf_pins rx/S_AXIS_DMA] + + # TX CHDR + connect_bd_intf_net -intf_net m_axis_dma_1 \ + [get_bd_intf_pins tx/M_AXIS_DMA] \ + [get_bd_intf_pins m_axis_dma] + + # IRQs and Frame Sizes + connect_bd_net -net frame_sizes \ + [get_bd_pins axi_regfile_0/regs] \ + [get_bd_pins rx/mtu_regs] + connect_bd_net -net rx_irq1 \ + [get_bd_pins rx/irq] \ + [get_bd_pins util_reduced_logic_0/Op1] + connect_bd_net -net tx_irq1 \ + [get_bd_pins tx/irq] \ + [get_bd_pins util_reduced_logic_1/Op1] + connect_bd_net -net util_reduced_logic_0_Res \ + [get_bd_pins rx_irq] \ + [get_bd_pins util_reduced_logic_0/Res] + connect_bd_net -net util_reduced_logic_1_Res \ + [get_bd_pins tx_irq] \ + [get_bd_pins util_reduced_logic_1/Res] + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_tx.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_tx.tcl new file mode 100644 index 000000000..e2d160f69 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_tx.tcl @@ -0,0 +1,193 @@ +# Hierarchical cell: tx +proc create_hier_cell_tx_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_tx() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 1 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_DMA + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq + + ######################### + # Instantiate IPs + ######################### + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI $numPorts \ + ] $axi_interconnect_0 + + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts + ] $axi_crossbar_0 + + set axis_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_interconnect:2.1 axis_interconnect_0 ] + set_property -dict [ list \ + CONFIG.ARB_ON_TLAST {1} \ + CONFIG.ARB_ON_MAX_XFERS {0} \ + CONFIG.ENABLE_ADVANCED_OPTIONS {1} \ + CONFIG.M00_HAS_REGSLICE {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts \ + ] $axis_interconnect_0 + + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.NUM_PORTS $numPorts \ + ] $xlconcat_0 + + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ +CONFIG.CONST_VAL {0} \ + ] $xlconstant_0 + + ######################### + # Wiring + ######################### + connect_bd_net -net bus_clk \ + [get_bd_pins bus_clk] \ + [get_bd_pins axis_interconnect_0/ACLK] \ + [get_bd_pins axis_interconnect_0/M00_AXIS_ACLK] + connect_bd_net -net bus_rstn \ + [get_bd_pins bus_rstn] \ + [get_bd_pins axis_interconnect_0/ARESETN] \ + [get_bd_pins axis_interconnect_0/M00_AXIS_ARESETN] + connect_bd_net -net clk40 \ + [get_bd_pins clk40] \ + [get_bd_pins axi_crossbar_0/aclk] \ + [get_bd_pins axi_interconnect_0/ACLK] \ + [get_bd_pins axi_interconnect_0/S00_ACLK] + connect_bd_net -net clk40_rstn \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_crossbar_0/aresetn] \ + [get_bd_pins axi_interconnect_0/ARESETN] \ + [get_bd_pins axi_interconnect_0/S00_ARESETN] + + connect_bd_net -net xlconstant_0_dout \ + [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconcat_0_dout \ + [get_bd_pins irq] \ + [get_bd_pins xlconcat_0/dout] + + connect_bd_intf_net -intf_net M_AXI_TX_DMAC_1 \ + [get_bd_intf_pins s_axi_tx_dmac] \ + [get_bd_intf_pins axi_interconnect_0/S00_AXI] + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \ + [get_bd_intf_pins M_AXI_TX_DMA] \ + [get_bd_intf_pins axi_crossbar_0/M00_AXI] + connect_bd_intf_net -intf_net axis_interconnect_0_M00_AXIS \ + [get_bd_intf_pins M_AXIS_DMA] \ + [get_bd_intf_pins axis_interconnect_0/M00_AXIS] + + ######################### + # Per-port Section + ######################### + for {set i 0} {$i < $numPorts} {incr i} { + # Configure each port on axi_crossbar and axis_interconnect + puts "Creating TX dma port ${i}" + set_property [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} $axi_crossbar_0 + set_property -dict [ list \ + [format "CONFIG.S%02d_HAS_REGSLICE" ${i}] {1} \ + ] $axis_interconnect_0 + + set axi_tx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_tx_dmac_$i ] + set_property -dict [ list \ + CONFIG.DMA_TYPE_DEST {1} \ + CONFIG.DMA_TYPE_SRC {0} \ + ] $axi_tx_dmac + + # Add a tuser signal indicating which DMA channel originated the packet + # Hard-coded to handle up to 16 DMA channels + # Convert i (in decimal) to 4-bit binary: + binary scan [binary format c ${i}] B* i_binary + set i_binary [string range ${i_binary} end-3 end] + + set tuser_appender [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_${i} ] + set_property -dict [ list \ + CONFIG.M_TUSER_WIDTH.VALUE_SRC USER \ + ] $tuser_appender + set_property -dict [ list \ + CONFIG.M_TUSER_WIDTH {4} \ + CONFIG.TUSER_REMAP 4'b${i_binary} \ + ] $tuser_appender + + connect_bd_intf_net -intf_net [format "axis_subset_converter_%d_S_AXIS" ${i}] \ + [get_bd_intf_pins $axi_tx_dmac/m_axis] \ + [get_bd_intf_pins ${tuser_appender}/S_AXIS] + connect_bd_intf_net -intf_net [format "S%02d_AXIS_1" ${i}] \ + [get_bd_intf_pins ${tuser_appender}/M_AXIS] \ + [get_bd_intf_pins [format "axis_interconnect_0/S%02d_AXIS" ${i}]] + connect_bd_intf_net -intf_net axi_dmac_${i}_m_src_axi \ + [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \ + [get_bd_intf_pins $axi_tx_dmac/m_src_axi] + connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \ + [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \ + [get_bd_intf_pins $axi_tx_dmac/s_axi] + + connect_bd_net [get_bd_pins $axi_tx_dmac/irq] [get_bd_pins xlconcat_0/In${i}] + + connect_bd_net -net clk40 \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]]\ + [get_bd_pins $axi_tx_dmac/m_axis_aclk] \ + [get_bd_pins $axi_tx_dmac/m_src_axi_aclk] \ + [get_bd_pins $axi_tx_dmac/s_axi_aclk] \ + [get_bd_pins $tuser_appender/aclk] \ + [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ACLK" ${i}]] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \ + [get_bd_pins $axi_tx_dmac/m_src_axi_aresetn] \ + [get_bd_pins $axi_tx_dmac/s_axi_aresetn] \ + [get_bd_pins $tuser_appender/aresetn] \ + [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ARESETN" ${i}]] + + connect_bd_net -net xlconstant_0_dout \ + [get_bd_pins [format "axis_interconnect_0/S%02d_ARB_REQ_SUPPRESS" ${i}]] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl new file mode 100644 index 000000000..b3516e2fa --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl @@ -0,0 +1,726 @@ +# CHANGE DESIGN NAME HERE +set design_name n310_ps_bd + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name +current_bd_design $design_name + +if { $nRet != 0 } { + puts $errMsg + return $nRet +} + +set scriptDir [file dirname [info script]] + +################################################################## +# DESIGN PROCs +################################################################## +source "$scriptDir/chdr_dma_top.tcl" + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0 ] + set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ] + set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ] + set_property -dict [ list \ + CONFIG.HAS_TLAST 1 \ + CONFIG.TDATA_NUM_BYTES 8 \ + CONFIG.TDEST_WIDTH 4 \ + ] $s_axis_dma + set WR_UART [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 WR_UART ] + set M_AXI_ETH_DMA0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_ETH_DMA0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_ETH_DMA0 + set M_AXI_WR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_WR ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {62500000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_WR + set M_AXI_ETH_DMA1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_ETH_DMA1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_ETH_DMA1 + set M_AXI_JESD0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_JESD0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_JESD0 + set M_AXI_JESD1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_JESD1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_JESD1 + set M_AXI_NET0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_NET0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_NET0 + set M_AXI_NET1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_NET1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_NET1 + set M_AXI_NET2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_NET2 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_NET2 + set M_AXI_XBAR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_XBAR ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_XBAR + set S_AXI_GP0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_GP0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.ARUSER_WIDTH {0} \ +CONFIG.AWUSER_WIDTH {0} \ +CONFIG.BUSER_WIDTH {0} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.HAS_BRESP {1} \ +CONFIG.HAS_BURST {1} \ +CONFIG.HAS_CACHE {1} \ +CONFIG.HAS_LOCK {1} \ +CONFIG.HAS_PROT {1} \ +CONFIG.HAS_QOS {1} \ +CONFIG.HAS_REGION {0} \ +CONFIG.HAS_RRESP {1} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.ID_WIDTH {5} \ +CONFIG.MAX_BURST_LENGTH {16} \ +CONFIG.NUM_READ_OUTSTANDING {8} \ +CONFIG.NUM_WRITE_OUTSTANDING {8} \ +CONFIG.PROTOCOL {AXI4} \ +CONFIG.READ_WRITE_MODE {READ_WRITE} \ +CONFIG.RUSER_WIDTH {0} \ +CONFIG.SUPPORTS_NARROW_BURST {1} \ +CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_GP0 + set S_AXI_GP1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_GP1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.ARUSER_WIDTH {0} \ +CONFIG.AWUSER_WIDTH {0} \ +CONFIG.BUSER_WIDTH {0} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.HAS_BRESP {1} \ +CONFIG.HAS_BURST {1} \ +CONFIG.HAS_CACHE {1} \ +CONFIG.HAS_LOCK {1} \ +CONFIG.HAS_PROT {1} \ +CONFIG.HAS_QOS {1} \ +CONFIG.HAS_REGION {0} \ +CONFIG.HAS_RRESP {1} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.ID_WIDTH {5} \ +CONFIG.MAX_BURST_LENGTH {16} \ +CONFIG.NUM_READ_OUTSTANDING {8} \ +CONFIG.NUM_WRITE_OUTSTANDING {8} \ +CONFIG.PROTOCOL {AXI4} \ +CONFIG.READ_WRITE_MODE {READ_WRITE} \ +CONFIG.RUSER_WIDTH {0} \ +CONFIG.SUPPORTS_NARROW_BURST {1} \ +CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_GP1 + set S_AXI_HP0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_HP0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.ARUSER_WIDTH {0} \ +CONFIG.AWUSER_WIDTH {0} \ +CONFIG.BUSER_WIDTH {0} \ +CONFIG.DATA_WIDTH {64} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BRESP {1} \ +CONFIG.HAS_BURST {1} \ +CONFIG.HAS_CACHE {1} \ +CONFIG.HAS_LOCK {1} \ +CONFIG.HAS_PROT {1} \ +CONFIG.HAS_QOS {1} \ +CONFIG.HAS_REGION {0} \ +CONFIG.HAS_RRESP {1} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.ID_WIDTH {5} \ +CONFIG.MAX_BURST_LENGTH {16} \ +CONFIG.NUM_READ_OUTSTANDING {8} \ +CONFIG.NUM_WRITE_OUTSTANDING {8} \ +CONFIG.PROTOCOL {AXI4} \ +CONFIG.READ_WRITE_MODE {READ_WRITE} \ +CONFIG.RUSER_WIDTH {0} \ +CONFIG.SUPPORTS_NARROW_BURST {1} \ +CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_HP0 + set S_AXI_HP1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_HP1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.ARUSER_WIDTH {0} \ +CONFIG.AWUSER_WIDTH {0} \ +CONFIG.BUSER_WIDTH {0} \ +CONFIG.DATA_WIDTH {64} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BRESP {1} \ +CONFIG.HAS_BURST {1} \ +CONFIG.HAS_CACHE {1} \ +CONFIG.HAS_LOCK {1} \ +CONFIG.HAS_PROT {1} \ +CONFIG.HAS_QOS {1} \ +CONFIG.HAS_REGION {0} \ +CONFIG.HAS_RRESP {1} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.ID_WIDTH {5} \ +CONFIG.MAX_BURST_LENGTH {16} \ +CONFIG.NUM_READ_OUTSTANDING {8} \ +CONFIG.NUM_WRITE_OUTSTANDING {8} \ +CONFIG.PROTOCOL {AXI4} \ +CONFIG.READ_WRITE_MODE {READ_WRITE} \ +CONFIG.RUSER_WIDTH {0} \ +CONFIG.SUPPORTS_NARROW_BURST {1} \ +CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_HP1 + set USBIND_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:usbctrl_rtl:1.0 USBIND_0 ] + + # Create ports + set DDR_VRN [ create_bd_port -dir IO DDR_VRN ] + set DDR_VRP [ create_bd_port -dir IO DDR_VRP ] + set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ] + set FCLK_CLK1 [ create_bd_port -dir O -type clk FCLK_CLK1 ] + set FCLK_CLK2 [ create_bd_port -dir O -type clk FCLK_CLK2 ] + set FCLK_CLK3 [ create_bd_port -dir O -type clk FCLK_CLK3 ] + set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ] + set FCLK_RESET1_N [ create_bd_port -dir O -type rst FCLK_RESET1_N ] + set FCLK_RESET2_N [ create_bd_port -dir O -type rst FCLK_RESET2_N ] + set FCLK_RESET3_N [ create_bd_port -dir O -type rst FCLK_RESET3_N ] + set IRQ_F2P [ create_bd_port -dir I -from 15 -to 0 -type intr IRQ_F2P ] + set_property -dict [ list \ +CONFIG.PortWidth {16} \ +CONFIG.SENSITIVITY {EDGE_RISING} \ + ] $IRQ_F2P + set MIO [ create_bd_port -dir IO -from 53 -to 0 MIO ] + set PS_CLK [ create_bd_port -dir IO PS_CLK ] + set PS_PORB [ create_bd_port -dir IO PS_PORB ] + set PS_SRSTB [ create_bd_port -dir IO PS_SRSTB ] + set SPI0_MISO_I [ create_bd_port -dir I SPI0_MISO_I ] + set SPI0_MISO_O [ create_bd_port -dir O SPI0_MISO_O ] + set SPI0_MISO_T [ create_bd_port -dir O SPI0_MISO_T ] + set SPI0_MOSI_I [ create_bd_port -dir I SPI0_MOSI_I ] + set SPI0_MOSI_O [ create_bd_port -dir O SPI0_MOSI_O ] + set SPI0_MOSI_T [ create_bd_port -dir O SPI0_MOSI_T ] + set SPI0_SCLK_I [ create_bd_port -dir I SPI0_SCLK_I ] + set SPI0_SCLK_O [ create_bd_port -dir O SPI0_SCLK_O ] + set SPI0_SCLK_T [ create_bd_port -dir O SPI0_SCLK_T ] + set SPI0_SS1_O [ create_bd_port -dir O SPI0_SS1_O ] + set SPI0_SS2_O [ create_bd_port -dir O SPI0_SS2_O ] + set SPI0_SS_I [ create_bd_port -dir I SPI0_SS_I ] + set SPI0_SS_O [ create_bd_port -dir O SPI0_SS_O ] + set SPI0_SS_T [ create_bd_port -dir O SPI0_SS_T ] + set SPI1_MISO_I [ create_bd_port -dir I SPI1_MISO_I ] + set SPI1_MISO_O [ create_bd_port -dir O SPI1_MISO_O ] + set SPI1_MISO_T [ create_bd_port -dir O SPI1_MISO_T ] + set SPI1_MOSI_I [ create_bd_port -dir I SPI1_MOSI_I ] + set SPI1_MOSI_O [ create_bd_port -dir O SPI1_MOSI_O ] + set SPI1_MOSI_T [ create_bd_port -dir O SPI1_MOSI_T ] + set SPI1_SCLK_I [ create_bd_port -dir I SPI1_SCLK_I ] + set SPI1_SCLK_O [ create_bd_port -dir O SPI1_SCLK_O ] + set SPI1_SCLK_T [ create_bd_port -dir O SPI1_SCLK_T ] + set SPI1_SS1_O [ create_bd_port -dir O SPI1_SS1_O ] + set SPI1_SS2_O [ create_bd_port -dir O SPI1_SS2_O ] + set SPI1_SS_I [ create_bd_port -dir I SPI1_SS_I ] + set SPI1_SS_O [ create_bd_port -dir O SPI1_SS_O ] + set SPI1_SS_T [ create_bd_port -dir O SPI1_SS_T ] + set JTAG0_TCK [ create_bd_port -dir IO JTAG0_TCK ] + set JTAG0_TMS [ create_bd_port -dir IO JTAG0_TMS ] + set JTAG0_TDI [ create_bd_port -dir IO JTAG0_TDI ] + set JTAG0_TDO [ create_bd_port -dir I JTAG0_TDO ] + set JTAG1_TCK [ create_bd_port -dir IO JTAG1_TCK ] + set JTAG1_TMS [ create_bd_port -dir IO JTAG1_TMS ] + set JTAG1_TDI [ create_bd_port -dir IO JTAG1_TDI ] + set JTAG1_TDO [ create_bd_port -dir I JTAG1_TDO ] + set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk S_AXI_GP0_ACLK ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_RESET {S_AXI_GP0_ARESETN} \ +CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_GP0_ACLK + set S_AXI_GP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP0_ARESETN ] + set S_AXI_GP1_ACLK [ create_bd_port -dir I -type clk S_AXI_GP1_ACLK ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_RESET {S_AXI_GP1_ARESETN} \ +CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_GP1_ACLK + set S_AXI_GP1_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP1_ARESETN ] + set S_AXI_HP0_ACLK [ create_bd_port -dir I -type clk S_AXI_HP0_ACLK ] + set_property -dict [ list \ +CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_HP0_ACLK + set S_AXI_HP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_HP0_ARESETN ] + set S_AXI_HP1_ACLK [ create_bd_port -dir I -type clk S_AXI_HP1_ACLK ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_RESET {S_AXI_HP1_ARESETN} \ +CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_HP1_ACLK + set S_AXI_HP1_ARESETN [ create_bd_port -dir I -type rst S_AXI_HP1_ARESETN ] + set bus_clk [ create_bd_port -dir I -type clk bus_clk ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_BUSIF {m_axis_dma:s_axis_dma} \ +CONFIG.ASSOCIATED_RESET {bus_rstn} \ +CONFIG.FREQ_HZ {200000000} \ + ] $bus_clk + set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ] + + set M_AXI_WR_CLK [ create_bd_port -dir I -type clk M_AXI_WR_CLK ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_BUSIF {M_AXI_WR} \ +CONFIG.ASSOCIATED_RESET {M_AXI_WR_RSTn} \ +CONFIG.FREQ_HZ {62500000} \ + ] $M_AXI_WR_CLK + set M_AXI_WR_RSTn [ create_bd_port -dir I -type rst M_AXI_WR_RSTn ] + + set clk40 [ create_bd_port -dir I -type clk clk40 ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_BUSIF {M_AXI_NET0:M_AXI_NET1:M_AXI_XBAR:M_AXI_JESD0:M_AXI_JESD1:M_AXI_ETH_DMA0:M_AXI_ETH_DMA1:M_AXI_NET2} \ +CONFIG.ASSOCIATED_RESET {clk40_rstn} \ +CONFIG.FREQ_HZ {40000000} \ + ] $clk40 + set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] + + create_bd_port -dir I qsfp_sda_i + create_bd_port -dir O qsfp_sda_o + create_bd_port -dir O qsfp_sda_t + create_bd_port -dir I qsfp_scl_i + create_bd_port -dir O qsfp_scl_o + create_bd_port -dir O qsfp_scl_t + + # Create instance: axi_interconnect_hp0, and set properties + set axi_interconnect_hp0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hp0 ] + set_property -dict [ list \ +CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ +CONFIG.NUM_MI {1} \ +CONFIG.NUM_SI {2} \ + ] $axi_interconnect_hp0 + + set axi_interconnect_hp1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hp1 ] + set_property -dict [ list \ +CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ +CONFIG.NUM_MI {1} \ +CONFIG.NUM_SI {2} \ + ] $axi_interconnect_hp1 + + # Create instance: axi_interconnect_0, and set properties + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ +CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ +CONFIG.NUM_MI {16} \ + ] $axi_interconnect_0 + + # Create instance: axi_uartlite_0, and set properties + set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ] + set_property -dict [ list \ +CONFIG.C_BAUDRATE {115200} \ + ] $axi_uartlite_0 + + # Create instance: dma + create_hier_cell_dma [current_bd_instance .] dma 10 + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ +CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {800} \ +CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ +CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ +CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_ENET0_RESET_ENABLE {1} \ +CONFIG.PCW_ENET0_RESET_IO {MIO 6} \ +CONFIG.PCW_EN_CLK1_PORT {1} \ +CONFIG.PCW_EN_CLK2_PORT {1} \ +CONFIG.PCW_EN_CLK3_PORT {1} \ +CONFIG.PCW_EN_RST1_PORT {1} \ +CONFIG.PCW_EN_RST2_PORT {1} \ +CONFIG.PCW_EN_RST3_PORT {1} \ +CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {40} \ +CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {166.6667} \ +CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ +CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ +CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ +CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \ +CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_I2C0_RESET_ENABLE {1} \ +CONFIG.PCW_I2C0_RESET_IO {MIO 3} \ +CONFIG.PCW_IRQ_F2P_INTR {1} \ +CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_PJTAG_PJTAG_IO {MIO 10 .. 13} \ +CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \ +CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ +CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ +CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART1_UART1_IO {MIO 8 .. 9} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.096} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.102} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.100} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.090} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.054} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.040} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.041} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.010} \ +CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \ +CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_USB0_RESET_ENABLE {1} \ +CONFIG.PCW_USB0_RESET_IO {MIO 7} \ +CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ +CONFIG.PCW_USE_S_AXI_GP0 {0} \ +CONFIG.PCW_USE_S_AXI_GP1 {0} \ +CONFIG.PCW_USE_S_AXI_HP0 {1} \ +CONFIG.PCW_USE_S_AXI_HP1 {1} \ +CONFIG.PCW_USE_S_AXI_HP2 {1} \ +CONFIG.PCW_USE_S_AXI_HP3 {1} \ + ] $processing_system7_0 + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ +CONFIG.IN0_WIDTH {8} \ +CONFIG.NUM_PORTS {9} \ + ] $xlconcat_0 + + # Create instance: xlslice_2, and set properties + set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] + set_property -dict [ list \ +CONFIG.DIN_FROM {7} \ +CONFIG.DIN_TO {0} \ +CONFIG.DIN_WIDTH {16} \ +CONFIG.DOUT_WIDTH {8} \ + ] $xlslice_2 + + # Create instance: jtag_0, jtag_1 + set jtag_0 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_bitq:1.0 jtag_0 ] + set jtag_1 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_bitq:1.0 jtag_1 ] + + # Create instance: axi_iic_0 for QSFP i2c + set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ] + + + # Create interface connections + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0] + connect_bd_intf_net -intf_net S_AXI_GP0_1 [get_bd_intf_ports S_AXI_GP0] [get_bd_intf_pins axi_interconnect_hp0/S01_AXI] + connect_bd_intf_net -intf_net S_AXI_GP1_1 [get_bd_intf_ports S_AXI_GP1] [get_bd_intf_pins axi_interconnect_hp1/S01_AXI] + connect_bd_intf_net -intf_net S_AXI_HP0_1 [get_bd_intf_ports S_AXI_HP0] [get_bd_intf_pins axi_interconnect_hp0/S00_AXI] + connect_bd_intf_net -intf_net S_AXI_HP1_1 [get_bd_intf_ports S_AXI_HP1] [get_bd_intf_pins axi_interconnect_hp1/S00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M_AXI_ETH_DMA0] [get_bd_intf_pins axi_interconnect_0/M00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports M_AXI_NET0] [get_bd_intf_pins axi_interconnect_0/M01_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports M_AXI_ETH_DMA1] [get_bd_intf_pins axi_interconnect_0/M02_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports M_AXI_NET1] [get_bd_intf_pins axi_interconnect_0/M03_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports M_AXI_XBAR] [get_bd_intf_pins axi_interconnect_0/M04_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_ports M_AXI_JESD0] [get_bd_intf_pins axi_interconnect_0/M05_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_ports M_AXI_JESD1] [get_bd_intf_pins axi_interconnect_0/M06_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_ports M_AXI_NET2] [get_bd_intf_pins axi_interconnect_0/M07_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_interconnect_0/M08_AXI] [get_bd_intf_pins dma/s_axi_rx_dmac] + connect_bd_intf_net -intf_net axi_interconnect_0_M09_AXI [get_bd_intf_pins axi_interconnect_0/M09_AXI] [get_bd_intf_pins dma/s_axi_tx_dmac] + connect_bd_intf_net -intf_net axi_interconnect_0_M10_AXI [get_bd_intf_pins axi_interconnect_0/M10_AXI] [get_bd_intf_pins dma/s_axi_regfile] + connect_bd_intf_net -intf_net axi_interconnect_0_M11_AXI [get_bd_intf_pins jtag_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M11_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M12_AXI [get_bd_intf_pins jtag_1/S_AXI] [get_bd_intf_pins axi_interconnect_0/M12_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M13_AXI [get_bd_intf_pins axi_interconnect_0/M13_AXI] [get_bd_intf_pins axi_uartlite_0/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M14_AXI [get_bd_intf_ports M_AXI_WR] [get_bd_intf_pins axi_interconnect_0/M14_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M15_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M15_AXI] + + connect_bd_intf_net -intf_net axi_protocol_converter_hp0_M_AXI [get_bd_intf_pins axi_interconnect_hp0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] + connect_bd_intf_net -intf_net axi_protocol_converter_hp1_M_AXI [get_bd_intf_pins axi_interconnect_hp1/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1] + connect_bd_intf_net -intf_net dma_M_AXI_RX_DMA [get_bd_intf_pins dma/M_AXI_RX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP2] + connect_bd_intf_net -intf_net dma_M_AXI_TX_DMA [get_bd_intf_pins dma/M_AXI_TX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP3] + connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_ports s_axis_dma] [get_bd_intf_pins dma/s_axis_dma] + connect_bd_intf_net -intf_net m_axis_dma_1 [get_bd_intf_ports m_axis_dma] [get_bd_intf_pins dma/m_axis_dma] + connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0] [get_bd_intf_pins processing_system7_0/GPIO_0] + connect_bd_intf_net -intf_net processing_system7_0_USBIND_0 [get_bd_intf_ports USBIND_0] [get_bd_intf_pins processing_system7_0/USBIND_0] + connect_bd_intf_net -intf_net WR_UART [get_bd_intf_ports WR_UART] [get_bd_intf_pins axi_uartlite_0/UART] + + # Create port connections + connect_bd_net -net IRQ_F2P_1 [get_bd_ports IRQ_F2P] [get_bd_pins xlslice_2/Din] + connect_bd_net -net SPI0_MISO_I_1 [get_bd_ports SPI0_MISO_I] [get_bd_pins processing_system7_0/SPI0_MISO_I] + connect_bd_net -net SPI0_MOSI_I_1 [get_bd_ports SPI0_MOSI_I] [get_bd_pins processing_system7_0/SPI0_MOSI_I] + connect_bd_net -net SPI0_SCLK_I_1 [get_bd_ports SPI0_SCLK_I] [get_bd_pins processing_system7_0/SPI0_SCLK_I] + connect_bd_net -net SPI0_SS_I_1 [get_bd_ports SPI0_SS_I] [get_bd_pins processing_system7_0/SPI0_SS_I] + connect_bd_net -net SPI1_MISO_I_1 [get_bd_ports SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MISO_I] + connect_bd_net -net SPI1_MOSI_I_1 [get_bd_ports SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] + connect_bd_net -net SPI1_SCLK_I_1 [get_bd_ports SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] + connect_bd_net -net SPI1_SS_I_1 [get_bd_ports SPI1_SS_I] [get_bd_pins processing_system7_0/SPI1_SS_I] + connect_bd_net -net S_AXI_HP0_ACLK_1 [get_bd_pins axi_interconnect_hp0/S01_ACLK] + connect_bd_net -net S_AXI_HP0_ARESETN_1 [get_bd_pins axi_interconnect_hp0/S01_ARESETN] + connect_bd_net -net S_AXI_HP1_ACLK_1 [get_bd_pins axi_interconnect_hp1/S01_ACLK] + connect_bd_net -net S_AXI_HP1_ARESETN_1 [get_bd_pins axi_interconnect_hp1/S01_ARESETN] + connect_bd_net -net S_AXI_HP0_ACLK_1 [get_bd_ports S_AXI_HP0_ACLK] [get_bd_pins axi_interconnect_hp0/M00_ACLK] [get_bd_pins axi_interconnect_hp0/S00_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins axi_interconnect_hp0/ACLK] + connect_bd_net -net S_AXI_HP0_ARESETN_1 [get_bd_ports S_AXI_HP0_ARESETN] [get_bd_pins axi_interconnect_hp0/M00_ARESETN] [get_bd_pins axi_interconnect_hp0/S00_ARESETN] [get_bd_pins axi_interconnect_hp0/ARESETN] + connect_bd_net -net S_AXI_HP1_ACLK_1 [get_bd_ports S_AXI_HP1_ACLK] [get_bd_pins axi_interconnect_hp1/M00_ACLK] [get_bd_pins axi_interconnect_hp1/S00_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins axi_interconnect_hp1/ACLK] + connect_bd_net -net S_AXI_HP1_ARESETN_1 [get_bd_ports S_AXI_HP1_ARESETN] [get_bd_pins axi_interconnect_hp1/M00_ARESETN] [get_bd_pins axi_interconnect_hp1/S00_ARESETN] [get_bd_pins axi_interconnect_hp1/ARESETN] + connect_bd_net -net bus_clk [get_bd_ports bus_clk] [get_bd_pins dma/bus_clk] + connect_bd_net -net bus_rstn [get_bd_ports bus_rstn] [get_bd_pins dma/bus_rstn] + connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins axi_interconnect_0/M10_ACLK] [get_bd_pins dma/clk40] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] [get_bd_pins axi_interconnect_0/M11_ACLK] [get_bd_pins axi_interconnect_0/M12_ACLK] [get_bd_pins axi_interconnect_0/M15_ACLK] + connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins axi_interconnect_0/M10_ARESETN] [get_bd_pins axi_interconnect_0/M11_ARESETN] [get_bd_pins axi_interconnect_0/M12_ARESETN] [get_bd_pins axi_interconnect_0/M15_ARESETN] [get_bd_pins dma/clk40_rstn] + connect_bd_net -net M_AXI_WR_CLK [get_bd_ports M_AXI_WR_CLK] [get_bd_pins axi_interconnect_0/M14_ACLK] + connect_bd_net -net M_AXI_WR_RSTn [get_bd_ports M_AXI_WR_RSTn] [get_bd_pins axi_interconnect_0/M14_ARESETN] + connect_bd_net -net ddr_vrn [get_bd_ports DDR_VRN] [get_bd_pins processing_system7_0/DDR_VRN] + connect_bd_net -net ddr_vrp [get_bd_ports DDR_VRP] [get_bd_pins processing_system7_0/DDR_VRP] + connect_bd_net -net dma_tx_irq [get_bd_pins dma/tx_irq] [get_bd_pins xlconcat_0/In2] + connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins jtag_0/S_AXI_ACLK] [get_bd_pins jtag_1/S_AXI_ACLK] [get_bd_pins axi_iic_0/s_axi_aclk] + connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins jtag_0/S_AXI_ARESETN] [get_bd_pins jtag_1/S_AXI_ARESETN] [get_bd_pins axi_iic_0/s_axi_aresetn] + connect_bd_net -net mio [get_bd_ports MIO] [get_bd_pins processing_system7_0/MIO] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins processing_system7_0/FCLK_CLK0] + connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_ports FCLK_CLK1] [get_bd_pins processing_system7_0/FCLK_CLK1] + connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_ports FCLK_CLK2] [get_bd_pins processing_system7_0/FCLK_CLK2] + connect_bd_net -net processing_system7_0_FCLK_CLK3 [get_bd_ports FCLK_CLK3] [get_bd_pins processing_system7_0/FCLK_CLK3] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins processing_system7_0/FCLK_RESET0_N] + connect_bd_net -net processing_system7_0_FCLK_RESET1_N [get_bd_ports FCLK_RESET1_N] [get_bd_pins processing_system7_0/FCLK_RESET1_N] + connect_bd_net -net processing_system7_0_FCLK_RESET2_N [get_bd_ports FCLK_RESET2_N] [get_bd_pins processing_system7_0/FCLK_RESET2_N] + connect_bd_net -net processing_system7_0_FCLK_RESET3_N [get_bd_ports FCLK_RESET3_N] [get_bd_pins processing_system7_0/FCLK_RESET3_N] + connect_bd_net -net processing_system7_0_SPI0_MISO_O [get_bd_ports SPI0_MISO_O] [get_bd_pins processing_system7_0/SPI0_MISO_O] + connect_bd_net -net processing_system7_0_SPI0_MISO_T [get_bd_ports SPI0_MISO_T] [get_bd_pins processing_system7_0/SPI0_MISO_T] + connect_bd_net -net processing_system7_0_SPI0_MOSI_O [get_bd_ports SPI0_MOSI_O] [get_bd_pins processing_system7_0/SPI0_MOSI_O] + connect_bd_net -net processing_system7_0_SPI0_MOSI_T [get_bd_ports SPI0_MOSI_T] [get_bd_pins processing_system7_0/SPI0_MOSI_T] + connect_bd_net -net processing_system7_0_SPI0_SCLK_O [get_bd_ports SPI0_SCLK_O] [get_bd_pins processing_system7_0/SPI0_SCLK_O] + connect_bd_net -net processing_system7_0_SPI0_SCLK_T [get_bd_ports SPI0_SCLK_T] [get_bd_pins processing_system7_0/SPI0_SCLK_T] + connect_bd_net -net processing_system7_0_SPI0_SS1_O [get_bd_ports SPI0_SS1_O] [get_bd_pins processing_system7_0/SPI0_SS1_O] + connect_bd_net -net processing_system7_0_SPI0_SS2_O [get_bd_ports SPI0_SS2_O] [get_bd_pins processing_system7_0/SPI0_SS2_O] + connect_bd_net -net processing_system7_0_SPI0_SS_O [get_bd_ports SPI0_SS_O] [get_bd_pins processing_system7_0/SPI0_SS_O] + connect_bd_net -net processing_system7_0_SPI0_SS_T [get_bd_ports SPI0_SS_T] [get_bd_pins processing_system7_0/SPI0_SS_T] + connect_bd_net -net processing_system7_0_SPI1_MISO_O [get_bd_ports SPI1_MISO_O] [get_bd_pins processing_system7_0/SPI1_MISO_O] + connect_bd_net -net processing_system7_0_SPI1_MISO_T [get_bd_ports SPI1_MISO_T] [get_bd_pins processing_system7_0/SPI1_MISO_T] + connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports SPI1_MOSI_O] [get_bd_pins processing_system7_0/SPI1_MOSI_O] + connect_bd_net -net processing_system7_0_SPI1_MOSI_T [get_bd_ports SPI1_MOSI_T] [get_bd_pins processing_system7_0/SPI1_MOSI_T] + connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports SPI1_SCLK_O] [get_bd_pins processing_system7_0/SPI1_SCLK_O] + connect_bd_net -net processing_system7_0_SPI1_SCLK_T [get_bd_ports SPI1_SCLK_T] [get_bd_pins processing_system7_0/SPI1_SCLK_T] + connect_bd_net -net processing_system7_0_SPI1_SS1_O [get_bd_ports SPI1_SS1_O] [get_bd_pins processing_system7_0/SPI1_SS1_O] + connect_bd_net -net processing_system7_0_SPI1_SS2_O [get_bd_ports SPI1_SS2_O] [get_bd_pins processing_system7_0/SPI1_SS2_O] + connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports SPI1_SS_O] [get_bd_pins processing_system7_0/SPI1_SS_O] + connect_bd_net -net processing_system7_0_SPI1_SS_T [get_bd_ports SPI1_SS_T] [get_bd_pins processing_system7_0/SPI1_SS_T] + connect_bd_net -net ps_clk [get_bd_ports PS_CLK] [get_bd_pins processing_system7_0/PS_CLK] + connect_bd_net -net ps_porb [get_bd_ports PS_PORB] [get_bd_pins processing_system7_0/PS_PORB] + connect_bd_net -net ps_srstb [get_bd_ports PS_SRSTB] [get_bd_pins processing_system7_0/PS_SRSTB] + connect_bd_net -net rx_dma_irq [get_bd_pins dma/rx_irq] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlslice_2_Dout [get_bd_pins xlconcat_0/In0] [get_bd_pins xlslice_2/Dout] + connect_bd_net -net JTAG0_TCK [get_bd_ports JTAG0_TCK] [get_bd_pins jtag_0/bit_clk] + connect_bd_net -net JTAG0_TMS [get_bd_ports JTAG0_TMS] [get_bd_pins jtag_0/bit_stb] + connect_bd_net -net JTAG0_TDI [get_bd_ports JTAG0_TDI] [get_bd_pins jtag_0/bit_out] + connect_bd_net -net JTAG0_TDO [get_bd_ports JTAG0_TDO] [get_bd_pins jtag_0/bit_in] + connect_bd_net -net JTAG1_TCK [get_bd_ports JTAG1_TCK] [get_bd_pins jtag_1/bit_clk] + connect_bd_net -net JTAG1_TMS [get_bd_ports JTAG1_TMS] [get_bd_pins jtag_1/bit_stb] + connect_bd_net -net JTAG1_TDI [get_bd_ports JTAG1_TDI] [get_bd_pins jtag_1/bit_out] + connect_bd_net -net JTAG1_TDO [get_bd_ports JTAG1_TDO] [get_bd_pins jtag_1/bit_in] + connect_bd_net [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins xlconcat_0/In3] + connect_bd_net [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins xlconcat_0/In4] + connect_bd_net -net qsfp_sda_i [get_bd_pins axi_iic_0/sda_i] [get_bd_ports qsfp_sda_i] + connect_bd_net -net qsfp_sda_o [get_bd_pins axi_iic_0/sda_o] [get_bd_ports qsfp_sda_o] + connect_bd_net -net qsfp_sda_t [get_bd_pins axi_iic_0/sda_t] [get_bd_ports qsfp_sda_t] + connect_bd_net -net qsfp_scl_i [get_bd_pins axi_iic_0/scl_i] [get_bd_ports qsfp_scl_i] + connect_bd_net -net qsfp_scl_o [get_bd_pins axi_iic_0/scl_o] [get_bd_ports qsfp_scl_o] + connect_bd_net -net qsfp_scl_t [get_bd_pins axi_iic_0/scl_t] [get_bd_ports qsfp_scl_t] + connect_bd_net [get_bd_ports clk40] [get_bd_pins axi_uartlite_0/s_axi_aclk] + connect_bd_net [get_bd_ports clk40_rstn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] + connect_bd_net [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M13_ACLK] + connect_bd_net [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M13_ARESETN] + + # Create address segments + create_bd_addr_seg -range 0x4000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_ETH_DMA0/Reg] SEG_M_AXI_ETH_DMA0_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40008000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_ETH_DMA1/Reg] SEG_M_AXI_ETH_DMA1_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40014000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_JESD0/Reg] SEG_M_AXI_JESD0_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40004000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET0/Reg] SEG_M_AXI_NET0_Reg + create_bd_addr_seg -range 0x4000 -offset 0x4000C000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET1/Reg] SEG_M_AXI_NET1_Reg + create_bd_addr_seg -range 0x20000 -offset 0x40020000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET2/Reg] SEG_M_AXI_NET2_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40018000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_JESD1/Reg] SEG_M_AXI_JESD1_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_XBAR/Reg] SEG_M_AXI_XBAR_Reg + create_bd_addr_seg -range 0x10000 -offset 0x43CA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_0/s_axi/axi_lite] SEG_axi_dmac_0_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CB0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_1/s_axi/axi_lite] SEG_axi_dmac_1_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CC0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_2/s_axi/axi_lite] SEG_axi_dmac_2_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CD0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_3/s_axi/axi_lite] SEG_axi_dmac_3_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CE0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_4/s_axi/axi_lite] SEG_axi_dmac_4_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CF0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_5/s_axi/axi_lite] SEG_axi_dmac_5_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43D00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_6/s_axi/axi_lite] SEG_axi_dmac_6_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43D10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_7/s_axi/axi_lite] SEG_axi_dmac_7_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43D20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_8/s_axi/axi_lite] SEG_axi_dmac_8_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43D30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_9/s_axi/axi_lite] SEG_axi_dmac_9_axi_lite + create_bd_addr_seg -range 0x40000 -offset 0x43D40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_WR/Reg] SEG_M_AXI_WR_Reg + create_bd_addr_seg -range 0x10000 -offset 0x43D80000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg + create_bd_addr_seg -range 0x1000 -offset 0x42080000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_regfile_0/S_AXI/regs] SEG_axi_regfile_0_regs + create_bd_addr_seg -range 0x10000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma0/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma1/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite11 + create_bd_addr_seg -range 0x10000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma2/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite13 + create_bd_addr_seg -range 0x10000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma3/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite15 + create_bd_addr_seg -range 0x10000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma4/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite17 + create_bd_addr_seg -range 0x10000 -offset 0x43C50000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma5/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite19 + create_bd_addr_seg -range 0x10000 -offset 0x43C60000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma6/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite21 + create_bd_addr_seg -range 0x10000 -offset 0x43C70000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma7/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite23 + create_bd_addr_seg -range 0x10000 -offset 0x43C80000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma8/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite25 + create_bd_addr_seg -range 0x10000 -offset 0x43C90000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma9/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite27 + create_bd_addr_seg -range 0x1000 -offset 0x42100000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs jtag_0/S_AXI/reg0] SEG_jtag_0_reg0 + create_bd_addr_seg -range 0x1000 -offset 0x42200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs jtag_1/S_AXI/reg0] SEG_jtag_1_reg0 + create_bd_addr_seg -range 0x1000 -offset 0x42C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs {axi_uartlite_0/S_AXI/Reg }] SEG_WR_UART_Reg + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_0/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_1/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_2/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_3/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_4/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_5/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_6/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_7/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_8/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_9/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma0/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma1/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma2/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma3/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma4/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma5/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma6/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma7/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma8/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma9/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces S_AXI_GP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_GP0_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces S_AXI_GP1] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_GP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces S_AXI_HP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces S_AXI_HP1] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..b159ce4b6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,45 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +ONE_GIGE_PHY_SRCS = \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gige_phy.v \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v \ +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/, \ +one_gig_eth_pcs_pma_example_design.v \ +one_gig_eth_pcs_pma_reset_sync_ex.v \ +one_gig_eth_pcs_pma_sync_block_ex.v \ +one_gig_eth_pcs_pma_tx_elastic_buffer.v \ +one_gig_eth_pcs_pma_gt_common.v \ +one_gig_eth_pcs_pma_resets.v \ +) + +IP_ONE_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + +IP_ONE_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/, \ +one_gig_eth_pcs_pma.xci.out \ +synth/one_gig_eth_pcs_pma_block.v \ +synth/one_gig_eth_pcs_pma_reset_sync.v \ +synth/one_gig_eth_pcs_pma.v \ +synth/one_gig_eth_pcs_pma_ooc.xdc \ +synth/one_gig_eth_pcs_pma_sync_block.v \ +synth/one_gig_eth_pcs_pma.xdc \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard.v \ +synth/transceiver/one_gig_eth_pcs_pma_transceiver.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_init.v \ +synth/transceiver/one_gig_eth_pcs_pma_reset_wtd_timer.v \ +synth/transceiver/one_gig_eth_pcs_pma_tx_startup_fsm.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_multi_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_rx_startup_fsm.v \ +) + +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) + +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,one_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..79d8850b4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci @@ -0,0 +1,353 @@ + + + xilinx.com + xci + unknown + 1.0 + + + one_gig_eth_pcs_pma + + + 1 + 1 + 1 + 1 + + + + 0 + + + + 0 + + + 0 + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + false + false + false + false + 0 + + + + 0 + + + + 0 + false + 100000000 + + + + 0 + + + + 0 + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + false + false + false + false + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + false + false + false + + + + 100000000 + 0 + 0.000 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + ACTIVE_LOW + ACTIVE_LOW + ACTIVE_LOW + ACTIVE_LOW + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + true + 0 + 0 + false + false + DIFF_PAIR_0 + DIFF_PAIR_1 + false + DIFF_PAIR_0 + DIFF_PAIR_1 + zynq + 0 + one_gig_eth_pcs_pma + 50 + false + . + false + false + false + false + zynq + 8 + 9 + X0Y0 + 7 + 4 + GTH + false + false + false + false + true + false + false + 1 + clk0 + 125 + TXOUTCLK + true + false + one_gig_eth_pcs_pma_gt + false + GTXE2 + false + 1 + false + false + true + xc7z100 + false + 1 + false + false + Sync + one_gig_eth_pcs_pma + Custom + 50 + TEMAC + Custom + 0 + false + false + false + false + X0Y0 + GTH + false + false + 125 + Custom + true + 1G + 1 + Transceiver + 125 + clk0 + TXOUTCLK + DIFF_PAIR_0 + DIFF_PAIR_1 + false + 10_100_1000 + false + 1000BASEX + Include_Shared_Logic_in_Example_Design + Time_of_day + false + DIFF_PAIR_0 + DIFF_PAIR_1 + 1 + false + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 6 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v new file mode 100644 index 000000000..e5e05c62b --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v @@ -0,0 +1,188 @@ +//------------------------------------------------------------------------------ +// File : one_gig_eth_pcs_pma_clocking.v +// Author : Xilinx Inc. +//------------------------------------------------------------------------------ +// (c) Copyright 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//------------------------------------------------------------------------------ +// Description: This module holds the Clocking logic for pcs/pma core. + + +`timescale 1 ps/1 ps + + +//------------------------------------------------------------------------------ +// The module declaration for the example design +//------------------------------------------------------------------------------ + +module one_gig_eth_pcs_pma_clocking + ( + input txoutclk, // txoutclk from GT transceiver. + input rxoutclk, // rxoutclk from GT transceiver. + input mmcm_reset, // MMCM Reset + output wire mmcm_locked, // MMCM locked + + output userclk, // for GT PMA reference clock + output userclk2, // 125MHz clock for core reference clock. + output rxuserclk, // for GT PMA reference clock + output rxuserclk2 // 125MHz clock for core reference clock. + ); + + wire clkout0; // MMCM output clock + wire clkout1; // MMCM output clock + wire clkfbout; // MMCM Feedback clock +// Route txoutclk input through a BUFG + wire txoutclk_bufg; + wire userclk_i; + wire rxoutclk_buf; + + //--------------------------------------------------------------------------- + // Transceiver Clock Management + //--------------------------------------------------------------------------- + + // Route txoutclk input through a BUFG + BUFG bufg_txoutclk ( + .I (txoutclk), + .O (txoutclk_bufg) + ); + + // The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is + // routed to an MMCM module where it is used to create phase and frequency + // related 62.5MHz and 125MHz clock sources + MMCME2_ADV # ( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.5), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.5), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (16.0), + .CLKFBOUT_MULT_F (16.000), + .CLKOUT0_DIVIDE_F (8.000), + .CLKOUT1_DIVIDE (16), + + .REF_JITTER1 (0.010) + ) mmcm_adv_inst ( + // Output clocks + .CLKFBOUT (clkfbout), + .CLKFBOUTB (), + .CLKOUT0 (clkout0), + .CLKOUT0B (), + .CLKOUT1 (clkout1), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (clkfbout), + .CLKIN1 (txoutclk_bufg), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (mmcm_locked), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (mmcm_reset) + ); + // This 62.5MHz clock is placed onto global clock routing and is then used + // for tranceiver TXUSRCLK/RXUSRCLK. + BUFG bufg_userclk ( + .I (clkout1), + .O (userclk_i) + ); + + + // This 125MHz clock is placed onto global clock routing and is then used + // to clock all Ethernet core logic. + BUFG bufg_userclk2 ( + .I (clkout0), + .O (userclk2) + ); + + + +assign userclk = userclk_i; + + + // Place the Rx recovered clock on a Global Clock Buffer (it may be possible + // to switch this for a BUFHCE/BUFR and BUFMR combination) + BUFG rxrecclkbufg ( + .I (rxoutclk), + .O (rxoutclk_buf) + ); + + assign rxuserclk2 = rxoutclk_buf; + assign rxuserclk = rxoutclk_buf; + +endmodule // one_gig_eth_pcs_pma_clocking diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v new file mode 100644 index 000000000..4c92d105a --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v @@ -0,0 +1,238 @@ +//------------------------------------------------------------------------------ +// File : one_gig_eth_pcs_pma_support.v +// Author : Xilinx Inc. +//------------------------------------------------------------------------------ +// (c) Copyright 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//------------------------------------------------------------------------------ +// Description: This module holds the support level for the pcs/pma core +// This can be used as-is in a single core design, or adapted +// for use with multi-core implementations + +`timescale 1 ps/1 ps +(* DowngradeIPIdentifiedWarnings="yes" *) + +//------------------------------------------------------------------------------ +// The module declaration for the Core Block wrapper. +//------------------------------------------------------------------------------ + +module one_gig_eth_pcs_pma_support + ( + // Transceiver Interface + //---------------------- + + + input gtrefclk, // gtrefclk routed through an IBUFG. + input gtrefclk_bufg, // gtrefclk routed through a BUFG for driving logic. + output txp, // Differential +ve of serial transmission from PMA to PMD. + output txn, // Differential -ve of serial transmission from PMA to PMD. + input rxp, // Differential +ve for serial reception from PMD to PMA. + input rxn, // Differential -ve for serial reception from PMD to PMA. + output userclk_out, + output userclk2_out, + output rxuserclk_out, + output rxuserclk2_out, + input independent_clock_bufg, // Freerun Independent clock, + output pma_reset_out, // transceiver PMA reset signal + output mmcm_locked_out, // MMCM Locked + output resetdone, + // GMII Interface + //--------------- + input [7:0] gmii_txd, // Transmit data from client MAC. + input gmii_tx_en, // Transmit control signal from client MAC. + input gmii_tx_er, // Transmit control signal from client MAC. + output [7:0] gmii_rxd, // Received Data to client MAC. + output gmii_rx_dv, // Received control signal to client MAC. + output gmii_rx_er, // Received control signal to client MAC. + output gmii_isolate, // Tristate control to electrically isolate GMII. + + // Management: MDIO Interface + //--------------------------- + + input mdc, // Management Data Clock + input mdio_i, // Management Data In + output mdio_o, // Management Data Out + output mdio_t, // Management Data Tristate + input [4:0] phyaddr, // MDIO address + input [4:0] configuration_vector, // Alternative to MDIO interface. + input configuration_valid, // Validation signal for Config vector + + // General IO's + //------------- + output [15:0] status_vector, // Core status. + input reset, // Asynchronous reset for entire core. + + input signal_detect, // Input from PMD to indicate presence of optical input. + input gt0_qplloutclk_in, + input gt0_qplloutrefclk_in + + + + ); + + + //--------------------------------------------------------------------------- + // Internal signals used in this block level wrapper. + //--------------------------------------------------------------------------- + + // Core <=> Transceiver interconnect + wire cplllock; // reset done indication from transceiver + wire mmcm_reset; // Reset to MMCM based on resetdone + wire mmcm_locked; // Signal indicating that MMCM has locked + wire pma_reset; // Reset synchronized to system clock + wire txoutclk; // txoutclk from GT transceiver (62.5MHz) + wire rxoutclk; // txoutclk from GT transceiver (62.5MHz) + wire userclk; + wire userclk2; + wire rxuserclk; + wire rxuserclk2; + + // GT Interface + //------------- + //wire gt0_qplloutclk; + //wire gt0_qplloutrefclk; + +one_gig_eth_pcs_pma +pcs_pma_i + ( + + // Transceiver Interface + //---------------------- + + .gtrefclk (gtrefclk), // Very high quality clock for GT transceiver. + .gtrefclk_bufg (gtrefclk_bufg), + .txp (txp), // Differential +ve of serial transmission from PMA to PMD. + .txn (txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp (rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn (rxn), // Differential -ve for serial reception from PMD to PMA. + + .txoutclk (txoutclk), + .rxoutclk (rxoutclk), + .resetdone (resetdone), + .cplllock (cplllock), + .mmcm_reset (mmcm_reset), + .userclk (userclk), + .userclk2 (userclk2), + .rxuserclk (rxuserclk), + .rxuserclk2 (rxuserclk2), + .independent_clock_bufg (independent_clock_bufg), + .pma_reset (pma_reset), + .mmcm_locked (mmcm_locked), + + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd), + .gmii_rx_dv (gmii_rx_dv), + .gmii_rx_er (gmii_rx_er), + .gmii_isolate (gmii_isolate), + + // Management: MDIO Interface + //--------------------------- + + .mdc (mdc), + .mdio_i (mdio_i), + .mdio_o (mdio_o), + .mdio_t (mdio_t), + .phyaddr (phyaddr), + .configuration_vector (configuration_vector), + .configuration_valid (configuration_valid), + + + // General IO's + //------------- + .status_vector (status_vector), // Core status. + .reset (pma_reset), // Asynchronous reset for entire core. + + .signal_detect (signal_detect) , // Input from PMD to indicate presence of optical input. + .gt0_qplloutclk_in (gt0_qplloutclk_in), + .gt0_qplloutrefclk_in (gt0_qplloutrefclk_in) + ); + + + //---------------------------------------------------------------------------- + // Instantiate the clocking module. + //---------------------------------------------------------------------------- + one_gig_eth_pcs_pma_clocking core_clocking_i + ( + .txoutclk (txoutclk), + .rxoutclk (rxoutclk), + .mmcm_reset (mmcm_reset), + .mmcm_locked (mmcm_locked), + .userclk (userclk), + .userclk2 (userclk2), + .rxuserclk (rxuserclk), + .rxuserclk2 (rxuserclk2) + ); + +assign gtrefclk_out = gtrefclk; +assign gtrefclk_bufg_out = gtrefclk_bufg; +assign userclk_out = userclk; +assign userclk2_out = userclk2; +assign rxuserclk_out = rxuserclk; +assign rxuserclk2_out = rxuserclk2; + + + //--------------------------------------------------------------------------- + // Transceiver PMA reset circuitry + //--------------------------------------------------------------------------- + one_gig_eth_pcs_pma_resets core_resets_i + ( + .reset (reset), + .independent_clock_bufg (independent_clock_bufg), + + .pma_reset (pma_reset) + ); + +assign pma_reset_out = pma_reset; + + + assign mmcm_locked_out = mmcm_locked; + +endmodule // one_gig_eth_pcs_pma_support + diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.v b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.v new file mode 100644 index 000000000..b02424f03 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.v @@ -0,0 +1,105 @@ +// +// Copyright 2014 Ettus Research LLC +// + +module one_gige_phy +( + input independent_clock, + input gt0_qplloutclk_in, + input gt0_qplloutrefclk_in, + + // Tranceiver Interface + //--------------------- + input gtrefclk, // Reference clock for MGT: 125MHz, very high quality. + input gtrefclk_bufg, // Reference clock routed through a BUFG + output txp, // Differential +ve of serial transmission from PMA to PMD. + output txn, // Differential -ve of serial transmission from PMA to PMD. + input rxp, // Differential +ve for serial reception from PMD to PMA. + input rxn, // Differential -ve for serial reception from PMD to PMA. + + // GMII Interface (client MAC <=> PCS) + //------------------------------------ + output gmii_clk, // Receive clock to client MAC. + input [7:0] gmii_txd, // Transmit data from client MAC. + input gmii_tx_en, // Transmit control signal from client MAC. + input gmii_tx_er, // Transmit control signal from client MAC. + output reg [7:0] gmii_rxd, // Received Data to client MAC. + output reg gmii_rx_dv, // Received control signal to client MAC. + output reg gmii_rx_er, // Received control signal to client MAC. + + // Management: MDIO Interface + //--------------------------- + input mdc, // Management Data Clock + input mdio_i, // Management Data In + output mdio_o, // Management Data Out + output mdio_t, // Management Data Tristate + input [4:0] phyaddr, // MDIO PHY Address + input [4:0] configuration_vector, // Alternative to MDIO interface. + input configuration_valid, // Validation signal for Config vector + + // General IO's + //------------- + output [15:0] status_vector, // Core status. + input reset, // Asynchronous reset for entire core. + input signal_detect, // Input from PMD to indicate presence of optical input. + output pma_reset_out +); + + wire resetdone; // To indicate that the GT transceiver has completed its reset cycle + wire userclk; // 62.5MHz clock for GT transceiver Tx/Rx user clocks + wire userclk2; // 125MHz clock for core reference clock. + wire rxuserclk2; + wire gmii_isolate; // internal gmii_isolate signal. + + wire [7:0] gmii_rxd_int; + wire gmii_rx_dv_int; + wire gmii_rx_er_int; + + always @(posedge gmii_clk) begin + gmii_rxd <= gmii_rxd_int; + gmii_rx_dv <= gmii_rx_dv_int; + gmii_rx_er <= gmii_rx_er_int; + end + + //---------------------------------------------------------------------------- + // Instantiate core wrapper + //---------------------------------------------------------------------------- + one_gig_eth_pcs_pma_support core_support_i ( + .gtrefclk (gtrefclk), + .gtrefclk_bufg (gtrefclk_bufg), + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + .mmcm_locked_out (), + .userclk_out (userclk), + .userclk2_out (userclk2), + .rxuserclk_out (), + .rxuserclk2_out (rxuserclk2), + .independent_clock_bufg(independent_clock), + .pma_reset_out (pma_reset_out), + .resetdone (resetdone), + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd_int), + .gmii_rx_dv (gmii_rx_dv_int), + .gmii_rx_er (gmii_rx_er_int), + .gmii_isolate (gmii_isolate), + .mdc (mdc), + .mdio_i (mdio_i), + .mdio_o (mdio_o), + .mdio_t (mdio_t), + .phyaddr (phyaddr), + .configuration_vector (configuration_vector), + .configuration_valid (configuration_valid), + .status_vector (status_vector), + .reset (reset), + .signal_detect (signal_detect), + .gt0_qplloutclk_in (gt0_qplloutclk_in), + .gt0_qplloutrefclk_in (gt0_qplloutrefclk_in) + ); + + assign gmii_clk = userclk2; + +endmodule // one_gige_phy diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc new file mode 100644 index 000000000..4dadace3b --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc @@ -0,0 +1,164 @@ + + +#*********************************************************** +# The following constraints target the Transceiver Physical* +# Interface which is instantiated in the Example Design. * +#*********************************************************** +#----------------------------------------------------------- +# Transceiver I/O placement: - +#----------------------------------------------------------- + + +# Place the transceiver components, chosen for this example design +# *** These values should be modified according to your specific design *** + +#set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells */*/*/transceiver_inst/gtwizard_inst/*/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i] + + +#----------------------------------------------------------- +# Clock source used for the IDELAY Controller (if present) - +# and for the transceiver reset circuitry - +#----------------------------------------------------------- + + +create_clock -name independent_clock -period 5.000 [get_ports independent_clock] + +#----------------------------------------------------------- +# PCS/PMA Clock period Constraints: please do not relax - +#----------------------------------------------------------- + +create_clock -add -name gtrefclk -period 8.000 [get_ports gtrefclk_p] + + +#----------------------------------------------------------- +# Transceiver I/O placement: - +#----------------------------------------------------------- + +# Place the transceiver components, chosen for this example design +# *** These values should be modified according to your specific design *** + +#set_property LOC H6 [get_ports gtrefclk_p] +#set_property LOC H5 [get_ports gtrefclk_n] + + +#*********************************************************** +# The following constraints target the GMII implemented in * +# the Example Design. * +#*********************************************************** +# If the GMII is intended to be an internal interface, * +# the GMII signals can be connected directly to user * +# logic and all of the following constraints in this file * +# should be removed. * +# * +# If the GMII is intended to be an external interface, * +# all of the following constraints in this file should be * +# maintained. * +#*********************************************************** + +#----------------------------------------------------------- +# GMII IOSTANDARD Constraints: please select an I/O - +# Standard (LVTTL is suggested). - +#----------------------------------------------------------- + +# Please update the IOSTANDARD according to that available in the device + +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[4]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er] + +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[4]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er] + +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_clk] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_clk] + +#----------------------------------------------------------- +# Lock down the GMII Tx signals to the same bank for low - +# skew. This is an example placement only. - +#----------------------------------------------------------- + + +#----------------------------------------------------------- +# To Adjust GMII Tx Input Setup/Hold Timing - +#----------------------------------------------------------- +# These constraints will be set at a later date when device speed files have matured + +#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_en] +#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_er] + +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[7].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[6].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[5].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[4].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[3].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[2].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[1].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[0].delay_gmii_txd}] + + + +#----------------------------------------------------------- +# To check (analyze) GMII Tx Input Setup/Hold Timing - +#----------------------------------------------------------- + +create_clock -name gmii_tx_clk -period 8.000 [get_ports gmii_tx_clk] + + + +#----------------------------------------------------------- +# Fast Skew maximises output setup and hold timing - +#----------------------------------------------------------- +set_property SLEW FAST [get_ports {gmii_rxd[*]}] +set_property SLEW FAST [get_ports gmii_rx_dv] +set_property SLEW FAST [get_ports gmii_rx_er] +set_property SLEW FAST [get_ports gmii_rx_clk] + + +#----------------------------------------------------------- +# GMII Transmitter Constraints: place flip-flops in IOB - +#----------------------------------------------------------- +#set_property IOB TRUE [get_cells gmii_txd_IBUF*] +#set_property IOB TRUE [get_cells gmii_tx_en_IBUF*] +#set_property IOB TRUE [get_cells gmii_tx_er_IBUF*] + +#----------------------------------------------------------- +# GMII Receiver Constraints: place flip-flops in IOB - +#----------------------------------------------------------- +#set_property IOB TRUE [get_cells gmii_rxd_obuf_reg*] +#set_property IOB TRUE [get_cells gmii_rx_dv_obuf_reg] +#set_property IOB TRUE [get_cells gmii_rx_er_obuf_reg] + + + +#----------------------------------------------------------- +# GMII Tx Elastic Buffer Constraints - +#----------------------------------------------------------- + +# Control Gray Code delay and skew across clock boundary +set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_rd_addrgray*/data_sync*/D}] +set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_wr_addrgray*/data_sync*/D}] + +# Constrain between Distributed Memory (output data) and the 1st set of flip-flops +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/tx_en_fifo_reg1*/D}] +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/tx_er_fifo_reg1*/D}] +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/txd_fifo_reg1*/D}] + +set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }] + +set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe_reg*/PRE}] +set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe*[0]/D}] diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..db95346bd --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,42 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +TEN_GIGE_PHY_SRCS = \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy.v \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_gt_common.v \ +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma_ex/imports/, \ +ten_gig_eth_pcs_pma_example_design.v \ +ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v \ +ten_gig_eth_pcs_pma_shared_clock_and_reset.v \ +ten_gig_eth_pcs_pma_support.v \ +) + +IP_TEN_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + +IP_TEN_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/, \ +ten_gig_eth_pcs_pma.xci.out \ +synth/ten_gig_eth_pcs_pma_block.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_multi_gt.v \ +synth/ten_gig_eth_pcs_pma_cable_pull_logic.v \ +synth/ten_gig_eth_pcs_pma_local_clock_and_reset.v \ +synth/ten_gig_eth_pcs_pma_clocks.xdc \ +synth/ten_gig_eth_pcs_pma_ooc.xdc \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer_rst.v \ +synth/ten_gig_eth_pcs_pma_sim_speedup_controller.v \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer.v \ +synth/ten_gig_eth_pcs_pma.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \ +synth/ten_gig_eth_pcs_pma.xdc \ +) + +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) + +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..8af7da882 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci @@ -0,0 +1,192 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ten_gig_eth_pcs_pma + + + 0 + 0 + 0 + 0 + 0 + + + 0 + 0.000 + + + + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 0 + false + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + false + 0 + 0 + + + 0 + 0.000 + 0 + + + + 0 + 0.000 + + + + 0 + 0.000 + 0 + + + + 0 + 0.000 + + + + 0 + 0.000 + + 0 + 0.000 + + + + 0 + 0.000 + 0 + ten_gig_eth_pcs_pma + 100.00 + zynq + X0Y0 + 32 + 0 + false + false + true + false + false + false + clk0 + 156 + 10 + ten_gig_eth_pcs_pma_gt + ten_gig_eth_pcs_pma + 100.00 + None + X0Y0 + true + clk0 + 156.25 + 0 + Time_of_day + false + false + false + BASE-R + 64bit + false + false + 10Gig + GTH + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 15 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_gt_common.v b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_gt_common.v new file mode 100644 index 000000000..8d03d78df --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_gt_common.v @@ -0,0 +1,202 @@ +//----------------------------------------------------------------------------- +// Title : GT Common wrapper +// Project : 10GBASE-R +//----------------------------------------------------------------------------- +// File : ten_gig_eth_pcs_pma_gt_common.v +//----------------------------------------------------------------------------- +// Description: This file contains the +// 10GBASE-R Transceiver GT Common block. +//----------------------------------------------------------------------------- +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + +`timescale 1ps / 1ps + +module ten_gig_eth_pcs_pma_gt_common # ( + parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false" ) //Does not affect hardware + ( + input refclk, + input qpllreset, + output qplllock, + output qplloutclk, + output qplloutrefclk, + input [2:0] qpllrefclksel + ); + + +//***************************** Parameter Declarations ************************ + localparam QPLL_FBDIV_TOP = 66; + + localparam QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 : + (QPLL_FBDIV_TOP == 20) ? 10'b0000110000 : + (QPLL_FBDIV_TOP == 32) ? 10'b0001100000 : + (QPLL_FBDIV_TOP == 40) ? 10'b0010000000 : + (QPLL_FBDIV_TOP == 64) ? 10'b0011100000 : + (QPLL_FBDIV_TOP == 66) ? 10'b0101000000 : + (QPLL_FBDIV_TOP == 80) ? 10'b0100100000 : + (QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000; + + localparam QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 : + (QPLL_FBDIV_TOP == 20) ? 1'b1 : + (QPLL_FBDIV_TOP == 32) ? 1'b1 : + (QPLL_FBDIV_TOP == 40) ? 1'b1 : + (QPLL_FBDIV_TOP == 64) ? 1'b1 : + (QPLL_FBDIV_TOP == 66) ? 1'b0 : + (QPLL_FBDIV_TOP == 80) ? 1'b1 : + (QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1; + +//***************************** Wire Declarations ***************************** + + // ground and vcc signals + wire tied_to_ground_i; + wire [63:0] tied_to_ground_vec_i; + wire tied_to_vcc_i; + wire [63:0] tied_to_vcc_vec_i; + +//********************************* Main Body of Code************************** + + assign tied_to_ground_i = 1'b0; + assign tied_to_ground_vec_i = 64'h0000000000000000; + assign tied_to_vcc_i = 1'b1; + assign tied_to_vcc_vec_i = 64'hffffffffffffffff; + + + wire gt0_gtrefclk0_common_in; + wire gt0_qpllreset_in; + wire gt0_qplllock_out; + wire gt0_qplloutclk_i; + wire gt0_qplloutrefclk_i; + + assign gt0_gtrefclk0_common_in = refclk; + assign gt0_qpllreset_in = qpllreset; + assign qplllock = gt0_qplllock_out; + assign qplloutclk = gt0_qplloutclk_i; + assign qplloutrefclk = gt0_qplloutrefclk_i; + + + //_________________________________________________________________________ + //_________________________________________________________________________ + //_________________________GTXE2_COMMON____________________________________ + + GTXE2_COMMON # + ( + // Simulation attributes + .SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP), + .SIM_QPLLREFCLK_SEL (3'b001), + .SIM_VERSION ("4.0"), + + + //----------------COMMON BLOCK Attributes--------------- + .BIAS_CFG (64'h0000040000001000), + .COMMON_CFG (32'h00000000), + .QPLL_CFG (27'h0680181), + .QPLL_CLKOUT_CFG (4'b0000), + .QPLL_COARSE_FREQ_OVRD (6'b010000), + .QPLL_COARSE_FREQ_OVRD_EN (1'b0), + .QPLL_CP (10'b0000011111), + .QPLL_CP_MONITOR_EN (1'b0), + .QPLL_DMONITOR_SEL (1'b0), + .QPLL_FBDIV (QPLL_FBDIV_IN), + .QPLL_FBDIV_MONITOR_EN (1'b0), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_INIT_CFG (24'h000006), + .QPLL_LOCK_CFG (16'h21E8), + .QPLL_LPF (4'b1111), + .QPLL_REFCLK_DIV (1) + ) + gtxe2_common_0_i + ( + //----------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- + .DRPADDR (tied_to_ground_vec_i[7:0]), + .DRPCLK (tied_to_ground_i), + .DRPDI (tied_to_ground_vec_i[15:0]), + .DRPDO (), + .DRPEN (tied_to_ground_i), + .DRPRDY (), + .DRPWE (tied_to_ground_i), + //-------------------- Common Block - Ref Clock Ports --------------------- + .GTGREFCLK (tied_to_ground_i), + .GTNORTHREFCLK0 (tied_to_ground_i), + .GTNORTHREFCLK1 (tied_to_ground_i), + .GTREFCLK0 (gt0_gtrefclk0_common_in), + .GTREFCLK1 (tied_to_ground_i), + .GTSOUTHREFCLK0 (tied_to_ground_i), + .GTSOUTHREFCLK1 (tied_to_ground_i), + //--------------------- Common Block - Clocking Ports ---------------------- + .QPLLOUTCLK (gt0_qplloutclk_i), + .QPLLOUTREFCLK (gt0_qplloutrefclk_i), + .REFCLKOUTMONITOR (), + //----------------------- Common Block - QPLL Ports ------------------------ + .QPLLDMONITOR (), + .QPLLFBCLKLOST (), + .QPLLLOCK (gt0_qplllock_out), + .QPLLLOCKDETCLK (1'b0), + .QPLLLOCKEN (tied_to_vcc_i), + .QPLLOUTRESET (tied_to_ground_i), + .QPLLPD (tied_to_ground_i), + .QPLLREFCLKLOST (), + .QPLLREFCLKSEL (qpllrefclksel), + .QPLLRESET (gt0_qpllreset_in), + .QPLLRSVD1 (16'b0000000000000000), + .QPLLRSVD2 (5'b11111), + //------------------------------- QPLL Ports ------------------------------- + .BGBYPASSB (tied_to_vcc_i), + .BGMONITORENB (tied_to_vcc_i), + .BGPDB (tied_to_vcc_i), + .BGRCALOVRD (5'b11111), + .PMARSVD (8'b00000000), + .RCALENB (tied_to_vcc_i) + + ); + + + + + +endmodule + + + diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v new file mode 100644 index 000000000..5c798136f --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v @@ -0,0 +1,241 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy +( + input refclk, + input clk156, + input dclk, + input areset, + input sim_speedup_control, + input [63:0] xgmii_txd, + input [7:0] xgmii_txc, + output reg [63:0] xgmii_rxd, + output reg [7:0] xgmii_rxc, + output txp, + output txn, + input rxp, + input rxn, + input mdc, + input mdio_in, + output reg mdio_out, + output reg mdio_tri, + input [4:0] prtad, + output [7:0] core_status, + output resetdone, + input signal_detect, + input tx_fault, + output tx_disable, + output qpllreset, + input qplllock, + input qplloutclk, + input qplloutrefclk, + output tx_out_clk +); + + reg [63:0] xgmii_txd_reg; + reg [7:0] xgmii_txc_reg; + wire [63:0] xgmii_rxd_int; + wire [7:0] xgmii_rxc_int; + + // Add a pipeline to the xmgii_tx inputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_txd_reg <= xgmii_txd; + xgmii_txc_reg <= xgmii_txc; + end + + // Add a pipeline to the xmgii_rx outputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_rxd <= xgmii_rxd_int; + xgmii_rxc <= xgmii_rxc_int; + end + + wire mdio_out_int; + wire mdio_tri_int; + reg mdc_reg; + reg mdio_in_reg; + + // Add a pipeline to the mdio in/outputs, to aid timing closure + // This is safe because the mdio clock is running so slowly + always @(posedge clk156) + begin + mdio_out <= mdio_out_int; + mdio_tri <= mdio_tri_int; + mdc_reg <= mdc; + mdio_in_reg <= mdio_in; + end + + // Signal declarations + wire txclk322; + + wire drp_gnt; + wire drp_req; + wire drp_den_o; + wire drp_dwe_o; + wire [15:0] drp_daddr_o; + wire [15:0] drp_di_o; + wire drp_drdy_o; + wire [15:0] drp_drpdo_o; + wire drp_den_i; + wire drp_dwe_i; + wire [15:0] drp_daddr_i; + wire [15:0] drp_di_i; + wire drp_drdy_i; + wire [15:0] drp_drpdo_i; + + wire tx_resetdone_int; + wire rx_resetdone_int; + + wire areset_clk156; + wire gttxreset; + wire gtrxreset; + wire qplllock_txusrclk2; + wire gttxreset_txusrclk2; + wire reset_counter_done; + wire txusrclk; + wire txusrclk2; + reg txuserrdy; + + assign resetdone = tx_resetdone_int && rx_resetdone_int; + + // If no arbitration is required on the GT DRP ports then connect REQ to GNT + // and connect other signals i <= o; + assign drp_gnt = drp_req; + assign drp_den_i = drp_den_o; + assign drp_dwe_i = drp_dwe_o; + assign drp_daddr_i = drp_daddr_o; + assign drp_di_i = drp_di_o; + assign drp_drdy_i = drp_drdy_o; + assign drp_drpdo_i = drp_drpdo_o; + + // Asynch reset synchronizers... + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) areset_clk156_sync_i ( + .clk(clk156), + .rst(areset), + .data_in(1'b0), + .data_out(areset_clk156) + ); + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b0) + ) qplllock_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(!qplllock), + .data_in(1'b1), + .data_out(qplllock_txusrclk2) + ); + + reg [7:0] reset_counter = 8'h00; + reg [3:0] reset_pulse = 4'b1110; + assign reset_counter_done = reset_counter[7]; + + // Hold off the GT resets until 500ns after configuration. + // 128 ticks at 6.4ns period will be >> 500 ns. + always @(posedge clk156) + begin + if (!reset_counter[7]) + reset_counter <= reset_counter + 1'b1; + else + reset_counter <= reset_counter; + end + + always @(posedge clk156) + begin + if (areset_clk156 == 1'b1) + reset_pulse <= 4'b1110; + else if(reset_counter[7]) + reset_pulse <= {1'b0, reset_pulse[3:1]}; + end + + assign qpllreset = reset_pulse[0]; + assign gttxreset = reset_pulse[0]; + assign gtrxreset = reset_pulse[0]; + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) gttxreset_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(gttxreset), + .data_in(1'b0), + .data_out(gttxreset_txusrclk2) + ); + + always @(posedge txusrclk2 or posedge gttxreset_txusrclk2) + begin + if(gttxreset_txusrclk2) + txuserrdy <= 1'b0; + else + txuserrdy <= qplllock_txusrclk2; + end + + BUFG tx322clk_bufg_i ( + .I (txclk322), + .O (txusrclk) + ); + + assign txusrclk2 = txusrclk; + assign tx_out_clk = txclk322; + + // Instantiate the 10GBASER/KR Block Level + ten_gig_eth_pcs_pma ten_gig_eth_pcs_pma_i ( + .coreclk(clk156), + .dclk(dclk), + .rxrecclk_out(), + .txusrclk(txusrclk), + .txusrclk2(txusrclk2), + .txoutclk(txclk322), + .areset_coreclk(areset_clk156), + .txuserrdy(txuserrdy), + .areset(areset), + .gttxreset(gttxreset), + .gtrxreset(gtrxreset), + .sim_speedup_control(sim_speedup_control), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .reset_counter_done(reset_counter_done), + .xgmii_txd(xgmii_txd_reg), + .xgmii_txc(xgmii_txc_reg), + .xgmii_rxd(xgmii_rxd_int), + .xgmii_rxc(xgmii_rxc_int), + .txp(txp), + .txn(txn), + .rxp(rxp), + .rxn(rxn), + .mdc(mdc_reg), + .mdio_in(mdio_in_reg), + .mdio_out(mdio_out_int), + .mdio_tri(mdio_tri_int), + .prtad(prtad), + .core_status(core_status), + .tx_resetdone(tx_resetdone_int), + .rx_resetdone(rx_resetdone_int), + .signal_detect(signal_detect), + .tx_fault(tx_fault), + .drp_req(drp_req), + .drp_gnt(drp_gnt), + .drp_den_o(drp_den_o), + .drp_dwe_o(drp_dwe_o), + .drp_daddr_o(drp_daddr_o), + .drp_di_o(drp_di_o), + .drp_drdy_o(drp_drdy_o), + .drp_drpdo_o(drp_drpdo_o), + .drp_den_i(drp_den_i), + .drp_dwe_i(drp_dwe_i), + .drp_daddr_i(drp_daddr_i), + .drp_di_i(drp_di_i), + .drp_drdy_i(drp_drdy_i), + .drp_drpdo_i(drp_drpdo_i), + .pma_pmd_type(3'b101), + .tx_disable(tx_disable) + ); + +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc new file mode 100644 index 000000000..3e637368a --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc @@ -0,0 +1,91 @@ +## (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. + +create_clock -period 6.400 [get_ports {dclk}] + +create_clock -period 6.400 [get_ports refclk_p] + +create_generated_clock -name ddrclock -divide_by 1 -invert -source [get_pins *rx_clk_ddr/C] [get_ports xgmii_rx_clk] +set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}] +set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}] +set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}] +set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}] + +# False paths for async reset removal synchronizers +set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *PRE}] +set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *CLR}] + + +## Sample constraint for GT location +#set_property LOC GTXE2_CHANNEL_X0Y18 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_i/*/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i] +#set_property LOC GTXE2_COMMON_X0Y4 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_gt_common_block/gtxe2_common_0_i] + +set_property IOSTANDARD HSTL_I [get_ports {xgmii_txc[*]}] +set_property IOSTANDARD HSTL_I [get_ports {xgmii_txd[*]}] + +set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxc[*]}] +set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxd[*]}] + +set_property IOB TRUE [get_cells {xgmii_rxc_reg[*]}] +set_property IOB TRUE [get_cells {xgmii_rxd_reg[*]}] + +set_property IOSTANDARD HSTL_I [get_ports xgmii_rx_clk] + + +################################################################## +# MDIO-related constraints # +################################################################## +set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_out*reg*}] +set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_tri*reg*}] +################################################################### + +################################################################## +# MDIO-related constraints # +################################################################## +set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdc_reg_reg}] +set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdio_in_reg_reg}] +################################################################### + diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v new file mode 100644 index 000000000..7c1d09fe6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v @@ -0,0 +1,37 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy_clk_gen +( + input refclk_ibuf, + output clk156, + output dclk +); + + wire dclk_buf; + + BUFG clk156_bufg_inst ( + .I (refclk_ibuf), + .O (clk156) + ); + + // Dividing independent clock by 2 as source for DRP clock + BUFR # ( + .BUFR_DIVIDE ("2") + ) dclk_divide_by_2_buf ( + .I (clk156), + .O (dclk_buf), + .CE (1'b1), + .CLR (1'b0) + ); + + BUFG dclk_bufg_i ( + .I (dclk_buf), + .O (dclk) + ); + +endmodule + + + diff --git a/fpga/usrp3/top/n3xx/mb_clocks.xdc b/fpga/usrp3/top/n3xx/mb_clocks.xdc new file mode 100644 index 000000000..30736155f --- /dev/null +++ b/fpga/usrp3/top/n3xx/mb_clocks.xdc @@ -0,0 +1,86 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Timing analysis is performed in "/n3xx/doc/mb_timing.xlsx". See +# the spreadsheet for more details and explanations. + +#******************************************************************************* +## Motherboard Clocks + +# 10/20/25 MHz reference clock from rear panel connector. Constrain to the fastest +# possible clock rate. +set REF_CLK_PERIOD 40.00 +create_clock -name ref_clk -period $REF_CLK_PERIOD [get_ports FPGA_REFCLK_P] +# 125 MHz RJ45 Ethernet clock +create_clock -name ge_phy_clk -period 8.000 [get_ports ENET0_CLK125] +# 156.25 MHz oscillator to MGT bank 110 +create_clock -name xge_clk -period 6.400 [get_ports MGT156MHZ_CLK1_P] +# 125 MHz PLL for MG bank 109 +create_clock -name net_clk -period 8.000 [get_ports NETCLK_P] + +# Virtual clocks for constraining I/O (used below) +create_clock -name async_in_clk -period 50.00 +create_clock -name async_out_clk -period 50.00 + + + +#******************************************************************************* +## Aliases for auto-generated clocks + +# Rename the PS clocks. These are originally declared in the PS7 IP block, but do not +# have super descriptive names. We rename them here for additional clarity, and to match +# the rest of the design. + +# First save off the input jitter setting for each, before we nuke the original clocks. +set clk100_jitter [get_property INPUT_JITTER [get_clocks clk_fpga_0]] +set clk40_jitter [get_property INPUT_JITTER [get_clocks clk_fpga_1]] +set meas_clk_ref_jitter [get_property INPUT_JITTER [get_clocks clk_fpga_2]] +set bus_clk_jitter [get_property INPUT_JITTER [get_clocks clk_fpga_3]] + +# Create the new clocks based on the old ones. This generates critical warnings that +# we are completely rewriting the old clock definition... this is OK. +create_clock -name clk100 \ + -period [get_property PERIOD [get_clocks clk_fpga_0]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_0]]] +create_clock -name clk40 \ + -period [get_property PERIOD [get_clocks clk_fpga_1]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_1]]] +create_clock -name meas_clk_ref \ + -period [get_property PERIOD [get_clocks clk_fpga_2]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_2]]] +create_clock -name bus_clk \ + -period [get_property PERIOD [get_clocks clk_fpga_3]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_3]]] + +# Apply the jitter setting from the original clocks. +set_input_jitter [get_clocks clk100] $clk100_jitter +set_input_jitter [get_clocks clk40] $clk40_jitter +set_input_jitter [get_clocks meas_clk_ref] $meas_clk_ref_jitter +set_input_jitter [get_clocks bus_clk] $bus_clk_jitter + + +# TDC Measurement Clock +create_generated_clock -name meas_clk_fb [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_inst/CLKFBOUT}] +create_generated_clock -name meas_clk [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_inst/CLKOUT0}] + +#******************************************************************************* +## White Rabbit DAC +# Constrain the DIN and NSYNC bits around the clock output. No readback. + +set WR_OUT_CLK [get_ports {WB_DAC_SCLK}] +create_generated_clock -name wr_bus_clk \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $WR_OUT_CLK]/C] \ + -divide_by 2 $WR_OUT_CLK + +#******************************************************************************* +## Front Panel GPIO +# These bits are driven from the DB-A radio clock. Although they are received async in +# the outside world, they should be constrained in the FPGA to avoid any race +# conditions. The best way to do this is a skew constraint across all the bits. + +set FP_GPIO_CLK [get_ports {FPGA_GPIO[0]}] +create_generated_clock -name fp_gpio_bus_clk \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $FP_GPIO_CLK]/C] \ + -divide_by 2 $FP_GPIO_CLK + diff --git a/fpga/usrp3/top/n3xx/mb_pins.xdc b/fpga/usrp3/top/n3xx/mb_pins.xdc new file mode 100644 index 000000000..6eecc42d5 --- /dev/null +++ b/fpga/usrp3/top/n3xx/mb_pins.xdc @@ -0,0 +1,386 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Motherboard Pin Definitions for the N3xx Product Family. +# + +## Bank 12: 3.3V Logic : ################################################################ +## Front-panel GPIO +## FPGA test outputs +######################################################################################### + +set_property PACKAGE_PIN AF25 [get_ports {FPGA_GPIO[0]}] +set_property PACKAGE_PIN AE25 [get_ports {FPGA_GPIO[1]}] +set_property PACKAGE_PIN AG26 [get_ports {FPGA_GPIO[2]}] +set_property PACKAGE_PIN AG27 [get_ports {FPGA_GPIO[3]}] +set_property PACKAGE_PIN AE26 [get_ports {FPGA_GPIO[4]}] +set_property PACKAGE_PIN AB26 [get_ports {FPGA_GPIO[5]}] +set_property PACKAGE_PIN AF27 [get_ports {FPGA_GPIO[6]}] +set_property PACKAGE_PIN AA27 [get_ports {FPGA_GPIO[7]}] +set_property PACKAGE_PIN AE27 [get_ports {FPGA_GPIO[8]}] +set_property PACKAGE_PIN AC26 [get_ports {FPGA_GPIO[9]}] +set_property PACKAGE_PIN AD25 [get_ports {FPGA_GPIO[10]}] +set_property PACKAGE_PIN AD26 [get_ports {FPGA_GPIO[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_GPIO[*]}] +set_property DRIVE 4 [get_ports {FPGA_GPIO[*]}] +set_property SLEW SLOW [get_ports {FPGA_GPIO[*]}] + +# These pins should be commented out for release hardware. +set_property PACKAGE_PIN Y30 [get_ports {FPGA_TEST[0]}] +set_property PACKAGE_PIN AA30 [get_ports {FPGA_TEST[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_TEST[*]}] + +# set_property PACKAGE_PIN AH27 [get_ports {MGMT-GPIO0}] +# set_property PACKAGE_PIN AH26 [get_ports {MGMT-GPIO1}] +# set_property PACKAGE_PIN AC27 [get_ports {MGMT-JTAG-TCK}] +# set_property PACKAGE_PIN AF29 [get_ports {MGMT-JTAG-TDI}] +# set_property PACKAGE_PIN AG29 [get_ports {MGMT-JTAG-TDO}] +# set_property PACKAGE_PIN AB27 [get_ports {MGMT-JTAG-TMS}] +# set_property PACKAGE_PIN Y28 [get_ports {MGMT-SPI-LE}] +# set_property PACKAGE_PIN AD28 [get_ports {MGMT-SPI-MISO}] +# set_property PACKAGE_PIN AA28 [get_ports {MGMT-SPI-MOSI}] +# set_property PACKAGE_PIN AE28 [get_ports {MGMT-SPI-RESET}] +# set_property PACKAGE_PIN AC28 [get_ports {MGMT-SPI-SCLK}] +# When implemented, the MGMT signals need DRIVE and SLEW attributes applied. + +# NPIO and QSFP located elsewhere + + +## Bank 9, 2.5V Logic : ################################################################# +## All of these are inputs and all require internal termination to meet voltage +## swing requirements at the pin. These ports and buffers should always be instantiated +## to meet the internal termination requirement. +######################################################################################### + +set_property PACKAGE_PIN AC18 [get_ports FPGA_REFCLK_P] +set_property PACKAGE_PIN AC19 [get_ports FPGA_REFCLK_N] +set_property IOSTANDARD LVDS_25 [get_ports FPGA_REFCLK_*] +set_property DIFF_TERM TRUE [get_ports FPGA_REFCLK_*] + +set_property PACKAGE_PIN AD18 [get_ports NETCLK_REF_P] +set_property PACKAGE_PIN AD19 [get_ports NETCLK_REF_N] +set_property DIFF_TERM TRUE [get_ports NETCLK_REF_*] +set_property IOSTANDARD LVDS_25 [get_ports NETCLK_REF_*] + +set_property PACKAGE_PIN AA18 [get_ports WB_20MHZ_P] +set_property PACKAGE_PIN AA19 [get_ports WB_20MHZ_N] +set_property DIFF_TERM TRUE [get_ports WB_20MHZ_*] +set_property IOSTANDARD LVDS_25 [get_ports WB_20MHZ_*] + + +## Bank 13, 3.3V : ###################################################################### +## PPS In/Out (including MGMT PPS, unused) +## GPS PPS Raw/Disciplined +## RJ45 signaling (unused) +## Authentication IC +## Resets +## Rear-panel LEDs +######################################################################################### + +set_property PACKAGE_PIN U24 [get_ports REF_1PPS_IN] +set_property IOSTANDARD LVCMOS33 [get_ports REF_1PPS_IN] + +set_property PACKAGE_PIN V29 [get_ports REF_1PPS_OUT] +set_property IOSTANDARD LVCMOS33 [get_ports REF_1PPS_OUT] +set_property DRIVE 12 [get_ports REF_1PPS_OUT] +set_property SLEW SLOW [get_ports REF_1PPS_OUT] +set_property IOB TRUE [get_ports REF_1PPS_OUT] + +# set_property PACKAGE_PIN U29 [get_ports REF_1PPS_IN_MGMT] +# set_property IOSTANDARD LVCMOS33 [get_ports REF_1PPS_IN_MGMT] + +set_property PACKAGE_PIN W30 [get_ports GPS_1PPS] +set_property IOSTANDARD LVCMOS33 [get_ports GPS_1PPS] + +# set_property PACKAGE_PIN V28 [get_ports GPS_1PPS_RAW] +# set_property IOSTANDARD LVCMOS33 [get_ports GPS_1PPS_RAW] + +set_property PACKAGE_PIN U26 [get_ports ENET0_CLK125] +set_property IOSTANDARD LVCMOS33 [get_ports ENET0_CLK125] + +# set_property PACKAGE_PIN R25 [get_ports ENET0_PTP] +# set_property IOSTANDARD LVCMOS33 [get_ports ENET0_PTP] + +# set_property PACKAGE_PIN R30 [get_ports ENET0_PTP_DIR] +# set_property IOSTANDARD LVCMOS33 [get_ports ENET0_PTP_DIR] + +# set_property PACKAGE_PIN U30 [get_ports ATSHA204_SDA] +# set_property IOSTANDARD LVCMOS33 [get_ports ATSHA204_SDA] + +set_property PACKAGE_PIN P26 [get_ports FPGA_PL_RESETN] +set_property IOSTANDARD LVCMOS33 [get_ports FPGA_PL_RESETN] + +set_property PACKAGE_PIN U25 [get_ports PANEL_LED_GPS] +set_property PACKAGE_PIN T25 [get_ports PANEL_LED_LINK] +set_property PACKAGE_PIN W29 [get_ports PANEL_LED_PPS] +set_property PACKAGE_PIN V24 [get_ports PANEL_LED_REF] +set_property IOSTANDARD LVCMOS33 [get_ports PANEL_LED_*] +set_property DRIVE 4 [get_ports PANEL_LED_*] +set_property SLEW SLOW [get_ports PANEL_LED_*] + +# SFP+ Sideband and White Rabbit DAC Control located elsewhere + + +## NanoPitch Interface : ################################################################ +## Bank 12, 3.3V +######################################################################################### + +# set_property PACKAGE_PIN AD29 [get_ports {NPIO-GPIO0}] +# set_property PACKAGE_PIN AC29 [get_ports {NPIO-GPIO1}] +# set_property PACKAGE_PIN AE30 [get_ports {NPIO-GPIO2}] +# set_property PACKAGE_PIN AD30 [get_ports {NPIO-GPIO3}] +# set_property PACKAGE_PIN AH29 [get_ports {NPIO-GPIO4}] +# set_property PACKAGE_PIN AH28 [get_ports {NPIO-GPIO5}] +# set_property PACKAGE_PIN AF30 [get_ports {NPIO-GPIO6}] +# set_property PACKAGE_PIN AG30 [get_ports {NPIO-GPIO7}] +# When implemented, the QSFP signals need DRIVE and SLEW attributes applied. + +set_property PACKAGE_PIN AE8 [get_ports {NPIO_RX0_P}] +set_property PACKAGE_PIN AE7 [get_ports {NPIO_RX0_N}] +set_property PACKAGE_PIN AG8 [get_ports {NPIO_RX1_P}] +set_property PACKAGE_PIN AG7 [get_ports {NPIO_RX1_N}] +set_property PACKAGE_PIN AK2 [get_ports {NPIO_TX0_P}] +set_property PACKAGE_PIN AK1 [get_ports {NPIO_TX0_N}] +set_property PACKAGE_PIN AJ4 [get_ports {NPIO_TX1_P}] +set_property PACKAGE_PIN AJ3 [get_ports {NPIO_TX1_N}] + + +## QSFP : ############################################################################### +## Bank 12, 3.3V +######################################################################################### + +set_property PACKAGE_PIN AJ26 [get_ports {QSFP_I2C_SCL}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_I2C_SCL}] +set_property DRIVE 8 [get_ports {QSFP_I2C_SCL}] + +set_property PACKAGE_PIN AK26 [get_ports {QSFP_I2C_SDA}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_I2C_SDA}] +set_property DRIVE 8 [get_ports {QSFP_I2C_SDA}] + +set_property PACKAGE_PIN AK28 [get_ports {QSFP_INT_B}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_INT_B}] + +set_property PACKAGE_PIN AK30 [get_ports {QSFP_LED}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_LED}] + +set_property PACKAGE_PIN AJ29 [get_ports {QSFP_LPMODE}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_LPMODE}] + +set_property PACKAGE_PIN AK27 [get_ports {QSFP_PRESENT_B}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_PRESENT_B}] + +set_property PACKAGE_PIN AJ28 [get_ports {QSFP_MODSEL_B}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_MODSEL_B}] + +set_property PACKAGE_PIN AJ30 [get_ports {QSFP_RESET_B}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_RESET_B}] + +# When implemented, the QSFP signals need DRIVE and SLEW attributes applied. + +set_property PACKAGE_PIN AD5 [get_ports {QSFP_RX_N[0]}] +set_property PACKAGE_PIN AD6 [get_ports {QSFP_RX_P[0]}] +set_property PACKAGE_PIN AF5 [get_ports {QSFP_RX_N[1]}] +set_property PACKAGE_PIN AF6 [get_ports {QSFP_RX_P[1]}] +set_property PACKAGE_PIN AG3 [get_ports {QSFP_RX_N[2]}] +set_property PACKAGE_PIN AG4 [get_ports {QSFP_RX_P[2]}] +set_property PACKAGE_PIN AH5 [get_ports {QSFP_RX_N[3]}] +set_property PACKAGE_PIN AH6 [get_ports {QSFP_RX_P[3]}] +set_property PACKAGE_PIN AD1 [get_ports {QSFP_TX_N[0]}] +set_property PACKAGE_PIN AD2 [get_ports {QSFP_TX_P[0]}] +set_property PACKAGE_PIN AE3 [get_ports {QSFP_TX_N[1]}] +set_property PACKAGE_PIN AE4 [get_ports {QSFP_TX_P[1]}] +set_property PACKAGE_PIN AF1 [get_ports {QSFP_TX_N[2]}] +set_property PACKAGE_PIN AF2 [get_ports {QSFP_TX_P[2]}] +set_property PACKAGE_PIN AH1 [get_ports {QSFP_TX_N[3]}] +set_property PACKAGE_PIN AH2 [get_ports {QSFP_TX_P[3]}] + + +## White Rabbit : ####################################################################### +## Bank 13, 3.3V +######################################################################################### + +set_property PACKAGE_PIN T29 [get_ports {WB_DAC_DIN}] +set_property PACKAGE_PIN T28 [get_ports {WB_DAC_NCLR}] +set_property PACKAGE_PIN T30 [get_ports {WB_DAC_NLDAC}] +set_property PACKAGE_PIN N29 [get_ports {WB_DAC_NSYNC}] +set_property PACKAGE_PIN P29 [get_ports {WB_DAC_SCLK}] +set_property IOSTANDARD LVCMOS33 [get_ports {WB_DAC_*}] +set_property DRIVE 4 [get_ports {WB_DAC_*}] +set_property SLEW SLOW [get_ports {WB_DAC_*}] + + +## SFP+ : ############################################################################### +## +######################################################################################### + +## Clocks, Bank 109 and 110 + +# These need to have the internal buffer in the FPGA enabled at all times to avoid +# damage to the part. Therefore declare them here in the top level pins file. +set_property PACKAGE_PIN AA8 [get_ports {MGT156MHZ_CLK1_P}] +set_property PACKAGE_PIN AA7 [get_ports {MGT156MHZ_CLK1_N}] + +set_property PACKAGE_PIN AF10 [get_ports {NETCLK_P}] +set_property PACKAGE_PIN AF9 [get_ports {NETCLK_N}] + +# Swapping SFP_0 and SFP_1 pinout to match the label on the silkscreen. +# These FPGA pins are reversed with respect to the schematic now. +## MGTs, Bank 109 + +set_property PACKAGE_PIN AJ7 [get_ports SFP_0_RX_N] +set_property PACKAGE_PIN AJ8 [get_ports SFP_0_RX_P] +set_property PACKAGE_PIN AK5 [get_ports SFP_0_TX_N] +set_property PACKAGE_PIN AK6 [get_ports SFP_0_TX_P] + +set_property PACKAGE_PIN AH9 [get_ports SFP_1_RX_N] +set_property PACKAGE_PIN AH10 [get_ports SFP_1_RX_P] +set_property PACKAGE_PIN AK9 [get_ports SFP_1_TX_N] +set_property PACKAGE_PIN AK10 [get_ports SFP_1_TX_P] + +## SFP+ 0, Sideband, Bank 13 3.3V + +set_property PACKAGE_PIN T27 [get_ports {SFP_0_I2C_NPRESENT}] +set_property IOSTANDARD LVCMOS33 [get_ports {SFP_0_I2C_NPRESENT}] + +set_property PACKAGE_PIN N27 [get_ports SFP_0_LED_A] +set_property PACKAGE_PIN N28 [get_ports SFP_0_LED_B] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_0_LED_*] +set_property DRIVE 4 [get_ports SFP_0_LED_*] +set_property SLEW SLOW [get_ports SFP_0_LED_*] + +set_property PACKAGE_PIN R27 [get_ports SFP_0_LOS] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_0_LOS] + +set_property PACKAGE_PIN R26 [get_ports SFP_0_RS0] +set_property PACKAGE_PIN P28 [get_ports SFP_0_RS1] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_0_RS*] +set_property DRIVE 4 [get_ports SFP_0_RS*] +set_property SLEW SLOW [get_ports SFP_0_RS*] + +set_property PACKAGE_PIN U27 [get_ports SFP_0_TXDISABLE] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_0_TXDISABLE] +set_property DRIVE 4 [get_ports SFP_0_TXDISABLE] +set_property SLEW SLOW [get_ports SFP_0_TXDISABLE] + +set_property PACKAGE_PIN V26 [get_ports SFP_0_TXFAULT] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_0_TXFAULT] + +## SFP+ 1, Slow Speed, Bank 13 3.3V + +# set_property PACKAGE_PIN V23 [get_ports {SFP_1_I2C_NPRESENT}] +# set_property IOSTANDARD LVCMOS33 [get_ports {SFP_1_I2C_NPRESENT}] + +set_property PACKAGE_PIN N26 [get_ports SFP_1_LED_A] +set_property PACKAGE_PIN P30 [get_ports SFP_1_LED_B] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_1_LED_*] +set_property DRIVE 4 [get_ports SFP_1_LED_*] +set_property SLEW SLOW [get_ports SFP_1_LED_*] + +set_property PACKAGE_PIN R28 [get_ports SFP_1_LOS] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_1_LOS] + +set_property PACKAGE_PIN T24 [get_ports SFP_1_RS0] +set_property PACKAGE_PIN P25 [get_ports SFP_1_RS1] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_1_RS*] +set_property DRIVE 4 [get_ports SFP_1_RS*] +set_property SLEW SLOW [get_ports SFP_1_RS*] + +set_property PACKAGE_PIN V27 [get_ports SFP_1_TXDISABLE] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_1_TXDISABLE] +set_property DRIVE 4 [get_ports SFP_1_TXDISABLE] +set_property SLEW SLOW [get_ports SFP_1_TXDISABLE] + +set_property PACKAGE_PIN W24 [get_ports SFP_1_TXFAULT] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_1_TXFAULT] + + +## PL DDR : ############################################################################# +## +######################################################################################### + +# This port must be always enabled due to a Xilinx bug in the silicon. +# https://www.xilinx.com/support/answers/63950.html +set_property PACKAGE_PIN A8 [get_ports FPGA_PUDC_B] +set_property IOSTANDARD LVDCI_15 [get_ports FPGA_PUDC_B] + +set_property PACKAGE_PIN D8 [get_ports {ddr3_addr[0]}] +set_property PACKAGE_PIN A7 [get_ports {ddr3_addr[1]}] +set_property PACKAGE_PIN C7 [get_ports {ddr3_addr[2]}] +set_property PACKAGE_PIN D9 [get_ports {ddr3_addr[3]}] +set_property PACKAGE_PIN J9 [get_ports {ddr3_addr[4]}] +set_property PACKAGE_PIN E8 [get_ports {ddr3_addr[5]}] +set_property PACKAGE_PIN G7 [get_ports {ddr3_addr[6]}] +set_property PACKAGE_PIN E7 [get_ports {ddr3_addr[7]}] +set_property PACKAGE_PIN G11 [get_ports {ddr3_addr[8]}] +set_property PACKAGE_PIN C6 [get_ports {ddr3_addr[9]}] +set_property PACKAGE_PIN B6 [get_ports {ddr3_addr[10]}] +set_property PACKAGE_PIN H7 [get_ports {ddr3_addr[11]}] +set_property PACKAGE_PIN B7 [get_ports {ddr3_addr[12]}] +set_property PACKAGE_PIN F7 [get_ports {ddr3_addr[13]}] +set_property PACKAGE_PIN F8 [get_ports {ddr3_addr[14]}] +set_property PACKAGE_PIN F9 [get_ports {ddr3_addr[15]}] + +set_property PACKAGE_PIN C9 [get_ports {ddr3_ba[0]}] +set_property PACKAGE_PIN E10 [get_ports {ddr3_ba[1]}] +set_property PACKAGE_PIN B9 [get_ports {ddr3_ba[2]}] + +set_property PACKAGE_PIN A10 [get_ports ddr3_cas_n] +set_property PACKAGE_PIN E11 [get_ports {ddr3_cke[0]}] +set_property PACKAGE_PIN H8 [get_ports {ddr3_ck_n[0]}] +set_property PACKAGE_PIN J8 [get_ports {ddr3_ck_p[0]}] +set_property PACKAGE_PIN D11 [get_ports {ddr3_cs_n[0]}] + +set_property PACKAGE_PIN B16 [get_ports {ddr3_dm[0]}] +set_property PACKAGE_PIN B11 [get_ports {ddr3_dm[1]}] +set_property PACKAGE_PIN H13 [get_ports {ddr3_dm[2]}] +set_property PACKAGE_PIN G15 [get_ports {ddr3_dm[3]}] + +set_property PACKAGE_PIN B17 [get_ports {ddr3_dq[0]}] +set_property PACKAGE_PIN A17 [get_ports {ddr3_dq[1]}] +set_property PACKAGE_PIN D15 [get_ports {ddr3_dq[2]}] +set_property PACKAGE_PIN D14 [get_ports {ddr3_dq[3]}] +set_property PACKAGE_PIN C17 [get_ports {ddr3_dq[4]}] +set_property PACKAGE_PIN E15 [get_ports {ddr3_dq[5]}] +set_property PACKAGE_PIN C16 [get_ports {ddr3_dq[6]}] +set_property PACKAGE_PIN D16 [get_ports {ddr3_dq[7]}] +set_property PACKAGE_PIN A13 [get_ports {ddr3_dq[8]}] +set_property PACKAGE_PIN A12 [get_ports {ddr3_dq[9]}] +set_property PACKAGE_PIN C14 [get_ports {ddr3_dq[10]}] +set_property PACKAGE_PIN B12 [get_ports {ddr3_dq[11]}] +set_property PACKAGE_PIN B14 [get_ports {ddr3_dq[12]}] +set_property PACKAGE_PIN C12 [get_ports {ddr3_dq[13]}] +set_property PACKAGE_PIN A14 [get_ports {ddr3_dq[14]}] +set_property PACKAGE_PIN C11 [get_ports {ddr3_dq[15]}] +set_property PACKAGE_PIN J15 [get_ports {ddr3_dq[16]}] +set_property PACKAGE_PIN L14 [get_ports {ddr3_dq[17]}] +set_property PACKAGE_PIN L15 [get_ports {ddr3_dq[18]}] +set_property PACKAGE_PIN J13 [get_ports {ddr3_dq[19]}] +set_property PACKAGE_PIN J14 [get_ports {ddr3_dq[20]}] +set_property PACKAGE_PIN K15 [get_ports {ddr3_dq[21]}] +set_property PACKAGE_PIN J16 [get_ports {ddr3_dq[22]}] +set_property PACKAGE_PIN H14 [get_ports {ddr3_dq[23]}] +set_property PACKAGE_PIN F15 [get_ports {ddr3_dq[24]}] +set_property PACKAGE_PIN G16 [get_ports {ddr3_dq[25]}] +set_property PACKAGE_PIN F14 [get_ports {ddr3_dq[26]}] +set_property PACKAGE_PIN E13 [get_ports {ddr3_dq[27]}] +set_property PACKAGE_PIN G14 [get_ports {ddr3_dq[28]}] +set_property PACKAGE_PIN D13 [get_ports {ddr3_dq[29]}] +set_property PACKAGE_PIN F13 [get_ports {ddr3_dq[30]}] +set_property PACKAGE_PIN E12 [get_ports {ddr3_dq[31]}] + +set_property PACKAGE_PIN F17 [get_ports {ddr3_dqs_p[0]}] +set_property PACKAGE_PIN E17 [get_ports {ddr3_dqs_n[0]}] +set_property PACKAGE_PIN B15 [get_ports {ddr3_dqs_p[1]}] +set_property PACKAGE_PIN A15 [get_ports {ddr3_dqs_n[1]}] +set_property PACKAGE_PIN L13 [get_ports {ddr3_dqs_p[2]}] +set_property PACKAGE_PIN K13 [get_ports {ddr3_dqs_n[2]}] +set_property PACKAGE_PIN F12 [get_ports {ddr3_dqs_n[3]}] +set_property PACKAGE_PIN G12 [get_ports {ddr3_dqs_p[3]}] + +set_property PACKAGE_PIN D10 [get_ports {ddr3_odt[0]}] +set_property PACKAGE_PIN B10 [get_ports ddr3_ras_n] +set_property PACKAGE_PIN D6 [get_ports ddr3_reset_n] +set_property PACKAGE_PIN G9 [get_ports sys_clk_n] +set_property PACKAGE_PIN H9 [get_ports sys_clk_p] +set_property PACKAGE_PIN A9 [get_ports ddr3_we_n] diff --git a/fpga/usrp3/top/n3xx/mb_timing.xdc b/fpga/usrp3/top/n3xx/mb_timing.xdc new file mode 100644 index 000000000..6aa3f8132 --- /dev/null +++ b/fpga/usrp3/top/n3xx/mb_timing.xdc @@ -0,0 +1,111 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Timing analysis is performed in "/n3xx/doc/mb_timing.xlsx". See +# the spreadsheet for more details and explanations. + +#******************************************************************************* +## Asynchronous clock groups + +# All the clocks from the PS are async to everything else except clocks generated +# from themselves. +set_clock_groups -asynchronous -group [get_clocks clk100 -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks clk40 -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks bus_clk -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks meas_clk_ref -include_generated_clocks] + + + +#******************************************************************************* +## PPS Input Timing + +# The external PPS is synchronous to the external reference clock, which is expected to +# be at 10 MHz. Given [setup, hold] of [5ns, 5ns] at the rear panel inputs of the N310, +# we have an adequate data valid window at the FPGA. However, since we overconstrain the +# reference clock to 25 MHz, we use the alternative period here for setup analysis. +set_input_delay -clock ref_clk -min 4.651 [get_ports REF_1PPS_IN] +set_input_delay -clock ref_clk -max [expr {$REF_CLK_PERIOD - 0.235}] [get_ports REF_1PPS_IN] + +# The GPS PPS is also synchronous to the external reference clock (since there is a +# switch on the clock input outside the FPGA). Again, use the overconstrained period. +set_input_delay -clock ref_clk -min 1.234 [get_ports GPS_1PPS] +set_input_delay -clock ref_clk -max [expr {$REF_CLK_PERIOD - 2.111}] [get_ports GPS_1PPS] + + + +#******************************************************************************* +## White Rabbit DAC +# Constrain the DIN and NSYNC bits around the clock output. No readback. + +set MAX_SKEW 5 +set SETUP_SKEW [expr {($MAX_SKEW / 2)-0.5}] +set HOLD_SKEW [expr {($MAX_SKEW / 2)+0.5}] +set PORT_LIST [get_ports {WB_DAC_DIN WB_DAC_NCLR WB_DAC_NSYNC WB_DAC_NLDAC}] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks wr_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks wr_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -clock [get_clocks wr_bus_clk] -min $HOLD_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks wr_bus_clk] -min $HOLD_SKEW $PORT_LIST +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -to [get_clocks wr_bus_clk] -start 0 +set_multicycle_path -hold -to [get_clocks wr_bus_clk] -1 +# Remove analysis from the output "clock" pin. There are ways to do this using TCL, but +# they aren't supported in XDC files... so we do it the old fashioned way. +set_output_delay -clock [get_clocks async_out_clk] 0.000 $WR_OUT_CLK +set_max_delay -to $WR_OUT_CLK 50.000 +set_min_delay -to $WR_OUT_CLK 0.000 + + + +#******************************************************************************* +## MB Async Ins/Outs + +set ASYNC_MB_INPUTS [get_ports {SFP_*_LOS SFP_*_TXFAULT UNUSED_PIN_TDC*}] + +set_input_delay -clock [get_clocks async_in_clk] 0.000 $ASYNC_MB_INPUTS +set_max_delay -from $ASYNC_MB_INPUTS 50.000 +set_min_delay -from $ASYNC_MB_INPUTS 0.000 + + +set ASYNC_MB_OUTPUTS [get_ports {*LED* SFP_*TXDISABLE UNUSED_PIN_TDC* \ + FPGA_TEST[*]}] + +set_output_delay -clock [get_clocks async_out_clk] 0.000 $ASYNC_MB_OUTPUTS +set_max_delay -to $ASYNC_MB_OUTPUTS 50.000 +set_min_delay -to $ASYNC_MB_OUTPUTS 0.000 + + + +#******************************************************************************* +## Front Panel GPIO +# These bits are driven from the DB-A radio clock. Although they are received async in +# the outside world, they should be constrained in the FPGA to avoid any race +# conditions. The best way to do this is a skew constraint across all the bits. + +set MAX_SKEW 10 +set SETUP_SKEW [expr {($MAX_SKEW / 2)-0.5}] +set HOLD_SKEW [expr {($MAX_SKEW / 2)+0.5}] +set PORT_LIST [get_ports {FPGA_GPIO[*]}] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks fp_gpio_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks fp_gpio_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -clock [get_clocks fp_gpio_bus_clk] -min $HOLD_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks fp_gpio_bus_clk] -min $HOLD_SKEW $PORT_LIST +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -to [get_clocks fp_gpio_bus_clk] -start 0 +set_multicycle_path -hold -to [get_clocks fp_gpio_bus_clk] -1 +# Remove analysis from the output "clock" pin. There are ways to do this using TCL, but +# they aren't supported in XDC files... so we do it the old fashioned way. +set_output_delay -clock [get_clocks async_out_clk] 0.000 $FP_GPIO_CLK +set_max_delay -to $FP_GPIO_CLK 50.000 +set_min_delay -to $FP_GPIO_CLK 0.000 +# All inputs on this interface are async. +set_input_delay -clock [get_clocks async_in_clk] 0.000 $PORT_LIST +set_max_delay -from $PORT_LIST 50.000 +set_min_delay -from $PORT_LIST 0.000 + +#****************************************************************************** +## Reset Sync False Path +set_false_path -to [get_pins */synchronizer_false_path/stages[0].value_reg[0]/D] +set_false_path -to [get_pins */synchronizer_false_path/stages[0].value_reg[0]/C] diff --git a/fpga/usrp3/top/n3xx/n300_bist_image_core.v b/fpga/usrp3/top/n3xx/n300_bist_image_core.v new file mode 100644 index 000000000..31d4eeb86 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_bist_image_core.v @@ -0,0 +1,885 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Module: rfnoc_image_core (for n300) +// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) +// Re-running that tool will overwrite this file! +// File generated on: 2019-11-08T15:58:13.938765 +// Source: ./n3xx/n300_bist_image_core.yml +// Source SHA256: 3bed6bab7b614594eb5ea4e49b34a6e9560b10ff4622c1033c206bec1f4a0f2c + +module rfnoc_image_core #( + parameter [15:0] PROTOVER = {8'd1, 8'd0} +)( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio_clk, + input wire dram_clk, + // Basic + input wire [15:0] device_id, +//// IO ports ////////////////////////////////// +// ctrlport_radio0 + output wire [ 1-1:0] m_ctrlport_radio0_req_wr, + output wire [ 1-1:0] m_ctrlport_radio0_req_rd, + output wire [ 20-1:0] m_ctrlport_radio0_req_addr, + output wire [ 32-1:0] m_ctrlport_radio0_req_data, + output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio0_req_time, + input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio0_resp_status, + input wire [ 32-1:0] m_ctrlport_radio0_resp_data, +// time_keeper + input wire [ 64-1:0] radio_time, +// x300_radio0 + input wire [ 64-1:0] radio_rx_data_radio0, + input wire [ 2-1:0] radio_rx_stb_radio0, + output wire [ 2-1:0] radio_rx_running_radio0, + output wire [ 64-1:0] radio_tx_data_radio0, + input wire [ 2-1:0] radio_tx_stb_radio0, + output wire [ 2-1:0] radio_tx_running_radio0, +// dram + input wire [ 1-1:0] axi_rst, + output wire [ 4-1:0] m_axi_awid, + output wire [128-1:0] m_axi_awaddr, + output wire [ 32-1:0] m_axi_awlen, + output wire [ 12-1:0] m_axi_awsize, + output wire [ 8-1:0] m_axi_awburst, + output wire [ 4-1:0] m_axi_awlock, + output wire [ 16-1:0] m_axi_awcache, + output wire [ 12-1:0] m_axi_awprot, + output wire [ 16-1:0] m_axi_awqos, + output wire [ 16-1:0] m_axi_awregion, + output wire [ 4-1:0] m_axi_awuser, + output wire [ 4-1:0] m_axi_awvalid, + input wire [ 4-1:0] m_axi_awready, + output wire [256-1:0] m_axi_wdata, + output wire [ 32-1:0] m_axi_wstrb, + output wire [ 4-1:0] m_axi_wlast, + output wire [ 4-1:0] m_axi_wuser, + output wire [ 4-1:0] m_axi_wvalid, + input wire [ 4-1:0] m_axi_wready, + input wire [ 4-1:0] m_axi_bid, + input wire [ 8-1:0] m_axi_bresp, + input wire [ 4-1:0] m_axi_buser, + input wire [ 4-1:0] m_axi_bvalid, + output wire [ 4-1:0] m_axi_bready, + output wire [ 4-1:0] m_axi_arid, + output wire [128-1:0] m_axi_araddr, + output wire [ 32-1:0] m_axi_arlen, + output wire [ 12-1:0] m_axi_arsize, + output wire [ 8-1:0] m_axi_arburst, + output wire [ 4-1:0] m_axi_arlock, + output wire [ 16-1:0] m_axi_arcache, + output wire [ 12-1:0] m_axi_arprot, + output wire [ 16-1:0] m_axi_arqos, + output wire [ 16-1:0] m_axi_arregion, + output wire [ 4-1:0] m_axi_aruser, + output wire [ 4-1:0] m_axi_arvalid, + input wire [ 4-1:0] m_axi_arready, + input wire [ 4-1:0] m_axi_rid, + input wire [256-1:0] m_axi_rdata, + input wire [ 8-1:0] m_axi_rresp, + input wire [ 4-1:0] m_axi_rlast, + input wire [ 4-1:0] m_axi_ruser, + input wire [ 4-1:0] m_axi_rvalid, + output wire [ 4-1:0] m_axi_rready, + // Transport 0 (eth0 1G) + input wire [64-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [64-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1 10G) + input wire [64-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [64-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma dma) + input wire [64-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [64-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam CHDR_W = 64; + localparam MTU = 10; + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + // ---------------------------------------------------- + // CHDR Crossbar + // ---------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [CHDR_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [CHDR_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep4_tdata ; + wire xb_to_ep4_tlast ; + wire xb_to_ep4_tvalid; + wire xb_to_ep4_tready; + wire [CHDR_W-1:0] ep4_to_xb_tdata ; + wire ep4_to_xb_tlast ; + wire ep4_to_xb_tvalid; + wire ep4_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep5_tdata ; + wire xb_to_ep5_tlast ; + wire xb_to_ep5_tvalid; + wire xb_to_ep5_tready; + wire [CHDR_W-1:0] ep5_to_xb_tdata ; + wire ep5_to_xb_tlast ; + wire ep5_to_xb_tvalid; + wire ep5_to_xb_tready; + + chdr_crossbar_nxn #( + .CHDR_W (CHDR_W), + .NPORTS (7), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (3), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_xb_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep5_to_xb_tdata, ep4_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), + .s_axis_tlast ({ep5_to_xb_tlast, ep4_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tvalid ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep5_to_xb_tready, ep4_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), + .m_axis_tlast ({xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tvalid ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + // ---------------------------------------------------- + // Stream Endpoints + // ---------------------------------------------------- + + wire [CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; + wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep0_tdata ), + .s_axis_chdr_tlast (xb_to_ep0_tlast ), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), + .s_axis_chdr_tready (xb_to_ep0_tready ), + .m_axis_chdr_tdata (ep0_to_xb_tdata ), + .m_axis_chdr_tlast (ep0_to_xb_tlast ), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), + .m_axis_chdr_tready (ep0_to_xb_tready ), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; + wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep1_tdata ), + .s_axis_chdr_tlast (xb_to_ep1_tlast ), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), + .s_axis_chdr_tready (xb_to_ep1_tready ), + .m_axis_chdr_tdata (ep1_to_xb_tdata ), + .m_axis_chdr_tlast (ep1_to_xb_tlast ), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), + .m_axis_chdr_tready (ep1_to_xb_tready ), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep4_out0_tdata; + wire m_ep4_out0_tlast; + wire m_ep4_out0_tvalid; + wire m_ep4_out0_tready; + wire [CHDR_W-1:0] s_ep4_in0_tdata; + wire s_ep4_in0_tlast; + wire s_ep4_in0_tvalid; + wire s_ep4_in0_tready; + wire [31:0] m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ; + wire m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ; + wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; + wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (2), + .CTRL_XBAR_PORT (3), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep4_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep4_tdata ), + .s_axis_chdr_tlast (xb_to_ep4_tlast ), + .s_axis_chdr_tvalid (xb_to_ep4_tvalid ), + .s_axis_chdr_tready (xb_to_ep4_tready ), + .m_axis_chdr_tdata (ep4_to_xb_tdata ), + .m_axis_chdr_tlast (ep4_to_xb_tlast ), + .m_axis_chdr_tvalid (ep4_to_xb_tvalid ), + .m_axis_chdr_tready (ep4_to_xb_tready ), + .s_axis_data_tdata ({s_ep4_in0_tdata}), + .s_axis_data_tlast ({s_ep4_in0_tlast}), + .s_axis_data_tvalid ({s_ep4_in0_tvalid}), + .s_axis_data_tready ({s_ep4_in0_tready}), + .m_axis_data_tdata ({m_ep4_out0_tdata}), + .m_axis_data_tlast ({m_ep4_out0_tlast}), + .m_axis_data_tvalid ({m_ep4_out0_tvalid}), + .m_axis_data_tready ({m_ep4_out0_tready}), + .s_axis_ctrl_tdata (s_ep4_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep4_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep4_ctrl_tready), + .m_axis_ctrl_tdata (m_ep4_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep4_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep4_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep5_out0_tdata; + wire m_ep5_out0_tlast; + wire m_ep5_out0_tvalid; + wire m_ep5_out0_tready; + wire [CHDR_W-1:0] s_ep5_in0_tdata; + wire s_ep5_in0_tlast; + wire s_ep5_in0_tvalid; + wire s_ep5_in0_tready; + wire [31:0] m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ; + wire m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ; + wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; + wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (3), + .CTRL_XBAR_PORT (4), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep5_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep5_tdata ), + .s_axis_chdr_tlast (xb_to_ep5_tlast ), + .s_axis_chdr_tvalid (xb_to_ep5_tvalid ), + .s_axis_chdr_tready (xb_to_ep5_tready ), + .m_axis_chdr_tdata (ep5_to_xb_tdata ), + .m_axis_chdr_tlast (ep5_to_xb_tlast ), + .m_axis_chdr_tvalid (ep5_to_xb_tvalid ), + .m_axis_chdr_tready (ep5_to_xb_tready ), + .s_axis_data_tdata ({s_ep5_in0_tdata}), + .s_axis_data_tlast ({s_ep5_in0_tlast}), + .s_axis_data_tvalid ({s_ep5_in0_tvalid}), + .s_axis_data_tready ({s_ep5_in0_tready}), + .m_axis_data_tdata ({m_ep5_out0_tdata}), + .m_axis_data_tlast ({m_ep5_out0_tlast}), + .m_axis_data_tvalid ({m_ep5_out0_tvalid}), + .m_axis_data_tready ({m_ep5_out0_tready}), + .s_axis_ctrl_tdata (s_ep5_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep5_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep5_ctrl_tready), + .m_axis_ctrl_tdata (m_ep5_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep5_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep5_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + + + // ---------------------------------------------------- + // Control Crossbar + // ---------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; + wire m_core_ctrl_tlast , s_core_ctrl_tlast ; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; + wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_fifo0_ctrl_tdata , s_fifo0_ctrl_tdata ; + wire m_fifo0_ctrl_tlast , s_fifo0_ctrl_tlast ; + wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid; + wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (4), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_fifo0_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_fifo0_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_fifo0_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_fifo0_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_fifo0_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_fifo0_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_fifo0_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_fifo0_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + // ---------------------------------------------------- + // RFNoC Core Kernel + // ---------------------------------------------------- + wire [(512*2)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'h1300), + .DEVICE_FAMILY ("7SERIES"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (2), + .NUM_STREAM_ENDPOINTS(4), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (3), + .NUM_EDGES (8), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata ), + .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata ), + .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + // ---------------------------------------------------- + // Blocks + // ---------------------------------------------------- + + // ---------------------------------------------------- + // radio0 + // ---------------------------------------------------- + wire radio0_radio_clk; + wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_1_tready, m_radio0_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio0_m_ctrlport_req_wr; + wire [ 1-1:0] radio0_m_ctrlport_req_rd; + wire [ 20-1:0] radio0_m_ctrlport_req_addr; + wire [ 32-1:0] radio0_m_ctrlport_req_data; + wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio0_m_ctrlport_req_has_time; + wire [ 64-1:0] radio0_m_ctrlport_req_time; + wire [ 1-1:0] radio0_m_ctrlport_resp_ack; + wire [ 2-1:0] radio0_m_ctrlport_resp_status; + wire [ 32-1:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio0_radio_time; + // x300_radio + wire [ 64-1:0] radio0_radio_rx_data; + wire [ 2-1:0] radio0_radio_rx_stb; + wire [ 2-1:0] radio0_radio_rx_running; + wire [ 64-1:0] radio0_radio_tx_data; + wire [ 2-1:0] radio0_radio_tx_stb; + wire [ 2-1:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(2), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + + .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time(radio0_radio_time), + .radio_rx_data(radio0_radio_rx_data), + .radio_rx_stb(radio0_radio_rx_stb), + .radio_rx_running(radio0_radio_rx_running), + .radio_tx_data(radio0_radio_tx_data), + .radio_tx_stb(radio0_radio_tx_stb), + .radio_tx_running(radio0_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // fifo0 + // ---------------------------------------------------- + wire fifo0_mem_clk; + wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; + wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; + wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid; + wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready; + wire [CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ; + wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ; + wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid; + wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; + + // axi_ram + wire [ 1-1:0] fifo0_axi_rst; + wire [ 4-1:0] fifo0_m_axi_awid; + wire [128-1:0] fifo0_m_axi_awaddr; + wire [ 32-1:0] fifo0_m_axi_awlen; + wire [ 12-1:0] fifo0_m_axi_awsize; + wire [ 8-1:0] fifo0_m_axi_awburst; + wire [ 4-1:0] fifo0_m_axi_awlock; + wire [ 16-1:0] fifo0_m_axi_awcache; + wire [ 12-1:0] fifo0_m_axi_awprot; + wire [ 16-1:0] fifo0_m_axi_awqos; + wire [ 16-1:0] fifo0_m_axi_awregion; + wire [ 4-1:0] fifo0_m_axi_awuser; + wire [ 4-1:0] fifo0_m_axi_awvalid; + wire [ 4-1:0] fifo0_m_axi_awready; + wire [256-1:0] fifo0_m_axi_wdata; + wire [ 32-1:0] fifo0_m_axi_wstrb; + wire [ 4-1:0] fifo0_m_axi_wlast; + wire [ 4-1:0] fifo0_m_axi_wuser; + wire [ 4-1:0] fifo0_m_axi_wvalid; + wire [ 4-1:0] fifo0_m_axi_wready; + wire [ 4-1:0] fifo0_m_axi_bid; + wire [ 8-1:0] fifo0_m_axi_bresp; + wire [ 4-1:0] fifo0_m_axi_buser; + wire [ 4-1:0] fifo0_m_axi_bvalid; + wire [ 4-1:0] fifo0_m_axi_bready; + wire [ 4-1:0] fifo0_m_axi_arid; + wire [128-1:0] fifo0_m_axi_araddr; + wire [ 32-1:0] fifo0_m_axi_arlen; + wire [ 12-1:0] fifo0_m_axi_arsize; + wire [ 8-1:0] fifo0_m_axi_arburst; + wire [ 4-1:0] fifo0_m_axi_arlock; + wire [ 16-1:0] fifo0_m_axi_arcache; + wire [ 12-1:0] fifo0_m_axi_arprot; + wire [ 16-1:0] fifo0_m_axi_arqos; + wire [ 16-1:0] fifo0_m_axi_arregion; + wire [ 4-1:0] fifo0_m_axi_aruser; + wire [ 4-1:0] fifo0_m_axi_arvalid; + wire [ 4-1:0] fifo0_m_axi_arready; + wire [ 4-1:0] fifo0_m_axi_rid; + wire [256-1:0] fifo0_m_axi_rdata; + wire [ 8-1:0] fifo0_m_axi_rresp; + wire [ 4-1:0] fifo0_m_axi_rlast; + wire [ 4-1:0] fifo0_m_axi_ruser; + wire [ 4-1:0] fifo0_m_axi_rvalid; + wire [ 4-1:0] fifo0_m_axi_rready; + + rfnoc_block_axi_ram_fifo #( + .THIS_PORTID(3), + .CHDR_W(CHDR_W), + .NUM_PORTS(4), + .MEM_DATA_W(64), + .MEM_ADDR_W(31), + .FIFO_ADDR_BASE({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), + .FIFO_ADDR_MASK({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), + .MEM_CLK_RATE(303819444), + .MTU(MTU) + ) b_fifo0_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .mem_clk(fifo0_mem_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + + .axi_rst(fifo0_axi_rst), + .m_axi_awid(fifo0_m_axi_awid), + .m_axi_awaddr(fifo0_m_axi_awaddr), + .m_axi_awlen(fifo0_m_axi_awlen), + .m_axi_awsize(fifo0_m_axi_awsize), + .m_axi_awburst(fifo0_m_axi_awburst), + .m_axi_awlock(fifo0_m_axi_awlock), + .m_axi_awcache(fifo0_m_axi_awcache), + .m_axi_awprot(fifo0_m_axi_awprot), + .m_axi_awqos(fifo0_m_axi_awqos), + .m_axi_awregion(fifo0_m_axi_awregion), + .m_axi_awuser(fifo0_m_axi_awuser), + .m_axi_awvalid(fifo0_m_axi_awvalid), + .m_axi_awready(fifo0_m_axi_awready), + .m_axi_wdata(fifo0_m_axi_wdata), + .m_axi_wstrb(fifo0_m_axi_wstrb), + .m_axi_wlast(fifo0_m_axi_wlast), + .m_axi_wuser(fifo0_m_axi_wuser), + .m_axi_wvalid(fifo0_m_axi_wvalid), + .m_axi_wready(fifo0_m_axi_wready), + .m_axi_bid(fifo0_m_axi_bid), + .m_axi_bresp(fifo0_m_axi_bresp), + .m_axi_buser(fifo0_m_axi_buser), + .m_axi_bvalid(fifo0_m_axi_bvalid), + .m_axi_bready(fifo0_m_axi_bready), + .m_axi_arid(fifo0_m_axi_arid), + .m_axi_araddr(fifo0_m_axi_araddr), + .m_axi_arlen(fifo0_m_axi_arlen), + .m_axi_arsize(fifo0_m_axi_arsize), + .m_axi_arburst(fifo0_m_axi_arburst), + .m_axi_arlock(fifo0_m_axi_arlock), + .m_axi_arcache(fifo0_m_axi_arcache), + .m_axi_arprot(fifo0_m_axi_arprot), + .m_axi_arqos(fifo0_m_axi_arqos), + .m_axi_arregion(fifo0_m_axi_arregion), + .m_axi_aruser(fifo0_m_axi_aruser), + .m_axi_arvalid(fifo0_m_axi_arvalid), + .m_axi_arready(fifo0_m_axi_arready), + .m_axi_rid(fifo0_m_axi_rid), + .m_axi_rdata(fifo0_m_axi_rdata), + .m_axi_rresp(fifo0_m_axi_rresp), + .m_axi_rlast(fifo0_m_axi_rlast), + .m_axi_ruser(fifo0_m_axi_ruser), + .m_axi_rvalid(fifo0_m_axi_rvalid), + .m_axi_rready(fifo0_m_axi_rready), + + .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_fifo0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_fifo0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_fifo0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_fifo0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // Static Router + // ---------------------------------------------------- + assign s_radio0_in_0_tdata = m_ep0_out0_tdata ; + assign s_radio0_in_0_tlast = m_ep0_out0_tlast ; + assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_radio0_in_0_tready; + + assign s_ep0_in0_tdata = m_radio0_out_0_tdata ; + assign s_ep0_in0_tlast = m_radio0_out_0_tlast ; + assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ep0_in0_tready; + + assign s_radio0_in_1_tdata = m_ep1_out0_tdata ; + assign s_radio0_in_1_tlast = m_ep1_out0_tlast ; + assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_radio0_in_1_tready; + + assign s_ep1_in0_tdata = m_radio0_out_1_tdata ; + assign s_ep1_in0_tlast = m_radio0_out_1_tlast ; + assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid; + assign m_radio0_out_1_tready = s_ep1_in0_tready; + + assign s_fifo0_in_0_tdata = m_ep4_out0_tdata ; + assign s_fifo0_in_0_tlast = m_ep4_out0_tlast ; + assign s_fifo0_in_0_tvalid = m_ep4_out0_tvalid; + assign m_ep4_out0_tready = s_fifo0_in_0_tready; + + assign s_ep4_in0_tdata = m_fifo0_out_0_tdata ; + assign s_ep4_in0_tlast = m_fifo0_out_0_tlast ; + assign s_ep4_in0_tvalid = m_fifo0_out_0_tvalid; + assign m_fifo0_out_0_tready = s_ep4_in0_tready; + + assign s_fifo0_in_1_tdata = m_ep5_out0_tdata ; + assign s_fifo0_in_1_tlast = m_ep5_out0_tlast ; + assign s_fifo0_in_1_tvalid = m_ep5_out0_tvalid; + assign m_ep5_out0_tready = s_fifo0_in_1_tready; + + assign s_ep5_in0_tdata = m_fifo0_out_1_tdata ; + assign s_ep5_in0_tlast = m_fifo0_out_1_tlast ; + assign s_ep5_in0_tvalid = m_fifo0_out_1_tvalid; + assign m_fifo0_out_1_tready = s_ep5_in0_tready; + + + // ---------------------------------------------------- + // Unused Ports + // ---------------------------------------------------- + assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}}; + assign s_fifo0_in_2_tlast = 1'b0; + assign s_fifo0_in_2_tvalid = 1'b0; + assign s_fifo0_in_3_tdata = {CHDR_W{1'b0}}; + assign s_fifo0_in_3_tlast = 1'b0; + assign s_fifo0_in_3_tvalid = 1'b0; + assign m_fifo0_out_2_tready = 1'b1; + assign m_fifo0_out_3_tready = 1'b1; + + // ---------------------------------------------------- + // Clock Domains + // ---------------------------------------------------- + assign radio0_radio_clk = radio_clk; + assign fifo0_mem_clk = dram_clk; + + + // ---------------------------------------------------- + // IO Port Connection + // ---------------------------------------------------- + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign fifo0_axi_rst = axi_rst; + assign m_axi_awid = fifo0_m_axi_awid; + assign m_axi_awaddr = fifo0_m_axi_awaddr; + assign m_axi_awlen = fifo0_m_axi_awlen; + assign m_axi_awsize = fifo0_m_axi_awsize; + assign m_axi_awburst = fifo0_m_axi_awburst; + assign m_axi_awlock = fifo0_m_axi_awlock; + assign m_axi_awcache = fifo0_m_axi_awcache; + assign m_axi_awprot = fifo0_m_axi_awprot; + assign m_axi_awqos = fifo0_m_axi_awqos; + assign m_axi_awregion = fifo0_m_axi_awregion; + assign m_axi_awuser = fifo0_m_axi_awuser; + assign m_axi_awvalid = fifo0_m_axi_awvalid; + assign fifo0_m_axi_awready = m_axi_awready; + assign m_axi_wdata = fifo0_m_axi_wdata; + assign m_axi_wstrb = fifo0_m_axi_wstrb; + assign m_axi_wlast = fifo0_m_axi_wlast; + assign m_axi_wuser = fifo0_m_axi_wuser; + assign m_axi_wvalid = fifo0_m_axi_wvalid; + assign fifo0_m_axi_wready = m_axi_wready; + assign fifo0_m_axi_bid = m_axi_bid; + assign fifo0_m_axi_bresp = m_axi_bresp; + assign fifo0_m_axi_buser = m_axi_buser; + assign fifo0_m_axi_bvalid = m_axi_bvalid; + assign m_axi_bready = fifo0_m_axi_bready; + assign m_axi_arid = fifo0_m_axi_arid; + assign m_axi_araddr = fifo0_m_axi_araddr; + assign m_axi_arlen = fifo0_m_axi_arlen; + assign m_axi_arsize = fifo0_m_axi_arsize; + assign m_axi_arburst = fifo0_m_axi_arburst; + assign m_axi_arlock = fifo0_m_axi_arlock; + assign m_axi_arcache = fifo0_m_axi_arcache; + assign m_axi_arprot = fifo0_m_axi_arprot; + assign m_axi_arqos = fifo0_m_axi_arqos; + assign m_axi_arregion = fifo0_m_axi_arregion; + assign m_axi_aruser = fifo0_m_axi_aruser; + assign m_axi_arvalid = fifo0_m_axi_arvalid; + assign fifo0_m_axi_arready = m_axi_arready; + assign fifo0_m_axi_rid = m_axi_rid; + assign fifo0_m_axi_rdata = m_axi_rdata; + assign fifo0_m_axi_rresp = m_axi_rresp; + assign fifo0_m_axi_rlast = m_axi_rlast; + assign fifo0_m_axi_ruser = m_axi_ruser; + assign fifo0_m_axi_rvalid = m_axi_rvalid; + assign m_axi_rready = fifo0_m_axi_rready; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time; + +endmodule diff --git a/fpga/usrp3/top/n3xx/n300_bist_image_core.yml b/fpga/usrp3/top/n3xx/n300_bist_image_core.yml new file mode 100644 index 000000000..446c0ae6b --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_bist_image_core.yml @@ -0,0 +1,87 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers +license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +version: 1.0 # File version +rfnoc_version: 1.0 # RFNoC protocol version +chdr_width: 64 # Bit width of the CHDR bus for this image +device: 'n300' +default_target: 'N300_AA' + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep1: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + # We call the next endpoints 4 and 5 to keep them consistent with the + # N310 version of this file + ep4: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep5: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + radio0: + block_desc: 'radio_2x64.yml' + fifo0: + block_desc: 'axi_ram_fifo_4x64.yml' + parameters: + # These parameters match the memory interface on the N3XX + NUM_PORTS: 4 + MEM_DATA_W: 64 + MEM_ADDR_W: 31 + FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}" + FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}" + MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + # ep0 to radio0(0) - RF0 TX + - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } + # radio0(0) to ep0 - RF0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } + # ep1 to radio0(1) - RF1 TX + - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 } + # radio0(1) to ep1 - RF1 RX + - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } + # ep4 to fifo0(0) + - { srcblk: ep4, srcport: out0, dstblk: fifo0, dstport: in_0 } + - { srcblk: fifo0, srcport: out_0, dstblk: ep4, dstport: in0 } + # ep5 to fifo0(1) + - { srcblk: ep5, srcport: out0, dstblk: fifo0, dstport: in_1 } + - { srcblk: fifo0, srcport: out_1, dstblk: ep5, dstport: in0 } + # BSP Connections + - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem } diff --git a/fpga/usrp3/top/n3xx/n300_bist_static_router.hex b/fpga/usrp3/top/n3xx/n300_bist_static_router.hex new file mode 100644 index 000000000..99c3acfdf --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_bist_static_router.hex @@ -0,0 +1,9 @@ +00000008 +00400140 +01400040 +00800141 +01410080 +00c00180 +018000c0 +01000181 +01810100 diff --git a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v new file mode 100644 index 000000000..064dcf16b --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v @@ -0,0 +1,652 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Module: rfnoc_image_core (for n300) +// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) +// Re-running that tool will overwrite this file! +// File generated on: 2019-11-08T15:58:12.572410 +// Source: ./n3xx/n300_rfnoc_image_core.yml +// Source SHA256: 0137aa82c54cb7f7e539f2b09d75ec9c2b5d0c97479431953ab78fc8c56b7201 + +module rfnoc_image_core #( + parameter [15:0] PROTOVER = {8'd1, 8'd0} +)( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio_clk, + input wire dram_clk, + // Basic + input wire [15:0] device_id, +//// IO ports ////////////////////////////////// +// ctrlport_radio0 + output wire [ 1-1:0] m_ctrlport_radio0_req_wr, + output wire [ 1-1:0] m_ctrlport_radio0_req_rd, + output wire [ 20-1:0] m_ctrlport_radio0_req_addr, + output wire [ 32-1:0] m_ctrlport_radio0_req_data, + output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio0_req_time, + input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio0_resp_status, + input wire [ 32-1:0] m_ctrlport_radio0_resp_data, +// time_keeper + input wire [ 64-1:0] radio_time, +// x300_radio0 + input wire [ 64-1:0] radio_rx_data_radio0, + input wire [ 2-1:0] radio_rx_stb_radio0, + output wire [ 2-1:0] radio_rx_running_radio0, + output wire [ 64-1:0] radio_tx_data_radio0, + input wire [ 2-1:0] radio_tx_stb_radio0, + output wire [ 2-1:0] radio_tx_running_radio0, +// dram + input wire [ 1-1:0] axi_rst, + output wire [ 4-1:0] m_axi_awid, + output wire [128-1:0] m_axi_awaddr, + output wire [ 32-1:0] m_axi_awlen, + output wire [ 12-1:0] m_axi_awsize, + output wire [ 8-1:0] m_axi_awburst, + output wire [ 4-1:0] m_axi_awlock, + output wire [ 16-1:0] m_axi_awcache, + output wire [ 12-1:0] m_axi_awprot, + output wire [ 16-1:0] m_axi_awqos, + output wire [ 16-1:0] m_axi_awregion, + output wire [ 4-1:0] m_axi_awuser, + output wire [ 4-1:0] m_axi_awvalid, + input wire [ 4-1:0] m_axi_awready, + output wire [256-1:0] m_axi_wdata, + output wire [ 32-1:0] m_axi_wstrb, + output wire [ 4-1:0] m_axi_wlast, + output wire [ 4-1:0] m_axi_wuser, + output wire [ 4-1:0] m_axi_wvalid, + input wire [ 4-1:0] m_axi_wready, + input wire [ 4-1:0] m_axi_bid, + input wire [ 8-1:0] m_axi_bresp, + input wire [ 4-1:0] m_axi_buser, + input wire [ 4-1:0] m_axi_bvalid, + output wire [ 4-1:0] m_axi_bready, + output wire [ 4-1:0] m_axi_arid, + output wire [128-1:0] m_axi_araddr, + output wire [ 32-1:0] m_axi_arlen, + output wire [ 12-1:0] m_axi_arsize, + output wire [ 8-1:0] m_axi_arburst, + output wire [ 4-1:0] m_axi_arlock, + output wire [ 16-1:0] m_axi_arcache, + output wire [ 12-1:0] m_axi_arprot, + output wire [ 16-1:0] m_axi_arqos, + output wire [ 16-1:0] m_axi_arregion, + output wire [ 4-1:0] m_axi_aruser, + output wire [ 4-1:0] m_axi_arvalid, + input wire [ 4-1:0] m_axi_arready, + input wire [ 4-1:0] m_axi_rid, + input wire [256-1:0] m_axi_rdata, + input wire [ 8-1:0] m_axi_rresp, + input wire [ 4-1:0] m_axi_rlast, + input wire [ 4-1:0] m_axi_ruser, + input wire [ 4-1:0] m_axi_rvalid, + output wire [ 4-1:0] m_axi_rready, + // Transport 0 (eth0 1G) + input wire [64-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [64-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1 10G) + input wire [64-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [64-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma dma) + input wire [64-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [64-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam CHDR_W = 64; + localparam MTU = 10; + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + // ---------------------------------------------------- + // CHDR Crossbar + // ---------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [CHDR_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [CHDR_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + + chdr_crossbar_nxn #( + .CHDR_W (CHDR_W), + .NPORTS (5), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (3), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_xb_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), + .s_axis_tlast ({ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tvalid ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), + .m_axis_tlast ({xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tvalid ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + // ---------------------------------------------------- + // Stream Endpoints + // ---------------------------------------------------- + + wire [CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; + wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep0_tdata ), + .s_axis_chdr_tlast (xb_to_ep0_tlast ), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), + .s_axis_chdr_tready (xb_to_ep0_tready ), + .m_axis_chdr_tdata (ep0_to_xb_tdata ), + .m_axis_chdr_tlast (ep0_to_xb_tlast ), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), + .m_axis_chdr_tready (ep0_to_xb_tready ), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; + wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep1_tdata ), + .s_axis_chdr_tlast (xb_to_ep1_tlast ), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), + .s_axis_chdr_tready (xb_to_ep1_tready ), + .m_axis_chdr_tdata (ep1_to_xb_tdata ), + .m_axis_chdr_tlast (ep1_to_xb_tlast ), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), + .m_axis_chdr_tready (ep1_to_xb_tready ), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + + + // ---------------------------------------------------- + // Control Crossbar + // ---------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; + wire m_core_ctrl_tlast , s_core_ctrl_tlast ; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_duc0_ctrl_tdata , s_duc0_ctrl_tdata ; + wire m_duc0_ctrl_tlast , s_duc0_ctrl_tlast ; + wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; + wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; + wire [31:0] m_ddc0_ctrl_tdata , s_ddc0_ctrl_tdata ; + wire m_ddc0_ctrl_tlast , s_ddc0_ctrl_tlast ; + wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; + wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; + wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (5), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + // ---------------------------------------------------- + // RFNoC Core Kernel + // ---------------------------------------------------- + wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'h1300), + .DEVICE_FAMILY ("7SERIES"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (3), + .NUM_STREAM_ENDPOINTS(2), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (3), + .NUM_EDGES (8), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata ), + .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata ), + .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + // ---------------------------------------------------- + // Blocks + // ---------------------------------------------------- + + // ---------------------------------------------------- + // duc0 + // ---------------------------------------------------- + wire duc0_ce_clk; + wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; + wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; + wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid; + wire s_duc0_in_1_tready, s_duc0_in_0_tready; + wire [CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ; + wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ; + wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; + wire m_duc0_out_1_tready, m_duc0_out_0_tready; + + + rfnoc_block_duc #( + .THIS_PORTID(2), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_INTERP(255), + .MTU(MTU) + ) b_duc0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(duc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + + + .s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_duc0_in_1_tready, s_duc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc0_out_1_tdata , m_duc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_duc0_out_1_tready, m_duc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_duc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_duc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_duc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_duc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // ddc0 + // ---------------------------------------------------- + wire ddc0_ce_clk; + wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; + wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; + wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; + wire s_ddc0_in_1_tready, s_ddc0_in_0_tready; + wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; + wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; + wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; + wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; + + + rfnoc_block_ddc #( + .THIS_PORTID(3), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_DECIM(255), + .MTU(MTU) + ) b_ddc0_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(ddc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + + + .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_ddc0_in_1_tready, s_ddc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc0_out_1_tdata , m_ddc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_ddc0_out_1_tready, m_ddc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_ddc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_ddc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_ddc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_ddc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio0 + // ---------------------------------------------------- + wire radio0_radio_clk; + wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_1_tready, m_radio0_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio0_m_ctrlport_req_wr; + wire [ 1-1:0] radio0_m_ctrlport_req_rd; + wire [ 20-1:0] radio0_m_ctrlport_req_addr; + wire [ 32-1:0] radio0_m_ctrlport_req_data; + wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio0_m_ctrlport_req_has_time; + wire [ 64-1:0] radio0_m_ctrlport_req_time; + wire [ 1-1:0] radio0_m_ctrlport_resp_ack; + wire [ 2-1:0] radio0_m_ctrlport_resp_status; + wire [ 32-1:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio0_radio_time; + // x300_radio + wire [ 64-1:0] radio0_radio_rx_data; + wire [ 2-1:0] radio0_radio_rx_stb; + wire [ 2-1:0] radio0_radio_rx_running; + wire [ 64-1:0] radio0_radio_tx_data; + wire [ 2-1:0] radio0_radio_tx_stb; + wire [ 2-1:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(4), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio0_2 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + + .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time(radio0_radio_time), + .radio_rx_data(radio0_radio_rx_data), + .radio_rx_stb(radio0_radio_rx_stb), + .radio_rx_running(radio0_radio_rx_running), + .radio_tx_data(radio0_radio_tx_data), + .radio_tx_stb(radio0_radio_tx_stb), + .radio_tx_running(radio0_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // Static Router + // ---------------------------------------------------- + assign s_duc0_in_0_tdata = m_ep0_out0_tdata ; + assign s_duc0_in_0_tlast = m_ep0_out0_tlast ; + assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_duc0_in_0_tready; + + assign s_radio0_in_0_tdata = m_duc0_out_0_tdata ; + assign s_radio0_in_0_tlast = m_duc0_out_0_tlast ; + assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid; + assign m_duc0_out_0_tready = s_radio0_in_0_tready; + + assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata ; + assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast ; + assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ddc0_in_0_tready; + + assign s_ep0_in0_tdata = m_ddc0_out_0_tdata ; + assign s_ep0_in0_tlast = m_ddc0_out_0_tlast ; + assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid; + assign m_ddc0_out_0_tready = s_ep0_in0_tready; + + assign s_duc0_in_1_tdata = m_ep1_out0_tdata ; + assign s_duc0_in_1_tlast = m_ep1_out0_tlast ; + assign s_duc0_in_1_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_duc0_in_1_tready; + + assign s_radio0_in_1_tdata = m_duc0_out_1_tdata ; + assign s_radio0_in_1_tlast = m_duc0_out_1_tlast ; + assign s_radio0_in_1_tvalid = m_duc0_out_1_tvalid; + assign m_duc0_out_1_tready = s_radio0_in_1_tready; + + assign s_ddc0_in_1_tdata = m_radio0_out_1_tdata ; + assign s_ddc0_in_1_tlast = m_radio0_out_1_tlast ; + assign s_ddc0_in_1_tvalid = m_radio0_out_1_tvalid; + assign m_radio0_out_1_tready = s_ddc0_in_1_tready; + + assign s_ep1_in0_tdata = m_ddc0_out_1_tdata ; + assign s_ep1_in0_tlast = m_ddc0_out_1_tlast ; + assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid; + assign m_ddc0_out_1_tready = s_ep1_in0_tready; + + + // ---------------------------------------------------- + // Unused Ports + // ---------------------------------------------------- + + // ---------------------------------------------------- + // Clock Domains + // ---------------------------------------------------- + assign radio0_radio_clk = radio_clk; + assign ddc0_ce_clk = rfnoc_chdr_clk; + assign duc0_ce_clk = rfnoc_chdr_clk; + + + // ---------------------------------------------------- + // IO Port Connection + // ---------------------------------------------------- + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time; + +endmodule diff --git a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml new file mode 100644 index 000000000..54df51725 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml @@ -0,0 +1,78 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers +license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +version: 1.0 # File version +rfnoc_version: 1.0 # RFNoC protocol version +chdr_width: 64 # Bit width of the CHDR bus for this image +device: 'n300' +default_target: 'N300_HG' + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep1: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + duc0: # NoC block name + block_desc: 'duc.yml' # Block device descriptor file + parameters: # Block HDL parameters + NUM_PORTS: 2 + ddc0: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 2 + radio0: + block_desc: 'radio_2x64.yml' + #fifo0: + #block_desc: 'axi_ram_fifo_4x64.yml' + #parameters: + ## These parameters match the memory interface on the N3XX + #NUM_PORTS: 4 + #MEM_DATA_W: 64 + #MEM_ADDR_W: 31 + #FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}" + #FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}" + #MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 } + - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } + - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 } + - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 } + - { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 } + - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 } + - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 } + - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0, dstport: ce } diff --git a/fpga/usrp3/top/n3xx/n300_static_router.hex b/fpga/usrp3/top/n3xx/n300_static_router.hex new file mode 100644 index 000000000..6e8701d3a --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_static_router.hex @@ -0,0 +1,9 @@ +00000008 +004000c0 +00c00140 +01400100 +01000040 +008000c1 +00c10141 +01410101 +01010080 diff --git a/fpga/usrp3/top/n3xx/n310_10ge.xdc b/fpga/usrp3/top/n3xx/n310_10ge.xdc new file mode 100644 index 000000000..a55fc1298 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_10ge.xdc @@ -0,0 +1,22 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +# No need for any asynchronous clock groups between bus_clk and the recovered clocks, +# because bus_clk already has a blanket asynchronous constraint from the top level XDC. + +# Remove analysis between the xge_clk and the recovered clocks from the MGT PHYs, +# since they cannot be related to one another with any known phase or period. +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/RXOUTCLK}] -group [get_clocks xge_clk] +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/TXOUTCLK}] -group [get_clocks xge_clk] + +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/RXOUTCLK}] -group [get_clocks xge_clk] +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/TXOUTCLK}] -group [get_clocks xge_clk] + +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *PRE}] +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *CLR}] + +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *PRE}] +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *CLR}] diff --git a/fpga/usrp3/top/n3xx/n310_1ge.xdc b/fpga/usrp3/top/n3xx/n310_1ge.xdc new file mode 100644 index 000000000..1f38f56b6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_1ge.xdc @@ -0,0 +1,15 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +# No need for any asynchronous clock groups between clk100 and the recovered clocks, +# because clk100 already has a blanket asynchronous constraint from the top level XDC. +set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks net_clk] +set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks -of_objects [get_pins sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige_phy_i/*/core_clocking_i/mmcm_*/CLKOUT0]] +set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks -of_objects [get_pins sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige_phy_i/*/core_clocking_i/mmcm_*/CLKOUT1]] + +set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige_phy_i/*reset_sync*/PRE}] +set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige_phy_i/*/pma_reset_pipe_reg*/PRE}] +set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige_phy_i/*/pma_reset_pipe*[0]/D}] diff --git a/fpga/usrp3/top/n3xx/n310_aurora.xdc b/fpga/usrp3/top/n3xx/n310_aurora.xdc new file mode 100644 index 000000000..1a76687e6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_aurora.xdc @@ -0,0 +1,15 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +create_generated_clock -name aurora_init_clk [get_pins -hierarchical -filter {NAME =~ "*aurora_clk_gen_i/dclk_divide_by_2_buf/O"}] + +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks aurora_init_clk] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/aurora_phy*/aurora_64b66b_pcs_pma*/*/gt_reset_sync/stg1_*_cdc_to_reg/D"}] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*npio*/aurora_phy*/aurora_64b66b_pcs_pma*/*/gt_reset_sync/stg1_*_cdc_to_reg/D"}] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/aurora_phy*/aurora_64b66b_pcs_pma*/*/gt_reset_sync/stg1_*_cdc_to_reg/D"}] diff --git a/fpga/usrp3/top/n3xx/n310_bist_image_core.v b/fpga/usrp3/top/n3xx/n310_bist_image_core.v new file mode 100644 index 000000000..64989fb3f --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_bist_image_core.v @@ -0,0 +1,1169 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Module: rfnoc_image_core (for n310) +// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) +// Re-running that tool will overwrite this file! +// File generated on: 2019-11-08T15:58:14.371732 +// Source: ./n3xx/n310_bist_image_core.yml +// Source SHA256: 1a9ffb97d9678e700ad2aa172d206b6be9af30c7c0b014c21007d1de028a59d4 + +module rfnoc_image_core #( + parameter [15:0] PROTOVER = {8'd1, 8'd0} +)( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio_clk, + input wire dram_clk, + // Basic + input wire [15:0] device_id, +//// IO ports ////////////////////////////////// +// ctrlport_radio0 + output wire [ 1-1:0] m_ctrlport_radio0_req_wr, + output wire [ 1-1:0] m_ctrlport_radio0_req_rd, + output wire [ 20-1:0] m_ctrlport_radio0_req_addr, + output wire [ 32-1:0] m_ctrlport_radio0_req_data, + output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio0_req_time, + input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio0_resp_status, + input wire [ 32-1:0] m_ctrlport_radio0_resp_data, +// ctrlport_radio1 + output wire [ 1-1:0] m_ctrlport_radio1_req_wr, + output wire [ 1-1:0] m_ctrlport_radio1_req_rd, + output wire [ 20-1:0] m_ctrlport_radio1_req_addr, + output wire [ 32-1:0] m_ctrlport_radio1_req_data, + output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio1_req_time, + input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio1_resp_status, + input wire [ 32-1:0] m_ctrlport_radio1_resp_data, +// time_keeper + input wire [ 64-1:0] radio_time, +// x300_radio0 + input wire [ 64-1:0] radio_rx_data_radio0, + input wire [ 2-1:0] radio_rx_stb_radio0, + output wire [ 2-1:0] radio_rx_running_radio0, + output wire [ 64-1:0] radio_tx_data_radio0, + input wire [ 2-1:0] radio_tx_stb_radio0, + output wire [ 2-1:0] radio_tx_running_radio0, +// x300_radio1 + input wire [ 64-1:0] radio_rx_data_radio1, + input wire [ 2-1:0] radio_rx_stb_radio1, + output wire [ 2-1:0] radio_rx_running_radio1, + output wire [ 64-1:0] radio_tx_data_radio1, + input wire [ 2-1:0] radio_tx_stb_radio1, + output wire [ 2-1:0] radio_tx_running_radio1, +// dram + input wire [ 1-1:0] axi_rst, + output wire [ 4-1:0] m_axi_awid, + output wire [128-1:0] m_axi_awaddr, + output wire [ 32-1:0] m_axi_awlen, + output wire [ 12-1:0] m_axi_awsize, + output wire [ 8-1:0] m_axi_awburst, + output wire [ 4-1:0] m_axi_awlock, + output wire [ 16-1:0] m_axi_awcache, + output wire [ 12-1:0] m_axi_awprot, + output wire [ 16-1:0] m_axi_awqos, + output wire [ 16-1:0] m_axi_awregion, + output wire [ 4-1:0] m_axi_awuser, + output wire [ 4-1:0] m_axi_awvalid, + input wire [ 4-1:0] m_axi_awready, + output wire [256-1:0] m_axi_wdata, + output wire [ 32-1:0] m_axi_wstrb, + output wire [ 4-1:0] m_axi_wlast, + output wire [ 4-1:0] m_axi_wuser, + output wire [ 4-1:0] m_axi_wvalid, + input wire [ 4-1:0] m_axi_wready, + input wire [ 4-1:0] m_axi_bid, + input wire [ 8-1:0] m_axi_bresp, + input wire [ 4-1:0] m_axi_buser, + input wire [ 4-1:0] m_axi_bvalid, + output wire [ 4-1:0] m_axi_bready, + output wire [ 4-1:0] m_axi_arid, + output wire [128-1:0] m_axi_araddr, + output wire [ 32-1:0] m_axi_arlen, + output wire [ 12-1:0] m_axi_arsize, + output wire [ 8-1:0] m_axi_arburst, + output wire [ 4-1:0] m_axi_arlock, + output wire [ 16-1:0] m_axi_arcache, + output wire [ 12-1:0] m_axi_arprot, + output wire [ 16-1:0] m_axi_arqos, + output wire [ 16-1:0] m_axi_arregion, + output wire [ 4-1:0] m_axi_aruser, + output wire [ 4-1:0] m_axi_arvalid, + input wire [ 4-1:0] m_axi_arready, + input wire [ 4-1:0] m_axi_rid, + input wire [256-1:0] m_axi_rdata, + input wire [ 8-1:0] m_axi_rresp, + input wire [ 4-1:0] m_axi_rlast, + input wire [ 4-1:0] m_axi_ruser, + input wire [ 4-1:0] m_axi_rvalid, + output wire [ 4-1:0] m_axi_rready, + // Transport 0 (eth0 1G) + input wire [64-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [64-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1 10G) + input wire [64-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [64-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma dma) + input wire [64-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [64-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam CHDR_W = 64; + localparam MTU = 10; + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + // ---------------------------------------------------- + // CHDR Crossbar + // ---------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [CHDR_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [CHDR_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep2_tdata ; + wire xb_to_ep2_tlast ; + wire xb_to_ep2_tvalid; + wire xb_to_ep2_tready; + wire [CHDR_W-1:0] ep2_to_xb_tdata ; + wire ep2_to_xb_tlast ; + wire ep2_to_xb_tvalid; + wire ep2_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep3_tdata ; + wire xb_to_ep3_tlast ; + wire xb_to_ep3_tvalid; + wire xb_to_ep3_tready; + wire [CHDR_W-1:0] ep3_to_xb_tdata ; + wire ep3_to_xb_tlast ; + wire ep3_to_xb_tvalid; + wire ep3_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep4_tdata ; + wire xb_to_ep4_tlast ; + wire xb_to_ep4_tvalid; + wire xb_to_ep4_tready; + wire [CHDR_W-1:0] ep4_to_xb_tdata ; + wire ep4_to_xb_tlast ; + wire ep4_to_xb_tvalid; + wire ep4_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep5_tdata ; + wire xb_to_ep5_tlast ; + wire xb_to_ep5_tvalid; + wire xb_to_ep5_tready; + wire [CHDR_W-1:0] ep5_to_xb_tdata ; + wire ep5_to_xb_tlast ; + wire ep5_to_xb_tvalid; + wire ep5_to_xb_tready; + + chdr_crossbar_nxn #( + .CHDR_W (CHDR_W), + .NPORTS (9), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (3), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_xb_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep5_to_xb_tdata, ep4_to_xb_tdata, ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), + .s_axis_tlast ({ep5_to_xb_tlast, ep4_to_xb_tlast, ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tvalid ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), + .m_axis_tlast ({xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tvalid ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + // ---------------------------------------------------- + // Stream Endpoints + // ---------------------------------------------------- + + wire [CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; + wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep0_tdata ), + .s_axis_chdr_tlast (xb_to_ep0_tlast ), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), + .s_axis_chdr_tready (xb_to_ep0_tready ), + .m_axis_chdr_tdata (ep0_to_xb_tdata ), + .m_axis_chdr_tlast (ep0_to_xb_tlast ), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), + .m_axis_chdr_tready (ep0_to_xb_tready ), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; + wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep1_tdata ), + .s_axis_chdr_tlast (xb_to_ep1_tlast ), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), + .s_axis_chdr_tready (xb_to_ep1_tready ), + .m_axis_chdr_tdata (ep1_to_xb_tdata ), + .m_axis_chdr_tlast (ep1_to_xb_tlast ), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), + .m_axis_chdr_tready (ep1_to_xb_tready ), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep2_out0_tdata; + wire m_ep2_out0_tlast; + wire m_ep2_out0_tvalid; + wire m_ep2_out0_tready; + wire [CHDR_W-1:0] s_ep2_in0_tdata; + wire s_ep2_in0_tlast; + wire s_ep2_in0_tvalid; + wire s_ep2_in0_tready; + wire [31:0] m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ; + wire m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ; + wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; + wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (2), + .CTRL_XBAR_PORT (3), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep2_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep2_tdata ), + .s_axis_chdr_tlast (xb_to_ep2_tlast ), + .s_axis_chdr_tvalid (xb_to_ep2_tvalid ), + .s_axis_chdr_tready (xb_to_ep2_tready ), + .m_axis_chdr_tdata (ep2_to_xb_tdata ), + .m_axis_chdr_tlast (ep2_to_xb_tlast ), + .m_axis_chdr_tvalid (ep2_to_xb_tvalid ), + .m_axis_chdr_tready (ep2_to_xb_tready ), + .s_axis_data_tdata ({s_ep2_in0_tdata}), + .s_axis_data_tlast ({s_ep2_in0_tlast}), + .s_axis_data_tvalid ({s_ep2_in0_tvalid}), + .s_axis_data_tready ({s_ep2_in0_tready}), + .m_axis_data_tdata ({m_ep2_out0_tdata}), + .m_axis_data_tlast ({m_ep2_out0_tlast}), + .m_axis_data_tvalid ({m_ep2_out0_tvalid}), + .m_axis_data_tready ({m_ep2_out0_tready}), + .s_axis_ctrl_tdata (s_ep2_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep2_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep2_ctrl_tready), + .m_axis_ctrl_tdata (m_ep2_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep2_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep2_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep3_out0_tdata; + wire m_ep3_out0_tlast; + wire m_ep3_out0_tvalid; + wire m_ep3_out0_tready; + wire [CHDR_W-1:0] s_ep3_in0_tdata; + wire s_ep3_in0_tlast; + wire s_ep3_in0_tvalid; + wire s_ep3_in0_tready; + wire [31:0] m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ; + wire m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ; + wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; + wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (3), + .CTRL_XBAR_PORT (4), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep3_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep3_tdata ), + .s_axis_chdr_tlast (xb_to_ep3_tlast ), + .s_axis_chdr_tvalid (xb_to_ep3_tvalid ), + .s_axis_chdr_tready (xb_to_ep3_tready ), + .m_axis_chdr_tdata (ep3_to_xb_tdata ), + .m_axis_chdr_tlast (ep3_to_xb_tlast ), + .m_axis_chdr_tvalid (ep3_to_xb_tvalid ), + .m_axis_chdr_tready (ep3_to_xb_tready ), + .s_axis_data_tdata ({s_ep3_in0_tdata}), + .s_axis_data_tlast ({s_ep3_in0_tlast}), + .s_axis_data_tvalid ({s_ep3_in0_tvalid}), + .s_axis_data_tready ({s_ep3_in0_tready}), + .m_axis_data_tdata ({m_ep3_out0_tdata}), + .m_axis_data_tlast ({m_ep3_out0_tlast}), + .m_axis_data_tvalid ({m_ep3_out0_tvalid}), + .m_axis_data_tready ({m_ep3_out0_tready}), + .s_axis_ctrl_tdata (s_ep3_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep3_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep3_ctrl_tready), + .m_axis_ctrl_tdata (m_ep3_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep3_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep3_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep4_out0_tdata; + wire m_ep4_out0_tlast; + wire m_ep4_out0_tvalid; + wire m_ep4_out0_tready; + wire [CHDR_W-1:0] s_ep4_in0_tdata; + wire s_ep4_in0_tlast; + wire s_ep4_in0_tvalid; + wire s_ep4_in0_tready; + wire [31:0] m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ; + wire m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ; + wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; + wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (4), + .CTRL_XBAR_PORT (5), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep4_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep4_tdata ), + .s_axis_chdr_tlast (xb_to_ep4_tlast ), + .s_axis_chdr_tvalid (xb_to_ep4_tvalid ), + .s_axis_chdr_tready (xb_to_ep4_tready ), + .m_axis_chdr_tdata (ep4_to_xb_tdata ), + .m_axis_chdr_tlast (ep4_to_xb_tlast ), + .m_axis_chdr_tvalid (ep4_to_xb_tvalid ), + .m_axis_chdr_tready (ep4_to_xb_tready ), + .s_axis_data_tdata ({s_ep4_in0_tdata}), + .s_axis_data_tlast ({s_ep4_in0_tlast}), + .s_axis_data_tvalid ({s_ep4_in0_tvalid}), + .s_axis_data_tready ({s_ep4_in0_tready}), + .m_axis_data_tdata ({m_ep4_out0_tdata}), + .m_axis_data_tlast ({m_ep4_out0_tlast}), + .m_axis_data_tvalid ({m_ep4_out0_tvalid}), + .m_axis_data_tready ({m_ep4_out0_tready}), + .s_axis_ctrl_tdata (s_ep4_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep4_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep4_ctrl_tready), + .m_axis_ctrl_tdata (m_ep4_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep4_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep4_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep5_out0_tdata; + wire m_ep5_out0_tlast; + wire m_ep5_out0_tvalid; + wire m_ep5_out0_tready; + wire [CHDR_W-1:0] s_ep5_in0_tdata; + wire s_ep5_in0_tlast; + wire s_ep5_in0_tvalid; + wire s_ep5_in0_tready; + wire [31:0] m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ; + wire m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ; + wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; + wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (5), + .CTRL_XBAR_PORT (6), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep5_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep5_tdata ), + .s_axis_chdr_tlast (xb_to_ep5_tlast ), + .s_axis_chdr_tvalid (xb_to_ep5_tvalid ), + .s_axis_chdr_tready (xb_to_ep5_tready ), + .m_axis_chdr_tdata (ep5_to_xb_tdata ), + .m_axis_chdr_tlast (ep5_to_xb_tlast ), + .m_axis_chdr_tvalid (ep5_to_xb_tvalid ), + .m_axis_chdr_tready (ep5_to_xb_tready ), + .s_axis_data_tdata ({s_ep5_in0_tdata}), + .s_axis_data_tlast ({s_ep5_in0_tlast}), + .s_axis_data_tvalid ({s_ep5_in0_tvalid}), + .s_axis_data_tready ({s_ep5_in0_tready}), + .m_axis_data_tdata ({m_ep5_out0_tdata}), + .m_axis_data_tlast ({m_ep5_out0_tlast}), + .m_axis_data_tvalid ({m_ep5_out0_tvalid}), + .m_axis_data_tready ({m_ep5_out0_tready}), + .s_axis_ctrl_tdata (s_ep5_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep5_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep5_ctrl_tready), + .m_axis_ctrl_tdata (m_ep5_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep5_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep5_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + + + // ---------------------------------------------------- + // Control Crossbar + // ---------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; + wire m_core_ctrl_tlast , s_core_ctrl_tlast ; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; + wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ; + wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + wire [31:0] m_fifo0_ctrl_tdata , s_fifo0_ctrl_tdata ; + wire m_fifo0_ctrl_tlast , s_fifo0_ctrl_tlast ; + wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid; + wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (5), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_fifo0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_fifo0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_fifo0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_fifo0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_fifo0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_fifo0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_fifo0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_fifo0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + // ---------------------------------------------------- + // RFNoC Core Kernel + // ---------------------------------------------------- + wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'h1300), + .DEVICE_FAMILY ("7SERIES"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (3), + .NUM_STREAM_ENDPOINTS(6), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (3), + .NUM_EDGES (12), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata ), + .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata ), + .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + // ---------------------------------------------------- + // Blocks + // ---------------------------------------------------- + + // ---------------------------------------------------- + // radio0 + // ---------------------------------------------------- + wire radio0_radio_clk; + wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_1_tready, m_radio0_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio0_m_ctrlport_req_wr; + wire [ 1-1:0] radio0_m_ctrlport_req_rd; + wire [ 20-1:0] radio0_m_ctrlport_req_addr; + wire [ 32-1:0] radio0_m_ctrlport_req_data; + wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio0_m_ctrlport_req_has_time; + wire [ 64-1:0] radio0_m_ctrlport_req_time; + wire [ 1-1:0] radio0_m_ctrlport_resp_ack; + wire [ 2-1:0] radio0_m_ctrlport_resp_status; + wire [ 32-1:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio0_radio_time; + // x300_radio + wire [ 64-1:0] radio0_radio_rx_data; + wire [ 2-1:0] radio0_radio_rx_stb; + wire [ 2-1:0] radio0_radio_rx_running; + wire [ 64-1:0] radio0_radio_tx_data; + wire [ 2-1:0] radio0_radio_tx_stb; + wire [ 2-1:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(2), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + + .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time(radio0_radio_time), + .radio_rx_data(radio0_radio_rx_data), + .radio_rx_stb(radio0_radio_rx_stb), + .radio_rx_running(radio0_radio_rx_running), + .radio_tx_data(radio0_radio_tx_data), + .radio_tx_stb(radio0_radio_tx_stb), + .radio_tx_running(radio0_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio1 + // ---------------------------------------------------- + wire radio1_radio_clk; + wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; + wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; + wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; + wire s_radio1_in_1_tready, s_radio1_in_0_tready; + wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; + wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; + wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; + wire m_radio1_out_1_tready, m_radio1_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio1_m_ctrlport_req_wr; + wire [ 1-1:0] radio1_m_ctrlport_req_rd; + wire [ 20-1:0] radio1_m_ctrlport_req_addr; + wire [ 32-1:0] radio1_m_ctrlport_req_data; + wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio1_m_ctrlport_req_has_time; + wire [ 64-1:0] radio1_m_ctrlport_req_time; + wire [ 1-1:0] radio1_m_ctrlport_resp_ack; + wire [ 2-1:0] radio1_m_ctrlport_resp_status; + wire [ 32-1:0] radio1_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio1_radio_time; + // x300_radio + wire [ 64-1:0] radio1_radio_rx_data; + wire [ 2-1:0] radio1_radio_rx_stb; + wire [ 2-1:0] radio1_radio_rx_running; + wire [ 64-1:0] radio1_radio_tx_data; + wire [ 2-1:0] radio1_radio_tx_stb; + wire [ 2-1:0] radio1_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(3), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio1_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + + .m_ctrlport_req_wr(radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio1_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), + .radio_time(radio1_radio_time), + .radio_rx_data(radio1_radio_rx_data), + .radio_rx_stb(radio1_radio_rx_stb), + .radio_rx_running(radio1_radio_rx_running), + .radio_tx_data(radio1_radio_tx_data), + .radio_tx_stb(radio1_radio_tx_stb), + .radio_tx_running(radio1_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio1_in_1_tready, s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio1_out_1_tready, m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // fifo0 + // ---------------------------------------------------- + wire fifo0_mem_clk; + wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; + wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; + wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid; + wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready; + wire [CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ; + wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ; + wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid; + wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; + + // axi_ram + wire [ 1-1:0] fifo0_axi_rst; + wire [ 4-1:0] fifo0_m_axi_awid; + wire [128-1:0] fifo0_m_axi_awaddr; + wire [ 32-1:0] fifo0_m_axi_awlen; + wire [ 12-1:0] fifo0_m_axi_awsize; + wire [ 8-1:0] fifo0_m_axi_awburst; + wire [ 4-1:0] fifo0_m_axi_awlock; + wire [ 16-1:0] fifo0_m_axi_awcache; + wire [ 12-1:0] fifo0_m_axi_awprot; + wire [ 16-1:0] fifo0_m_axi_awqos; + wire [ 16-1:0] fifo0_m_axi_awregion; + wire [ 4-1:0] fifo0_m_axi_awuser; + wire [ 4-1:0] fifo0_m_axi_awvalid; + wire [ 4-1:0] fifo0_m_axi_awready; + wire [256-1:0] fifo0_m_axi_wdata; + wire [ 32-1:0] fifo0_m_axi_wstrb; + wire [ 4-1:0] fifo0_m_axi_wlast; + wire [ 4-1:0] fifo0_m_axi_wuser; + wire [ 4-1:0] fifo0_m_axi_wvalid; + wire [ 4-1:0] fifo0_m_axi_wready; + wire [ 4-1:0] fifo0_m_axi_bid; + wire [ 8-1:0] fifo0_m_axi_bresp; + wire [ 4-1:0] fifo0_m_axi_buser; + wire [ 4-1:0] fifo0_m_axi_bvalid; + wire [ 4-1:0] fifo0_m_axi_bready; + wire [ 4-1:0] fifo0_m_axi_arid; + wire [128-1:0] fifo0_m_axi_araddr; + wire [ 32-1:0] fifo0_m_axi_arlen; + wire [ 12-1:0] fifo0_m_axi_arsize; + wire [ 8-1:0] fifo0_m_axi_arburst; + wire [ 4-1:0] fifo0_m_axi_arlock; + wire [ 16-1:0] fifo0_m_axi_arcache; + wire [ 12-1:0] fifo0_m_axi_arprot; + wire [ 16-1:0] fifo0_m_axi_arqos; + wire [ 16-1:0] fifo0_m_axi_arregion; + wire [ 4-1:0] fifo0_m_axi_aruser; + wire [ 4-1:0] fifo0_m_axi_arvalid; + wire [ 4-1:0] fifo0_m_axi_arready; + wire [ 4-1:0] fifo0_m_axi_rid; + wire [256-1:0] fifo0_m_axi_rdata; + wire [ 8-1:0] fifo0_m_axi_rresp; + wire [ 4-1:0] fifo0_m_axi_rlast; + wire [ 4-1:0] fifo0_m_axi_ruser; + wire [ 4-1:0] fifo0_m_axi_rvalid; + wire [ 4-1:0] fifo0_m_axi_rready; + + rfnoc_block_axi_ram_fifo #( + .THIS_PORTID(4), + .CHDR_W(CHDR_W), + .NUM_PORTS(4), + .MEM_DATA_W(64), + .MEM_ADDR_W(31), + .FIFO_ADDR_BASE({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), + .FIFO_ADDR_MASK({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), + .MEM_CLK_RATE(303819444), + .MTU(MTU) + ) b_fifo0_2 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .mem_clk(fifo0_mem_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + + .axi_rst(fifo0_axi_rst), + .m_axi_awid(fifo0_m_axi_awid), + .m_axi_awaddr(fifo0_m_axi_awaddr), + .m_axi_awlen(fifo0_m_axi_awlen), + .m_axi_awsize(fifo0_m_axi_awsize), + .m_axi_awburst(fifo0_m_axi_awburst), + .m_axi_awlock(fifo0_m_axi_awlock), + .m_axi_awcache(fifo0_m_axi_awcache), + .m_axi_awprot(fifo0_m_axi_awprot), + .m_axi_awqos(fifo0_m_axi_awqos), + .m_axi_awregion(fifo0_m_axi_awregion), + .m_axi_awuser(fifo0_m_axi_awuser), + .m_axi_awvalid(fifo0_m_axi_awvalid), + .m_axi_awready(fifo0_m_axi_awready), + .m_axi_wdata(fifo0_m_axi_wdata), + .m_axi_wstrb(fifo0_m_axi_wstrb), + .m_axi_wlast(fifo0_m_axi_wlast), + .m_axi_wuser(fifo0_m_axi_wuser), + .m_axi_wvalid(fifo0_m_axi_wvalid), + .m_axi_wready(fifo0_m_axi_wready), + .m_axi_bid(fifo0_m_axi_bid), + .m_axi_bresp(fifo0_m_axi_bresp), + .m_axi_buser(fifo0_m_axi_buser), + .m_axi_bvalid(fifo0_m_axi_bvalid), + .m_axi_bready(fifo0_m_axi_bready), + .m_axi_arid(fifo0_m_axi_arid), + .m_axi_araddr(fifo0_m_axi_araddr), + .m_axi_arlen(fifo0_m_axi_arlen), + .m_axi_arsize(fifo0_m_axi_arsize), + .m_axi_arburst(fifo0_m_axi_arburst), + .m_axi_arlock(fifo0_m_axi_arlock), + .m_axi_arcache(fifo0_m_axi_arcache), + .m_axi_arprot(fifo0_m_axi_arprot), + .m_axi_arqos(fifo0_m_axi_arqos), + .m_axi_arregion(fifo0_m_axi_arregion), + .m_axi_aruser(fifo0_m_axi_aruser), + .m_axi_arvalid(fifo0_m_axi_arvalid), + .m_axi_arready(fifo0_m_axi_arready), + .m_axi_rid(fifo0_m_axi_rid), + .m_axi_rdata(fifo0_m_axi_rdata), + .m_axi_rresp(fifo0_m_axi_rresp), + .m_axi_rlast(fifo0_m_axi_rlast), + .m_axi_ruser(fifo0_m_axi_ruser), + .m_axi_rvalid(fifo0_m_axi_rvalid), + .m_axi_rready(fifo0_m_axi_rready), + + .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_fifo0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_fifo0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_fifo0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_fifo0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // Static Router + // ---------------------------------------------------- + assign s_radio0_in_0_tdata = m_ep0_out0_tdata ; + assign s_radio0_in_0_tlast = m_ep0_out0_tlast ; + assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_radio0_in_0_tready; + + assign s_ep0_in0_tdata = m_radio0_out_0_tdata ; + assign s_ep0_in0_tlast = m_radio0_out_0_tlast ; + assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ep0_in0_tready; + + assign s_radio0_in_1_tdata = m_ep1_out0_tdata ; + assign s_radio0_in_1_tlast = m_ep1_out0_tlast ; + assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_radio0_in_1_tready; + + assign s_ep1_in0_tdata = m_radio0_out_1_tdata ; + assign s_ep1_in0_tlast = m_radio0_out_1_tlast ; + assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid; + assign m_radio0_out_1_tready = s_ep1_in0_tready; + + assign s_radio1_in_0_tdata = m_ep2_out0_tdata ; + assign s_radio1_in_0_tlast = m_ep2_out0_tlast ; + assign s_radio1_in_0_tvalid = m_ep2_out0_tvalid; + assign m_ep2_out0_tready = s_radio1_in_0_tready; + + assign s_ep2_in0_tdata = m_radio1_out_0_tdata ; + assign s_ep2_in0_tlast = m_radio1_out_0_tlast ; + assign s_ep2_in0_tvalid = m_radio1_out_0_tvalid; + assign m_radio1_out_0_tready = s_ep2_in0_tready; + + assign s_radio1_in_1_tdata = m_ep3_out0_tdata ; + assign s_radio1_in_1_tlast = m_ep3_out0_tlast ; + assign s_radio1_in_1_tvalid = m_ep3_out0_tvalid; + assign m_ep3_out0_tready = s_radio1_in_1_tready; + + assign s_ep3_in0_tdata = m_radio1_out_1_tdata ; + assign s_ep3_in0_tlast = m_radio1_out_1_tlast ; + assign s_ep3_in0_tvalid = m_radio1_out_1_tvalid; + assign m_radio1_out_1_tready = s_ep3_in0_tready; + + assign s_fifo0_in_0_tdata = m_ep4_out0_tdata ; + assign s_fifo0_in_0_tlast = m_ep4_out0_tlast ; + assign s_fifo0_in_0_tvalid = m_ep4_out0_tvalid; + assign m_ep4_out0_tready = s_fifo0_in_0_tready; + + assign s_ep4_in0_tdata = m_fifo0_out_0_tdata ; + assign s_ep4_in0_tlast = m_fifo0_out_0_tlast ; + assign s_ep4_in0_tvalid = m_fifo0_out_0_tvalid; + assign m_fifo0_out_0_tready = s_ep4_in0_tready; + + assign s_fifo0_in_1_tdata = m_ep5_out0_tdata ; + assign s_fifo0_in_1_tlast = m_ep5_out0_tlast ; + assign s_fifo0_in_1_tvalid = m_ep5_out0_tvalid; + assign m_ep5_out0_tready = s_fifo0_in_1_tready; + + assign s_ep5_in0_tdata = m_fifo0_out_1_tdata ; + assign s_ep5_in0_tlast = m_fifo0_out_1_tlast ; + assign s_ep5_in0_tvalid = m_fifo0_out_1_tvalid; + assign m_fifo0_out_1_tready = s_ep5_in0_tready; + + + // ---------------------------------------------------- + // Unused Ports + // ---------------------------------------------------- + assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}}; + assign s_fifo0_in_2_tlast = 1'b0; + assign s_fifo0_in_2_tvalid = 1'b0; + assign s_fifo0_in_3_tdata = {CHDR_W{1'b0}}; + assign s_fifo0_in_3_tlast = 1'b0; + assign s_fifo0_in_3_tvalid = 1'b0; + assign m_fifo0_out_2_tready = 1'b1; + assign m_fifo0_out_3_tready = 1'b1; + + // ---------------------------------------------------- + // Clock Domains + // ---------------------------------------------------- + assign radio0_radio_clk = radio_clk; + assign radio1_radio_clk = radio_clk; + assign fifo0_mem_clk = dram_clk; + + + // ---------------------------------------------------- + // IO Port Connection + // ---------------------------------------------------- + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr; + assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd; + assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr; + assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data; + assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en; + assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time; + assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time; + assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack; + assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; + assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign radio1_radio_rx_data = radio_rx_data_radio1; + assign radio1_radio_rx_stb = radio_rx_stb_radio1; + assign radio_rx_running_radio1 = radio1_radio_rx_running; + assign radio_tx_data_radio1 = radio1_radio_tx_data; + assign radio1_radio_tx_stb = radio_tx_stb_radio1; + assign radio_tx_running_radio1 = radio1_radio_tx_running; + + assign fifo0_axi_rst = axi_rst; + assign m_axi_awid = fifo0_m_axi_awid; + assign m_axi_awaddr = fifo0_m_axi_awaddr; + assign m_axi_awlen = fifo0_m_axi_awlen; + assign m_axi_awsize = fifo0_m_axi_awsize; + assign m_axi_awburst = fifo0_m_axi_awburst; + assign m_axi_awlock = fifo0_m_axi_awlock; + assign m_axi_awcache = fifo0_m_axi_awcache; + assign m_axi_awprot = fifo0_m_axi_awprot; + assign m_axi_awqos = fifo0_m_axi_awqos; + assign m_axi_awregion = fifo0_m_axi_awregion; + assign m_axi_awuser = fifo0_m_axi_awuser; + assign m_axi_awvalid = fifo0_m_axi_awvalid; + assign fifo0_m_axi_awready = m_axi_awready; + assign m_axi_wdata = fifo0_m_axi_wdata; + assign m_axi_wstrb = fifo0_m_axi_wstrb; + assign m_axi_wlast = fifo0_m_axi_wlast; + assign m_axi_wuser = fifo0_m_axi_wuser; + assign m_axi_wvalid = fifo0_m_axi_wvalid; + assign fifo0_m_axi_wready = m_axi_wready; + assign fifo0_m_axi_bid = m_axi_bid; + assign fifo0_m_axi_bresp = m_axi_bresp; + assign fifo0_m_axi_buser = m_axi_buser; + assign fifo0_m_axi_bvalid = m_axi_bvalid; + assign m_axi_bready = fifo0_m_axi_bready; + assign m_axi_arid = fifo0_m_axi_arid; + assign m_axi_araddr = fifo0_m_axi_araddr; + assign m_axi_arlen = fifo0_m_axi_arlen; + assign m_axi_arsize = fifo0_m_axi_arsize; + assign m_axi_arburst = fifo0_m_axi_arburst; + assign m_axi_arlock = fifo0_m_axi_arlock; + assign m_axi_arcache = fifo0_m_axi_arcache; + assign m_axi_arprot = fifo0_m_axi_arprot; + assign m_axi_arqos = fifo0_m_axi_arqos; + assign m_axi_arregion = fifo0_m_axi_arregion; + assign m_axi_aruser = fifo0_m_axi_aruser; + assign m_axi_arvalid = fifo0_m_axi_arvalid; + assign fifo0_m_axi_arready = m_axi_arready; + assign fifo0_m_axi_rid = m_axi_rid; + assign fifo0_m_axi_rdata = m_axi_rdata; + assign fifo0_m_axi_rresp = m_axi_rresp; + assign fifo0_m_axi_rlast = m_axi_rlast; + assign fifo0_m_axi_ruser = m_axi_ruser; + assign fifo0_m_axi_rvalid = m_axi_rvalid; + assign m_axi_rready = fifo0_m_axi_rready; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time; + + assign radio1_radio_time = radio_time; + +endmodule diff --git a/fpga/usrp3/top/n3xx/n310_bist_image_core.yml b/fpga/usrp3/top/n3xx/n310_bist_image_core.yml new file mode 100644 index 000000000..cb4331b15 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_bist_image_core.yml @@ -0,0 +1,107 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers +license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +version: 1.0 # File version +rfnoc_version: 1.0 # RFNoC protocol version +chdr_width: 64 # Bitwidth of the CHDR bus for this block +device: 'n310' +default_target: 'N310_AA' + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep1: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep2: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep3: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep4: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep5: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + radio0: + block_desc: 'radio_2x64.yml' + radio1: + block_desc: 'radio_2x64.yml' + fifo0: + block_desc: 'axi_ram_fifo_4x64.yml' + parameters: + # These parameters match the memory interface on the N3XX + NUM_PORTS: 4 + MEM_DATA_W: 64 + MEM_ADDR_W: 31 + FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}" + FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}" + MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + # ep0 to radio0(0) - RF0 TX + - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } + # radio0(0) to ep0 - RF0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } + # ep1 to radio0(1) - RF0 TX + - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 } + # radio0(1) to ep1 - RF0 RX + - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } + # ep2 to radio1(0) - RF1 TX + - { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 } + # radio1(0) to ep2 - RF1 RX + - { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 } + # ep3 to radio1(1) - RF1 TX + - { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 } + # radio1(1) to ep3 - RF1 RX + - { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 } + # ep4 to fifo0(0) + - { srcblk: ep4, srcport: out0, dstblk: fifo0, dstport: in_0 } + - { srcblk: fifo0, srcport: out_0, dstblk: ep4, dstport: in0 } + # ep5 to fifo0(1) + - { srcblk: ep5, srcport: out0, dstblk: fifo0, dstport: in_1 } + - { srcblk: fifo0, srcport: out_1, dstblk: ep5, dstport: in0 } + # BSP Connections + - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio } + - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper } + - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram } + +# A list of all clock domain connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem } diff --git a/fpga/usrp3/top/n3xx/n310_bist_static_router.hex b/fpga/usrp3/top/n3xx/n310_bist_static_router.hex new file mode 100644 index 000000000..1e8382a50 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_bist_static_router.hex @@ -0,0 +1,13 @@ +0000000C +004001c0 +01c00040 +008001c1 +01c10080 +00c00200 +020000c0 +01000201 +02010100 +01400240 +02400140 +01800241 +02410180 diff --git a/fpga/usrp3/top/n3xx/n310_dram.xdc b/fpga/usrp3/top/n3xx/n310_dram.xdc new file mode 100644 index 000000000..4b8218b2b --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_dram.xdc @@ -0,0 +1,33 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +# Declare the 100 MHz DRAM subsystem clock. +create_clock -name ddr3_ext_refclk -period 10.0 [get_ports sys_clk_p] + +# Rename IODELAY reference clock outputs from the MMCM inside MIG. +# These are based off the 200 MHz bus_clk. +create_generated_clock -name ddr3_iodelay_refclk \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKOUT1}] +create_generated_clock -name ddr3_iodelay_refclk_fb \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKFBOUT}] + +# Rename the UI clock appropriately. This clocks the slave AXI4 ports of the MIG as well +# as the AXI logic/interconnects in the remainder of the FPGA design. Should be 200 MHz. +create_generated_clock -name ddr3_ui_clk \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT}] + +# Another UI clock at 300 MHz... not quite at 2x due to timing. +create_generated_clock -name ddr3_ui_clk_2x \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0}] + +# Phase shifting clock for the MIG. Drives a few resets. +create_generated_clock -name ddr3_ps_clk \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT5}] + + + +# No need for any asynchronous clock groups between bus_clk and the MIG UI clocks, +# because bus_clk already has a blanket asynchronous constraint from the top level XDC. \ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v new file mode 100644 index 000000000..027f176ce --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v @@ -0,0 +1,1062 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Module: rfnoc_image_core (for n310) +// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) +// Re-running that tool will overwrite this file! +// File generated on: 2019-11-08T15:58:13.073656 +// Source: ./n3xx/n310_rfnoc_image_core.yml +// Source SHA256: a4a2464a5fdebb8ac35e78c2ea53ad7be23f8106376098188c9a4caeba8bcf0e + +module rfnoc_image_core #( + parameter [15:0] PROTOVER = {8'd1, 8'd0} +)( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio_clk, + input wire dram_clk, + // Basic + input wire [15:0] device_id, +//// IO ports ////////////////////////////////// +// ctrlport_radio0 + output wire [ 1-1:0] m_ctrlport_radio0_req_wr, + output wire [ 1-1:0] m_ctrlport_radio0_req_rd, + output wire [ 20-1:0] m_ctrlport_radio0_req_addr, + output wire [ 32-1:0] m_ctrlport_radio0_req_data, + output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio0_req_time, + input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio0_resp_status, + input wire [ 32-1:0] m_ctrlport_radio0_resp_data, +// ctrlport_radio1 + output wire [ 1-1:0] m_ctrlport_radio1_req_wr, + output wire [ 1-1:0] m_ctrlport_radio1_req_rd, + output wire [ 20-1:0] m_ctrlport_radio1_req_addr, + output wire [ 32-1:0] m_ctrlport_radio1_req_data, + output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio1_req_time, + input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio1_resp_status, + input wire [ 32-1:0] m_ctrlport_radio1_resp_data, +// time_keeper + input wire [ 64-1:0] radio_time, +// x300_radio0 + input wire [ 64-1:0] radio_rx_data_radio0, + input wire [ 2-1:0] radio_rx_stb_radio0, + output wire [ 2-1:0] radio_rx_running_radio0, + output wire [ 64-1:0] radio_tx_data_radio0, + input wire [ 2-1:0] radio_tx_stb_radio0, + output wire [ 2-1:0] radio_tx_running_radio0, +// x300_radio1 + input wire [ 64-1:0] radio_rx_data_radio1, + input wire [ 2-1:0] radio_rx_stb_radio1, + output wire [ 2-1:0] radio_rx_running_radio1, + output wire [ 64-1:0] radio_tx_data_radio1, + input wire [ 2-1:0] radio_tx_stb_radio1, + output wire [ 2-1:0] radio_tx_running_radio1, +// dram + input wire [ 1-1:0] axi_rst, + output wire [ 4-1:0] m_axi_awid, + output wire [128-1:0] m_axi_awaddr, + output wire [ 32-1:0] m_axi_awlen, + output wire [ 12-1:0] m_axi_awsize, + output wire [ 8-1:0] m_axi_awburst, + output wire [ 4-1:0] m_axi_awlock, + output wire [ 16-1:0] m_axi_awcache, + output wire [ 12-1:0] m_axi_awprot, + output wire [ 16-1:0] m_axi_awqos, + output wire [ 16-1:0] m_axi_awregion, + output wire [ 4-1:0] m_axi_awuser, + output wire [ 4-1:0] m_axi_awvalid, + input wire [ 4-1:0] m_axi_awready, + output wire [256-1:0] m_axi_wdata, + output wire [ 32-1:0] m_axi_wstrb, + output wire [ 4-1:0] m_axi_wlast, + output wire [ 4-1:0] m_axi_wuser, + output wire [ 4-1:0] m_axi_wvalid, + input wire [ 4-1:0] m_axi_wready, + input wire [ 4-1:0] m_axi_bid, + input wire [ 8-1:0] m_axi_bresp, + input wire [ 4-1:0] m_axi_buser, + input wire [ 4-1:0] m_axi_bvalid, + output wire [ 4-1:0] m_axi_bready, + output wire [ 4-1:0] m_axi_arid, + output wire [128-1:0] m_axi_araddr, + output wire [ 32-1:0] m_axi_arlen, + output wire [ 12-1:0] m_axi_arsize, + output wire [ 8-1:0] m_axi_arburst, + output wire [ 4-1:0] m_axi_arlock, + output wire [ 16-1:0] m_axi_arcache, + output wire [ 12-1:0] m_axi_arprot, + output wire [ 16-1:0] m_axi_arqos, + output wire [ 16-1:0] m_axi_arregion, + output wire [ 4-1:0] m_axi_aruser, + output wire [ 4-1:0] m_axi_arvalid, + input wire [ 4-1:0] m_axi_arready, + input wire [ 4-1:0] m_axi_rid, + input wire [256-1:0] m_axi_rdata, + input wire [ 8-1:0] m_axi_rresp, + input wire [ 4-1:0] m_axi_rlast, + input wire [ 4-1:0] m_axi_ruser, + input wire [ 4-1:0] m_axi_rvalid, + output wire [ 4-1:0] m_axi_rready, + // Transport 0 (eth0 1G) + input wire [64-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [64-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1 10G) + input wire [64-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [64-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma dma) + input wire [64-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [64-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam CHDR_W = 64; + localparam MTU = 10; + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + // ---------------------------------------------------- + // CHDR Crossbar + // ---------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [CHDR_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [CHDR_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep2_tdata ; + wire xb_to_ep2_tlast ; + wire xb_to_ep2_tvalid; + wire xb_to_ep2_tready; + wire [CHDR_W-1:0] ep2_to_xb_tdata ; + wire ep2_to_xb_tlast ; + wire ep2_to_xb_tvalid; + wire ep2_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep3_tdata ; + wire xb_to_ep3_tlast ; + wire xb_to_ep3_tvalid; + wire xb_to_ep3_tready; + wire [CHDR_W-1:0] ep3_to_xb_tdata ; + wire ep3_to_xb_tlast ; + wire ep3_to_xb_tvalid; + wire ep3_to_xb_tready; + + chdr_crossbar_nxn #( + .CHDR_W (CHDR_W), + .NPORTS (7), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (3), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_xb_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), + .s_axis_tlast ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tvalid ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), + .m_axis_tlast ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tvalid ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + // ---------------------------------------------------- + // Stream Endpoints + // ---------------------------------------------------- + + wire [CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; + wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep0_tdata ), + .s_axis_chdr_tlast (xb_to_ep0_tlast ), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), + .s_axis_chdr_tready (xb_to_ep0_tready ), + .m_axis_chdr_tdata (ep0_to_xb_tdata ), + .m_axis_chdr_tlast (ep0_to_xb_tlast ), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), + .m_axis_chdr_tready (ep0_to_xb_tready ), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; + wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep1_tdata ), + .s_axis_chdr_tlast (xb_to_ep1_tlast ), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), + .s_axis_chdr_tready (xb_to_ep1_tready ), + .m_axis_chdr_tdata (ep1_to_xb_tdata ), + .m_axis_chdr_tlast (ep1_to_xb_tlast ), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), + .m_axis_chdr_tready (ep1_to_xb_tready ), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep2_out0_tdata; + wire m_ep2_out0_tlast; + wire m_ep2_out0_tvalid; + wire m_ep2_out0_tready; + wire [CHDR_W-1:0] s_ep2_in0_tdata; + wire s_ep2_in0_tlast; + wire s_ep2_in0_tvalid; + wire s_ep2_in0_tready; + wire [31:0] m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ; + wire m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ; + wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; + wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (2), + .CTRL_XBAR_PORT (3), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep2_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep2_tdata ), + .s_axis_chdr_tlast (xb_to_ep2_tlast ), + .s_axis_chdr_tvalid (xb_to_ep2_tvalid ), + .s_axis_chdr_tready (xb_to_ep2_tready ), + .m_axis_chdr_tdata (ep2_to_xb_tdata ), + .m_axis_chdr_tlast (ep2_to_xb_tlast ), + .m_axis_chdr_tvalid (ep2_to_xb_tvalid ), + .m_axis_chdr_tready (ep2_to_xb_tready ), + .s_axis_data_tdata ({s_ep2_in0_tdata}), + .s_axis_data_tlast ({s_ep2_in0_tlast}), + .s_axis_data_tvalid ({s_ep2_in0_tvalid}), + .s_axis_data_tready ({s_ep2_in0_tready}), + .m_axis_data_tdata ({m_ep2_out0_tdata}), + .m_axis_data_tlast ({m_ep2_out0_tlast}), + .m_axis_data_tvalid ({m_ep2_out0_tvalid}), + .m_axis_data_tready ({m_ep2_out0_tready}), + .s_axis_ctrl_tdata (s_ep2_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep2_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep2_ctrl_tready), + .m_axis_ctrl_tdata (m_ep2_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep2_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep2_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep3_out0_tdata; + wire m_ep3_out0_tlast; + wire m_ep3_out0_tvalid; + wire m_ep3_out0_tready; + wire [CHDR_W-1:0] s_ep3_in0_tdata; + wire s_ep3_in0_tlast; + wire s_ep3_in0_tvalid; + wire s_ep3_in0_tready; + wire [31:0] m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ; + wire m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ; + wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; + wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (3), + .CTRL_XBAR_PORT (4), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep3_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep3_tdata ), + .s_axis_chdr_tlast (xb_to_ep3_tlast ), + .s_axis_chdr_tvalid (xb_to_ep3_tvalid ), + .s_axis_chdr_tready (xb_to_ep3_tready ), + .m_axis_chdr_tdata (ep3_to_xb_tdata ), + .m_axis_chdr_tlast (ep3_to_xb_tlast ), + .m_axis_chdr_tvalid (ep3_to_xb_tvalid ), + .m_axis_chdr_tready (ep3_to_xb_tready ), + .s_axis_data_tdata ({s_ep3_in0_tdata}), + .s_axis_data_tlast ({s_ep3_in0_tlast}), + .s_axis_data_tvalid ({s_ep3_in0_tvalid}), + .s_axis_data_tready ({s_ep3_in0_tready}), + .m_axis_data_tdata ({m_ep3_out0_tdata}), + .m_axis_data_tlast ({m_ep3_out0_tlast}), + .m_axis_data_tvalid ({m_ep3_out0_tvalid}), + .m_axis_data_tready ({m_ep3_out0_tready}), + .s_axis_ctrl_tdata (s_ep3_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep3_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep3_ctrl_tready), + .m_axis_ctrl_tdata (m_ep3_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep3_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep3_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + + + // ---------------------------------------------------- + // Control Crossbar + // ---------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; + wire m_core_ctrl_tlast , s_core_ctrl_tlast ; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_duc0_ctrl_tdata , s_duc0_ctrl_tdata ; + wire m_duc0_ctrl_tlast , s_duc0_ctrl_tlast ; + wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; + wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; + wire [31:0] m_ddc0_ctrl_tdata , s_ddc0_ctrl_tdata ; + wire m_ddc0_ctrl_tlast , s_ddc0_ctrl_tlast ; + wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; + wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; + wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_duc1_ctrl_tdata , s_duc1_ctrl_tdata ; + wire m_duc1_ctrl_tlast , s_duc1_ctrl_tlast ; + wire m_duc1_ctrl_tvalid, s_duc1_ctrl_tvalid; + wire m_duc1_ctrl_tready, s_duc1_ctrl_tready; + wire [31:0] m_ddc1_ctrl_tdata , s_ddc1_ctrl_tdata ; + wire m_ddc1_ctrl_tlast , s_ddc1_ctrl_tlast ; + wire m_ddc1_ctrl_tvalid, s_ddc1_ctrl_tvalid; + wire m_ddc1_ctrl_tready, s_ddc1_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ; + wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (8), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + // ---------------------------------------------------- + // RFNoC Core Kernel + // ---------------------------------------------------- + wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'h1300), + .DEVICE_FAMILY ("7SERIES"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (6), + .NUM_STREAM_ENDPOINTS(4), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (3), + .NUM_EDGES (16), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata ), + .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata ), + .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + // ---------------------------------------------------- + // Blocks + // ---------------------------------------------------- + + // ---------------------------------------------------- + // duc0 + // ---------------------------------------------------- + wire duc0_ce_clk; + wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; + wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; + wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid; + wire s_duc0_in_1_tready, s_duc0_in_0_tready; + wire [CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ; + wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ; + wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; + wire m_duc0_out_1_tready, m_duc0_out_0_tready; + + + rfnoc_block_duc #( + .THIS_PORTID(2), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_INTERP(255), + .MTU(MTU) + ) b_duc0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(duc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + + + .s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_duc0_in_1_tready, s_duc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc0_out_1_tdata , m_duc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_duc0_out_1_tready, m_duc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_duc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_duc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_duc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_duc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // ddc0 + // ---------------------------------------------------- + wire ddc0_ce_clk; + wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; + wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; + wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; + wire s_ddc0_in_1_tready, s_ddc0_in_0_tready; + wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; + wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; + wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; + wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; + + + rfnoc_block_ddc #( + .THIS_PORTID(3), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_DECIM(255), + .MTU(MTU) + ) b_ddc0_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(ddc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + + + .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_ddc0_in_1_tready, s_ddc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc0_out_1_tdata , m_ddc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_ddc0_out_1_tready, m_ddc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_ddc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_ddc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_ddc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_ddc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio0 + // ---------------------------------------------------- + wire radio0_radio_clk; + wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_1_tready, m_radio0_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio0_m_ctrlport_req_wr; + wire [ 1-1:0] radio0_m_ctrlport_req_rd; + wire [ 20-1:0] radio0_m_ctrlport_req_addr; + wire [ 32-1:0] radio0_m_ctrlport_req_data; + wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio0_m_ctrlport_req_has_time; + wire [ 64-1:0] radio0_m_ctrlport_req_time; + wire [ 1-1:0] radio0_m_ctrlport_resp_ack; + wire [ 2-1:0] radio0_m_ctrlport_resp_status; + wire [ 32-1:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio0_radio_time; + // x300_radio + wire [ 64-1:0] radio0_radio_rx_data; + wire [ 2-1:0] radio0_radio_rx_stb; + wire [ 2-1:0] radio0_radio_rx_running; + wire [ 64-1:0] radio0_radio_tx_data; + wire [ 2-1:0] radio0_radio_tx_stb; + wire [ 2-1:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(4), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio0_2 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + + .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time(radio0_radio_time), + .radio_rx_data(radio0_radio_rx_data), + .radio_rx_stb(radio0_radio_rx_stb), + .radio_rx_running(radio0_radio_rx_running), + .radio_tx_data(radio0_radio_tx_data), + .radio_tx_stb(radio0_radio_tx_stb), + .radio_tx_running(radio0_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // duc1 + // ---------------------------------------------------- + wire duc1_ce_clk; + wire [CHDR_W-1:0] s_duc1_in_1_tdata , s_duc1_in_0_tdata ; + wire s_duc1_in_1_tlast , s_duc1_in_0_tlast ; + wire s_duc1_in_1_tvalid, s_duc1_in_0_tvalid; + wire s_duc1_in_1_tready, s_duc1_in_0_tready; + wire [CHDR_W-1:0] m_duc1_out_1_tdata , m_duc1_out_0_tdata ; + wire m_duc1_out_1_tlast , m_duc1_out_0_tlast ; + wire m_duc1_out_1_tvalid, m_duc1_out_0_tvalid; + wire m_duc1_out_1_tready, m_duc1_out_0_tready; + + + rfnoc_block_duc #( + .THIS_PORTID(5), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_INTERP(255), + .MTU(MTU) + ) b_duc1_3 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(duc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), + .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), + + + .s_rfnoc_chdr_tdata ({s_duc1_in_1_tdata , s_duc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc1_in_1_tlast , s_duc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_duc1_in_1_tvalid, s_duc1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_duc1_in_1_tready, s_duc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc1_out_1_tdata , m_duc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc1_out_1_tlast , m_duc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_duc1_out_1_tvalid, m_duc1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_duc1_out_1_tready, m_duc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_duc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_duc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_duc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_duc1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // ddc1 + // ---------------------------------------------------- + wire ddc1_ce_clk; + wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ; + wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ; + wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid; + wire s_ddc1_in_1_tready, s_ddc1_in_0_tready; + wire [CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ; + wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ; + wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid; + wire m_ddc1_out_1_tready, m_ddc1_out_0_tready; + + + rfnoc_block_ddc #( + .THIS_PORTID(6), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_DECIM(255), + .MTU(MTU) + ) b_ddc1_4 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(ddc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), + .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), + + + .s_rfnoc_chdr_tdata ({s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_ddc1_in_1_tready, s_ddc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc1_out_1_tdata , m_ddc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc1_out_1_tlast , m_ddc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_ddc1_out_1_tready, m_ddc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_ddc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_ddc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_ddc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_ddc1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio1 + // ---------------------------------------------------- + wire radio1_radio_clk; + wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; + wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; + wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; + wire s_radio1_in_1_tready, s_radio1_in_0_tready; + wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; + wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; + wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; + wire m_radio1_out_1_tready, m_radio1_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio1_m_ctrlport_req_wr; + wire [ 1-1:0] radio1_m_ctrlport_req_rd; + wire [ 20-1:0] radio1_m_ctrlport_req_addr; + wire [ 32-1:0] radio1_m_ctrlport_req_data; + wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio1_m_ctrlport_req_has_time; + wire [ 64-1:0] radio1_m_ctrlport_req_time; + wire [ 1-1:0] radio1_m_ctrlport_resp_ack; + wire [ 2-1:0] radio1_m_ctrlport_resp_status; + wire [ 32-1:0] radio1_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio1_radio_time; + // x300_radio + wire [ 64-1:0] radio1_radio_rx_data; + wire [ 2-1:0] radio1_radio_rx_stb; + wire [ 2-1:0] radio1_radio_rx_running; + wire [ 64-1:0] radio1_radio_tx_data; + wire [ 2-1:0] radio1_radio_tx_stb; + wire [ 2-1:0] radio1_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(7), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio1_5 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), + .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), + + .m_ctrlport_req_wr(radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio1_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), + .radio_time(radio1_radio_time), + .radio_rx_data(radio1_radio_rx_data), + .radio_rx_stb(radio1_radio_rx_stb), + .radio_rx_running(radio1_radio_rx_running), + .radio_tx_data(radio1_radio_tx_data), + .radio_tx_stb(radio1_radio_tx_stb), + .radio_tx_running(radio1_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio1_in_1_tready, s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio1_out_1_tready, m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // Static Router + // ---------------------------------------------------- + assign s_duc0_in_0_tdata = m_ep0_out0_tdata ; + assign s_duc0_in_0_tlast = m_ep0_out0_tlast ; + assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_duc0_in_0_tready; + + assign s_radio0_in_0_tdata = m_duc0_out_0_tdata ; + assign s_radio0_in_0_tlast = m_duc0_out_0_tlast ; + assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid; + assign m_duc0_out_0_tready = s_radio0_in_0_tready; + + assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata ; + assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast ; + assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ddc0_in_0_tready; + + assign s_ep0_in0_tdata = m_ddc0_out_0_tdata ; + assign s_ep0_in0_tlast = m_ddc0_out_0_tlast ; + assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid; + assign m_ddc0_out_0_tready = s_ep0_in0_tready; + + assign s_duc0_in_1_tdata = m_ep1_out0_tdata ; + assign s_duc0_in_1_tlast = m_ep1_out0_tlast ; + assign s_duc0_in_1_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_duc0_in_1_tready; + + assign s_radio0_in_1_tdata = m_duc0_out_1_tdata ; + assign s_radio0_in_1_tlast = m_duc0_out_1_tlast ; + assign s_radio0_in_1_tvalid = m_duc0_out_1_tvalid; + assign m_duc0_out_1_tready = s_radio0_in_1_tready; + + assign s_ddc0_in_1_tdata = m_radio0_out_1_tdata ; + assign s_ddc0_in_1_tlast = m_radio0_out_1_tlast ; + assign s_ddc0_in_1_tvalid = m_radio0_out_1_tvalid; + assign m_radio0_out_1_tready = s_ddc0_in_1_tready; + + assign s_ep1_in0_tdata = m_ddc0_out_1_tdata ; + assign s_ep1_in0_tlast = m_ddc0_out_1_tlast ; + assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid; + assign m_ddc0_out_1_tready = s_ep1_in0_tready; + + assign s_duc1_in_0_tdata = m_ep2_out0_tdata ; + assign s_duc1_in_0_tlast = m_ep2_out0_tlast ; + assign s_duc1_in_0_tvalid = m_ep2_out0_tvalid; + assign m_ep2_out0_tready = s_duc1_in_0_tready; + + assign s_radio1_in_0_tdata = m_duc1_out_0_tdata ; + assign s_radio1_in_0_tlast = m_duc1_out_0_tlast ; + assign s_radio1_in_0_tvalid = m_duc1_out_0_tvalid; + assign m_duc1_out_0_tready = s_radio1_in_0_tready; + + assign s_ddc1_in_0_tdata = m_radio1_out_0_tdata ; + assign s_ddc1_in_0_tlast = m_radio1_out_0_tlast ; + assign s_ddc1_in_0_tvalid = m_radio1_out_0_tvalid; + assign m_radio1_out_0_tready = s_ddc1_in_0_tready; + + assign s_ep2_in0_tdata = m_ddc1_out_0_tdata ; + assign s_ep2_in0_tlast = m_ddc1_out_0_tlast ; + assign s_ep2_in0_tvalid = m_ddc1_out_0_tvalid; + assign m_ddc1_out_0_tready = s_ep2_in0_tready; + + assign s_duc1_in_1_tdata = m_ep3_out0_tdata ; + assign s_duc1_in_1_tlast = m_ep3_out0_tlast ; + assign s_duc1_in_1_tvalid = m_ep3_out0_tvalid; + assign m_ep3_out0_tready = s_duc1_in_1_tready; + + assign s_radio1_in_1_tdata = m_duc1_out_1_tdata ; + assign s_radio1_in_1_tlast = m_duc1_out_1_tlast ; + assign s_radio1_in_1_tvalid = m_duc1_out_1_tvalid; + assign m_duc1_out_1_tready = s_radio1_in_1_tready; + + assign s_ddc1_in_1_tdata = m_radio1_out_1_tdata ; + assign s_ddc1_in_1_tlast = m_radio1_out_1_tlast ; + assign s_ddc1_in_1_tvalid = m_radio1_out_1_tvalid; + assign m_radio1_out_1_tready = s_ddc1_in_1_tready; + + assign s_ep3_in0_tdata = m_ddc1_out_1_tdata ; + assign s_ep3_in0_tlast = m_ddc1_out_1_tlast ; + assign s_ep3_in0_tvalid = m_ddc1_out_1_tvalid; + assign m_ddc1_out_1_tready = s_ep3_in0_tready; + + + // ---------------------------------------------------- + // Unused Ports + // ---------------------------------------------------- + + // ---------------------------------------------------- + // Clock Domains + // ---------------------------------------------------- + assign radio0_radio_clk = radio_clk; + assign ddc0_ce_clk = rfnoc_chdr_clk; + assign duc0_ce_clk = rfnoc_chdr_clk; + assign radio1_radio_clk = radio_clk; + assign ddc1_ce_clk = rfnoc_chdr_clk; + assign duc1_ce_clk = rfnoc_chdr_clk; + + + // ---------------------------------------------------- + // IO Port Connection + // ---------------------------------------------------- + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr; + assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd; + assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr; + assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data; + assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en; + assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time; + assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time; + assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack; + assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; + assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign radio1_radio_rx_data = radio_rx_data_radio1; + assign radio1_radio_rx_stb = radio_rx_stb_radio1; + assign radio_rx_running_radio1 = radio1_radio_rx_running; + assign radio_tx_data_radio1 = radio1_radio_tx_data; + assign radio1_radio_tx_stb = radio_tx_stb_radio1; + assign radio_tx_running_radio1 = radio1_radio_tx_running; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time; + + assign radio1_radio_time = radio_time; + +endmodule diff --git a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml new file mode 100644 index 000000000..d930baf6f --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml @@ -0,0 +1,111 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers +license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +version: 1.0 # File version +rfnoc_version: 1.0 # RFNoC protocol version +chdr_width: 64 # Bit width of the CHDR bus for this image +device: 'n310' +default_target: 'N310_HG' + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep1: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep2: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep3: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + duc0: # NoC block name + block_desc: 'duc.yml' # Block device descriptor file + parameters: + NUM_PORTS: 2 + ddc0: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 2 + radio0: + block_desc: 'radio_2x64.yml' + duc1: + block_desc: 'duc.yml' + parameters: + NUM_PORTS: 2 + ddc1: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 2 + radio1: + block_desc: 'radio_2x64.yml' + #fifo0: + #block_desc: 'axi_ram_fifo_4x64.yml' + #parameters: + ## These parameters match the memory interface on the N3XX + #NUM_PORTS: 4 + #MEM_DATA_W: 64 + #MEM_ADDR_W: 31 + #FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}" + #FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}" + #MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 } + - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } + - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 } + - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 } + - { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 } + - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 } + - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 } + - { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 } + - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 } + - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 } + - { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 } + - { srcblk: ep3, srcport: out0, dstblk: duc1, dstport: in_1 } + - { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 } + - { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 } + - { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 } + - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio } + - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc1, dstport: ce } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc1, dstport: ce } +# - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem } diff --git a/fpga/usrp3/top/n3xx/n310_static_router.hex b/fpga/usrp3/top/n3xx/n310_static_router.hex new file mode 100644 index 000000000..73449b968 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_static_router.hex @@ -0,0 +1,17 @@ +00000010 +00400140 +014001c0 +01c00180 +01800040 +00800141 +014101c1 +01c10181 +01810080 +00c00200 +02000280 +02800240 +024000c0 +01000201 +02010281 +02810241 +02410100 diff --git a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v new file mode 100644 index 000000000..875c8ade1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v @@ -0,0 +1,884 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Module: rfnoc_image_core (for n320) +// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) +// Re-running that tool will overwrite this file! +// File generated on: 2019-11-08T15:58:13.514800 +// Source: ./n3xx/n320_rfnoc_image_core.yml +// Source SHA256: 2641d416e72d1a537f6a832837fc0c9b69675bfe6be7521370900c067742b0bb + +module rfnoc_image_core #( + parameter [15:0] PROTOVER = {8'd1, 8'd0} +)( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio_clk, + input wire dram_clk, + // Basic + input wire [15:0] device_id, +//// IO ports ////////////////////////////////// +// ctrlport_radio0 + output wire [ 1-1:0] m_ctrlport_radio0_req_wr, + output wire [ 1-1:0] m_ctrlport_radio0_req_rd, + output wire [ 20-1:0] m_ctrlport_radio0_req_addr, + output wire [ 32-1:0] m_ctrlport_radio0_req_data, + output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio0_req_time, + input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio0_resp_status, + input wire [ 32-1:0] m_ctrlport_radio0_resp_data, +// ctrlport_radio1 + output wire [ 1-1:0] m_ctrlport_radio1_req_wr, + output wire [ 1-1:0] m_ctrlport_radio1_req_rd, + output wire [ 20-1:0] m_ctrlport_radio1_req_addr, + output wire [ 32-1:0] m_ctrlport_radio1_req_data, + output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio1_req_time, + input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio1_resp_status, + input wire [ 32-1:0] m_ctrlport_radio1_resp_data, +// time_keeper + input wire [ 64-1:0] radio_time, +// radio_ch0 + input wire [ 32-1:0] radio_rx_data_radio0, + input wire [ 1-1:0] radio_rx_stb_radio0, + output wire [ 1-1:0] radio_rx_running_radio0, + output wire [ 32-1:0] radio_tx_data_radio0, + input wire [ 1-1:0] radio_tx_stb_radio0, + output wire [ 1-1:0] radio_tx_running_radio0, +// radio_ch1 + input wire [ 32-1:0] radio_rx_data_radio1, + input wire [ 1-1:0] radio_rx_stb_radio1, + output wire [ 1-1:0] radio_rx_running_radio1, + output wire [ 32-1:0] radio_tx_data_radio1, + input wire [ 1-1:0] radio_tx_stb_radio1, + output wire [ 1-1:0] radio_tx_running_radio1, +// dram + input wire [ 1-1:0] axi_rst, + output wire [ 4-1:0] m_axi_awid, + output wire [128-1:0] m_axi_awaddr, + output wire [ 32-1:0] m_axi_awlen, + output wire [ 12-1:0] m_axi_awsize, + output wire [ 8-1:0] m_axi_awburst, + output wire [ 4-1:0] m_axi_awlock, + output wire [ 16-1:0] m_axi_awcache, + output wire [ 12-1:0] m_axi_awprot, + output wire [ 16-1:0] m_axi_awqos, + output wire [ 16-1:0] m_axi_awregion, + output wire [ 4-1:0] m_axi_awuser, + output wire [ 4-1:0] m_axi_awvalid, + input wire [ 4-1:0] m_axi_awready, + output wire [256-1:0] m_axi_wdata, + output wire [ 32-1:0] m_axi_wstrb, + output wire [ 4-1:0] m_axi_wlast, + output wire [ 4-1:0] m_axi_wuser, + output wire [ 4-1:0] m_axi_wvalid, + input wire [ 4-1:0] m_axi_wready, + input wire [ 4-1:0] m_axi_bid, + input wire [ 8-1:0] m_axi_bresp, + input wire [ 4-1:0] m_axi_buser, + input wire [ 4-1:0] m_axi_bvalid, + output wire [ 4-1:0] m_axi_bready, + output wire [ 4-1:0] m_axi_arid, + output wire [128-1:0] m_axi_araddr, + output wire [ 32-1:0] m_axi_arlen, + output wire [ 12-1:0] m_axi_arsize, + output wire [ 8-1:0] m_axi_arburst, + output wire [ 4-1:0] m_axi_arlock, + output wire [ 16-1:0] m_axi_arcache, + output wire [ 12-1:0] m_axi_arprot, + output wire [ 16-1:0] m_axi_arqos, + output wire [ 16-1:0] m_axi_arregion, + output wire [ 4-1:0] m_axi_aruser, + output wire [ 4-1:0] m_axi_arvalid, + input wire [ 4-1:0] m_axi_arready, + input wire [ 4-1:0] m_axi_rid, + input wire [256-1:0] m_axi_rdata, + input wire [ 8-1:0] m_axi_rresp, + input wire [ 4-1:0] m_axi_rlast, + input wire [ 4-1:0] m_axi_ruser, + input wire [ 4-1:0] m_axi_rvalid, + output wire [ 4-1:0] m_axi_rready, + // Transport 0 (eth0 1G) + input wire [64-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [64-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1 10G) + input wire [64-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [64-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma dma) + input wire [64-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [64-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam CHDR_W = 64; + localparam MTU = 10; + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + // ---------------------------------------------------- + // CHDR Crossbar + // ---------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [CHDR_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [CHDR_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + + chdr_crossbar_nxn #( + .CHDR_W (CHDR_W), + .NPORTS (5), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (3), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_xb_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), + .s_axis_tlast ({ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tvalid ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), + .m_axis_tlast ({xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tvalid ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + // ---------------------------------------------------- + // Stream Endpoints + // ---------------------------------------------------- + + wire [CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; + wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep0_tdata ), + .s_axis_chdr_tlast (xb_to_ep0_tlast ), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), + .s_axis_chdr_tready (xb_to_ep0_tready ), + .m_axis_chdr_tdata (ep0_to_xb_tdata ), + .m_axis_chdr_tlast (ep0_to_xb_tlast ), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), + .m_axis_chdr_tready (ep0_to_xb_tready ), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; + wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep1_tdata ), + .s_axis_chdr_tlast (xb_to_ep1_tlast ), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), + .s_axis_chdr_tready (xb_to_ep1_tready ), + .m_axis_chdr_tdata (ep1_to_xb_tdata ), + .m_axis_chdr_tlast (ep1_to_xb_tlast ), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), + .m_axis_chdr_tready (ep1_to_xb_tready ), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + + + // ---------------------------------------------------- + // Control Crossbar + // ---------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; + wire m_core_ctrl_tlast , s_core_ctrl_tlast ; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_duc0_ctrl_tdata , s_duc0_ctrl_tdata ; + wire m_duc0_ctrl_tlast , s_duc0_ctrl_tlast ; + wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; + wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; + wire [31:0] m_ddc0_ctrl_tdata , s_ddc0_ctrl_tdata ; + wire m_ddc0_ctrl_tlast , s_ddc0_ctrl_tlast ; + wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; + wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; + wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_duc1_ctrl_tdata , s_duc1_ctrl_tdata ; + wire m_duc1_ctrl_tlast , s_duc1_ctrl_tlast ; + wire m_duc1_ctrl_tvalid, s_duc1_ctrl_tvalid; + wire m_duc1_ctrl_tready, s_duc1_ctrl_tready; + wire [31:0] m_ddc1_ctrl_tdata , s_ddc1_ctrl_tdata ; + wire m_ddc1_ctrl_tlast , s_ddc1_ctrl_tlast ; + wire m_ddc1_ctrl_tvalid, s_ddc1_ctrl_tvalid; + wire m_ddc1_ctrl_tready, s_ddc1_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ; + wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (8), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + // ---------------------------------------------------- + // RFNoC Core Kernel + // ---------------------------------------------------- + wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'h1320), + .DEVICE_FAMILY ("7SERIES"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (6), + .NUM_STREAM_ENDPOINTS(2), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (3), + .NUM_EDGES (8), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata ), + .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata ), + .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + // ---------------------------------------------------- + // Blocks + // ---------------------------------------------------- + + // ---------------------------------------------------- + // duc0 + // ---------------------------------------------------- + wire duc0_ce_clk; + wire [CHDR_W-1:0] s_duc0_in_0_tdata ; + wire s_duc0_in_0_tlast ; + wire s_duc0_in_0_tvalid; + wire s_duc0_in_0_tready; + wire [CHDR_W-1:0] m_duc0_out_0_tdata ; + wire m_duc0_out_0_tlast ; + wire m_duc0_out_0_tvalid; + wire m_duc0_out_0_tready; + + + rfnoc_block_duc #( + .THIS_PORTID(2), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .NUM_HB(3), + .CIC_MAX_INTERP(255), + .MTU(MTU) + ) b_duc0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(duc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + + + .s_rfnoc_chdr_tdata ({s_duc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_duc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_duc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_duc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_duc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_duc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_duc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_duc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_duc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // ddc0 + // ---------------------------------------------------- + wire ddc0_ce_clk; + wire [CHDR_W-1:0] s_ddc0_in_0_tdata ; + wire s_ddc0_in_0_tlast ; + wire s_ddc0_in_0_tvalid; + wire s_ddc0_in_0_tready; + wire [CHDR_W-1:0] m_ddc0_out_0_tdata ; + wire m_ddc0_out_0_tlast ; + wire m_ddc0_out_0_tvalid; + wire m_ddc0_out_0_tready; + + + rfnoc_block_ddc #( + .THIS_PORTID(3), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .NUM_HB(3), + .CIC_MAX_DECIM(255), + .MTU(MTU) + ) b_ddc0_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(ddc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + + + .s_rfnoc_chdr_tdata ({s_ddc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_ddc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_ddc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_ddc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_ddc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_ddc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_ddc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_ddc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_ddc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio0 + // ---------------------------------------------------- + wire radio0_radio_clk; + wire [CHDR_W-1:0] s_radio0_in_0_tdata ; + wire s_radio0_in_0_tlast ; + wire s_radio0_in_0_tvalid; + wire s_radio0_in_0_tready; + wire [CHDR_W-1:0] m_radio0_out_0_tdata ; + wire m_radio0_out_0_tlast ; + wire m_radio0_out_0_tvalid; + wire m_radio0_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio0_m_ctrlport_req_wr; + wire [ 1-1:0] radio0_m_ctrlport_req_rd; + wire [ 20-1:0] radio0_m_ctrlport_req_addr; + wire [ 32-1:0] radio0_m_ctrlport_req_data; + wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio0_m_ctrlport_req_has_time; + wire [ 64-1:0] radio0_m_ctrlport_req_time; + wire [ 1-1:0] radio0_m_ctrlport_resp_ack; + wire [ 2-1:0] radio0_m_ctrlport_resp_status; + wire [ 32-1:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio0_radio_time; + // radio_iface + wire [ 32-1:0] radio0_radio_rx_data; + wire [ 1-1:0] radio0_radio_rx_stb; + wire [ 1-1:0] radio0_radio_rx_running; + wire [ 32-1:0] radio0_radio_tx_data; + wire [ 1-1:0] radio0_radio_tx_stb; + wire [ 1-1:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(4), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .MTU(MTU) + ) b_radio0_2 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + + .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time(radio0_radio_time), + .radio_rx_data(radio0_radio_rx_data), + .radio_rx_stb(radio0_radio_rx_stb), + .radio_rx_running(radio0_radio_rx_running), + .radio_tx_data(radio0_radio_tx_data), + .radio_tx_stb(radio0_radio_tx_stb), + .radio_tx_running(radio0_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // duc1 + // ---------------------------------------------------- + wire duc1_ce_clk; + wire [CHDR_W-1:0] s_duc1_in_0_tdata ; + wire s_duc1_in_0_tlast ; + wire s_duc1_in_0_tvalid; + wire s_duc1_in_0_tready; + wire [CHDR_W-1:0] m_duc1_out_0_tdata ; + wire m_duc1_out_0_tlast ; + wire m_duc1_out_0_tvalid; + wire m_duc1_out_0_tready; + + + rfnoc_block_duc #( + .THIS_PORTID(5), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .NUM_HB(3), + .CIC_MAX_INTERP(255), + .MTU(MTU) + ) b_duc1_3 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(duc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), + .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), + + + .s_rfnoc_chdr_tdata ({s_duc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_duc1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_duc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_duc1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_duc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_duc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_duc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_duc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_duc1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // ddc1 + // ---------------------------------------------------- + wire ddc1_ce_clk; + wire [CHDR_W-1:0] s_ddc1_in_0_tdata ; + wire s_ddc1_in_0_tlast ; + wire s_ddc1_in_0_tvalid; + wire s_ddc1_in_0_tready; + wire [CHDR_W-1:0] m_ddc1_out_0_tdata ; + wire m_ddc1_out_0_tlast ; + wire m_ddc1_out_0_tvalid; + wire m_ddc1_out_0_tready; + + + rfnoc_block_ddc #( + .THIS_PORTID(6), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .NUM_HB(3), + .CIC_MAX_DECIM(255), + .MTU(MTU) + ) b_ddc1_4 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(ddc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), + .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), + + + .s_rfnoc_chdr_tdata ({s_ddc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_ddc1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_ddc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_ddc1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_ddc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_ddc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_ddc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_ddc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_ddc1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio1 + // ---------------------------------------------------- + wire radio1_radio_clk; + wire [CHDR_W-1:0] s_radio1_in_0_tdata ; + wire s_radio1_in_0_tlast ; + wire s_radio1_in_0_tvalid; + wire s_radio1_in_0_tready; + wire [CHDR_W-1:0] m_radio1_out_0_tdata ; + wire m_radio1_out_0_tlast ; + wire m_radio1_out_0_tvalid; + wire m_radio1_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio1_m_ctrlport_req_wr; + wire [ 1-1:0] radio1_m_ctrlport_req_rd; + wire [ 20-1:0] radio1_m_ctrlport_req_addr; + wire [ 32-1:0] radio1_m_ctrlport_req_data; + wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio1_m_ctrlport_req_has_time; + wire [ 64-1:0] radio1_m_ctrlport_req_time; + wire [ 1-1:0] radio1_m_ctrlport_resp_ack; + wire [ 2-1:0] radio1_m_ctrlport_resp_status; + wire [ 32-1:0] radio1_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio1_radio_time; + // radio_iface + wire [ 32-1:0] radio1_radio_rx_data; + wire [ 1-1:0] radio1_radio_rx_stb; + wire [ 1-1:0] radio1_radio_rx_running; + wire [ 32-1:0] radio1_radio_tx_data; + wire [ 1-1:0] radio1_radio_tx_stb; + wire [ 1-1:0] radio1_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(7), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .MTU(MTU) + ) b_radio1_5 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), + .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), + + .m_ctrlport_req_wr(radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio1_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), + .radio_time(radio1_radio_time), + .radio_rx_data(radio1_radio_rx_data), + .radio_rx_stb(radio1_radio_rx_stb), + .radio_rx_running(radio1_radio_rx_running), + .radio_tx_data(radio1_radio_tx_data), + .radio_tx_stb(radio1_radio_tx_stb), + .radio_tx_running(radio1_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // Static Router + // ---------------------------------------------------- + assign s_duc0_in_0_tdata = m_ep0_out0_tdata ; + assign s_duc0_in_0_tlast = m_ep0_out0_tlast ; + assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_duc0_in_0_tready; + + assign s_radio0_in_0_tdata = m_duc0_out_0_tdata ; + assign s_radio0_in_0_tlast = m_duc0_out_0_tlast ; + assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid; + assign m_duc0_out_0_tready = s_radio0_in_0_tready; + + assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata ; + assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast ; + assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ddc0_in_0_tready; + + assign s_ep0_in0_tdata = m_ddc0_out_0_tdata ; + assign s_ep0_in0_tlast = m_ddc0_out_0_tlast ; + assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid; + assign m_ddc0_out_0_tready = s_ep0_in0_tready; + + assign s_duc1_in_0_tdata = m_ep1_out0_tdata ; + assign s_duc1_in_0_tlast = m_ep1_out0_tlast ; + assign s_duc1_in_0_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_duc1_in_0_tready; + + assign s_radio1_in_0_tdata = m_duc1_out_0_tdata ; + assign s_radio1_in_0_tlast = m_duc1_out_0_tlast ; + assign s_radio1_in_0_tvalid = m_duc1_out_0_tvalid; + assign m_duc1_out_0_tready = s_radio1_in_0_tready; + + assign s_ddc1_in_0_tdata = m_radio1_out_0_tdata ; + assign s_ddc1_in_0_tlast = m_radio1_out_0_tlast ; + assign s_ddc1_in_0_tvalid = m_radio1_out_0_tvalid; + assign m_radio1_out_0_tready = s_ddc1_in_0_tready; + + assign s_ep1_in0_tdata = m_ddc1_out_0_tdata ; + assign s_ep1_in0_tlast = m_ddc1_out_0_tlast ; + assign s_ep1_in0_tvalid = m_ddc1_out_0_tvalid; + assign m_ddc1_out_0_tready = s_ep1_in0_tready; + + + // ---------------------------------------------------- + // Unused Ports + // ---------------------------------------------------- + + // ---------------------------------------------------- + // Clock Domains + // ---------------------------------------------------- + assign radio0_radio_clk = radio_clk; + assign ddc0_ce_clk = radio_clk; + assign duc0_ce_clk = radio_clk; + assign radio1_radio_clk = radio_clk; + assign ddc1_ce_clk = radio_clk; + assign duc1_ce_clk = radio_clk; + + + // ---------------------------------------------------- + // IO Port Connection + // ---------------------------------------------------- + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr; + assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd; + assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr; + assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data; + assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en; + assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time; + assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time; + assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack; + assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; + assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign radio1_radio_rx_data = radio_rx_data_radio1; + assign radio1_radio_rx_stb = radio_rx_stb_radio1; + assign radio_rx_running_radio1 = radio1_radio_rx_running; + assign radio_tx_data_radio1 = radio1_radio_tx_data; + assign radio1_radio_tx_stb = radio_tx_stb_radio1; + assign radio_tx_running_radio1 = radio1_radio_tx_running; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time; + + assign radio1_radio_time = radio_time; + +endmodule diff --git a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml new file mode 100644 index 000000000..e107eebc7 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml @@ -0,0 +1,95 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers +license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +version: 1.0 # File version +rfnoc_version: 1.0 # RFNoC protocol version +chdr_width: 64 # Bit width of the CHDR bus for this image +device: 'n320' +default_target: 'N320_HG' + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep1: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + duc0: # NoC block name + block_desc: 'duc.yml' # Block device descriptor file + parameters: + NUM_PORTS: 1 + ddc0: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 1 + radio0: + block_desc: 'radio_1x64.yml' + duc1: + block_desc: 'duc.yml' + parameters: + NUM_PORTS: 1 + ddc1: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 1 + radio1: + block_desc: 'radio_1x64.yml' + #fifo0: + #block_desc: 'axi_ram_fifo_4x64.yml' + #parameters: + ## These parameters match the memory interface on the N3XX + #NUM_PORTS: 4 + #MEM_DATA_W: 64 + #MEM_ADDR_W: 31 + #FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}" + #FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}" + #MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 } + - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } + - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 } + - { srcblk: ep1, srcport: out0, dstblk: duc1, dstport: in_0 } + - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 } + - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 } + - { srcblk: ddc1, srcport: out_0, dstblk: ep1, dstport: in0 } + - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: _device_, srcport: radio_ch0, dstblk: radio0, dstport: radio_iface } + - { srcblk: _device_, srcport: radio_ch1, dstblk: radio1, dstport: radio_iface } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: radio, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: radio, dstblk: ddc1, dstport: ce } + - { srcblk: _device_, srcport: radio, dstblk: duc1, dstport: ce } +# - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem } diff --git a/fpga/usrp3/top/n3xx/n320_static_router.hex b/fpga/usrp3/top/n3xx/n320_static_router.hex new file mode 100644 index 000000000..eeaf5024d --- /dev/null +++ b/fpga/usrp3/top/n3xx/n320_static_router.hex @@ -0,0 +1,9 @@ +00000008 +004000c0 +00c00140 +01400100 +01000040 +00800180 +01800200 +020001c0 +01c00080 diff --git a/fpga/usrp3/top/n3xx/n3xx_clocking.v b/fpga/usrp3/top/n3xx/n3xx_clocking.v new file mode 100644 index 000000000..fc7ecbe49 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_clocking.v @@ -0,0 +1,238 @@ +///////////////////////////////////////////////////////////////////// +// +// Copyright 2017 Ettus Research, A National Instruments Company +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx_clocking.v +// +// Purpose: +// +// First, instantiate clock input buffers on all clocks to provide termination +// for the PCB traces. This file also includes the MMCM for generating meas_clk at +// specific rates and a global buffer for the reference clock to be able to use it +// directly within and outside of this module. +// +// Second, PPS inputs from the back panel (called external) and the GPSDO are captured by +// the Reference Clock. Selection is performed amongst these and the internally-generated +// options. +// +// NOTE: BUFGs are NOT instantiated on the following clocks, denoted by the _buf suffix: +// wr_refclk_buf, netclk_buf, gige_refclk_buf, xgige_refclk_buf +// +////////////////////////////////////////////////////////////////////// + +module n3xx_clocking ( + // Input buffers for clocks + input enable_ref_clk_async, // enables the ref_clk BUFG (driven async to ref_clk) + input FPGA_REFCLK_P, FPGA_REFCLK_N, + output ref_clk, + + input WB_20MHz_P, WB_20MHz_N, + output wr_refclk_buf, + + input NETCLK_REF_P, NETCLK_REF_N, + output netclk_buf, + + input NETCLK_P, NETCLK_N, + output gige_refclk_buf, + + input MGT156MHZ_CLK1_P, MGT156MHZ_CLK1_N, + output xgige_refclk_buf, + + // Measurement Clock Generation + input misc_clks_ref, + output meas_clk, + output ddr3_dma_clk, + input misc_clks_reset, + output misc_clks_locked, + + // PPS Capture & Selection + input ext_pps_from_pin, + input gps_pps_from_pin, + input [3:0] pps_select, + output reg pps_refclk + ); + + // Clock Buffering and Generation : /////////////////////////////////////////////////// + // + // Manually instantiate input buffers on all clocks, and a global buffer on the + // Reference Clock for use in the rest of the design. All other clocks must have + // global buffers other places, since the declarations here are for SI purposes. + // + /////////////////////////////////////////////////////////////////////////////////////// + + wire ref_clk_buf; + + // FPGA Reference Clock Buffering + // + // Only require an IBUF and BUFG here, since an MMCM is (thankfully) not needed + // to meet timing with the PPS signal. + IBUFGDS ref_clk_ibuf ( + .O(ref_clk_buf), + .I(FPGA_REFCLK_P), + .IB(FPGA_REFCLK_N) + ); + + // BUFG ref_clk_bufg ( + // .I(ref_clk_buf), + // .O(ref_clk) + // ); + WrapBufg #( + .kEnableIsAsync(1'b1) + ) ref_clk_bufg ( + .ClkIn(ref_clk_buf), + .aCe(enable_ref_clk_async), + .ClkOut(ref_clk) + ); + + // Buffers for SI Purposes + // + // Instantiate buffers on each of these differential clock inputs with DONT_TOUCH + // attributes in order to preserve the internal termination regardless of whether + // these clocks are used in the design. The lack of termination would place the + // voltage swings for these pins outside the acceptable range for the FPGA inputs. + (* dont_touch = "true" *) IBUFGDS wr_refclk_ibuf ( + .I (WB_20MHz_P), + .IB(WB_20MHz_N), + .O (wr_refclk_buf) + ); + + (* dont_touch = "true" *) IBUFGDS netclk_ref_ibuf ( + .I (NETCLK_REF_P), + .IB(NETCLK_REF_N), + .O (netclk_buf) + ); + + // Same deal for the MGT reference clock buffers. + (* dont_touch = "true" *) IBUFDS_GTE2 gige_refclk_ibuf ( + .ODIV2(), + .CEB (1'b0), + .I (NETCLK_P), + .IB(NETCLK_N), + .O (gige_refclk_buf) + ); + + (* dont_touch = "true" *) IBUFDS_GTE2 ten_gige_refclk_ibuf ( + .ODIV2(), + .CEB (1'b0), + .I (MGT156MHZ_CLK1_P), + .IB(MGT156MHZ_CLK1_N), + .O (xgige_refclk_buf) + ); + + // Measurement Clock MMCM Instantiation + // + // This must be an MMCM to hit the weird rates we need for meas_clk. It takes the + // 166.6667 MHz clock from the PS and provides the correct meas_clk rate for the TDC. + // BUFG is embedded in the MMCM files. + //---------------------------------------------------------------------------- + // Output Output Phase Duty Cycle Pk-to-Pk Phase + // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + //---------------------------------------------------------------------------- + // CLK_OUT1___170.543______0.000______50.0______105.052_____94.905 (meas_clk) + // CLK_OUT2___305.556______0.000______50.0_______93.867_____94.905 (ddr3_dma_clk) + // + //---------------------------------------------------------------------------- + // Input Clock Freq (MHz) Input Jitter (UI) + //---------------------------------------------------------------------------- + // __primary________166.666667____________0.010 + + misc_clock_gen misc_clock_gen_i ( + .clk_in (misc_clks_ref), + .meas_clk (meas_clk), + .ddr3_dma_clk (ddr3_dma_clk), + .reset (misc_clks_reset), + .locked (misc_clks_locked) + ); + + + // PPS Capture and Generation : /////////////////////////////////////////////////////// + // + // The following shows the support matrix for PPS with respect to the + // reference clock source and rate. + // _______________________________ + // ____________| PPS | + // | Clocks | External | FPGA | GPSDO | WR | + // |--------------------------------------------| + // |External 10 | x | x | | | + // |Internal 25 | | x | | x | + // |GPSDO 20 | | | x | | + // |--------------------------------------------| + // + /////////////////////////////////////////////////////////////////////////////////////// + + wire pps_ext_refclk; + wire pps_gps_refclk; + wire [3:0] pps_select_refclk; + + // Generate two internal PPS signals, each with a 25% duty cycle, based on + // 10 MHz and 25 MHz Reference Clock rates. Only one will be used at a time. + wire int_pps_10mhz_refclk; + pps_generator #( + .CLK_FREQ(32'd10_000_000), .DUTY_CYCLE(25) + ) pps_gen_10 ( + .clk(ref_clk), .reset(1'b0), .pps(int_pps_10mhz_refclk) + ); + wire int_pps_25mhz_refclk; + pps_generator #( + .CLK_FREQ(32'd25_000_000), .DUTY_CYCLE(25) + ) pps_gen_25 ( + .clk(ref_clk), .reset(1'b0), .pps(int_pps_25mhz_refclk) + ); + + // Capture the external PPSs with a FF before sending them to the mux. To be safe, + // we double-synchronize the external signals. If we meet timing (which we should) + // then this is a two-cycle delay. If we don't meet timing, then it's 1-2 cycles + // and our system timing is thrown off--but at least our downstream logic doesn't + // go metastable! + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) ext_pps_dsync ( + .clk(ref_clk), .rst(1'b0), .in(ext_pps_from_pin), .out(pps_ext_refclk) + ); + // Same deal with the GPSDO PPS input. Double-sync, then use it. + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) gps_pps_dsync ( + .clk(ref_clk), .rst(1'b0), .in(gps_pps_from_pin), .out(pps_gps_refclk) + ); + + // Synchronize the select bits over to the reference clock as well. Note that this is + // a vector, so we could have some non-one-hot values creep through when changing. + // See the note below as to why this is safe. + synchronizer #( + .FALSE_PATH_TO_IN(1), + .WIDTH(4) + ) pps_select_dsync ( + .clk(ref_clk), .rst(1'b0), .in(pps_select), .out(pps_select_refclk) + ); + + // Bit locations for the pps_select vector. + localparam BIT_PPS_SEL_INT_10 = 0; + localparam BIT_PPS_SEL_INT_25 = 1; + localparam BIT_PPS_SEL_EXT = 2; + localparam BIT_PPS_SEL_GPSDO = 3; + + // PPS MUX - selects internal or external PPS. + always @(posedge ref_clk) begin + + // Encoding is one-hot on these bits. It is possible when the vector is being double- + // synchronized to the reference clock domain that there could be multiple bits + // asserted simultaneously. This is not problematic because the order of operations + // in the following selection mux should take over and only one PPS should win. + // This could result in glitches, but that is expected during ANY PPS switchover + // since the switch is performed asynchronously to the PPS signal. + if (pps_select_refclk[BIT_PPS_SEL_INT_10]) + pps_refclk <= int_pps_10mhz_refclk; + else if (pps_select_refclk[BIT_PPS_SEL_INT_25]) + pps_refclk <= int_pps_25mhz_refclk; + else if (pps_select_refclk[BIT_PPS_SEL_EXT]) + pps_refclk <= pps_ext_refclk; + else if (pps_select_refclk[BIT_PPS_SEL_GPSDO]) + pps_refclk <= pps_gps_refclk; + else + pps_refclk <= pps_ext_refclk; // Compatibility with old SW stacks, pps_select_refclk = 0 = external + + end + +endmodule diff --git a/fpga/usrp3/top/n3xx/n3xx_core.v b/fpga/usrp3/top/n3xx/n3xx_core.v new file mode 100644 index 000000000..676bc782d --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_core.v @@ -0,0 +1,1287 @@ +///////////////////////////////////////////////////////////////////// +// +// Copyright 2017-2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx_core +// Description: +// - Motherboard Registers +// - Crossbar +// - Noc Block Radios +// - Noc Block Dram fifo +// - Radio Front End control +// +///////////////////////////////////////////////////////////////////// + +module n3xx_core #( + parameter REG_DWIDTH = 32, // Width of the AXI4-Lite data bus (must be 32 or 64) + parameter REG_AWIDTH = 32, // Width of the address bus + parameter BUS_CLK_RATE = 200000000, // BUS_CLK rate + parameter CHANNEL_WIDTH = 32, + parameter NUM_CHANNELS_PER_RADIO = 1, + parameter NUM_CHANNELS = 4, + parameter NUM_DBOARDS = 2, + parameter NUM_SPI_PER_DBOARD = 8, + parameter USE_CORRECTION = 0, + parameter USE_REPLAY = 0, // 1 for Replay block instead of DMA FIFO + parameter FP_GPIO_WIDTH = 12, // Front panel GPIO width + parameter RFNOC_PROTOVER = {8'd1, 8'd0}, + parameter CHDR_WIDTH = 16'd64 +)( + // Clocks and resets + input radio_clk, + input radio_rst, + input bus_clk, + input bus_rst, + input ddr3_dma_clk, + input clk40, + + // Clocking and PPS Controls/Indicators + input pps, + output reg[3:0] pps_select = 4'h1, + output reg pps_out_enb, + output reg[1:0] pps_select_sfp = 2'b0, + output reg ref_clk_reset, + output reg meas_clk_reset, + input ref_clk_locked, + input meas_clk_locked, + output reg enable_ref_clk_async, + + // Motherboard Registers: AXI lite interface + input s_axi_aclk, + input s_axi_aresetn, + input [REG_AWIDTH-1:0] s_axi_awaddr, + input s_axi_awvalid, + output s_axi_awready, + + input [REG_DWIDTH-1:0] s_axi_wdata, + input [REG_DWIDTH/8-1:0] s_axi_wstrb, + input s_axi_wvalid, + output s_axi_wready, + + output [1:0] s_axi_bresp, + output s_axi_bvalid, + input s_axi_bready, + + input [REG_AWIDTH-1:0] s_axi_araddr, + input s_axi_arvalid, + output s_axi_arready, + + output [REG_DWIDTH-1:0] s_axi_rdata, + output [1:0] s_axi_rresp, + output s_axi_rvalid, + input s_axi_rready, + + // PS GPIO source + input [FP_GPIO_WIDTH-1:0] ps_gpio_out, + input [FP_GPIO_WIDTH-1:0] ps_gpio_tri, + output [FP_GPIO_WIDTH-1:0] ps_gpio_in, + + // Front Panel GPIO + inout [FP_GPIO_WIDTH-1:0] fp_gpio_inout, + + // Radio GPIO control for DSA + output [16*NUM_CHANNELS-1:0] db_gpio_out_flat, + output [16*NUM_CHANNELS-1:0] db_gpio_ddr_flat, + input [16*NUM_CHANNELS-1:0] db_gpio_in_flat, + input [16*NUM_CHANNELS-1:0] db_gpio_fab_flat, + + // Radio ATR + output [NUM_CHANNELS-1:0] rx_atr, + output [NUM_CHANNELS-1:0] tx_atr, + + // Radio Data + input [NUM_CHANNELS-1:0] rx_stb, + input [NUM_CHANNELS-1:0] tx_stb, + input [CHANNEL_WIDTH*NUM_CHANNELS-1:0] rx, + output [CHANNEL_WIDTH*NUM_CHANNELS-1:0] tx, + + // CPLD + output [NUM_SPI_PER_DBOARD*NUM_DBOARDS-1:0] sen_flat, + output [NUM_DBOARDS-1:0] sclk_flat, + output [NUM_DBOARDS-1:0] mosi_flat, + input [NUM_DBOARDS-1:0] miso_flat, + + // DMA xport adapter to PS + input wire [63:0] s_dma_tdata, + input wire [3:0] s_dma_tuser, + input wire s_dma_tlast, + output wire s_dma_tready, + input wire s_dma_tvalid, + + output wire [63:0] m_dma_tdata, + output wire [3:0] m_dma_tdest, + output wire m_dma_tlast, + input wire m_dma_tready, + output wire m_dma_tvalid, + + // AXI4 (256b@200MHz) interface to DDR3 controller + input ddr3_axi_clk, + input ddr3_axi_rst, + input ddr3_running, + // Write Address Ports + output [3:0] ddr3_axi_awid, + output [31:0] ddr3_axi_awaddr, + output [7:0] ddr3_axi_awlen, + output [2:0] ddr3_axi_awsize, + output [1:0] ddr3_axi_awburst, + output [0:0] ddr3_axi_awlock, + output [3:0] ddr3_axi_awcache, + output [2:0] ddr3_axi_awprot, + output [3:0] ddr3_axi_awqos, + output ddr3_axi_awvalid, + input ddr3_axi_awready, + // Write Data Ports + output [255:0] ddr3_axi_wdata, + output [31:0] ddr3_axi_wstrb, + output ddr3_axi_wlast, + output ddr3_axi_wvalid, + input ddr3_axi_wready, + // Write Response Ports + output ddr3_axi_bready, + input [3:0] ddr3_axi_bid, + input [1:0] ddr3_axi_bresp, + input ddr3_axi_bvalid, + // Read Address Ports + output [3:0] ddr3_axi_arid, + output [31:0] ddr3_axi_araddr, + output [7:0] ddr3_axi_arlen, + output [2:0] ddr3_axi_arsize, + output [1:0] ddr3_axi_arburst, + output [0:0] ddr3_axi_arlock, + output [3:0] ddr3_axi_arcache, + output [2:0] ddr3_axi_arprot, + output [3:0] ddr3_axi_arqos, + output ddr3_axi_arvalid, + input ddr3_axi_arready, + // Read Data Ports + output ddr3_axi_rready, + input [3:0] ddr3_axi_rid, + input [255:0] ddr3_axi_rdata, + input [1:0] ddr3_axi_rresp, + input ddr3_axi_rlast, + input ddr3_axi_rvalid, + + // v2e (vita to ethernet) and e2v (eth to vita) + output [63:0] v2e0_tdata, + output v2e0_tvalid, + output v2e0_tlast, + input v2e0_tready, + + output [63:0] v2e1_tdata, + output v2e1_tlast, + output v2e1_tvalid, + input v2e1_tready, + + input [63:0] e2v0_tdata, + input e2v0_tlast, + input e2v0_tvalid, + output e2v0_tready, + + input [63:0] e2v1_tdata, + input e2v1_tlast, + input e2v1_tvalid, + output e2v1_tready, + + // RegPort interface to NPIO + output reg_wr_req_npio, + output [REG_AWIDTH-1:0] reg_wr_addr_npio, + output [REG_DWIDTH-1:0] reg_wr_data_npio, + output reg_rd_req_npio, + output [REG_AWIDTH-1:0] reg_rd_addr_npio, + input reg_rd_resp_npio, + input [REG_DWIDTH-1:0] reg_rd_data_npio, + + // Misc + input [31:0] build_datestamp, + input [31:0] xadc_readback, + input [63:0] sfp_ports_info, + output reg [15:0] device_id +); + + ///////////////////////////////////////////////////////////////////////////////// + // + // FPGA Compatibility Number + // Rules for modifying compat number: + // - Major is updated when the FPGA is changed and requires a software + // change as a result. + // - Minor is updated when a new feature is added to the FPGA that does not + // break software compatibility. + // + ///////////////////////////////////////////////////////////////////////////////// + + localparam [15:0] COMPAT_MAJOR = 16'd7; + localparam [15:0] COMPAT_MINOR = 16'd0; + ///////////////////////////////////////////////////////////////////////////////// + + ///////////////////////////////////////////////////////////////////////////////// + // Motherboard Registers + ///////////////////////////////////////////////////////////////////////////////// + + // Register base + localparam REG_BASE_MISC = 14'h0; + localparam REG_BASE_TIMEKEEPER = 14'h1000; + + // Misc Motherboard Registers + localparam REG_COMPAT_NUM = REG_BASE_MISC + 14'h00; + localparam REG_DATESTAMP = REG_BASE_MISC + 14'h04; + localparam REG_GIT_HASH = REG_BASE_MISC + 14'h08; + localparam REG_SCRATCH = REG_BASE_MISC + 14'h0C; + localparam REG_DEVICE_ID = REG_BASE_MISC + 14'h10; + localparam REG_RFNOC_INFO = REG_BASE_MISC + 14'h14; + localparam REG_CLOCK_CTRL = REG_BASE_MISC + 14'h18; + localparam REG_XADC_READBACK = REG_BASE_MISC + 14'h1C; + localparam REG_BUS_CLK_RATE = REG_BASE_MISC + 14'h20; + localparam REG_BUS_CLK_COUNT = REG_BASE_MISC + 14'h24; + localparam REG_SFP_PORT0_INFO = REG_BASE_MISC + 14'h28; + localparam REG_SFP_PORT1_INFO = REG_BASE_MISC + 14'h2C; + localparam REG_FP_GPIO_MASTER = REG_BASE_MISC + 14'h30; + localparam REG_FP_GPIO_RADIO_SRC = REG_BASE_MISC + 14'h34; + localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48; + + localparam NUM_TIMEKEEPERS = 16'd1; + + wire m_ctrlport_req_wr_radio0; + wire m_ctrlport_req_rd_radio0; + wire [19:0] m_ctrlport_req_addr_radio0; + wire [31:0] m_ctrlport_req_data_radio0; + wire [3:0] m_ctrlport_req_byte_en_radio0; + wire m_ctrlport_req_has_time_radio0; + wire [63:0] m_ctrlport_req_time_radio0; + wire m_ctrlport_resp_ack_radio0; + wire [1:0] m_ctrlport_resp_status_radio0; + wire [31:0] m_ctrlport_resp_data_radio0; + `ifndef N300 + wire m_ctrlport_req_wr_radio1; + wire m_ctrlport_req_rd_radio1; + wire [19:0] m_ctrlport_req_addr_radio1; + wire [31:0] m_ctrlport_req_data_radio1; + wire [3:0] m_ctrlport_req_byte_en_radio1; + wire m_ctrlport_req_has_time_radio1; + wire [63:0] m_ctrlport_req_time_radio1; + wire m_ctrlport_resp_ack_radio1; + wire [1:0] m_ctrlport_resp_status_radio1; + wire [31:0] m_ctrlport_resp_data_radio1; + `endif + + reg [31:0] scratch_reg = 32'b0; + reg [31:0] bus_counter = 32'h0; + reg [31:0] fp_gpio_master_reg = 32'h0; + reg [31:0] fp_gpio_src_reg = 32'h0; + + always @(posedge bus_clk) begin + if (bus_rst) + bus_counter <= 32'd0; + else + bus_counter <= bus_counter + 32'd1; + end + + // Regport + wire reg_wr_req; + wire [REG_AWIDTH-1:0] reg_wr_addr; + wire [REG_DWIDTH-1:0] reg_wr_data; + wire reg_rd_req; + wire [REG_AWIDTH-1:0] reg_rd_addr; + wire reg_rd_resp; + wire [REG_DWIDTH-1:0] reg_rd_data; + + reg reg_rd_resp_glob; + reg [REG_DWIDTH-1:0] reg_rd_data_glob; + wire reg_rd_resp_tk; + wire [REG_DWIDTH-1:0] reg_rd_data_tk; + + regport_resp_mux #( + .WIDTH(REG_DWIDTH), + .NUM_SLAVES(3) + ) inst_mboard_regport_resp_mux ( + .clk(bus_clk), + .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_npio, reg_rd_resp_glob, reg_rd_resp_tk}), + .sla_rd_data({reg_rd_data_npio, reg_rd_data_glob, reg_rd_data_tk}), + .mst_rd_resp(reg_rd_resp), + .mst_rd_data(reg_rd_data) + ); + + // Regport Master to convert AXI4-Lite to regport + axil_regport_master #( + .DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .AWIDTH (REG_AWIDTH), // Width of the address bus + .WRBASE (0), // Write address base + .RDBASE (0), // Read address base + .TIMEOUT (10) // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles + ) mboard_regport_master_i ( + // Clock and reset + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp (s_axi_bresp), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (s_axi_rdata), + .s_axi_rresp (s_axi_rresp), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + // Register port: Write port (domain: reg_clk) + .reg_clk (bus_clk), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_wr_keep (/*unused*/), + // Register port: Read port (domain: reg_clk) + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp), + .reg_rd_data (reg_rd_data) + ); + + assign reg_wr_req_npio = reg_wr_req; + assign reg_wr_addr_npio = reg_wr_addr; + assign reg_wr_data_npio = reg_wr_data; + assign reg_rd_req_npio = reg_rd_req; + assign reg_rd_addr_npio = reg_rd_addr; + + reg b_ref_clk_locked_ms; + reg b_ref_clk_locked; + reg b_meas_clk_locked_ms; + reg b_meas_clk_locked; + + // Write Registers + always @ (posedge bus_clk) begin + if (bus_rst) begin + scratch_reg <= 32'h0; + fp_gpio_master_reg <= 32'h0; + fp_gpio_src_reg <= 32'h0; + pps_select <= 4'h1; + pps_select_sfp <= 2'h0; + pps_out_enb <= 1'b0; + ref_clk_reset <= 1'b0; + meas_clk_reset <= 1'b0; + enable_ref_clk_async <= 1'b1; + device_id <= 16'h0; + end else if (reg_wr_req) begin + case (reg_wr_addr) + REG_DEVICE_ID: begin + device_id <= reg_wr_data[15:0]; + end + REG_FP_GPIO_MASTER: begin + fp_gpio_master_reg <= reg_wr_data; + end + REG_FP_GPIO_RADIO_SRC: begin + fp_gpio_src_reg <= reg_wr_data; + end + REG_SCRATCH: begin + scratch_reg <= reg_wr_data; + end + REG_CLOCK_CTRL: begin + pps_select <= reg_wr_data[3:0]; + pps_out_enb <= reg_wr_data[4]; + pps_select_sfp <= reg_wr_data[6:5]; + ref_clk_reset <= reg_wr_data[8]; + meas_clk_reset <= reg_wr_data[12]; + // This bit is defined as "to disable, write '1' to bit 16" for backwards + // compatibility. + enable_ref_clk_async <= ~reg_wr_data[16]; + end + endcase + end + end + + // Read Registers + always @ (posedge bus_clk) begin + if (bus_rst) begin + reg_rd_resp_glob <= 1'b0; + b_ref_clk_locked_ms <= 1'b0; + b_ref_clk_locked <= 1'b0; + b_meas_clk_locked_ms <= 1'b0; + b_meas_clk_locked <= 1'b0; + end + else begin + + // double-sync the locked bits into the bus_clk domain before using them + b_ref_clk_locked_ms <= ref_clk_locked; + b_ref_clk_locked <= b_ref_clk_locked_ms; + b_meas_clk_locked_ms <= meas_clk_locked; + b_meas_clk_locked <= b_meas_clk_locked_ms; + + if (reg_rd_req) begin + reg_rd_resp_glob <= 1'b1; + + case (reg_rd_addr) + REG_DEVICE_ID: + reg_rd_data_glob <= device_id; + + REG_RFNOC_INFO: + reg_rd_data_glob <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]}; + + REG_COMPAT_NUM: + reg_rd_data_glob <= {COMPAT_MAJOR, COMPAT_MINOR}; + + REG_DATESTAMP: + reg_rd_data_glob <= build_datestamp; + + REG_GIT_HASH: + `ifndef GIT_HASH + `define GIT_HASH 32'h0BADC0DE + `endif + reg_rd_data_glob <= `GIT_HASH; + + REG_FP_GPIO_MASTER: + reg_rd_data_glob <= fp_gpio_master_reg; + + REG_FP_GPIO_RADIO_SRC: + reg_rd_data_glob <= fp_gpio_src_reg; + + REG_SCRATCH: + reg_rd_data_glob <= scratch_reg; + + REG_CLOCK_CTRL: begin + reg_rd_data_glob <= 32'b0; + reg_rd_data_glob[3:0] <= pps_select; + reg_rd_data_glob[4] <= pps_out_enb; + reg_rd_data_glob[6:5] <= pps_select_sfp; + reg_rd_data_glob[8] <= ref_clk_reset; + reg_rd_data_glob[9] <= b_ref_clk_locked; + reg_rd_data_glob[12] <= meas_clk_reset; + reg_rd_data_glob[13] <= b_meas_clk_locked; + reg_rd_data_glob[16] <= ~enable_ref_clk_async; + end + + REG_XADC_READBACK: + reg_rd_data_glob <= xadc_readback; + + REG_BUS_CLK_RATE: + reg_rd_data_glob <= BUS_CLK_RATE; + + REG_BUS_CLK_COUNT: + reg_rd_data_glob <= bus_counter; + + REG_SFP_PORT0_INFO: + reg_rd_data_glob <= sfp_ports_info[31:0]; + + REG_SFP_PORT1_INFO: + reg_rd_data_glob <= sfp_ports_info[63:32]; + + REG_NUM_TIMEKEEPERS: + reg_rd_data_glob <= NUM_TIMEKEEPERS; + + default: + reg_rd_resp_glob <= 1'b0; + endcase + end + else if (reg_rd_resp_glob) begin + reg_rd_resp_glob <= 1'b0; + end + end + end + + ///////////////////////////////////////////////////////////////////////////// + // + // DMA Transport Adapter + // + ///////////////////////////////////////////////////////////////////////////// + wire [63:0] dmao_tdata; + wire dmao_tlast; + wire dmao_tvalid; + wire dmao_tready; + + wire [63:0] dmai_tdata; + wire dmai_tlast; + wire dmai_tvalid; + wire dmai_tready; + + liberio_chdr64_adapter #( + .DMA_ID_WIDTH (4) + ) dma_xport_adapter ( + .clk (bus_clk), + .rst (bus_rst), + .device_id (device_id), + // From DMA engine to core + .s_dma_tdata (s_dma_tdata), + .s_dma_tuser (s_dma_tuser), + .s_dma_tlast (s_dma_tlast), + .s_dma_tvalid (s_dma_tvalid), + .s_dma_tready (s_dma_tready), + // From core to DMA engine + .m_dma_tdata (m_dma_tdata), + .m_dma_tuser (m_dma_tdest), + .m_dma_tlast (m_dma_tlast), + .m_dma_tvalid (m_dma_tvalid), + .m_dma_tready (m_dma_tready), + // CHDR buses + .s_chdr_tdata (dmao_tdata), + .s_chdr_tlast (dmao_tlast), + .s_chdr_tvalid (dmao_tvalid), + .s_chdr_tready (dmao_tready), + .m_chdr_tdata (dmai_tdata), + .m_chdr_tlast (dmai_tlast), + .m_chdr_tvalid (dmai_tvalid), + .m_chdr_tready (dmai_tready) + ); + + ///////////////////////////////////////////////////////////////////// + // + // AXI Interconnect + // + ///////////////////////////////////////////////////////////////////// + + localparam NUM_DRAM_FIFOS = 4; + localparam DRAM_FIFO_INPUT_BUFF_SIZE = 8'd13; + + wire ddr3_dma_rst; + synchronizer #( + .INITIAL_VAL(1'b1) + ) ddr3_dma_rst_sync_i ( + .clk(ddr3_dma_clk), .rst(1'b0), .in(ddr3_axi_rst), .out(ddr3_dma_rst) + ); + + // AXI4 MM buses + wire [0:0] dram_axi_awid [0:NUM_DRAM_FIFOS-1]; + wire [31:0] dram_axi_awaddr [0:NUM_DRAM_FIFOS-1]; + wire [7:0] dram_axi_awlen [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_awsize [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_awburst [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_awlock [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_awcache [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_awprot [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_awqos [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_awregion [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_awuser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_awvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_awready [0:NUM_DRAM_FIFOS-1]; + wire [63:0] dram_axi_wdata [0:NUM_DRAM_FIFOS-1]; + wire [7:0] dram_axi_wstrb [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_wlast [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_wuser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_wvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_wready [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_bid [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_bresp [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_buser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_bvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_bready [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_arid [0:NUM_DRAM_FIFOS-1]; + wire [31:0] dram_axi_araddr [0:NUM_DRAM_FIFOS-1]; + wire [7:0] dram_axi_arlen [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_arsize [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_arburst [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_arlock [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_arcache [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_arprot [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_arqos [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_arregion [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_aruser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_arvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_arready [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_rid [0:NUM_DRAM_FIFOS-1]; + wire [63:0] dram_axi_rdata [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_rresp [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_rlast [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_ruser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_rvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_rready [0:NUM_DRAM_FIFOS-1]; + + axi_intercon_4x64_256_bd_wrapper axi_intercon_2x64_256_bd_i ( + .S00_AXI_ACLK (ddr3_dma_clk ), + .S00_AXI_ARESETN (~ddr3_dma_rst ), + .S00_AXI_AWID (dram_axi_awid [0]), + .S00_AXI_AWADDR (dram_axi_awaddr [0]), + .S00_AXI_AWLEN (dram_axi_awlen [0]), + .S00_AXI_AWSIZE (dram_axi_awsize [0]), + .S00_AXI_AWBURST (dram_axi_awburst [0]), + .S00_AXI_AWLOCK (dram_axi_awlock [0]), + .S00_AXI_AWCACHE (dram_axi_awcache [0]), + .S00_AXI_AWPROT (dram_axi_awprot [0]), + .S00_AXI_AWQOS (dram_axi_awqos [0]), + .S00_AXI_AWREGION (dram_axi_awregion[0]), + .S00_AXI_AWVALID (dram_axi_awvalid [0]), + .S00_AXI_AWREADY (dram_axi_awready [0]), + .S00_AXI_WDATA (dram_axi_wdata [0]), + .S00_AXI_WSTRB (dram_axi_wstrb [0]), + .S00_AXI_WLAST (dram_axi_wlast [0]), + .S00_AXI_WVALID (dram_axi_wvalid [0]), + .S00_AXI_WREADY (dram_axi_wready [0]), + .S00_AXI_BID (dram_axi_bid [0]), + .S00_AXI_BRESP (dram_axi_bresp [0]), + .S00_AXI_BVALID (dram_axi_bvalid [0]), + .S00_AXI_BREADY (dram_axi_bready [0]), + .S00_AXI_ARID (dram_axi_arid [0]), + .S00_AXI_ARADDR (dram_axi_araddr [0]), + .S00_AXI_ARLEN (dram_axi_arlen [0]), + .S00_AXI_ARSIZE (dram_axi_arsize [0]), + .S00_AXI_ARBURST (dram_axi_arburst [0]), + .S00_AXI_ARLOCK (dram_axi_arlock [0]), + .S00_AXI_ARCACHE (dram_axi_arcache [0]), + .S00_AXI_ARPROT (dram_axi_arprot [0]), + .S00_AXI_ARQOS (dram_axi_arqos [0]), + .S00_AXI_ARREGION (dram_axi_arregion[0]), + .S00_AXI_ARVALID (dram_axi_arvalid [0]), + .S00_AXI_ARREADY (dram_axi_arready [0]), + .S00_AXI_RID (dram_axi_rid [0]), + .S00_AXI_RDATA (dram_axi_rdata [0]), + .S00_AXI_RRESP (dram_axi_rresp [0]), + .S00_AXI_RLAST (dram_axi_rlast [0]), + .S00_AXI_RVALID (dram_axi_rvalid [0]), + .S00_AXI_RREADY (dram_axi_rready [0]), + // + .S01_AXI_ACLK (ddr3_dma_clk ), + .S01_AXI_ARESETN (~ddr3_dma_rst ), + .S01_AXI_AWID (dram_axi_awid [1]), + .S01_AXI_AWADDR (dram_axi_awaddr [1]), + .S01_AXI_AWLEN (dram_axi_awlen [1]), + .S01_AXI_AWSIZE (dram_axi_awsize [1]), + .S01_AXI_AWBURST (dram_axi_awburst [1]), + .S01_AXI_AWLOCK (dram_axi_awlock [1]), + .S01_AXI_AWCACHE (dram_axi_awcache [1]), + .S01_AXI_AWPROT (dram_axi_awprot [1]), + .S01_AXI_AWQOS (dram_axi_awqos [1]), + .S01_AXI_AWREGION (dram_axi_awregion[1]), + .S01_AXI_AWVALID (dram_axi_awvalid [1]), + .S01_AXI_AWREADY (dram_axi_awready [1]), + .S01_AXI_WDATA (dram_axi_wdata [1]), + .S01_AXI_WSTRB (dram_axi_wstrb [1]), + .S01_AXI_WLAST (dram_axi_wlast [1]), + .S01_AXI_WVALID (dram_axi_wvalid [1]), + .S01_AXI_WREADY (dram_axi_wready [1]), + .S01_AXI_BID (dram_axi_bid [1]), + .S01_AXI_BRESP (dram_axi_bresp [1]), + .S01_AXI_BVALID (dram_axi_bvalid [1]), + .S01_AXI_BREADY (dram_axi_bready [1]), + .S01_AXI_ARID (dram_axi_arid [1]), + .S01_AXI_ARADDR (dram_axi_araddr [1]), + .S01_AXI_ARLEN (dram_axi_arlen [1]), + .S01_AXI_ARSIZE (dram_axi_arsize [1]), + .S01_AXI_ARBURST (dram_axi_arburst [1]), + .S01_AXI_ARLOCK (dram_axi_arlock [1]), + .S01_AXI_ARCACHE (dram_axi_arcache [1]), + .S01_AXI_ARPROT (dram_axi_arprot [1]), + .S01_AXI_ARQOS (dram_axi_arqos [1]), + .S01_AXI_ARREGION (dram_axi_arregion[1]), + .S01_AXI_ARVALID (dram_axi_arvalid [1]), + .S01_AXI_ARREADY (dram_axi_arready [1]), + .S01_AXI_RID (dram_axi_rid [1]), + .S01_AXI_RDATA (dram_axi_rdata [1]), + .S01_AXI_RRESP (dram_axi_rresp [1]), + .S01_AXI_RLAST (dram_axi_rlast [1]), + .S01_AXI_RVALID (dram_axi_rvalid [1]), + .S01_AXI_RREADY (dram_axi_rready [1]), + // + .S02_AXI_ACLK (ddr3_dma_clk ), + .S02_AXI_ARESETN (~ddr3_dma_rst ), + .S02_AXI_AWID (dram_axi_awid [2]), + .S02_AXI_AWADDR (dram_axi_awaddr [2]), + .S02_AXI_AWLEN (dram_axi_awlen [2]), + .S02_AXI_AWSIZE (dram_axi_awsize [2]), + .S02_AXI_AWBURST (dram_axi_awburst [2]), + .S02_AXI_AWLOCK (dram_axi_awlock [2]), + .S02_AXI_AWCACHE (dram_axi_awcache [2]), + .S02_AXI_AWPROT (dram_axi_awprot [2]), + .S02_AXI_AWQOS (dram_axi_awqos [2]), + .S02_AXI_AWREGION (dram_axi_awregion[2]), + .S02_AXI_AWVALID (dram_axi_awvalid [2]), + .S02_AXI_AWREADY (dram_axi_awready [2]), + .S02_AXI_WDATA (dram_axi_wdata [2]), + .S02_AXI_WSTRB (dram_axi_wstrb [2]), + .S02_AXI_WLAST (dram_axi_wlast [2]), + .S02_AXI_WVALID (dram_axi_wvalid [2]), + .S02_AXI_WREADY (dram_axi_wready [2]), + .S02_AXI_BID (dram_axi_bid [2]), + .S02_AXI_BRESP (dram_axi_bresp [2]), + .S02_AXI_BVALID (dram_axi_bvalid [2]), + .S02_AXI_BREADY (dram_axi_bready [2]), + .S02_AXI_ARID (dram_axi_arid [2]), + .S02_AXI_ARADDR (dram_axi_araddr [2]), + .S02_AXI_ARLEN (dram_axi_arlen [2]), + .S02_AXI_ARSIZE (dram_axi_arsize [2]), + .S02_AXI_ARBURST (dram_axi_arburst [2]), + .S02_AXI_ARLOCK (dram_axi_arlock [2]), + .S02_AXI_ARCACHE (dram_axi_arcache [2]), + .S02_AXI_ARPROT (dram_axi_arprot [2]), + .S02_AXI_ARQOS (dram_axi_arqos [2]), + .S02_AXI_ARREGION (dram_axi_arregion[2]), + .S02_AXI_ARVALID (dram_axi_arvalid [2]), + .S02_AXI_ARREADY (dram_axi_arready [2]), + .S02_AXI_RID (dram_axi_rid [2]), + .S02_AXI_RDATA (dram_axi_rdata [2]), + .S02_AXI_RRESP (dram_axi_rresp [2]), + .S02_AXI_RLAST (dram_axi_rlast [2]), + .S02_AXI_RVALID (dram_axi_rvalid [2]), + .S02_AXI_RREADY (dram_axi_rready [2]), + // + .S03_AXI_ACLK (ddr3_dma_clk ), + .S03_AXI_ARESETN (~ddr3_dma_rst ), + .S03_AXI_AWID (dram_axi_awid [3]), + .S03_AXI_AWADDR (dram_axi_awaddr [3]), + .S03_AXI_AWLEN (dram_axi_awlen [3]), + .S03_AXI_AWSIZE (dram_axi_awsize [3]), + .S03_AXI_AWBURST (dram_axi_awburst [3]), + .S03_AXI_AWLOCK (dram_axi_awlock [3]), + .S03_AXI_AWCACHE (dram_axi_awcache [3]), + .S03_AXI_AWPROT (dram_axi_awprot [3]), + .S03_AXI_AWQOS (dram_axi_awqos [3]), + .S03_AXI_AWREGION (dram_axi_awregion[3]), + .S03_AXI_AWVALID (dram_axi_awvalid [3]), + .S03_AXI_AWREADY (dram_axi_awready [3]), + .S03_AXI_WDATA (dram_axi_wdata [3]), + .S03_AXI_WSTRB (dram_axi_wstrb [3]), + .S03_AXI_WLAST (dram_axi_wlast [3]), + .S03_AXI_WVALID (dram_axi_wvalid [3]), + .S03_AXI_WREADY (dram_axi_wready [3]), + .S03_AXI_BID (dram_axi_bid [3]), + .S03_AXI_BRESP (dram_axi_bresp [3]), + .S03_AXI_BVALID (dram_axi_bvalid [3]), + .S03_AXI_BREADY (dram_axi_bready [3]), + .S03_AXI_ARID (dram_axi_arid [3]), + .S03_AXI_ARADDR (dram_axi_araddr [3]), + .S03_AXI_ARLEN (dram_axi_arlen [3]), + .S03_AXI_ARSIZE (dram_axi_arsize [3]), + .S03_AXI_ARBURST (dram_axi_arburst [3]), + .S03_AXI_ARLOCK (dram_axi_arlock [3]), + .S03_AXI_ARCACHE (dram_axi_arcache [3]), + .S03_AXI_ARPROT (dram_axi_arprot [3]), + .S03_AXI_ARQOS (dram_axi_arqos [3]), + .S03_AXI_ARREGION (dram_axi_arregion[3]), + .S03_AXI_ARVALID (dram_axi_arvalid [3]), + .S03_AXI_ARREADY (dram_axi_arready [3]), + .S03_AXI_RID (dram_axi_rid [3]), + .S03_AXI_RDATA (dram_axi_rdata [3]), + .S03_AXI_RRESP (dram_axi_rresp [3]), + .S03_AXI_RLAST (dram_axi_rlast [3]), + .S03_AXI_RVALID (dram_axi_rvalid [3]), + .S03_AXI_RREADY (dram_axi_rready [3]), + // + .M00_AXI_ACLK (ddr3_axi_clk ), + .M00_AXI_ARESETN (~ddr3_axi_rst ), + .M00_AXI_AWID (ddr3_axi_awid ), + .M00_AXI_AWADDR (ddr3_axi_awaddr ), + .M00_AXI_AWLEN (ddr3_axi_awlen ), + .M00_AXI_AWSIZE (ddr3_axi_awsize ), + .M00_AXI_AWBURST (ddr3_axi_awburst ), + .M00_AXI_AWLOCK (ddr3_axi_awlock ), + .M00_AXI_AWCACHE (ddr3_axi_awcache ), + .M00_AXI_AWPROT (ddr3_axi_awprot ), + .M00_AXI_AWQOS (ddr3_axi_awqos ), + .M00_AXI_AWREGION ( ), + .M00_AXI_AWVALID (ddr3_axi_awvalid ), + .M00_AXI_AWREADY (ddr3_axi_awready ), + .M00_AXI_WDATA (ddr3_axi_wdata ), + .M00_AXI_WSTRB (ddr3_axi_wstrb ), + .M00_AXI_WLAST (ddr3_axi_wlast ), + .M00_AXI_WVALID (ddr3_axi_wvalid ), + .M00_AXI_WREADY (ddr3_axi_wready ), + .M00_AXI_BID (ddr3_axi_bid ), + .M00_AXI_BRESP (ddr3_axi_bresp ), + .M00_AXI_BVALID (ddr3_axi_bvalid ), + .M00_AXI_BREADY (ddr3_axi_bready ), + .M00_AXI_ARID (ddr3_axi_arid ), + .M00_AXI_ARADDR (ddr3_axi_araddr ), + .M00_AXI_ARLEN (ddr3_axi_arlen ), + .M00_AXI_ARSIZE (ddr3_axi_arsize ), + .M00_AXI_ARBURST (ddr3_axi_arburst ), + .M00_AXI_ARLOCK (ddr3_axi_arlock ), + .M00_AXI_ARCACHE (ddr3_axi_arcache ), + .M00_AXI_ARPROT (ddr3_axi_arprot ), + .M00_AXI_ARQOS (ddr3_axi_arqos ), + .M00_AXI_ARREGION ( ), + .M00_AXI_ARVALID (ddr3_axi_arvalid ), + .M00_AXI_ARREADY (ddr3_axi_arready ), + .M00_AXI_RID (ddr3_axi_rid ), + .M00_AXI_RDATA (ddr3_axi_rdata ), + .M00_AXI_RRESP (ddr3_axi_rresp ), + .M00_AXI_RLAST (ddr3_axi_rlast ), + .M00_AXI_RVALID (ddr3_axi_rvalid ), + .M00_AXI_RREADY (ddr3_axi_rready ) + ); + + + ///////////////////////////////////////////////////////////////////////////// + // + // Radios + // + ///////////////////////////////////////////////////////////////////////////// + + + wire [NUM_SPI_PER_DBOARD-1:0] sen[0:NUM_CHANNELS-1]; + wire sclk[0:NUM_CHANNELS-1], mosi[0:NUM_CHANNELS-1], miso[0:NUM_CHANNELS-1]; + // Data + wire [CHANNEL_WIDTH-1:0] rx_int[0:NUM_CHANNELS-1], tx_int[0:NUM_CHANNELS-1]; + wire [CHANNEL_WIDTH-1:0] rx_data[0:NUM_CHANNELS-1], tx_data[0:NUM_CHANNELS-1]; + wire db_fe_set_stb[0:NUM_CHANNELS-1]; + wire [7:0] db_fe_set_addr[0:NUM_CHANNELS-1]; + wire [31:0] db_fe_set_data[0:NUM_CHANNELS-1]; + wire db_fe_rb_stb[0:NUM_CHANNELS-1]; + wire [7:0] db_fe_rb_addr[0:NUM_CHANNELS-1]; + wire [63:0] db_fe_rb_data[0:NUM_CHANNELS-1]; + wire rx_running[0:NUM_CHANNELS-1], tx_running[0:NUM_CHANNELS-1]; + + genvar i; + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: gen_gpio_control + assign rx_atr[i] = rx_running[i]; + assign tx_atr[i] = tx_running[i]; + end + endgenerate + + + ///////////////////////////////////////////////////////////////////////////////// + // + // TX/RX FrontEnd + // + ///////////////////////////////////////////////////////////////////////////////// + + wire [15:0] db_gpio_in[0:NUM_CHANNELS-1]; + wire [15:0] db_gpio_out[0:NUM_CHANNELS-1]; + wire [15:0] db_gpio_ddr[0:NUM_CHANNELS-1]; + wire [15:0] db_gpio_fab[0:NUM_CHANNELS-1]; + + wire [31:0] radio_gpio_out[0:NUM_CHANNELS-1]; + wire [31:0] radio_gpio_ddr[0:NUM_CHANNELS-1]; + wire [31:0] radio_gpio_in[0:NUM_CHANNELS-1]; + wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_out; + reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_out_reg; + wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr; + reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr_reg; + reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_in; + wire [FP_GPIO_WIDTH-1:0] radio_gpio_sync; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_in_int; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_out_int; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_ddr_int; + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + // Radio Data + assign rx_int[i] = rx[CHANNEL_WIDTH*i +: CHANNEL_WIDTH]; + assign tx[CHANNEL_WIDTH*i +: CHANNEL_WIDTH] = tx_int[i]; + // GPIO + assign db_gpio_out_flat[16*i+15:16*i] = db_gpio_out[i]; + assign db_gpio_ddr_flat[16*i+15:16*i] = db_gpio_ddr[i]; + assign db_gpio_in[i] = db_gpio_in_flat[16*i+15:16*i]; + assign db_gpio_fab[i] = db_gpio_fab_flat[16*i+15:16*i]; + end + endgenerate + + generate if (NUM_CHANNELS_PER_RADIO == 1) + begin + for (i = 0; i < NUM_DBOARDS; i = i + 1) begin + // SPI + assign miso[i] = miso_flat[i]; + assign sclk_flat[i] = sclk[i]; + assign sen_flat[NUM_SPI_PER_DBOARD*i +: NUM_SPI_PER_DBOARD] = sen[i]; + assign mosi_flat[i] = mosi[i]; + end + end else if (NUM_CHANNELS_PER_RADIO == 2) + begin + for (i = 0; i < NUM_DBOARDS; i = i + 1) begin + // SPI + assign miso[2*i] = miso_flat[i]; + assign sclk_flat[i] = sclk[2*i]; + assign sen_flat[NUM_SPI_PER_DBOARD*i +: NUM_SPI_PER_DBOARD] = sen[2*i]; + assign mosi_flat[i] = mosi[2*i]; + end + end + endgenerate + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + n3xx_db_fe_core #( + .USE_CORRECTION(USE_CORRECTION), + .NUM_SPI_SEN(NUM_SPI_PER_DBOARD), + .WIDTH(CHANNEL_WIDTH) + ) db_fe_core_i ( + .clk(radio_clk), + .reset(radio_rst), + .set_stb(db_fe_set_stb[i]), + .set_addr(db_fe_set_addr[i]), + .set_data(db_fe_set_data[i]), + .rb_stb(db_fe_rb_stb[i]), + .rb_addr(db_fe_rb_addr[i]), + .rb_data(db_fe_rb_data[i]), + .tx_stb(tx_stb[i]), + .tx_data_in(tx_data[i]), + .tx_data_out(tx_int[i]), + .tx_running(tx_running[i]), + .rx_stb(rx_stb[i]), + .rx_data_in(rx_int[i]), + .rx_data_out(rx_data[i]), + .rx_running(rx_running[i]), + .misc_ins(32'h0), + .misc_outs(), + .fp_gpio_in(radio_gpio_in[i]), + .fp_gpio_out(radio_gpio_out[i]), + .fp_gpio_ddr(radio_gpio_ddr[i]), + .fp_gpio_fab(32'h0), + .db_gpio_in(db_gpio_in[i]), + .db_gpio_out(db_gpio_out[i]), + .db_gpio_ddr(db_gpio_ddr[i]), + .db_gpio_fab(db_gpio_fab[i]), + .leds(), + .spi_clk(radio_clk), + .spi_rst(radio_rst), + .sen(sen[i]), + .sclk(sclk[i]), + .mosi(mosi[i]), + .miso(miso[i]) + ); + end + endgenerate + + // Front panel GPIOs logic + // Double-sync for the GPIO inputs to the PS and to the Radio blocks. + synchronizer #( + .INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH) + ) ps_gpio_in_sync_i ( + .clk(bus_clk), .rst(1'b0), .in(fp_gpio_in_int), .out(ps_gpio_in) + ); + synchronizer #( + .INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH) + ) radio_gpio_in_sync_i ( + .clk(radio_clk), .rst(1'b0), .in(fp_gpio_in_int), .out(radio_gpio_sync) + ); + + generate + for (i=0; i PCS) + .xgmii_txd(xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_in(mdio_m2s), // Management Data In + .mdio_out(mdio_s2m), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(MDIO_PHYADDR), // MDIO address + // General IO's + .core_status(phy_status[7:0]), // Core status + .resetdone(xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), + .tx_disable(sfpp_tx_disable), + .qpllreset(qpllreset), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .tx_out_clk(gt_tx_out_clk_unbuf) + ); + end else begin + ten_gige_phy ten_gige_phy_i ( + // Clocks and Reset + .areset(areset | phy_ctrl_reg[0]), // Asynchronous reset for entire core. + .refclk(gt_refclk), // Transciever reference clock: 156.25MHz + .clk156(gb_refclk), // Globally buffered core clock: 156.25MHz + .dclk(misc_clk), // Management/DRP clock: 78.125MHz + .sim_speedup_control(1'b0), + // GMII Interface (client MAC <=> PCS) + .xgmii_txd(xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_in(mdio_m2s), // Management Data In + .mdio_out(mdio_s2m), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(MDIO_PHYADDR), // MDIO address + // General IO's + .core_status(phy_status[7:0]), // Core status + .resetdone(xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), + .tx_disable(sfpp_tx_disable) + ); + assign qpllreset = 1'b0; + assign gt_pll_lock = 1'b0; + assign gt_tx_out_clk_unbuf = 1'b0; + end + + xge_mac_wrapper #( + .PORTNUM(PORTNUM), + .WISHBONE(0) + ) xge_mac_wrapper_i ( + // XGMII + .xgmii_clk(gb_refclk), + .xgmii_txd(xgmii_txd), + .xgmii_txc(xgmii_txc), + .xgmii_rxd(xgmii_rxd), + .xgmii_rxc(xgmii_rxc), + // Client FIFO Interfaces + .sys_clk(bus_clk), + .sys_rst(bus_rst), + .rx_tdata(m_axis_tdata), + .rx_tuser(m_axis_tuser), + .rx_tlast(m_axis_tlast), + .rx_tvalid(m_axis_tvalid), + .rx_tready(m_axis_tready), + .tx_tdata(c2mac_tdata), + .tx_tuser(c2mac_tuser), // Bit[3] (error) is ignored for now. + .tx_tlast(c2mac_tlast), + .tx_tvalid(c2mac_tvalid), + .tx_tready(c2mac_tready), + // Other + .phy_ready(xge_phy_resetdone), + .ctrl_tx_enable(mac_ctrl_reg[0]), + .status_crc_error(mac_status[0]), + .status_fragment_error(mac_status[1]), + .status_txdfifo_ovflow(mac_status[2]), + .status_txdfifo_udflow(mac_status[3]), + .status_rxdfifo_ovflow(mac_status[4]), + .status_rxdfifo_udflow(mac_status[5]), + .status_pause_frame_rx(mac_status[6]), + .status_local_fault(mac_status[7]), + .status_remote_fault(mac_status[8]), + .wb_ack_o(), + .wb_dat_o(), + .wb_adr_i(1'b0), + .wb_clk_i(1'b0), + .wb_cyc_i(1'b0), + .wb_dat_i(1'b0), + .wb_rst_i(1'b0), + .wb_stb_i(1'b0), + .wb_we_i (1'b0), + .wb_int_o() + ); + + assign phy_status[31:8] = 24'h0; + assign mac_status[31:9] = 23'h0; + assign link_up = phy_status_bclk[0]; + + end else if (PROTOCOL == "1GbE") begin + + //----------------------------------------------------------------- + // 1 Gigabit Ethernet + //----------------------------------------------------------------- + wire [7:0] gmii_txd, gmii_rxd; + wire gmii_tx_en, gmii_tx_er, gmii_rx_dv, gmii_rx_er; + wire gmii_clk; + wire gt0_qplloutclk, gt0_qplloutrefclk; //unused in 7-series Zynq + + assign gt0_qplloutclk = 1'b0; + assign gt0_qplloutrefclk = 1'b0; + assign sfpp_tx_disable = 1'b0; // Always on. + + if (GT_COMMON == 1) begin + one_gige_phy one_gige_phy_i ( + .reset(areset | phy_ctrl_reg[0]), // Asynchronous reset for entire core. + .independent_clock(bus_clk), + .pma_reset_out(/*unused*/), + .gt0_qplloutclk_in(gt0_qplloutclk), + .gt0_qplloutrefclk_in(gt0_qplloutrefclk), + // Tranceiver Interface + .gtrefclk(gt_refclk), // Reference clock for MGT: 125MHz, very high quality. + .gtrefclk_bufg(gb_refclk), // Reference clock routed through a BUFG + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // GMII Interface (client MAC <=> PCS) + .gmii_clk(gmii_clk), // Clock to client MAC. + .gmii_txd(gmii_txd), // Transmit data from client MAC. + .gmii_tx_en(gmii_tx_en), // Transmit control signal from client MAC. + .gmii_tx_er(gmii_tx_er), // Transmit control signal from client MAC. + .gmii_rxd(gmii_rxd), // Received Data to client MAC. + .gmii_rx_dv(gmii_rx_dv), // Received control signal to client MAC. + .gmii_rx_er(gmii_rx_er), // Received control signal to client MAC. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_i(mdio_m2s), // Management Data In + .mdio_o(mdio_s2m), // Management Data Out + .mdio_t(), // Management Data Tristate + .phyaddr(MDIO_PHYADDR), // MDIO address + .configuration_vector(5'd0), // Alternative to MDIO interface. + .configuration_valid(1'b1), // Validation signal for Config vector (MUST be 1 for proper functionality...undocumented) + // General IO's + .status_vector(phy_status[15:0]), // Core status. + .signal_detect(1'b1 /*Optical module not supported*/) // Input from PMD to indicate presence of optical input. + ); + end else begin + one_gige_phy one_gige_phy_i ( + .reset(areset | phy_ctrl_reg[0]), // Asynchronous reset for entire core. + .independent_clock(bus_clk), + // Tranceiver Interface + .gtrefclk(gt_refclk), // Reference clock for MGT: 125MHz, very high quality. + .gtrefclk_bufg(gb_refclk), // Reference clock routed through a BUFG + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // GMII Interface (client MAC <=> PCS) + .gmii_clk(gmii_clk), // Clock to client MAC. + .gmii_txd(gmii_txd), // Transmit data from client MAC. + .gmii_tx_en(gmii_tx_en), // Transmit control signal from client MAC. + .gmii_tx_er(gmii_tx_er), // Transmit control signal from client MAC. + .gmii_rxd(gmii_rxd), // Received Data to client MAC. + .gmii_rx_dv(gmii_rx_dv), // Received control signal to client MAC. + .gmii_rx_er(gmii_rx_er), // Received control signal to client MAC. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_i(mdio_m2s), // Management Data In + .mdio_o(mdio_s2m), // Management Data Out + .mdio_t(), // Management Data Tristate + .phyaddr(MDIO_PHYADDR), // MDIO address + .configuration_vector(5'd0), // Alternative to MDIO interface. + .configuration_valid(1'b1), // Validation signal for Config vector (MUST be 1 for proper functionality...undocumented) + // General IO's + .status_vector(phy_status[15:0]), // Core status. + .signal_detect(1'b1 /*Optical module not supported*/) // Input from PMD to indicate presence of optical input. + ); + assign qpllreset = 1'b0; + assign gt_pll_lock = 1'b0; + assign gt_tx_out_clk_unbuf = 1'b0; + end + + simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_i + ( + .clk125(gmii_clk), + .reset(areset), + + .GMII_GTX_CLK(), + .GMII_TX_EN(gmii_tx_en), + .GMII_TX_ER(gmii_tx_er), + .GMII_TXD(gmii_txd), + .GMII_RX_CLK(gmii_clk), + .GMII_RX_DV(gmii_rx_dv), + .GMII_RX_ER(gmii_rx_er), + .GMII_RXD(gmii_rxd), + + .sys_clk(bus_clk), + .rx_tdata(m_axis_tdata), + .rx_tuser(m_axis_tuser), + .rx_tlast(m_axis_tlast), + .rx_tvalid(m_axis_tvalid), + .rx_tready(m_axis_tready), + .tx_tdata(c2mac_tdata), + .tx_tuser(c2mac_tuser), + .tx_tlast(c2mac_tlast), + .tx_tvalid(c2mac_tvalid), + .tx_tready(c2mac_tready), + + .wb_clk_i(1'b0), + .wb_rst_i(1'b0), + .wb_adr_i(8'h0), + .wb_dat_i(32'h0), + .wb_we_i(1'b0), + .wb_stb_i(1'b0), + .wb_cyc_i(1'b0), + .wb_dat_o(), + .wb_ack_o(), + .wb_int_o(), + .mdc(), + .mdio_out(1'b0), + .mdio_tri(), + .mdio_in(), + .debug_tx(), + .debug_rx() + ); + + assign phy_status[31:16] = 16'h0; + assign mac_status[31:0] = 32'h0; + assign link_up = phy_status_bclk[0]; + + assign gt_tx_out_clk_unbuf = 1'b0; + + end else if (PROTOCOL == "Aurora") begin + + //----------------------------------------------------------------- + // Aurora + //----------------------------------------------------------------- + wire user_rst; + wire [63:0] m2p_tdata, p2m_tdata; + wire m2p_tvalid, m2p_tready, p2m_tvalid; + wire channel_up, hard_err, soft_err, mac_crit_err; + + wire bist_checker_en = mac_ctrl_reg[0]; + wire bist_gen_en = mac_ctrl_reg[1]; + wire bist_loopback_en = mac_ctrl_reg[2]; + wire [5:0] bist_gen_rate = mac_ctrl_reg[8:3]; + wire phy_areset = mac_ctrl_reg[9]; + wire mac_clear = mac_ctrl_reg[10]; + wire bist_checker_locked; + + assign sfpp_tx_disable = 1'b0; // Always on. + + if (GT_COMMON == 1) begin + aurora_phy_x1 aurora_phy_i ( + // Resets + .areset(areset | phy_areset), + // Clocks + .refclk(gt_refclk), + .init_clk(misc_clk), + .user_clk(user_clk), + .user_rst(user_rst), + .sync_clk(sync_clk), + .qpllclk(qplloutclk), + .qpllrefclk(qplloutrefclk), + // GTX Serial I/O + .tx_p(txp), + .tx_n(txn), + .rx_p(rxp), + .rx_n(rxn), + // AXI4-Stream TX Interface + .s_axis_tdata(m2p_tdata), + .s_axis_tvalid(m2p_tvalid), + .s_axis_tready(m2p_tready), + // AXI4-Stream RX Interface + .m_axis_tdata(p2m_tdata), + .m_axis_tvalid(p2m_tvalid), + // AXI4-Lite Config Interface (unused) + .s_axi_awaddr(32'h0), + .s_axi_araddr(32'h0), + .s_axi_awvalid(1'b0), + .s_axi_awready(), + .s_axi_wdata(32'h0), + .s_axi_wvalid(1'b0), + .s_axi_wstrb(1'b0), + .s_axi_wready(), + .s_axi_bvalid(), + .s_axi_bresp(), + .s_axi_bready(1'b1), + .s_axi_arready(), + .s_axi_arvalid(1'b0), + .s_axi_rdata(), + .s_axi_rvalid(), + .s_axi_rresp(), + .s_axi_rready(1'b1), + // Status and Error Reporting Interface + .channel_up(channel_up), + .hard_err(hard_err), + .soft_err(soft_err), + .qplllock(qplllock), + .qpllreset(qpllreset), + .qpllrefclklost(qpllrefclklost), + .tx_out_clk(gt_tx_out_clk_unbuf), + .gt_pll_lock(gt_pll_lock), + .mmcm_locked(mmcm_locked) + ); + end else begin + aurora_phy_x1 aurora_phy_i ( + // Resets + .areset(areset | phy_areset), + // Clocks + .refclk(gt_refclk), + .init_clk(misc_clk), + .user_clk(user_clk), + .user_rst(user_rst), + // GTX Serial I/O + .tx_p(txp), + .tx_n(txn), + .rx_p(rxp), + .rx_n(rxn), + // AXI4-Stream TX Interface + .s_axis_tdata(m2p_tdata), + .s_axis_tvalid(m2p_tvalid), + .s_axis_tready(m2p_tready), + // AXI4-Stream RX Interface + .m_axis_tdata(p2m_tdata), + .m_axis_tvalid(p2m_tvalid), + // AXI4-Lite Config Interface (unused) + .s_axi_awaddr(32'h0), + .s_axi_araddr(32'h0), + .s_axi_awvalid(1'b0), + .s_axi_awready(), + .s_axi_wdata(32'h0), + .s_axi_wvalid(1'b0), + .s_axi_wstrb(1'b0), + .s_axi_wready(), + .s_axi_bvalid(), + .s_axi_bresp(), + .s_axi_bready(1'b1), + .s_axi_arready(), + .s_axi_arvalid(1'b0), + .s_axi_rdata(), + .s_axi_rvalid(), + .s_axi_rresp(), + .s_axi_rready(1'b1), + // Status and Error Reporting Interface + .channel_up(channel_up), + .hard_err(hard_err), + .soft_err(soft_err) + ); + assign qpllreset = 1'b0; + assign gt_pll_lock = 1'b0; + assign gt_tx_out_clk_unbuf = 1'b0; + end + + aurora_axis_mac #( + .PHY_ENDIANNESS ("LITTLE"), + .PACKET_MODE (1), + .MAX_PACKET_SIZE(1024), + .BIST_ENABLED (1) + ) aurora_mac_i ( + // Clocks and resets + .phy_clk(user_clk), .phy_rst(user_rst), + .sys_clk(bus_clk), .sys_rst(bus_rst), + .clear(mac_clear), + // PHY Interface (Synchronous to phy_clk) + .phy_s_axis_tdata(p2m_tdata), + .phy_s_axis_tvalid(p2m_tvalid), + .phy_m_axis_tdata(m2p_tdata), + .phy_m_axis_tvalid(m2p_tvalid), + .phy_m_axis_tready(m2p_tready), + // User Interface (Synchronous to sys_clk) + .s_axis_tdata(c2mac_tdata), + .s_axis_tlast(c2mac_tlast), + .s_axis_tvalid(c2mac_tvalid), + .s_axis_tready(c2mac_tready), + .m_axis_tdata(m_axis_tdata), + .m_axis_tlast(m_axis_tlast), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_tready(m_axis_tready), + // PHY Status Inputs (Synchronous to phy_clk) + .channel_up(channel_up), + .hard_err(hard_err), + .soft_err(soft_err), + // Status and Error Outputs (Synchronous to sys_clk) + .overruns(overruns), + .soft_errors(), + .checksum_errors(checksum_errors), + .critical_err(mac_crit_err), + // BIST Interface (Synchronous to sys_clk) + .bist_gen_en(bist_gen_en), + .bist_gen_rate(bist_gen_rate), + .bist_checker_en(bist_checker_en), + .bist_loopback_en(bist_loopback_en), + .bist_checker_locked(bist_checker_locked), + .bist_checker_samps(bist_checker_samps), + .bist_checker_errors(bist_checker_errors) + ); + + assign m_axis_tuser = 4'd0; + + wire channel_up_bclk, hard_err_bclk, soft_err_bclk, mac_crit_err_bclk, gt_pll_lock_bclk; + synchronizer #(.INITIAL_VAL(1'b0)) channel_up_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(channel_up), .out(channel_up_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) hard_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(hard_err), .out(hard_err_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) soft_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(soft_err), .out(soft_err_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) mac_crit_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(mac_crit_err), .out(mac_crit_err_bclk)); + + if (GT_COMMON == 1) begin + synchronizer #(.INITIAL_VAL(1'b0)) gt_pll_lock_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(gt_pll_lock), .out(gt_pll_lock_bclk)); + end else begin + assign gt_pll_lock_bclk = 1'b0; + end + + reg [19:0] bist_lock_latency; + always @(posedge bus_clk) begin + if (!bist_checker_en && !bist_checker_locked) + bist_lock_latency <= 20'd0; + else if (bist_checker_en && !bist_checker_locked) + bist_lock_latency <= bist_lock_latency + 20'd1; + end + + reg mac_crit_err_latch; + always @(posedge bus_clk) begin + if (bus_rst | mac_clear) begin + mac_crit_err_latch <= 1'b0; + end else begin + if (mac_crit_err_bclk) + mac_crit_err_latch <= 1'b1; + end + end + + assign phy_status = {30'd0, hard_err, channel_up}; + assign mac_status = { + 6'h0, //[31:26] + mac_crit_err_latch, //[25] + 1'b1, //[24] + gt_pll_lock_bclk, //[23] + qpllrefclklost, //[22] + qplllock, //[21] + qpllreset, //[20] + bist_lock_latency[19:4], //[19:4] + bist_checker_locked, //[3] + soft_err_bclk, //[2] + hard_err_bclk, //[1] + channel_up_bclk //[0] + }; + + assign link_up = channel_up_bclk; + + end else begin + + //----------------------------------------------------------------- + // Disabled + //----------------------------------------------------------------- + + assign phy_status = 'h0; + assign mac_status = 'h0; + assign link_up = 1'b0; + + assign sfpp_tx_disable = 1'b0; // Always on. + + assign c2mac_tready = 1'b1; + assign m_axis_tdata = 64'h0; + assign m_axis_tuser = 4'h0; + assign m_axis_tlast = 1'b0; + assign m_axis_tvalid = 1'b0; + + assign qpllreset = 1'b0; + assign gt_pll_lock = 1'b0; + assign gt_tx_out_clk_unbuf = 1'b0; + + end + endgenerate + + wire identify_enable = mac_led_ctl[0]; + wire identify_value = mac_led_ctl[1]; + + //----------------------------------------------------------------- + // Activity detector + //----------------------------------------------------------------- + + wire activity_int; + + pulse_stretch act_pulse_str_i ( + .clk(bus_clk), + .rst(bus_rst | ~link_up), + .pulse((s_axis_tvalid & s_axis_tready) | (m_axis_tvalid & m_axis_tready)), + .pulse_stretched(activity_int) + ); + + always @ (posedge bus_clk) activity <= identify_enable ? identify_value : activity_int; + +endmodule diff --git a/fpga/usrp3/top/n3xx/n3xx_mgt_wrapper.v b/fpga/usrp3/top/n3xx/n3xx_mgt_wrapper.v new file mode 100644 index 000000000..fa1d5fe5d --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_mgt_wrapper.v @@ -0,0 +1,440 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx_mgt_wrapper +// Description: +// Provides wrapper for just the pieces specific to an MGT lane +// (for easy use with generate) +// +////////////////////////////////////////////////////////////////////// + +`default_nettype none +module n3xx_mgt_wrapper #( + parameter PROTOCOL = "10GbE", // Must be {10GbE, Aurora, Disabled} + parameter REG_DWIDTH = 32, + parameter REG_AWIDTH = 14, + parameter GT_COMMON = 1, + parameter [7:0] PORTNUM = 8'd0, + parameter MDIO_EN = 0, + parameter [4:0] MDIO_PHYADDR = 5'd0, + parameter REG_BASE = 16'h0000 +)( + // Resets + input wire areset, + input wire bus_rst, + + // Clocks + input wire gt_refclk, + input wire gb_refclk, + input wire misc_clk, + input wire bus_clk, + input wire user_clk, + input wire sync_clk, + + // RegPort interface + input wire reg_wr_req, + input wire [REG_AWIDTH-1:0] reg_wr_addr, + input wire [REG_DWIDTH-1:0] reg_wr_data, + input wire reg_rd_req, + input wire [REG_AWIDTH-1:0] reg_rd_addr, + output wire reg_rd_resp, + output wire [REG_DWIDTH-1:0] reg_rd_data, + + // High-speed IO + output wire txp, + output wire txn, + input wire rxp, + input wire rxn, + + // SFP low-speed IO + input wire mod_present_n, + input wire mod_rxlos, + input wire mod_tx_fault, + output wire mod_tx_disable, + + // GT Common + input wire qpllrefclklost, + input wire qplllock, + input wire qplloutclk, + input wire qplloutrefclk, + output wire qpllreset, + + // Aurora MMCM + input wire mmcm_locked, + output wire gt_pll_lock, + output wire gt_tx_out_clk_unbuf, + + // Vita router interface + output wire [63:0] e2v_tdata, + output wire e2v_tlast, + output wire e2v_tvalid, + input wire e2v_tready, + + input wire [63:0] v2e_tdata, + input wire v2e_tlast, + input wire v2e_tvalid, + output wire v2e_tready, + + // CPU + output wire [63:0] e2c_tdata, + output wire [7:0] e2c_tkeep, + output wire e2c_tlast, + output wire e2c_tvalid, + input wire e2c_tready, + + input wire [63:0] c2e_tdata, + input wire [7:0] c2e_tkeep, + input wire c2e_tlast, + input wire c2e_tvalid, + output wire c2e_tready, + + // MISC + output wire [31:0] port_info, + input wire [15:0] device_id, + + // Timebase Outputs + output wire mod_pps, + output wire mod_refclk, + + // Sideband White Rabbit Control + input wire wr_reset_n, + input wire wr_refclk, + + output wire wr_dac_sclk, + output wire wr_dac_din, + output wire wr_dac_clr_n, + output wire wr_dac_cs_n, + output wire wr_dac_ldac_n, + + output wire wr_eeprom_scl_o, + input wire wr_eeprom_scl_i, + output wire wr_eeprom_sda_o, + input wire wr_eeprom_sda_i, + + input wire wr_uart_rx, + output wire wr_uart_tx, + + // WR AXI Control + output wire wr_axi_aclk, + input wire wr_axi_aresetn, + input wire [31:0] wr_axi_awaddr, + input wire wr_axi_awvalid, + output wire wr_axi_awready, + input wire [REG_DWIDTH-1:0] wr_axi_wdata, + input wire [REG_DWIDTH/8-1:0] wr_axi_wstrb, + input wire wr_axi_wvalid, + output wire wr_axi_wready, + output wire [1:0] wr_axi_bresp, + output wire wr_axi_bvalid, + input wire wr_axi_bready, + input wire [31:0] wr_axi_araddr, + input wire wr_axi_arvalid, + output wire wr_axi_arready, + output wire [REG_DWIDTH-1:0] wr_axi_rdata, + output wire [1:0] wr_axi_rresp, + output wire wr_axi_rvalid, + input wire wr_axi_rready, + output wire wr_axi_rlast, + + output wire link_up, + output wire activity + +); + + localparam [REG_AWIDTH-1:0] REG_BASE_MGT_IO = {REG_AWIDTH{1'b0}} + REG_BASE; + localparam [REG_AWIDTH-1:0] REG_BASE_ETH_SWITCH = {REG_AWIDTH{1'b0}} + 16'h1000 + REG_BASE; + + // AXI4-Lite to RegPort (PS to PL Register Access) + wire reg_rd_resp_io, reg_rd_resp_eth_if; + wire [REG_DWIDTH-1:0] reg_rd_data_io, reg_rd_data_eth_if; + + // Regport Mux for response + regport_resp_mux #( + .WIDTH (REG_DWIDTH), + .NUM_SLAVES (2) + ) reg_resp_mux_i ( + .clk(bus_clk), .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_eth_if, reg_rd_resp_io}), + .sla_rd_data({reg_rd_data_eth_if, reg_rd_data_io}), + .mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data) + ); + + wire [63:0] mgto_tdata, mgti_tdata; + wire [3:0] mgto_tuser, mgti_tuser; + wire mgto_tlast, mgti_tlast, mgto_tvalid, mgti_tvalid, mgto_tready, mgti_tready; + + generate + if (PROTOCOL != "WhiteRabbit") begin + n3xx_mgt_io_core #( + .PROTOCOL (PROTOCOL), + .REG_BASE (REG_BASE_MGT_IO), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .GT_COMMON (GT_COMMON), + .MDIO_EN (MDIO_EN), + .MDIO_PHYADDR (MDIO_PHYADDR), + .PORTNUM (PORTNUM) + ) mgt_io_i ( + //must reset all channels on quad when other gtx core is reset + .areset (areset), + .gt_refclk (gt_refclk), + .gb_refclk (gb_refclk), + .misc_clk (misc_clk), + .user_clk (user_clk), + .sync_clk (sync_clk), + .gt_tx_out_clk_unbuf(gt_tx_out_clk_unbuf), + + .bus_rst (bus_rst), + .bus_clk (bus_clk), + .qpllreset (qpllreset), + .qplllock (qplllock), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qpllrefclklost (qpllrefclklost), + .mmcm_locked (mmcm_locked), + .gt_pll_lock (gt_pll_lock), + + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + + .sfpp_rxlos (mod_rxlos), + .sfpp_tx_fault (mod_tx_fault), + .sfpp_tx_disable(mod_tx_disable), + + //RegPort + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp_io), + .reg_rd_data (reg_rd_data_io), + + // Vita to Ethernet + .s_axis_tdata (mgti_tdata), + .s_axis_tuser (mgti_tuser), + .s_axis_tlast (mgti_tlast), + .s_axis_tvalid (mgti_tvalid), + .s_axis_tready (mgti_tready), + + // Ethernet to Vita + .m_axis_tdata (mgto_tdata), + .m_axis_tuser (mgto_tuser), + .m_axis_tlast (mgto_tlast), + .m_axis_tvalid (mgto_tvalid), + .m_axis_tready (mgto_tready), + + .port_info (port_info), + .link_up (link_up), + .activity (activity) + ); + + end else begin + //--------------------------------------------------------------------------------- + // White Rabbit + //--------------------------------------------------------------------------------- + + wire wr_sfp_scl, wr_sfp_sda_o, wr_sfp_sda_i; + + n3xx_wr_top #( + .g_simulation(1'b0), // in std_logic + .g_dpram_size(131072/4), + .g_dpram_initf("../../../../bin/wrpc/wrc_phy16.bram") + ) wr_inst ( + .areset_n_i (wr_reset_n), // in std_logic; -- active low reset, optional + .wr_refclk_buf_i (wr_refclk), // in std_logic; -- 20MHz VCXO after IBUFGDS + .gige_refclk_buf_i (gt_refclk), // in std_logic; -- 125 MHz MGT Ref after IBUFDS_GTE2 + .dac_sclk_o (wr_dac_sclk), // out std_logic; -- N3xx cWB-DAC-SCLK + .dac_din_o (wr_dac_din), // out std_logic; -- N3xx cWB-DAC-DIN + .dac_clr_n_o (wr_dac_clr_n), // out std_logic; -- N3xx cWB-DAC-nCLR + .dac_cs_n_o (wr_dac_cs_n), // out std_logic; -- N3xx cWB-DAC-nSYNC + .dac_ldac_n_o (wr_dac_ldac_n), // out std_logic; -- N3xx cWB-DAC-nLDAC + .LED_ACT (activity), // out std_logic; -- connect to SFP+ ACT + .LED_LINK (link_up), // out std_logic; -- connect to SFP+ LINK + .sfp_txp_o (txp), // out std_logic; + .sfp_txn_o (txn), // out std_logic; + .sfp_rxp_i (rxp), // in std_logic; + .sfp_rxn_i (rxn), // in std_logic; + .sfp_mod_def0_b (mod_present_n), // in std_logic; - sfp detect + .eeprom_scl_o (wr_eeprom_scl_o), + .eeprom_scl_i (wr_eeprom_scl_i), + .eeprom_sda_o (wr_eeprom_sda_o), + .eeprom_sda_i (wr_eeprom_sda_i), + .sfp_scl_o (wr_sfp_scl), + .sfp_scl_i (wr_sfp_scl), + .sfp_sda_o (wr_sfp_sda_o), + .sfp_sda_i (wr_sfp_sda_i), + .sfp_tx_fault_i (mod_tx_fault), // in std_logic; + .sfp_tx_disable_o (mod_tx_disable), // out std_logic; + .sfp_los_i (mod_rxlos), // in std_logic; + .wr_uart_rxd (wr_uart_rx), // in std_logic; + .wr_uart_txd (wr_uart_tx), // out std_logic; + + .s00_axi_aclk_o (wr_axi_aclk), + .s00_axi_aresetn (wr_axi_aresetn), + .s00_axi_awaddr (wr_axi_awaddr), + .s00_axi_awprot (3'b0), + .s00_axi_awvalid (wr_axi_awvalid), + .s00_axi_awready (wr_axi_awready), + .s00_axi_wdata (wr_axi_wdata), + .s00_axi_wstrb (wr_axi_wstrb), + .s00_axi_wvalid (wr_axi_wvalid), + .s00_axi_wready (wr_axi_wready), + .s00_axi_bresp (wr_axi_bresp), + .s00_axi_bvalid (wr_axi_bvalid), + .s00_axi_bready (wr_axi_bready), + .s00_axi_araddr (wr_axi_araddr), + .s00_axi_arprot (3'b0), + .s00_axi_arvalid (wr_axi_arvalid), + .s00_axi_arready (wr_axi_arready), + .s00_axi_rdata (wr_axi_rdata), + .s00_axi_rresp (wr_axi_rresp), + .s00_axi_rvalid (wr_axi_rvalid), + .s00_axi_rready (wr_axi_rready), + .s00_axi_rlast (wr_axi_rlast), + .axi_int_o (), + + .pps_o (mod_pps), // out std_logic; + .clk_pps_o (mod_refclk), // out std_logic; + .link_ok_o (), // out std_logic; + .clk_sys_locked_o (), // out std_logic; + .clk_dmtd_locked_o (), // out std_logic); + .wr_debug0_o (), + .wr_debug1_o () + ); + + // TEMPORARY mimic the AXGE SFP EEROM + sfp_eeprom sfp_eeprom_i ( + .clk_i(bus_clk), + .sfp_scl(wr_sfp_scl), + .sfp_sda_i(wr_sfp_sda_o), + .sfp_sda_o(wr_sfp_sda_i)); + + // Assign the port_info vector similarly to mgt_io_core + localparam [7:0] COMPAT_NUM = 8'd2; + localparam [7:0] MGT_PROTOCOL = 8'd4; + assign port_info = {COMPAT_NUM, 6'h0, activity, link_up, MGT_PROTOCOL, PORTNUM}; + + // Tie off unused outputs. + assign gt_pll_lock = 1'b0; + assign gt_tx_out_clk_unbuf = 1'b0; + end + endgenerate + + generate + // Tie off the Ethernet switch for these protocols that do not use it. + if(PROTOCOL == "Aurora" || PROTOCOL == "Disabled" || PROTOCOL == "WhiteRabbit") begin + + //set unused wires to default value + assign e2c_tdata = 64'h0; + assign e2c_tkeep = 8'h0; + assign e2c_tlast = 1'b0; + assign e2c_tvalid = 1'b0; + assign c2e_tready = 1'b1; + + assign reg_rd_resp_eth_if = 1'b0; + assign reg_rd_data_eth_if = 'h0; + + assign e2v_tdata = mgto_tdata; + assign e2v_tlast = mgto_tlast; + assign e2v_tvalid = mgto_tvalid; + assign mgto_tready = e2v_tready; + + assign mgti_tdata = v2e_tdata; + assign mgti_tlast = v2e_tlast; + assign mgti_tvalid = v2e_tvalid; + assign v2e_tready = mgti_tready; + + end else begin + + wire [3:0] e2c_tuser; + wire [3:0] c2e_tuser; + + // In AXI Stream, tkeep is the byte qualifier that indicates + // whether the content of the associated byte + // of TDATA is processed as part of the data stream. + // tuser as used in eth_switch is the numbier of valid bytes + + // Converting tuser to tkeep for ingress packets + assign e2c_tkeep = ~e2c_tlast ? 8'b1111_1111 + : (e2c_tuser == 4'd0) ? 8'b1111_1111 + : (e2c_tuser == 4'd1) ? 8'b0000_0001 + : (e2c_tuser == 4'd2) ? 8'b0000_0011 + : (e2c_tuser == 4'd3) ? 8'b0000_0111 + : (e2c_tuser == 4'd4) ? 8'b0000_1111 + : (e2c_tuser == 4'd5) ? 8'b0001_1111 + : (e2c_tuser == 4'd6) ? 8'b0011_1111 + : 8'b0111_1111; + + // Converting tkeep to tuser for egress packets + assign c2e_tuser = ~c2e_tlast ? 4'd0 + : (c2e_tkeep == 8'b1111_1111) ? 4'd0 + : (c2e_tkeep == 8'b0111_1111) ? 4'd7 + : (c2e_tkeep == 8'b0011_1111) ? 4'd6 + : (c2e_tkeep == 8'b0001_1111) ? 4'd5 + : (c2e_tkeep == 8'b0000_1111) ? 4'd4 + : (c2e_tkeep == 8'b0000_0111) ? 4'd3 + : (c2e_tkeep == 8'b0000_0011) ? 4'd2 + : (c2e_tkeep == 8'b0000_0001) ? 4'd1 + : 4'd0; + + eth_interface #( + .PROTOVER ({8'd1,8'd0}), //FIXME. This should come from outside + .MTU (10), + .NODE_INST (0), + .REG_AWIDTH (REG_AWIDTH), + .BASE (REG_BASE_ETH_SWITCH) + ) eth_interface ( + .clk (bus_clk), + .reset (bus_rst), + .device_id (device_id), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp_eth_if), + .reg_rd_data (reg_rd_data_eth_if), + .my_mac (), + .my_ip (), + .my_udp_port (), + .eth_tx_tdata (mgti_tdata), + .eth_tx_tuser (mgti_tuser), + .eth_tx_tlast (mgti_tlast), + .eth_tx_tvalid (mgti_tvalid), + .eth_tx_tready (mgti_tready), + .eth_rx_tdata (mgto_tdata), + .eth_rx_tuser (mgto_tuser), + .eth_rx_tlast (mgto_tlast), + .eth_rx_tvalid (mgto_tvalid), + .eth_rx_tready (mgto_tready), + .e2v_tdata (e2v_tdata), + .e2v_tlast (e2v_tlast), + .e2v_tvalid (e2v_tvalid), + .e2v_tready (e2v_tready), + .v2e_tdata (v2e_tdata), + .v2e_tlast (v2e_tlast), + .v2e_tvalid (v2e_tvalid), + .v2e_tready (v2e_tready), + .e2c_tdata (e2c_tdata), + .e2c_tuser (e2c_tuser), + .e2c_tlast (e2c_tlast), + .e2c_tvalid (e2c_tvalid), + .e2c_tready (e2c_tready), + .c2e_tdata (c2e_tdata), + .c2e_tuser (c2e_tuser), + .c2e_tlast (c2e_tlast), + .c2e_tvalid (c2e_tvalid), + .c2e_tready (c2e_tready) + ); + + end + endgenerate + +endmodule // n3xx_mgt_wrapper +`default_nettype wire diff --git a/fpga/usrp3/top/n3xx/n3xx_serial_dac.vhd b/fpga/usrp3/top/n3xx/n3xx_serial_dac.vhd new file mode 100644 index 000000000..148a66185 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_serial_dac.vhd @@ -0,0 +1,218 @@ +------------------------------------------------------------------------------- +-- Title : N3xx Serial DAC interface +-- Project : White Rabbit Switch +------------------------------------------------------------------------------- +-- File : n3xx_serial_dac.vhd +-- Author : paas, slayer, dbaker +-- Company : CERN BE-Co-HT +-- Created : 2010-02-25 +-- Last update: 2011-05-10 +-- Platform : fpga-generic +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: The dac unit provides an interface to a 16 bit serial Digital to +-- Analogue converter (AD5663, SPI?/QSPI?/MICROWIRE? compatible) +-- +------------------------------------------------------------------------------- +-- Copyright (c) 2010 CERN +-- +-- This source file is free software; you can redistribute it +-- and/or modify it under the terms of the GNU Lesser General +-- Public License as published by the Free Software Foundation; +-- either version 2.1 of the License, or (at your option) any +-- later version. +-- +-- This source is distributed in the hope that it will be +-- useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +-- PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General +-- Public License along with this source; if not, download it +-- from http://www.gnu.org/licenses/lgpl-2.1.html +------------------------------------------------------------------------------- +-- Revisions :1 +-- Date Version Author Description +-- 2009-01-24 1.0 paas Created +-- 2010-02-25 1.1 slayer Modified for rev 1.1 switch +-- 2018-02-01 2.0 dbaker Modified for n3xx +------------------------------------------------------------------------------- + + +library IEEE; + +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + + +entity n3xx_serial_dac is + + generic ( + g_num_data_bits : integer := 16; + g_num_extra_bits : integer := 8; + g_num_cs_select : integer := 2 + ); + + port ( +-- clock & reset + clk_i : in std_logic; + rst_n_i : in std_logic; + +-- channel 1 value and value load strobe + value_i : in std_logic_vector(g_num_data_bits-1 downto 0); + cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0); + load_i : in std_logic; + +-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024 + sclk_divsel_i : in std_logic_vector(2 downto 0); + +-- DAC I/F + dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0); + dac_sclk_o : out std_logic; + dac_sdata_o : out std_logic; + + xdone_o : out std_logic + ); +end n3xx_serial_dac; + + +architecture syn of n3xx_serial_dac is + + signal divider : unsigned(11 downto 0); + signal dataSh : std_logic_vector(g_num_data_bits + g_num_extra_bits-1 downto 0); + signal bitCounter : std_logic_vector(g_num_data_bits + g_num_extra_bits+1 downto 0); + signal endSendingData : std_logic; + signal sendingData : std_logic; + signal iDacClk : std_logic; + signal iValidValue : std_logic; + + signal divider_muxed : std_logic; + + signal cs_sel_reg : std_logic_vector(g_num_cs_select-1 downto 0); + + constant k_cmd_hi : integer := 21; + constant k_cmd_lo : integer := 19; + constant k_addr_hi : integer := 18; + constant k_addr_lo : integer := 16; +begin + + select_divider : process (divider, sclk_divsel_i) + begin -- process + case sclk_divsel_i is + when "000" => divider_muxed <= divider(1); -- sclk = clk_i/8 + when "001" => divider_muxed <= divider(2); -- sclk = clk_i/16 + when "010" => divider_muxed <= divider(3); -- sclk = clk_i/32 + when "011" => divider_muxed <= divider(4); -- sclk = clk_i/64 + when "100" => divider_muxed <= divider(5); -- sclk = clk_i/128 + when "101" => divider_muxed <= divider(6); -- sclk = clk_i/256 + when "110" => divider_muxed <= divider(7); -- sclk = clk_i/512 + when "111" => divider_muxed <= divider(8); -- sclk = clk_i/1024 + when others => null; + end case; + end process; + + + iValidValue <= load_i; + + process(clk_i, rst_n_i) + begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + sendingData <= '0'; + else + if iValidValue = '1' and sendingData = '0' then + sendingData <= '1'; + elsif endSendingData = '1' then + sendingData <= '0'; + end if; + end if; + end if; + end process; + + process(clk_i) + begin + if rising_edge(clk_i) then + if iValidValue = '1' then + divider <= (others => '0'); + elsif sendingData = '1' then + if(divider_muxed = '1') then + divider <= (others => '0'); + else + divider <= divider + 1; + end if; + elsif endSendingData = '1' then + divider <= (others => '0'); + end if; + end if; + end process; + + + process(clk_i, rst_n_i) + begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + iDacClk <= '1'; -- 0 + else + if iValidValue = '1' then + iDacClk <= '1'; -- 0 + elsif divider_muxed = '1' then + iDacClk <= not(iDacClk); + elsif endSendingData = '1' then + iDacClk <= '1'; -- 0 + end if; + end if; + end if; + end process; + + process(clk_i, rst_n_i) + begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + dataSh <= (others => '0'); + else + if iValidValue = '1' and sendingData = '0' then + cs_sel_reg <= cs_sel_i; + dataSh <= (others => '0'); + if cs_sel_i(0) = '1' then + dataSh(k_addr_hi downto k_addr_lo) <= "000"; + elsif cs_sel_i(1) = '1' then + dataSh(k_addr_hi downto k_addr_lo) <= "001"; + end if; + dataSh(k_cmd_hi downto k_cmd_lo) <= "011"; + dataSh(g_num_data_bits-1 downto 0) <= value_i; + elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then + dataSh(0) <= dataSh(dataSh'left); + dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0); + end if; + end if; + end if; + end process; + + process(clk_i) + begin + if rising_edge(clk_i) then + if iValidValue = '1' and sendingData = '0' then + bitCounter(0) <= '1'; + bitCounter(bitCounter'left downto 1) <= (others => '0'); + elsif sendingData = '1' and to_integer(divider) = 0 and iDacClk = '1' then + bitCounter(0) <= '0'; + bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0); + end if; + end if; + end process; + + endSendingData <= bitCounter(bitCounter'left); + + xdone_o <= not SendingData; + + dac_sdata_o <= dataSh(dataSh'left); + + gen_cs_out : for i in 0 to g_num_cs_select-1 generate + dac_cs_n_o(i) <= not(sendingData); + end generate gen_cs_out; + + dac_sclk_o <= iDacClk; + + +end syn; diff --git a/fpga/usrp3/top/n3xx/n3xx_serial_dac_arb.vhd b/fpga/usrp3/top/n3xx/n3xx_serial_dac_arb.vhd new file mode 100644 index 000000000..9049bd845 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_serial_dac_arb.vhd @@ -0,0 +1,187 @@ +------------------------------------------------------------------------------- +-- Title : N3xx serial DAC interface with arbiter +-- Project : White Rabbit +------------------------------------------------------------------------------- +-- File : spec_serial_dac.vhd +-- Author : Tomasz Wlostowski, modifications by dbaker +-- Company : CERN BE-Co-HT +-- Platform : fpga-generic +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2011 CERN +-- +-- This source file is free software; you can redistribute it +-- and/or modify it under the terms of the GNU Lesser General +-- Public License as published by the Free Software Foundation; +-- either version 2.1 of the License, or (at your option) any +-- later version. +-- +-- This source is distributed in the hope that it will be +-- useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +-- PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General +-- Public License along with this source; if not, download it +-- from http://www.gnu.org/licenses/lgpl-2.1.html +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity n3xx_serial_dac_arb is + generic( + g_invert_sclk : boolean; + g_num_extra_bits : integer + ); + port( + clk_i : in std_logic; + rst_n_i : in std_logic; + + val1_i : in std_logic_vector(15 downto 0); + load1_i : in std_logic; + val2_i : in std_logic_vector(15 downto 0); + load2_i : in std_logic; + + dac_cs_n_o : out std_logic_vector(1 downto 0); + dac_clr_n_o : out std_logic; + dac_sclk_o : out std_logic; + dac_din_o : out std_logic); + +end n3xx_serial_dac_arb; + +architecture behavioral of n3xx_serial_dac_arb is + + component n3xx_serial_dac + generic ( + g_num_data_bits : integer; + g_num_extra_bits : integer; + g_num_cs_select : integer); + port ( + clk_i : in std_logic; + rst_n_i : in std_logic; + value_i : in std_logic_vector(g_num_data_bits-1 downto 0); + cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0); + load_i : in std_logic; + sclk_divsel_i : in std_logic_vector(2 downto 0); + dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0); + dac_sclk_o : out std_logic; + dac_sdata_o : out std_logic; + xdone_o : out std_logic); + end component; + + signal d1, d2 : std_logic_vector(15 downto 0) := (others=>'0'); + signal d1_ready, d2_ready : std_logic := '0'; + + + signal dac_data : std_logic_vector(15 downto 0) := (others=>'0'); + signal dac_load : std_logic := '0'; + signal dac_cs_sel : std_logic_vector(1 downto 0) := (others=>'0'); + signal dac_done : std_logic := '0'; + signal dac_sclk_int : std_logic := '0'; + + type t_state is (WAIT_DONE, LOAD_DAC, WAIT_DATA); + + signal state : t_state; + + signal trig0 : std_logic_vector(31 downto 0); + signal trig1 : std_logic_vector(31 downto 0); + signal trig2 : std_logic_vector(31 downto 0); + signal trig3 : std_logic_vector(31 downto 0); + signal CONTROL0 : std_logic_vector(35 downto 0); + +begin -- behavioral + + dac_clr_n_o <= '1'; + + U_DAC : n3xx_serial_dac + generic map ( + g_num_data_bits => 16, + g_num_extra_bits => g_num_extra_bits, + g_num_cs_select => 2) + port map ( + clk_i => clk_i, + rst_n_i => rst_n_i, + value_i => dac_data, + cs_sel_i => dac_cs_sel, + load_i => dac_load, + sclk_divsel_i => "001", + dac_cs_n_o => dac_cs_n_o, + dac_sclk_o => dac_sclk_int, + dac_sdata_o => dac_din_o, + xdone_o => dac_done); + + + p_drive_sclk: process(dac_sclk_int) + begin + if(g_invert_sclk) then + dac_sclk_o <= not dac_sclk_int; + else + dac_sclk_o <= dac_sclk_int; + end if; + end process; + + process(clk_i) + begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + d1 <= (others => '0'); + d1_ready <= '0'; + d2 <= (others => '0'); + d2_ready <= '0'; + dac_load <= '0'; + dac_cs_sel <= (others => '0'); + state <= WAIT_DATA; + else + + if(load1_i = '1' or load2_i = '1') then + + if(load1_i = '1') then + d1_ready <= '1'; + d1 <= val1_i; + end if; + + if(load2_i = '1') then + d2_ready <= '1'; + d2 <= val2_i; + end if; + else + case state is + when WAIT_DATA => + if(d1_ready = '1') then + dac_cs_sel <= "01"; + dac_data <= d1; + dac_load <= '1'; + d1_ready <= '0'; + state <= LOAD_DAC; + elsif(d2_ready = '1') then + dac_cs_sel <= "10"; + dac_data <= d2; + dac_load <= '1'; + d2_ready <= '0'; + state <= LOAD_DAC; + end if; + + when LOAD_DAC=> + dac_load <= '0'; + state <= WAIT_DONE; + + when WAIT_DONE => + if(dac_done = '1') then + state <= WAIT_DATA; + end if; + when others => null; + end case; + end if; + end if; + end if; + end process; + + + + +end behavioral; diff --git a/fpga/usrp3/top/n3xx/n3xx_wr.xdc b/fpga/usrp3/top/n3xx/n3xx_wr.xdc new file mode 100644 index 000000000..2b69c9ead --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_wr.xdc @@ -0,0 +1,78 @@ +# +# Copyright 2018 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +# 20 MHz White Rabbit reference +create_clock -name wr_refclk -period 50.000 [get_ports WB_20MHZ_P] + +# 62.5M TXOUTCLK from the MGT that does most of the heavy lifting +create_clock -name wr_txoutclk -period 16.000 \ + [get_pins -hierarchical -filter \ + {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/TXOUTCLK}] + +# 62.5M RXOUTCLK from the MGT that doesn't do as much as the TXOUTCLK +create_clock -name wr_rxoutclk -period 16.000 \ + [get_pins -hierarchical -filter \ + {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/RXOUTCLK}] + +# Rename the WR 62.5M system clock +create_generated_clock -name wr_sysclk \ + [get_pins -hierarchical -filter {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_default_plls.gen_kintex7_default_plls.cmp_sys_clk_pll/CLKOUT0}] + +# Rename the WR ~62.5M DMTD clock +create_generated_clock -name wr_dmtdclk \ + [get_pins -hierarchical -filter {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_default_plls.gen_kintex7_default_plls.cmp_dmtd_clk_pll/CLKOUT0}] + + + +# Clock Interaction Matrix : ------------------------------------------------------------ +# Everything is basically async to everything else, except for the net_clk group. +# Blanks mean there are no paths there (in the WR v4.2 build). +# +# The wr_sysclk (62.5 MHz) is derived from the 125 MHz MGT Reference clock (NETCLK). +# On the other hand, the wr_dmtdclk, also a 62.5 MHz clock, is derived from the 20 MHz +# WR VCXO. This two clock groups could be considered asynchronous due to its different +# source and different MMCM primitive (which unrelates them even more). +# +# | wr_RXOUTCLK | wr_TXOUTCLK | wr_dmtdclk | wr_sysclk | net_clk +# wr_RXOUTCLK | timed | async | async | async | +# wr_TXOUTCLK | async | timed | async | async | +# wr_dmtdclk | | | timed | async | +# wr_sysclk | async | async | async | timed | timed +# net_clk | async | | | timed | timed + +set_clock_groups -asynchronous -group [get_clocks wr_rxoutclk] \ + -group [get_clocks wr_txoutclk] \ + -group [get_clocks wr_dmtdclk] \ + -group [get_clocks net_clk] + +set_clock_groups -asynchronous -group [get_clocks wr_sysclk] \ + -group [get_clocks wr_txoutclk] \ + -group [get_clocks wr_rxoutclk] \ + -group [get_clocks wr_dmtdclk] + +# Safe paths : -------------------------------------------------------------------------- +# There is a mix of safe and unknown clock interactions between wr_sysclk and wr_dmtdclk. +# The safe crossings refer to those using a synchronizer structure; and to avoid +# failing timing on those paths, we ignore them (i.e. false paths), and allow the tools +# to time the rest. +# +# The WR IP uses easily identifiable single-bit synchronizers to transfer strobes from +# the wr_dmtdclk to the wr_sysclk domain. +# +# Commenting out command since the asynchronous groups were updated and paths ignored. +# set_false_path -from [get_clocks wr_dmtdclk] \ +# -to [get_pins -hierarchical -filter {NAME =~ */sync_posedge.sync0_reg/D}] +# +# +# The tags generated by the DDMTD (wr_dmtdclk domain) are deglitched before being output +# to the upstream logic in the wr_sysclk domain. Thus, a safe multi-bit crossing is +# expected between these two domains, and we tell the tools to ignore those paths. +# See usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_with_deglitcher.vhd for +# implementation details. +# +# Commenting out command since the asynchronous groups were updated and paths ignored. +# set_false_path -from [get_clocks wr_dmtdclk] \ +# -to [get_pins -hierarchical -filter {NAME =~ */U_Wrapped_Softpll/tags_masked_reg*/D}] diff --git a/fpga/usrp3/top/n3xx/n3xx_wr_top.vhd b/fpga/usrp3/top/n3xx/n3xx_wr_top.vhd new file mode 100644 index 000000000..277b6684f --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_wr_top.vhd @@ -0,0 +1,496 @@ +------------------------------------------------------------------------------- +-- +-- File: n3xx_wr_top.vhd +-- Author: +-- Original Project: N310 +-- Date: 22 February 2018 +-- +------------------------------------------------------------------------------- +-- Copyright 2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Wrapper file for the White Rabbit cores. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.gencores_pkg.all; +use work.wishbone_pkg.all; +use work.wr_fabric_pkg.all; +use work.wrcore_pkg.all; +use work.etherbone_pkg.all; +use work.endpoint_pkg.all; +use work.streamers_pkg.all; +use work.wr_xilinx_pkg.all; +use work.wr_board_pkg.all; +use work.axi4_pkg.all; + +library unisim; +use unisim.VCOMPONENTS.all; + + +entity n3xx_wr_top is + generic( + g_simulation : integer := 0; + g_dpram_size : integer := 131072/4; + g_dpram_initf : string := "../../../../bin/wrpc/wrc_phy16.bram"); + port ( + --------------------------------------------------------------------------- + -- Resets + --------------------------------------------------------------------------- + -- Reset input (active low, can be async) + areset_n_i : in std_logic; + + --------------------------------------------------------------------------- + -- Oscillators and control DACs + --------------------------------------------------------------------------- + wr_refclk_buf_i : in std_logic; -- 20MHz VCXO after IBUFGDS + + gige_refclk_buf_i : in std_logic; -- 125 MHz MGT Ref after IBUFDS_GTE2 + + dac_sclk_o : out std_logic; -- N310 cWB-DAC-SCLK + dac_din_o : out std_logic; -- N310 cWB-DAC-DIN + dac_clr_n_o : out std_logic; -- N310 cWB-DAC-nCLR + dac_cs_n_o : out std_logic; -- N310 cWB-DAC-nSYNC + dac_ldac_n_o : out std_logic; -- N310 cWB-DAC-nLDAC + + eeprom_scl_o : out std_logic; + eeprom_scl_i : in std_logic; + eeprom_sda_o : out std_logic; + eeprom_sda_i : in std_logic; + + --------------------------------------------------------------------------- + -- SFP pins + --------------------------------------------------------------------------- + -- LEDs + LED_ACT : out std_logic; -- connect to SFP+ ACT + LED_LINK : out std_logic; -- connect to SFP+ LINK + + sfp_txp_o : out std_logic; + sfp_txn_o : out std_logic; + + sfp_rxp_i : in std_logic; + sfp_rxn_i : in std_logic; + + sfp_mod_def0_b : in std_logic; -- sfp detect + --sfp_mod_def1_b : inout std_logic; -- scl + --sfp_mod_def2_b : inout std_logic; -- sda + sfp_scl_o : out std_logic; + sfp_scl_i : in std_logic; + sfp_sda_o : out std_logic; + sfp_sda_i : in std_logic; + sfp_tx_fault_i : in std_logic; + sfp_tx_disable_o : out std_logic; + sfp_los_i : in std_logic; + + --------------------------------------------------------------------------- + -- Grandmaster mode inputs, optional + --------------------------------------------------------------------------- + + -- 10MHz clock generated by N310 when using WR in grandmaster mode + --clk_ext_gm_i : in std_logic := '0'; + -- PPS generated by N310 when using WR in grandmaster mode + --pps_ext_gm_i : in std_logic := '0'; + + --------------------------------------------------------------------------- + --UART + --------------------------------------------------------------------------- + wr_uart_rxd : in std_logic; + wr_uart_txd : out std_logic; + + + ------------------------------------------ + -- Axi Slave Bus Interface S00_AXI + ------------------------------------------ + -- aclk provided by this IP, wire to master! + s00_axi_aclk_o : out std_logic; + s00_axi_aresetn : in std_logic; + s00_axi_awaddr : in std_logic_vector(31 downto 0); + s00_axi_awprot : in std_logic_vector(2 downto 0); + s00_axi_awvalid : in std_logic; + s00_axi_awready : out std_logic; + s00_axi_wdata : in std_logic_vector(31 downto 0); + s00_axi_wstrb : in std_logic_vector(3 downto 0); + s00_axi_wvalid : in std_logic; + s00_axi_wready : out std_logic; + s00_axi_bresp : out std_logic_vector(1 downto 0); + s00_axi_bvalid : out std_logic; + s00_axi_bready : in std_logic; + s00_axi_araddr : in std_logic_vector(31 downto 0); + s00_axi_arprot : in std_logic_vector(2 downto 0); + s00_axi_arvalid : in std_logic; + s00_axi_arready : out std_logic; + s00_axi_rdata : out std_logic_vector(31 downto 0); + s00_axi_rresp : out std_logic_vector(1 downto 0); + s00_axi_rvalid : out std_logic; + s00_axi_rready : in std_logic; + s00_axi_rlast : out std_logic; + axi_int_o : out std_logic; -- axi interrupt signal + + + --------------------------------------------------------------------------- + -- PPS and main clock + --------------------------------------------------------------------------- + -- PPS output from WR Core, in 125M domain + pps_o : out std_logic; + clk_pps_o : out std_logic; + link_ok_o : out std_logic; + + --------------------------------------------------------------------------- + -- Debug + --------------------------------------------------------------------------- + clk_sys_locked_o : out std_logic; + clk_dmtd_locked_o : out std_logic; + wr_debug0_o : out std_logic; + wr_debug1_o : out std_logic); +end entity n3xx_wr_top; + +architecture structure of n3xx_wr_top is + + component n3xx_serial_dac_arb + generic( + g_invert_sclk : boolean; + g_num_extra_bits : integer); + port ( + clk_i : in std_logic; + rst_n_i : in std_logic; + val1_i : in std_logic_vector(15 downto 0); + load1_i : in std_logic; + val2_i : in std_logic_vector(15 downto 0); + load2_i : in std_logic; + dac_cs_n_o : out std_logic_vector(1 downto 0); + dac_clr_n_o : out std_logic; + dac_sclk_o : out std_logic; + dac_din_o : out std_logic); + end component; + + ------------------------------------------------------------------------------ + -- Signals declaration + ------------------------------------------------------------------------------ + + -- PLLs, clocks + signal clk_pll_62m5 : std_logic; + signal clk_pll_125m : std_logic; + signal clk_ref_62m5 : std_logic; + signal clk_pll_dmtd : std_logic; + signal pll_locked : std_logic; + signal clk_10m_ext : std_logic; + + -- Reset logic + signal rst_pll_62m5_n : std_logic; + signal rstlogic_arst_n : std_logic; + signal rstlogic_clk_in : std_logic_vector(1 downto 0); + signal rstlogic_rst_out : std_logic_vector(1 downto 0); + + -- PLL DAC ARB + signal dac_hpll_load_p1 : std_logic; + signal dac_hpll_data : std_logic_vector(15 downto 0); + signal dac_dpll_load_p1 : std_logic; + signal dac_dpll_data : std_logic_vector(15 downto 0); + signal dac_cs_vec_n : std_logic_vector(1 downto 0); + + -- OneWire + signal onewire_in : std_logic_vector(1 downto 0); + signal onewire_en : std_logic_vector(1 downto 0); + + -- PHY + signal phy16_to_wrc : t_phy_16bits_to_wrc; + signal phy16_from_wrc : t_phy_16bits_from_wrc; + + -- External reference + signal ext_ref_mul : std_logic; + signal ext_ref_mul_locked : std_logic; + signal ext_ref_mul_stopped : std_logic; + signal ext_ref_rst : std_logic; + + -- SFP I2C + --signal sfp_scl_o : std_logic; + --signal sfp_scl_i : std_logic; + --signal sfp_sda_o : std_logic; + --signal sfp_sda_i : std_logic; + + -- WRC WB Slave interface + signal wb_slave_out : t_wishbone_slave_out; + signal wb_slave_in : t_wishbone_slave_in; + signal zero : std_logic; + + + signal ref_clk_fb_o, pps, ref_clk_fb_i, clk_ref_125m, clk_ref_125m_bufg : std_logic; + + +begin + + wr_debug0_o <= dac_dpll_load_p1; + wr_debug1_o <= dac_hpll_load_p1; + + ----------------------------------------------------------------------------- + -- Platform-dependent part (PHY, PLLs, buffers, etc) + ----------------------------------------------------------------------------- + + cmp_xwrc_platform : xwrc_platform_xilinx + generic map ( + g_fpga_family => "kintex7", + g_with_external_clock_input => false, + g_use_default_plls => TRUE, + g_simulation => 0, + g_use_ibufgds => false ) + port map ( + areset_n_i => areset_n_i, + clk_10m_ext_i => '0', + clk_20m_vcxo_i => wr_refclk_buf_i, + clk_125m_pllref_i => '0', -- only used for "spartan6" g_fpga_family + clk_125m_gtp_p_i => gige_refclk_buf_i, -- buffered on top level with IBUFDS_GTE2 + clk_125m_gtp_n_i => '0', + sfp_txn_o => sfp_txn_o, + sfp_txp_o => sfp_txp_o, + sfp_rxn_i => sfp_rxn_i, + sfp_rxp_i => sfp_rxp_i, + sfp_tx_fault_i => sfp_tx_fault_i, + sfp_los_i => sfp_los_i, + sfp_tx_disable_o => sfp_tx_disable_o, + clk_62m5_sys_o => clk_pll_62m5, -- gige_refclk_buf_i > BUFG > MMCM > BUFG 62.5M + clk_125m_ref_o => clk_ref_62m5, -- gige_refclk_buf_i > GTX > TXOUTCLK > BUFG 62.5M + clk_62m5_dmtd_o => clk_pll_dmtd, -- wr_refclk_buf_i > BUFG > MMCM > BUFG ~62.5M + pll_locked_o => pll_locked, + clk_10m_ext_o => clk_10m_ext, + phy16_o => phy16_to_wrc, + phy16_i => phy16_from_wrc, + ext_ref_mul_o => ext_ref_mul, + ext_ref_mul_locked_o => ext_ref_mul_locked, + ext_ref_mul_stopped_o => ext_ref_mul_stopped, + ext_ref_rst_i => ext_ref_rst); + + ----------------------------------------------------------------------------- + -- Reset logic + ----------------------------------------------------------------------------- + + -- logic AND of all async reset sources (active low) + rstlogic_arst_n <= pll_locked and areset_n_i; + + -- concatenation of all clocks required to have synced resets + rstlogic_clk_in(0) <= clk_pll_62m5; + rstlogic_clk_in(1) <= clk_ref_62m5; + + cmp_rstlogic_reset : gc_reset + generic map ( + g_clocks => 2, -- 62.5MHz, 125MHz + g_logdelay => 4, -- 16 clock cycles + g_syncdepth => 3) -- length of sync chains + port map ( + free_clk_i => gige_refclk_buf_i, + locked_i => rstlogic_arst_n, + clks_i => rstlogic_clk_in, + rstn_o => rstlogic_rst_out); + + -- distribution of resets (already synchronized to their clock domains) + rst_pll_62m5_n <= rstlogic_rst_out(0); + + -- rst_sys_62m5_n_o <= rst_pll_62m5_n; -- reset in 62.5 MHz domain, if needed + -- rst_ref_125m_n_o <= rstlogic_rst_out(1); -- reset in 125 MHz domain, if needed + + + ----------------------------------------------------------------------------- + -- 2x SPI DAC + ----------------------------------------------------------------------------- + + cmp_dac_arb : n3xx_serial_dac_arb + generic map ( + g_invert_sclk => FALSE, + g_num_extra_bits => 8) + port map ( + clk_i => clk_pll_62m5, + rst_n_i => rst_pll_62m5_n, + val1_i => dac_dpll_data, + load1_i => dac_dpll_load_p1, + val2_i => dac_hpll_data, + load2_i => dac_hpll_load_p1, + dac_cs_n_o => dac_cs_vec_n, + dac_clr_n_o => dac_clr_n_o, -- unused, always '1' + dac_sclk_o => dac_sclk_o, + dac_din_o => dac_din_o); + + -- only need one CS for the AD5663 DAC, channel is selected with data bits + dac_cs_n_o <= dac_cs_vec_n(0); + + -- nLDAC is unused. A command embedded in the DAC SPI transaction is used instead + -- to transfer the write from the input register to the DAC output. + dac_ldac_n_o <= '1'; + + + + ----------------------------------------------------------------------------- + -- The WR PTP core with optional fabric interface attached + ----------------------------------------------------------------------------- + + cmp_board_common : xwrc_board_common + generic map ( + g_simulation => 0, + g_with_external_clock_input => false, -- eventually true ! DJB ! + g_board_name => "NA ", + g_phys_uart => TRUE, + g_virtual_uart => false, + g_aux_clks => 0, + g_ep_rxbuf_size => 1024, + g_tx_runt_padding => TRUE, + g_dpram_initf => g_dpram_initf, + g_dpram_size => 131072/4, + g_interface_mode => PIPELINED, + g_address_granularity => BYTE, + g_aux_sdb => c_wrc_periph3_sdb, + g_softpll_enable_debugger => TRUE, -- was FALSE + g_vuart_fifo_size => 1024, + g_pcs_16bit => TRUE, + g_diag_id => 0, -- guessing about this + g_diag_ver => 185, -- setting the version reg to 0xB9 + g_diag_ro_size => 0, -- not sure if this is needed to enable diag regs + g_diag_rw_size => 16, -- not sure if this is needed to enable diag regs + g_streamers_op_mode => TX_AND_RX, + g_tx_streamer_params => c_tx_streamer_params_defaut, + g_rx_streamer_params => c_rx_streamer_params_defaut, + g_fabric_iface => plain + ) + port map ( + clk_sys_i => clk_pll_62m5, + clk_dmtd_i => clk_pll_dmtd, + clk_ref_i => clk_ref_62m5, + clk_aux_i => (others => '0'), + clk_10m_ext_i => '0', -- ! DJB ! eventually external 10 MHz clock + clk_ext_mul_i => ext_ref_mul, + clk_ext_mul_locked_i => ext_ref_mul_locked, + clk_ext_stopped_i => ext_ref_mul_stopped, + clk_ext_rst_o => ext_ref_rst, + pps_ext_i => '0', -- ! DJB ! eventually external PPS + rst_n_i => rst_pll_62m5_n, + dac_hpll_load_p1_o => dac_hpll_load_p1, + dac_hpll_data_o => dac_hpll_data, + dac_dpll_load_p1_o => dac_dpll_load_p1, + dac_dpll_data_o => dac_dpll_data, + phy16_o => phy16_from_wrc, + phy16_i => phy16_to_wrc, + scl_o => eeprom_scl_o, -- not using the I2C bus because we don't have a + scl_i => eeprom_scl_i, -- dedicated EEPROm for WR Cal. Instead plan + sda_o => eeprom_sda_o, -- to read cal values over the UART and store + sda_i => eeprom_sda_i, -- on the main uSD card. + sfp_scl_o => sfp_scl_o, + sfp_scl_i => sfp_scl_i, + sfp_sda_o => sfp_sda_o, + sfp_sda_i => sfp_sda_i, + sfp_det_i => sfp_mod_def0_b, + spi_sclk_o => open, + spi_ncs_o => open, + spi_mosi_o => open, + spi_miso_i => '0', + uart_rxd_i => wr_uart_rxd, + uart_txd_o => wr_uart_txd, + owr_pwren_o => open, + owr_en_o => open, + owr_i => "11", + wb_slave_i => wb_slave_in, + wb_slave_o => wb_slave_out, + aux_master_o => open, + aux_master_i => cc_dummy_master_in, + wrf_src_o => open, + wrf_src_i => c_dummy_src_in, + wrf_snk_o => open, + wrf_snk_i => c_dummy_snk_in, + wrs_tx_data_i => (others=>'0'), + wrs_tx_valid_i => '0', + wrs_tx_dreq_o => open, + wrs_tx_last_i => '1', + wrs_tx_flush_i => '0', + wrs_tx_cfg_i => c_tx_streamer_cfg_default, + wrs_rx_first_o => open, + wrs_rx_last_o => open, + wrs_rx_data_o => open, + wrs_rx_valid_o => open, + wrs_rx_dreq_i => '0', + wrs_rx_cfg_i => c_rx_streamer_cfg_default, + wb_eth_master_o => open, + wb_eth_master_i => cc_dummy_master_in, + aux_diag_i => (others=>(others=>'0')), + aux_diag_o => open, + tm_dac_value_o => open, + tm_dac_wr_o => open, + tm_clk_aux_lock_en_i => (others=>'0'), + tm_clk_aux_locked_o => open, + timestamps_o => open, + timestamps_ack_i => '1', + abscal_txts_o => open, + abscal_rxts_o => open, + fc_tx_pause_req_i => '0', + fc_tx_pause_delay_i => (others=>'0'), + fc_tx_pause_ready_o => open, + tm_link_up_o => open, + tm_time_valid_o => open, + tm_tai_o => open, + tm_cycles_o => open, + led_act_o => LED_ACT, + led_link_o => LED_LINK, + btn1_i => '1', + btn2_i => '1', + pps_p_o => pps, + pps_led_o => open, + link_ok_o => link_ok_o); + + -- I2C interface for SFP + --sfp_mod_def1_b <= '0' when sfp_scl_o = '0' else 'Z'; + --sfp_mod_def2_b <= '0' when sfp_sda_o = '0' else 'Z'; + --sfp_scl_i <= sfp_mod_def1_b; + --sfp_sda_i <= sfp_mod_def2_b; + + s00_axi_aclk_o <= clk_pll_62m5; + + zero <= '0'; + cmp_axi4lite_wbm: wb_axi4lite_bridge + port map ( + clk_sys_i => clk_pll_62m5, + rst_n_i => s00_axi_aresetn, + + AWADDR => s00_axi_awaddr, + AWVALID => s00_axi_awvalid, + AWREADY => s00_axi_awready, + WDATA => s00_axi_wdata, + WSTRB => s00_axi_wstrb, + WVALID => s00_axi_wvalid, + WREADY => s00_axi_wready, + WLAST => zero, + BRESP => s00_axi_bresp, + BVALID => s00_axi_bvalid, + BREADY => s00_axi_bready, + ARADDR => s00_axi_araddr, + ARVALID => s00_axi_arvalid, + ARREADY => s00_axi_arready, + RDATA => s00_axi_rdata, + RRESP => s00_axi_rresp, + RVALID => s00_axi_rvalid, + RREADY => s00_axi_rready, + RLAST => s00_axi_rlast, + + wb_adr => wb_slave_in.adr, + wb_dat_m2s => wb_slave_in.dat, + wb_sel => wb_slave_in.sel, + wb_cyc => wb_slave_in.cyc, + wb_stb => wb_slave_in.stb, + wb_we => wb_slave_in.we, + + wb_dat_s2m => wb_slave_out.dat, + wb_err => wb_slave_out.err, + wb_rty => wb_slave_out.rty, + wb_ack => wb_slave_out.ack, + wb_stall => wb_slave_out.stall + ); + + + -- locals to outputs + clk_pps_o <= clk_ref_62m5; -- ref_clk + pps_o <= pps; -- pps + +end architecture structure ; -- of n3xx_wr_top + diff --git a/fpga/usrp3/top/n3xx/setupenv.sh b/fpga/usrp3/top/n3xx/setupenv.sh new file mode 100644 index 000000000..0be100b62 --- /dev/null +++ b/fpga/usrp3/top/n3xx/setupenv.sh @@ -0,0 +1,13 @@ +#!/bin/bash + +VIVADO_VER=2019.1 +DISPLAY_NAME="USRP-N3x0" +REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd) + +declare -A PRODUCT_ID_MAP +PRODUCT_ID_MAP["N300"]="zynq/xc7z035/ffg900/-2" +PRODUCT_ID_MAP["N310"]="zynq/xc7z100/ffg900/-2" +PRODUCT_ID_MAP["N320"]="zynq/xc7z100/ffg900/-2" +PRODUCT_ID_MAP["EISCAT"]="zynq/xc7z100/ffg900/-2" + +source $REPO_BASE_PATH/tools/scripts/setupenv_base.sh diff --git a/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/Makefile b/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/Makefile new file mode 100644 index 000000000..1e783b2de --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/Makefile @@ -0,0 +1,84 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID = xc7z100/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs +include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs +include $(BASE_DIR)/../lib/xge/Makefile.srcs +include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/ten_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(XGE_SRCS) \ +$(XGE_INTERFACE_SRCS) \ +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_TEN_GIGE_PHY_XCI_SRCS) \ +$(TEN_GIGE_PHY_SRCS) \ +$(IP_AXI64_8K_2CLK_FIFO_SRCS) \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(PACKET_PROC_SRCS) \ +) +#$(IP_FIFO_SHORT_2CLK_SRCS) \ + + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +#include $(BASE_DIR)/../sim/general/Makefile.srcs +#include $(BASE_DIR)/../sim/control/Makefile.srcs +#include $(BASE_DIR)/../sim/axi/Makefile.srcs + +# Define only one toplevel module +SIM_TOP = arm_to_sfp_tb +# Simulation runtime in microseconds +SIM_RUNTIME_US = 30000 + +SIM_SRCS = \ +$(abspath arm_to_sfp_tb.sv) \ +$(SIM_GENERAL_SRCS) \ +$(SIM_CONTROL_SRCS) \ +$(SIM_AXI_SRCS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/arm_to_sfp_tb.sv b/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/arm_to_sfp_tb.sv new file mode 100644 index 000000000..46005a13a --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/arm_to_sfp_tb.sv @@ -0,0 +1,528 @@ +// +// Copyright 2017 Ettus Research +// + + +`timescale 1ns/1ps +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 13 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axis_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +module arm_to_sfp_tb(); + `TEST_BENCH_INIT("arm_to_sfp_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_CLK(XG_CLK_P, 1000/156.25, 50) //156.25MHz GT transceiver clock + `DEFINE_RESET(GSR, 0, 100) //100ns for GSR to deassert + + wire XG_CLK_N = ~XG_CLK_P; + wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N; + + //localparam PACKET_MODE = 0; + localparam PORTNUM = 8'd0; + + // ARM to SFP Loopback Topology: + // + // TB Simulus ====> |------------| |----------------| + // | XgigE MAC | <===> | XgigE PCS/PMA | <====>|| + // TB Checker <==== |------------| |----------------| || Loopback through + // || + // ====> |------------| |----------------| || perfect serial channel + // Loopback | | XgigE MAC | <===> | XgigE PCS/PMA | <====>|| + // <==== |------------| |----------------| + + // Initialize DUT + wire xgige_refclk, xgige_clk156, xgige_dclk; + wire m_user_clk, s_user_clk; + wire m_channel_up, s_channel_up; + + wire [63:0] m_xgmii_txd; + wire [7:0] m_xgmii_txc; + wire [63:0] m_xgmii_rxd; + wire [7:0] m_xgmii_rxc; + wire [63:0] s_xgmii_txd; + wire [7:0] s_xgmii_txc; + wire [63:0] s_xgmii_rxd; + wire [7:0] s_xgmii_rxc; + wire [7:0] m_xgmii_status; + wire [7:0] s_xgmii_status; + wire m_xge_phy_resetdone; + wire s_xge_phy_resetdone; + wire m_mdc, m_mdio_in, m_mdio_out; + wire s_mdc, s_mdio_in, s_mdio_out; + wire sfpp_rxlos,sfpp_tx_fault,sfpp_tx_disable; + + + wire [15:0] m_phy_status; + wire [15:0] s_phy_status; + wire [63:0] loop_tdata; + wire [3:0] loop_tuser; + wire loop_tlast, loop_tvalid, loop_tready; + + wire [7:0] wb_adr_i; + wire wb_cyc_i; + wire [31:0] wb_dat_i; + wire wb_stb_i; + wire wb_we_i; + wire wb_ack_o; + wire [31:0] wb_dat_o; + wire wb_int_o; + wire [63:0] c2e_tdata_int; + wire [3:0] c2e_tuser_int; + wire c2e_tlast_int; + wire c2e_tvalid_int; + wire c2e_tready_int; + wire [63:0] c2e_tdata; + wire [3:0] c2e_tuser; + wire c2e_tlast; + wire c2e_tvalid; + wire c2e_tready; + wire m_axis_tvalid; + wire m_axis_tlast; + wire [63:0] m_axis_tdata; + wire m_axis_tready; + wire [3:0] m_axis_tuser; + + reg independent_clock; + assign m_channel_up = m_phy_status[0]; + assign s_channel_up = s_phy_status[0]; + //assign m_user_clk = xgige_refclk; + //assign s_user_clk = xgige_refclk; + assign m_user_clk = independent_clock; + assign s_user_clk = independent_clock; + + ten_gige_phy_clk_gen xgige_clk_gen_i ( + .areset(GSR), + .refclk_p(XG_CLK_P), + .refclk_n(XG_CLK_N), + .refclk(xgige_refclk), + .clk156(xgige_clk156), + .dclk(xgige_dclk) + ); + + axis_master #(.DWIDTH(34)) m_axis (.clk(m_user_clk)); + axis_slave #(.DWIDTH(68)) s_axis (.clk(s_user_clk)); + + initial + begin + independent_clock <= 1'b0; + forever + begin + independent_clock <= 1'b0; + #2.5; + independent_clock <= 1'b1; + #2.5; + end + end + + assign sfpp_rxlos = 1'b0; + assign sfpp_tx_fault = 1'b0; + + // Instantiate the 10GBASER/KR GT Common block + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") ) //Does not affect hardware + ten_gig_eth_pcs_pma_gt_common_block + ( + .refclk(xgige_refclk), + .qpllreset(qpllreset), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclksel(3'b001 /*3'b101*GTSOUTHREFCLK0*/) + ); + + ten_gige_phy ten_gige_phy_master_i + ( + // Clocks and Reset + .areset(GSR), // Asynchronous reset for entire core. + .refclk(xgige_refclk), // Transciever reference clock: 156.25MHz + .clk156(xgige_clk156), // Globally buffered core clock: 156.25MHz + .dclk(xgige_dclk), // Management/DRP clock: 78.125MHz + .sim_speedup_control(~GSR), + // GMII Interface (client MAC <=> PCS) + .xgmii_txd(m_xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(m_xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(m_xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(m_xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(SFP_LN0_P), // Differential +ve of serial transmission from PMA to PMD. + .txn(SFP_LN0_N), // Differential -ve of serial transmission from PMA to PMD. + .rxp(SFP_LN1_P), // Differential +ve for serial reception from PMD to PMA. + .rxn(SFP_LN1_N), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(m_mdc), // Management Data Clock + .mdio_in(m_mdio_in), // Management Data In + .mdio_out(m_mdio_out), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(5'd4), // MDIO address is 4 + // General IO's + .core_status(m_xgmii_status), // Core status + .resetdone(m_xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), //FIXME // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), //FIXME + .tx_disable(/*sfpp_tx_disable*/), //FIXME + .qpllreset(qpllreset1), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk) + + ); + + n310_xge_mac_wrapper #(.PORTNUM(PORTNUM)) xge_mac_wrapper_master_i + ( + // XGMII + .xgmii_clk(xgige_clk156), + .xgmii_txd(m_xgmii_txd), + .xgmii_txc(m_xgmii_txc), + .xgmii_rxd(m_xgmii_rxd), + .xgmii_rxc(m_xgmii_rxc), + // Client FIFO Interfaces + .sys_clk(m_user_clk), + .sys_rst(GSR), + .rx_tdata(s_axis.axis.tdata[63:0]), + .rx_tuser(s_axis.axis.tdata[67:64]), + .rx_tlast(s_axis.axis.tlast), + .rx_tvalid(s_axis.axis.tvalid), + .rx_tready(/*s_axis.axis.tready*/1'b1), + .tx_tdata(c2e_tdata), + .tx_tuser(c2e_tuser), // Bit[3] (error) is ignored for now. + .tx_tlast(c2e_tlast), + .tx_tvalid(c2e_tvalid), + .tx_tready(c2e_tready), + // Other + .phy_ready(m_xge_phy_resetdone), + .ctrl_tx_enable (/*mac_ctrl_reg[0]*/1'b1), //FIXME: Remove hardcoded value + .status_crc_error (), + .status_fragment_error (), + .status_txdfifo_ovflow (), + .status_txdfifo_udflow (), + .status_rxdfifo_ovflow (), + .status_rxdfifo_udflow (), + .status_pause_frame_rx (), + .status_local_fault (), + .status_remote_fault () + ); + + assign m_phy_status = {8'h00, m_xgmii_status}; + + axi_fifo32_to_fifo64 inst_axi_fifo32_to_fifo64 + ( + .clk(m_user_clk), + .reset(GSR), + .i_tdata({m_axis.axis.tdata[31:0]}), // endian swap + .i_tuser(m_axis.axis.tdata[33:32]), + .i_tlast(m_axis.axis.tlast), + .i_tvalid(m_axis.axis.tvalid), + .i_tready(m_axis.axis.tready), + .o_tdata(m_axis_tdata), + .o_tuser(m_axis_tuser), + .o_tlast(m_axis_tlast), + .o_tvalid(m_axis_tvalid), + .o_tready(m_axis_tready) + ); + + arm_framer inst_arm_framer ( + .clk (m_user_clk), + .reset (GSR), + .clear (clear), + .s_axis_tdata (m_axis_tdata), + .s_axis_tuser (m_axis_tuser), + .s_axis_tlast (m_axis_tlast), + .s_axis_tvalid (m_axis_tvalid), + .s_axis_tready (m_axis_tready), + .m_axis_tdata (c2e_tdata_int), + .m_axis_tuser (c2e_tuser_int), + .m_axis_tlast (c2e_tlast_int), + .m_axis_tvalid (c2e_tvalid_int), + .m_axis_tready (c2e_tready_int) + ); + + axi_mux4 #(.PRIO(0), .WIDTH(68)) eth_mux + (.clk(m_user_clk), .reset(GSR), .clear(clear), + .i0_tdata({c2e_tuser_int,c2e_tdata_int}), .i0_tlast(c2e_tlast_int), .i0_tvalid(c2e_tvalid_int), .i0_tready(c2e_tready_int), + .i1_tdata(), .i1_tlast(), .i1_tvalid(), .i1_tready(), + .i2_tdata(), .i2_tlast(), .i2_tvalid(), .i2_tready(), + .i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(), + .o_tdata({c2e_tuser,c2e_tdata}), .o_tlast(c2e_tlast), .o_tvalid(c2e_tvalid), .o_tready(c2e_tready)); + + ten_gige_phy ten_gige_phy_slave_i + ( + // Clocks and Reset + .areset(GSR), // Asynchronous reset for entire core. + .refclk(xgige_refclk), // Transciever reference clock: 156.25MHz + .clk156(xgige_clk156), // Globally buffered core clock: 156.25MHz + .dclk(xgige_dclk), // Management/DRP clock: 78.125MHz + .sim_speedup_control(~GSR), + // GMII Interface (client MAC <=> PCS) + .xgmii_txd(s_xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(s_xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(s_xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(s_xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(SFP_LN1_P), // Differential +ve of serial transmission from PMA to PMD. + .txn(SFP_LN1_N), // Differential -ve of serial transmission from PMA to PMD. + .rxp(SFP_LN0_P), // Differential +ve for serial reception from PMD to PMA. + .rxn(SFP_LN0_N), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(s_mdc), // Management Data Clock + .mdio_in(s_mdio_in), // Management Data In + .mdio_out(s_mdio_out), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(5'd4), // MDIO address is 4 + // General IO's + .core_status(s_xgmii_status), // Core status + .resetdone(s_xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), //FIXME // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), //FIXME + .tx_disable(/*sfpp_tx_disable*/), //FIXME + .qpllreset(qpllreset2), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk) + ); + + n310_xge_mac_wrapper #(.PORTNUM(PORTNUM)) xge_mac_wrapper_slave_i + ( + // XGMII + .xgmii_clk(xgige_clk156), + .xgmii_txd(s_xgmii_txd), + .xgmii_txc(s_xgmii_txc), + .xgmii_rxd(s_xgmii_rxd), + .xgmii_rxc(s_xgmii_rxc), + // Client FIFO Interfaces + .sys_clk(s_user_clk), + .sys_rst(GSR), + .rx_tdata(loop_tdata), + .rx_tuser(loop_tuser), + .rx_tlast(loop_tlast), + .rx_tvalid(loop_tvalid), + .rx_tready(loop_tready), + .tx_tdata(loop_tdata), + .tx_tuser(loop_tuser), // Bit[3] (error) is ignored for now. + .tx_tlast(loop_tlast), + .tx_tvalid(loop_tvalid), + .tx_tready(loop_tready), + // Other + .phy_ready(s_xge_phy_resetdone), + .ctrl_tx_enable (/*mac_ctrl_reg[0]*/1'b1), //FIXME: Remove hardcoded value + .status_crc_error (), + .status_fragment_error (), + .status_txdfifo_ovflow (), + .status_txdfifo_udflow (), + .status_rxdfifo_ovflow (), + .status_rxdfifo_udflow (), + .status_pause_frame_rx (), + .status_local_fault (), + .status_remote_fault () + ); + + assign s_phy_status = {8'h00, s_xgmii_status}; + + //Testbench variables + cvita_hdr_t header, header_out; + cvita_stats_t stats; + logic [63:0] crc_cache; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + `TEST_CASE_START("Wait for reset"); + m_axis.reset; + while (GSR) @(posedge XG_CLK_P); + `TEST_CASE_DONE((~GSR)); + + m_axis.push_bubble(); + + `TEST_CASE_START("Wait for master channel to come up"); + while (m_channel_up !== 1'b1) @(posedge m_user_clk); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Wait for slave channel to come up"); + while (s_channel_up !== 1'b1) @(posedge s_user_clk); + `TEST_CASE_DONE(1'b1); + + repeat(2000) @(posedge m_user_clk); + + //`TEST_CASE_START("Test Ethernet packet"); + // s_axis.axis.tready = 0; + // m_axis.push_word({4'b0, 64'h0000_0000_0000_ffff}, 1'b0); + // s_axis.axis.tready = 1; + // m_axis.push_word({4'b0, 64'hffff_ffff_ce20_ad1b}, 1'b0); + // m_axis.push_word({4'b0, 64'hc57a_0806_0001_0800}, 1'b0); + // m_axis.push_word({4'b0, 64'h0604_0001_ce20_ad1b}, 1'b0); + // m_axis.push_word({4'b0, 64'hc57a_c0a8_0a64_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_c0a8_0a0a}, 1'b1); + //`TEST_CASE_DONE(1'b1); + //`TEST_CASE_START("Test Ethernet packet"); + // s_axis.axis.tready = 0; + // m_axis.push_word({4'b0, 64'hffff_ffff_ffff_ce20}, 1'b0); + // s_axis.axis.tready = 1; + // m_axis.push_word({4'b0, 64'had1b_c57a_0806_0001}, 1'b0); + // m_axis.push_word({4'b0, 64'h0800_0604_0001_ce20}, 1'b0); + // m_axis.push_word({4'b0, 64'had1b_c57a_c0a8_0a64}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_c0a8}, 1'b0); + // m_axis.push_word({4'd2, 64'h0a0a_1111_1111_1111}, 1'b1); + //`TEST_CASE_DONE(1'b1); + // repeat(2000) @(posedge m_user_clk); + `TEST_CASE_START("Test Ethernet packet"); + s_axis.axis.tready = 0; + m_axis.push_word({2'b0, 32'hffff_ffff}, 1'b0); + s_axis.axis.tready = 1; + m_axis.push_word({2'b0, 32'hffff_9aa9}, 1'b0); + m_axis.push_word({2'b0, 32'h6400_e341}, 1'b0); + m_axis.push_word({2'b0, 32'h0800_4500}, 1'b0); + m_axis.push_word({2'b0, 32'h0148_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_4011}, 1'b0); + m_axis.push_word({2'b0, 32'h79a6_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_ffff}, 1'b0); + m_axis.push_word({2'b0, 32'hffff_0044}, 1'b0); + m_axis.push_word({2'b0, 32'h0043_0134}, 1'b0); + m_axis.push_word({2'b0, 32'h90be_0101}, 1'b0); + m_axis.push_word({2'b0, 32'h0600_d2ab}, 1'b0); + m_axis.push_word({2'b0, 32'h9f01_0007}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_9aa9}, 1'b0); + m_axis.push_word({2'b0, 32'h6400_e341}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_6382}, 1'b0); + m_axis.push_word({2'b0, 32'h5363_3501}, 1'b0); + m_axis.push_word({2'b0, 32'h013d_0701}, 1'b0); + m_axis.push_word({2'b0, 32'h9aa9_6400}, 1'b0); + m_axis.push_word({2'b0, 32'he341_3902}, 1'b0); + m_axis.push_word({2'b0, 32'h0240_3707}, 1'b0); + m_axis.push_word({2'b0, 32'h0103_060c}, 1'b0); + m_axis.push_word({2'b0, 32'h0f1c_2a3c}, 1'b0); + m_axis.push_word({2'b0, 32'h0c75_6468}, 1'b0); + m_axis.push_word({2'b0, 32'h6370_2031}, 1'b0); + m_axis.push_word({2'b0, 32'h2e32_342e}, 1'b0); + m_axis.push_word({2'b0, 32'h31ff_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'd2, 32'h0000_0000}, 1'b1); + + `TEST_CASE_DONE(1'b1); + + repeat(2000) @(posedge m_user_clk); + + `TEST_CASE_START("Test Ethernet packet"); + s_axis.axis.tready = 0; + m_axis.push_word({2'b0, 32'h01005e7f }, 1'b0); + s_axis.axis.tready = 1; + m_axis.push_word({2'b0, 32'hfffa90e2 }, 1'b0); + m_axis.push_word({2'b0, 32'hba3aa7e8 }, 1'b0); + m_axis.push_word({2'b0, 32'h08004500 }, 1'b0); + m_axis.push_word({2'b0, 32'h00c7515e }, 1'b0); + m_axis.push_word({2'b0, 32'h40000111 }, 1'b0); + m_axis.push_word({2'b0, 32'h6d1bc0a8 }, 1'b0); + m_axis.push_word({2'b0, 32'h0a0aefff }, 1'b0); + m_axis.push_word({2'b0, 32'hfffad40f }, 1'b0); + m_axis.push_word({2'b0, 32'h076c00b3 }, 1'b0); + m_axis.push_word({2'b0, 32'hbb714d2d }, 1'b0); + m_axis.push_word({2'b0, 32'h53454152 }, 1'b0); + m_axis.push_word({2'b0, 32'h4348202a }, 1'b0); + m_axis.push_word({2'b0, 32'h20485454 }, 1'b0); + m_axis.push_word({2'b0, 32'h502f312e }, 1'b0); + m_axis.push_word({2'b0, 32'h310d0a48 }, 1'b0); + m_axis.push_word({2'b0, 32'h4f53543a }, 1'b0); + m_axis.push_word({2'b0, 32'h20323339 }, 1'b0); + m_axis.push_word({2'b0, 32'h2e323535 }, 1'b0); + m_axis.push_word({2'b0, 32'h2e323535 }, 1'b0); + m_axis.push_word({2'b0, 32'h2e323530 }, 1'b0); + m_axis.push_word({2'b0, 32'h3a313930 }, 1'b0); + m_axis.push_word({2'b0, 32'h300d0a4d }, 1'b0); + m_axis.push_word({2'b0, 32'h414e3a20 }, 1'b0); + m_axis.push_word({2'b0, 32'h22737364 }, 1'b0); + m_axis.push_word({2'b0, 32'h703a6469 }, 1'b0); + m_axis.push_word({2'b0, 32'h73636f76 }, 1'b0); + m_axis.push_word({2'b0, 32'h6572220d }, 1'b0); + m_axis.push_word({2'b0, 32'h0a4d583a }, 1'b0); + m_axis.push_word({2'b0, 32'h20310d0a }, 1'b0); + m_axis.push_word({2'b0, 32'h53543a20 }, 1'b0); + m_axis.push_word({2'b0, 32'h75726e3a }, 1'b0); + m_axis.push_word({2'b0, 32'h6469616c }, 1'b0); + m_axis.push_word({2'b0, 32'h2d6d756c }, 1'b0); + m_axis.push_word({2'b0, 32'h74697363 }, 1'b0); + m_axis.push_word({2'b0, 32'h7265656e }, 1'b0); + m_axis.push_word({2'b0, 32'h2d6f7267 }, 1'b0); + m_axis.push_word({2'b0, 32'h3a736572 }, 1'b0); + m_axis.push_word({2'b0, 32'h76696365 }, 1'b0); + m_axis.push_word({2'b0, 32'h3a646961 }, 1'b0); + m_axis.push_word({2'b0, 32'h6c3a310d }, 1'b0); + m_axis.push_word({2'b0, 32'h0a555345 }, 1'b0); + m_axis.push_word({2'b0, 32'h522d4147 }, 1'b0); + m_axis.push_word({2'b0, 32'h454e543a }, 1'b0); + m_axis.push_word({2'b0, 32'h20476f6f }, 1'b0); + m_axis.push_word({2'b0, 32'h676c6520 }, 1'b0); + m_axis.push_word({2'b0, 32'h4368726f }, 1'b0); + m_axis.push_word({2'b0, 32'h6d652f35 }, 1'b0); + m_axis.push_word({2'b0, 32'h342e302e }, 1'b0); + m_axis.push_word({2'b0, 32'h32383430 }, 1'b0); + m_axis.push_word({2'b0, 32'h2e353920 }, 1'b0); + m_axis.push_word({2'b0, 32'h4c696e75 }, 1'b0); + m_axis.push_word({2'b1, 32'h78111111 }, 1'b1); + + `TEST_CASE_DONE(1'b1); + end + +endmodule diff --git a/fpga/usrp3/top/n3xx/sim/aurora_loopback/Makefile b/fpga/usrp3/top/n3xx/sim/aurora_loopback/Makefile new file mode 100644 index 000000000..c4cdf38dd --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/aurora_loopback/Makefile @@ -0,0 +1,80 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID = xc7z100/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs +include $(BASE_DIR)/../lib/rfnoc/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +$(RFNOC_SRCS) \ +../../n3xx_npio_qsfp_wrapper.v \ +../../n3xx_mgt_io_core.v \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/aurora_64b66b_pcs_pma/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_AURORA_64B66B_PCS_PMA_SRCS) \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +$(AURORA_PHY_SRCS) \ +$(AURORA_PHY_1_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +include $(BASE_DIR)/../sim/general/Makefile.srcs +include $(BASE_DIR)/../sim/control/Makefile.srcs +include $(BASE_DIR)/../sim/axi/Makefile.srcs + +# Define only one toplevel module +SIM_TOP = aurora_loopback_tb +# Simulation runtime in microseconds +SIM_RUNTIME_US = 70 + +SIM_SRCS = \ +$(abspath aurora_loopback_tb.sv) \ +$(SIM_GENERAL_SRCS) \ +$(SIM_CONTROL_SRCS) \ +$(SIM_AXI_SRCS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/n3xx/sim/aurora_loopback/aurora_loopback_tb.sv b/fpga/usrp3/top/n3xx/sim/aurora_loopback/aurora_loopback_tb.sv new file mode 100644 index 000000000..ed328f153 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/aurora_loopback/aurora_loopback_tb.sv @@ -0,0 +1,395 @@ +///////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +///////////////////////////////////////////////////////////////// + + + +`timescale 1ns/1ps +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 13 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +module aurora_loopback_tb(); + `TEST_BENCH_INIT("aurora_loopback_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_CLK(XG_CLK_P, 1000/156.25, 50) //156.25MHz GT transceiver clock + `DEFINE_CLK(bus_clk, 1000/200, 50) //define 200 MHz bus clk + `DEFINE_RESET(GSR, 0, 100) //100ns for GSR to deassert + + wire XG_CLK_N = ~XG_CLK_P; + wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N; + + localparam PACKET_MODE = 1; + + // Aurora Loopback Topology: + // + // TB Simulus ====> |------------| |----------------| + // | Aurora MAC | <===> | Aurora PCS/PMA | <====>|| + // TB Checker <==== |------------| |----------------| || Loopback through + // || + // + // |-------------------------------------| + // | n3xx_npio_qsfp_wrapper | + // ====> |------------| |----------------| || perfect serial channel + // Loopback | | Aurora MAC | <===> | Aurora PCS/PMA | <====>|| + // <==== |------------| |----------------| + // |-------------------------------------| + + // Initialize DUT + wire aurora_refclk, aurora_init_clk; + wire aurora_clk156; + wire m_user_rst, s_user_rst; + wire m_channel_up, s_channel_up; + wire m_hard_err, s_hard_err; + wire m_soft_err, s_soft_err; + wire s_link_up; + +(* dont_touch = "true" *) IBUFDS_GTE2 aurora_refclk_ibuf ( + .ODIV2(), + .CEB (1'b0), + .I (XG_CLK_P), + .IB(XG_CLK_N), + .O (aurora_refclk) + ); + + aurora_phy_clk_gen aurora_clk_gen_i ( + .refclk_ibuf(aurora_refclk), + .clk156(aurora_clk156), + .init_clk(aurora_init_clk) + ); + wire qpllreset, qpllreset_slave; + wire qplllock, qplllock_slave; + wire qplloutclk, qplloutclk_slave; + wire qplloutrefclk, qplloutrefclk_slave; + wire qpllrefclklost, qpllrefclklost_slave; + wire [7:0] qpll_drpaddr_in_i = 8'h0; + wire [15:0] qpll_drpdi_in_i = 16'h0; + wire qpll_drpen_in_i = 1'b0; + wire qpll_drpwe_in_i = 1'b0; + wire [15:0] qpll_drpdo_out_i, qpll_drpdo_out_s_i; + wire qpll_drprdy_out_i, qpll_drprdy_out_s_i; + + aurora_64b66b_pcs_pma_gt_common_wrapper gt_common_support ( + .gt_qpllclk_quad1_out (qplloutclk), //to sfp + .gt_qpllrefclk_quad1_out (qplloutrefclk), // to sfp + .GT0_GTREFCLK0_COMMON_IN (aurora_refclk), +//----------------------- Common Block - QPLL Ports ------------------------ + .GT0_QPLLLOCK_OUT (qplllock), //from 1st sfp + .GT0_QPLLRESET_IN (qpllreset), //from 1st sfp + .GT0_QPLLLOCKDETCLK_IN (aurora_init_clk), + .GT0_QPLLREFCLKLOST_OUT (qpllrefclklost), //from 1st sfp +//---------------------- Common DRP Ports ---------------------- //not really used??? + .qpll_drpaddr_in (qpll_drpaddr_in_i), + .qpll_drpdi_in (qpll_drpdi_in_i), + .qpll_drpclk_in (aurora_init_clk), + .qpll_drpdo_out (qpll_drpdo_out_i), + .qpll_drprdy_out (qpll_drprdy_out_i), + .qpll_drpen_in (qpll_drpen_in_i), + .qpll_drpwe_in (qpll_drpwe_in_i) + ); + + wire au_master_tx_out_clk, au_slave_tx_out_clk; + wire au_master_gt_pll_lock, au_slave_gt_pll_lock; + wire au_user_clk, au_sync_clk, au_mmcm_locked; + wire au_s_user_clk, au_s_sync_clk, au_s_mmcm_locked; + wire au_master_phy_reset; + + aurora_phy_mmcm aurora_phy_mmcm_0 ( + .aurora_tx_clk_unbuf(au_master_tx_out_clk), + .mmcm_reset(!au_master_gt_pll_lock), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .mmcm_locked(au_mmcm_locked) + ); + + wire [63:0] m_i_tdata, m_o_tdata; + wire m_i_tvalid, m_i_tready, m_o_tvalid; + wire [63:0] s_i_tdata, s_o_tdata; + wire s_i_tvalid, s_i_tready, s_o_tvalid; + wire [63:0] loop_tdata; + wire loop_tlast, loop_tvalid, loop_tready; + wire [31:0] m_overruns; + reg [31:0] s_overruns; + wire [31:0] m_soft_errors, s_soft_errors; + reg m_bist_gen, m_bist_check, s_bist_loopback; + reg [5:0] m_bist_rate; + wire m_bist_locked; + wire [47:0] m_bist_samps, m_bist_errors; + + cvita_master m_tx_chdr (.clk(au_user_clk)); + cvita_slave m_rx_chdr (.clk(au_user_clk)); + + aurora_phy_x1 #(.SIMULATION(1)) aurora_phy_master_i ( + // Resets + .areset(GSR), + // Clocks + .refclk(aurora_refclk), + .qpllclk(qplloutclk), + .qpllrefclk(qplloutrefclk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .init_clk(aurora_init_clk), + .user_rst(m_user_rst), + // GTX Serial I/O + .tx_p(SFP_LN0_P), .tx_n(SFP_LN0_N), + .rx_p(SFP_LN1_P), .rx_n(SFP_LN1_N), + // AXI4-Stream TX Interface + .s_axis_tdata(m_i_tdata), .s_axis_tvalid(m_i_tvalid), .s_axis_tready(m_i_tready), + // AXI4-Stream RX Interface + .m_axis_tdata(m_o_tdata), .m_axis_tvalid(m_o_tvalid), + // AXI4-Lite Config Interface + .s_axi_awaddr(32'h0), .s_axi_araddr(32'h0), .s_axi_awvalid(1'b0), .s_axi_awready(), + .s_axi_wdata(32'h0), .s_axi_wvalid(1'b0), .s_axi_wstrb(1'b0), .s_axi_wready(), + .s_axi_bvalid(), .s_axi_bresp(), .s_axi_bready(1'b1), + .s_axi_arready(), .s_axi_arvalid(1'b0), + .s_axi_rdata(), .s_axi_rvalid(), .s_axi_rresp(), .s_axi_rready(1'b1), + // Status and Error Reporting Interface + .channel_up(m_channel_up), .hard_err(m_hard_err), .soft_err(m_soft_err), + .qplllock(qplllock), + .qpllreset(qpllreset), + .qpllrefclklost(qpllrefclklost), + .tx_out_clk(au_master_tx_out_clk), + .gt_pll_lock(au_master_gt_pll_lock), + .mmcm_locked(au_mmcm_locked) + ); + + aurora_axis_mac #(.PACKET_MODE(PACKET_MODE), .BIST_ENABLED(1)) aurora_mac_master_i ( + // Clocks and resets + .phy_clk(au_user_clk), .phy_rst(m_user_rst), + .sys_clk(au_user_clk), .sys_rst(m_user_rst), + .clear(1'b0), + // PHY Interface + .phy_s_axis_tdata(m_o_tdata), .phy_s_axis_tvalid(m_o_tvalid), + .phy_m_axis_tdata(m_i_tdata), .phy_m_axis_tvalid(m_i_tvalid), .phy_m_axis_tready(m_i_tready), + // User Interface + .s_axis_tdata(m_tx_chdr.axis.tdata), .s_axis_tlast(m_tx_chdr.axis.tlast), + .s_axis_tvalid(m_tx_chdr.axis.tvalid), .s_axis_tready(m_tx_chdr.axis.tready), + .m_axis_tdata(m_rx_chdr.axis.tdata), .m_axis_tlast(m_rx_chdr.axis.tlast), + .m_axis_tvalid(m_rx_chdr.axis.tvalid), .m_axis_tready(m_rx_chdr.axis.tready), + // Misc PHY + .channel_up(m_channel_up), .hard_err(m_hard_err), .soft_err(m_soft_err), + .overruns(m_overruns), .soft_errors(m_soft_errors), + //BIST + .bist_gen_en(m_bist_gen), .bist_checker_en(m_bist_check), .bist_loopback_en(1'b0), .bist_gen_rate(m_bist_rate), + .bist_checker_locked(m_bist_locked), .bist_checker_samps(m_bist_samps), .bist_checker_errors(m_bist_errors) + ); + +reg reg_wr_req_s; +reg [13:0] reg_wr_addr_s; +reg [31:0] reg_wr_data_s; +reg reg_rd_req_s; +reg [13:0] reg_rd_addr_s; +wire reg_rd_resp_s; +wire [31:0] reg_rd_data_s; + +n3xx_npio_qsfp_wrapper #( + .LANES(1), // Number of lanes of Aurora to instantiate (Supported = {1,2,3,4}) + .REG_BASE(32'h0), // Base register address + .PORTNUM_BASE(4), // Base port number for discovery + .REG_DWIDTH(32), // Width of regport address bus + .REG_AWIDTH(14) // Width of regport data bus +) qsfp_wrapper_inst ( + // Clocks and Resets + .areset(GSR), + .bus_clk(bus_clk), + .misc_clk(aurora_init_clk), + .bus_rst(GSR), + .gt_refclk(aurora_refclk), + .gt_clk156(aurora_clk156), + // Serial lanes + .txp(SFP_LN1_P), + .txn(SFP_LN1_N), + .rxp(SFP_LN0_P), + .rxn(SFP_LN0_N), + // AXIS input interface + .s_axis_tdata(loop_tdata), + .s_axis_tlast(loop_tlast), + .s_axis_tvalid(~s_bist_loopback & loop_tvalid), + .s_axis_tready(loop_tready), + // AXIS output interface + .m_axis_tdata(loop_tdata), + .m_axis_tlast(loop_tlast), + .m_axis_tvalid(loop_tvalid), + .m_axis_tready(~s_bist_loopback & loop_tready), + // Register ports + .reg_wr_req(reg_wr_req_s), //input reg_wr_req, + .reg_wr_addr(reg_wr_addr_s), //input [REG_AWIDTH-1:0] reg_wr_addr, + .reg_wr_data(reg_wr_data_s), //input [REG_DWIDTH-1:0] reg_wr_data, + .reg_rd_req(reg_rd_req_s), //input reg_rd_req, + .reg_rd_addr(reg_rd_addr_s), //input [REG_AWIDTH-1:0] reg_rd_addr, + .reg_rd_resp(reg_rd_resp_s), //output reg_rd_resp, + .reg_rd_data(reg_rd_data_s), //output [REG_DWIDTH-1:0] reg_rd_data, + + .link_up(s_link_up), + .activity() +); + + //Testbench variables + cvita_hdr_t header, header_out; + cvita_stats_t stats; + logic [63:0] crc_cache; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + `TEST_CASE_START("Wait for reset"); + while (GSR) @(posedge aurora_refclk); + `TEST_CASE_DONE((~GSR)); + + m_bist_gen <= 1'b0; + m_bist_rate <= 6'd0; + m_bist_check <= 1'b0; + s_bist_loopback <= 1'b0; + + m_tx_chdr.push_bubble(); + + `TEST_CASE_START("Wait for master channel to come up"); + while (m_channel_up !== 1'b1) @(posedge au_user_clk); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Wait for slave channel to come up. Uses QSFP Wrapper"); + while (s_link_up !== 1'b1) @(posedge bus_clk); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Run PRBS BIST"); + s_bist_loopback <= PACKET_MODE; + $display("Need to interact with regport to set s_bist_loopback."); + reg_wr_req_s <= 1; + reg_wr_addr_s <= 4; + reg_wr_data_s <= 4; + @(posedge bus_clk); + repeat (3) @(posedge au_user_clk); + reg_wr_req_s <= 0; + m_bist_rate <= 6'd60; + m_bist_gen <= 1'b1; + m_bist_check <= 1'b1; + @(posedge au_user_clk); + while (m_bist_locked !== 1'b1) @(posedge au_user_clk); + repeat (512) @(posedge au_user_clk); + `ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + `ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + @(posedge au_user_clk); + m_bist_gen <= 1'b0; + repeat (256) @(posedge au_user_clk); + m_bist_check <= 1'b0; + `TEST_CASE_DONE(1'b1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Fill up empty FIFO then drain (short packet)"); + m_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(16, 64'd0, 64'h100, header); + m_rx_chdr.axis.tready = 1; + m_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==16, "Bad packet: Length mismatch"); + `ASSERT_ERROR(header.src_sid==header_out.src_sid, "Bad packet: Wrong Src SID"); + `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong Dst SID"); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Fill up empty FIFO then drain (long packet)"); + m_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(256, 64'd0, 64'h100, header); + m_rx_chdr.axis.tready = 1; + m_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==256, "Bad packet: Length mismatch"); + `ASSERT_ERROR(header.src_sid==header_out.src_sid, "Bad packet: Wrong Src SID"); + `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong Dst SID"); + `TEST_CASE_DONE(1); + + header = '{ + pkt_type:DATA, has_time:1, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Concurrent read and write (single packet)"); + repeat (10) @(posedge au_user_clk); //Wait for clear to go low + m_rx_chdr.axis.tready = 1; + fork + begin + m_tx_chdr.push_ramp_pkt(200, 64'd0, 64'h100, header); + end + begin + m_rx_chdr.wait_for_pkt_get_info(header_out, stats); + end + join + crc_cache = stats.crc; //Cache CRC for future test cases + `ASSERT_ERROR(stats.count==201, "Bad packet: Length mismatch"); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Concurrent read and write (multiple packets)"); + m_rx_chdr.axis.tready = 1; + fork + begin + repeat (20) begin + m_tx_chdr.push_ramp_pkt(20, 64'd0, 64'h100, header); + m_tx_chdr.push_bubble(); + end + end + begin + repeat (20) begin + m_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==21, "Bad packet: Length mismatch"); + `ASSERT_ERROR(crc_cache==stats.crc, "Bad packet: Wrong CRC"); + end + end + join + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Validate no drops (master)"); + `TEST_CASE_DONE((m_overruns === 32'd0)); + + `TEST_CASE_START("Validate no drops (slave)"); + reg_rd_req_s <= 1; + reg_rd_addr_s <= 'h20; + @(posedge reg_rd_resp_s) + reg_rd_req_s <= 0; + s_overruns <= reg_rd_data_s; + `TEST_CASE_DONE((s_overruns === 32'd0)); + + s_bist_loopback <= 1'b1; + + `TEST_CASE_START("Run PRBS BIST (Loopback Mode)"); + @(posedge au_user_clk); + m_bist_gen <= 1'b1; + m_bist_rate <= 6'd60; + m_bist_check <= 1'b1; + @(posedge au_user_clk); + while (m_bist_locked !== 1'b1) @(posedge au_user_clk); + repeat (512) @(posedge au_user_clk); + `ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + `ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + @(posedge au_user_clk); + m_bist_gen <= 1'b0; + repeat (256) @(posedge au_user_clk); + m_bist_check <= 1'b0; + `TEST_CASE_DONE(1'b1); + + s_bist_loopback <= 1'b0; + + `TEST_CASE_START("Validate no drops (master)"); + `TEST_CASE_DONE((m_overruns === 32'd0)); + + `TEST_CASE_START("Validate no drops (slave)"); + reg_rd_req_s <= 1; + reg_rd_addr_s <= 'h20; + @(posedge reg_rd_resp_s) + reg_rd_req_s <= 0; + s_overruns <= reg_rd_data_s; + `TEST_CASE_DONE((s_overruns === 32'd0)); + + `TEST_BENCH_DONE; + end + +endmodule diff --git a/fpga/usrp3/top/n3xx/sim/dram_fifo/Makefile b/fpga/usrp3/top/n3xx/sim/dram_fifo/Makefile new file mode 100644 index 000000000..738cb12dc --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/dram_fifo/Makefile @@ -0,0 +1,70 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID = xc7z100/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/ddr3_32bit/Makefile.inc +include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_DDR3_32BIT_SRCS) \ +$(IP_AXI_INTERCON_4X64_256_SRCS) \ +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = dram_fifo_tb + +SIM_SRCS = \ +$(abspath dram_fifo_tb.sv) \ +$(abspath axis_dram_fifo_single.sv) \ +$(IP_DDR3_32BIT_SIM_OUTS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/n3xx/sim/dram_fifo/axis_dram_fifo_single.sv b/fpga/usrp3/top/n3xx/sim/dram_fifo/axis_dram_fifo_single.sv new file mode 100644 index 000000000..63bea218e --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/dram_fifo/axis_dram_fifo_single.sv @@ -0,0 +1,493 @@ +// +// Copyright 2015 Ettus Research LLC +// + +`timescale 1ns/1ps + +module axis_dram_fifo_single +#( + parameter DIFF_CLK = 0, + parameter SR_BASE = 0 +) ( + input bus_clk, + input bus_rst, + input sys_clk_p, + input sys_clk_n, + input sys_rst_n, + input dma_engine_clk, + + input [63:0] i_tdata, + input i_tlast, + input i_tvalid, + output i_tready, + + output [63:0] o_tdata, + output o_tlast, + output o_tvalid, + input o_tready, + + input set_stb, + input [7:0] set_addr, + input [31:0] set_data, + output [31:0] rb_data, + + input [63:0] forced_bit_err, + + output init_calib_complete +); + + wire ddr3_axi_clk; // 1/4 DDR external clock rate (250MHz) + wire ddr3_axi_rst; // Synchronized to ddr_sys_clk + reg ddr3_axi_rst_reg_n; // Synchronized to ddr_sys_clk + + // Misc declarations + axi4_rd_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_rd(.clk(dma_engine_clk)); + axi4_wr_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_wr(.clk(dma_engine_clk)); + axi4_rd_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(4)) mig_axi_rd(.clk(ddr3_axi_clk)); + axi4_wr_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(4)) mig_axi_wr(.clk(ddr3_axi_clk)); + + wire [31:0] ddr3_dq; // Data pins. Input for Reads; Output for Writes. + wire [3:0] ddr3_dqs_n; // Data Strobes. Input for Reads; Output for Writes. + wire [3:0] ddr3_dqs_p; + wire [15:0] ddr3_addr; // Address + wire [2:0] ddr3_ba; // Bank Address + wire ddr3_ras_n; // Row Address Strobe. + wire ddr3_cas_n; // Column address select + wire ddr3_we_n; // Write Enable + wire ddr3_reset_n; // SDRAM reset pin. + wire [0:0] ddr3_ck_p; // Differential clock + wire [0:0] ddr3_ck_n; + wire [0:0] ddr3_cke; // Clock Enable + wire [0:0] ddr3_cs_n; // Chip Select + wire [3:0] ddr3_dm; // Data Mask [3] = UDM.U26; [2] = LDM.U26; ... + wire [0:0] ddr3_odt; // On-Die termination enable. + + always @(posedge ddr3_axi_clk) + ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; + + axi_dma_fifo #( + .DEFAULT_BASE(30'h02000000), + .DEFAULT_MASK(30'hFF000000), + .DEFAULT_TIMEOUT(280), + .SR_BASE(SR_BASE), + .EXT_BIST(1), + .SIMULATION(1) + ) axi_dma_fifo_i0 ( + // + // Clocks and reset + .bus_clk (bus_clk), + .bus_reset (bus_rst), + .dram_clk (dma_engine_clk), + .dram_reset (ddr3_axi_rst), + // + // AXI Write address channel + .m_axi_awid (dma_axi_wr.addr.id), + .m_axi_awaddr (dma_axi_wr.addr.addr), + .m_axi_awlen (dma_axi_wr.addr.len), + .m_axi_awsize (dma_axi_wr.addr.size), + .m_axi_awburst (dma_axi_wr.addr.burst), + .m_axi_awlock (dma_axi_wr.addr.lock), + .m_axi_awcache (dma_axi_wr.addr.cache), + .m_axi_awprot (dma_axi_wr.addr.prot), + .m_axi_awqos (dma_axi_wr.addr.qos), + .m_axi_awregion (dma_axi_wr.addr.region), + .m_axi_awuser (dma_axi_wr.addr.user), + .m_axi_awvalid (dma_axi_wr.addr.valid), + .m_axi_awready (dma_axi_wr.addr.ready), + // + // AXI Write data channel. + .m_axi_wdata (dma_axi_wr.data.data), + .m_axi_wstrb (dma_axi_wr.data.strb), + .m_axi_wlast (dma_axi_wr.data.last), + .m_axi_wuser (dma_axi_wr.data.user), + .m_axi_wvalid (dma_axi_wr.data.valid), + .m_axi_wready (dma_axi_wr.data.ready), + // + // AXI Write response channel signals + .m_axi_bid (dma_axi_wr.resp.id), + .m_axi_bresp (dma_axi_wr.resp.resp), + .m_axi_buser (dma_axi_wr.resp.user), + .m_axi_bvalid (dma_axi_wr.resp.valid), + .m_axi_bready (dma_axi_wr.resp.ready), + // + // AXI Read address channel + .m_axi_arid (dma_axi_rd.addr.id), + .m_axi_araddr (dma_axi_rd.addr.addr), + .m_axi_arlen (dma_axi_rd.addr.len), + .m_axi_arsize (dma_axi_rd.addr.size), + .m_axi_arburst (dma_axi_rd.addr.burst), + .m_axi_arlock (dma_axi_rd.addr.lock), + .m_axi_arcache (dma_axi_rd.addr.cache), + .m_axi_arprot (dma_axi_rd.addr.prot), + .m_axi_arqos (dma_axi_rd.addr.qos), + .m_axi_arregion (dma_axi_rd.addr.region), + .m_axi_aruser (dma_axi_rd.addr.user), + .m_axi_arvalid (dma_axi_rd.addr.valid), + .m_axi_arready (dma_axi_rd.addr.ready), + // + // AXI Read data channel + .m_axi_rid (dma_axi_rd.data.id), + .m_axi_rdata (dma_axi_rd.data.data), + .m_axi_rresp (dma_axi_rd.data.resp), + .m_axi_rlast (dma_axi_rd.data.last), + .m_axi_ruser (dma_axi_rd.data.user), + .m_axi_rvalid (dma_axi_rd.data.valid), + .m_axi_rready (dma_axi_rd.data.ready), + // + // CHDR friendly AXI stream input + .i_tdata (i_tdata), + .i_tlast (i_tlast), + .i_tvalid (i_tvalid), + .i_tready (i_tready), + // + // CHDR friendly AXI Stream output + .o_tdata (o_tdata), + .o_tlast (o_tlast), + .o_tvalid (o_tvalid), + .o_tready (o_tready), + // + // Settings + .set_stb (set_stb), + .set_addr (set_addr), + .set_data (set_data), + .rb_data (rb_data), + + .debug() + ); + + //--------------------------------------------------- + // We use an interconnect to connect to FIFOs. + //--------------------------------------------------- + // Attach to third slave just to validate proper ID handling in interconnect + + axi_intercon_4x64_256_bd_wrapper axi_intercon_i ( + // + .S00_AXI_ACLK (dma_engine_clk), // input S01_AXI_ACLK + .S00_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN + .S00_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID + .S00_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR + .S00_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN + .S00_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE + .S00_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST + .S00_AXI_AWLOCK (0), // input S01_AXI_AWLOCK + .S00_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE + .S00_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT + .S00_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS + .S00_AXI_AWVALID (0), // input S01_AXI_AWVALID + .S00_AXI_AWREADY (), // output S01_AXI_AWREADY + .S00_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA + .S00_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB + .S00_AXI_WLAST (0), // input S01_AXI_WLAST + .S00_AXI_WVALID (0), // input S01_AXI_WVALID + .S00_AXI_WREADY (), // output S01_AXI_WREADY + .S00_AXI_BID (), // output [0 : 0] S01_AXI_BID + .S00_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP + .S00_AXI_BVALID (), // output S01_AXI_BVALID + .S00_AXI_BREADY (1), // input S01_AXI_BREADY + .S00_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID + .S00_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR + .S00_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN + .S00_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE + .S00_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST + .S00_AXI_ARLOCK (0), // input S01_AXI_ARLOCK + .S00_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE + .S00_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT + .S00_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS + .S00_AXI_ARVALID (0), // input S01_AXI_ARVALID + .S00_AXI_ARREADY (), // output S01_AXI_ARREADY + .S00_AXI_RID (), // output [0 : 0] S01_AXI_RID + .S00_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA + .S00_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP + .S00_AXI_RLAST (), // output S01_AXI_RLAST + .S00_AXI_RVALID (), // output S01_AXI_RVALID + .S00_AXI_RREADY (1), // input S01_AXI_RREADY + // + .S01_AXI_ACLK (dma_engine_clk), // input S01_AXI_ACLK + .S01_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN + .S01_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID + .S01_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR + .S01_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN + .S01_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE + .S01_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST + .S01_AXI_AWLOCK (0), // input S01_AXI_AWLOCK + .S01_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE + .S01_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT + .S01_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS + .S01_AXI_AWVALID (0), // input S01_AXI_AWVALID + .S01_AXI_AWREADY (), // output S01_AXI_AWREADY + .S01_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA + .S01_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB + .S01_AXI_WLAST (0), // input S01_AXI_WLAST + .S01_AXI_WVALID (0), // input S01_AXI_WVALID + .S01_AXI_WREADY (), // output S01_AXI_WREADY + .S01_AXI_BID (), // output [0 : 0] S01_AXI_BID + .S01_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP + .S01_AXI_BVALID (), // output S01_AXI_BVALID + .S01_AXI_BREADY (1), // input S01_AXI_BREADY + .S01_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID + .S01_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR + .S01_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN + .S01_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE + .S01_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST + .S01_AXI_ARLOCK (0), // input S01_AXI_ARLOCK + .S01_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE + .S01_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT + .S01_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS + .S01_AXI_ARVALID (0), // input S01_AXI_ARVALID + .S01_AXI_ARREADY (), // output S01_AXI_ARREADY + .S01_AXI_RID (), // output [0 : 0] S01_AXI_RID + .S01_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA + .S01_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP + .S01_AXI_RLAST (), // output S01_AXI_RLAST + .S01_AXI_RVALID (), // output S01_AXI_RVALID + .S01_AXI_RREADY (1), // input S01_AXI_RREADY + // + .S02_AXI_ACLK (dma_engine_clk), // input S01_AXI_ACLK + .S02_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN + .S02_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID + .S02_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR + .S02_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN + .S02_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE + .S02_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST + .S02_AXI_AWLOCK (0), // input S01_AXI_AWLOCK + .S02_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE + .S02_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT + .S02_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS + .S02_AXI_AWVALID (0), // input S01_AXI_AWVALID + .S02_AXI_AWREADY (), // output S01_AXI_AWREADY + .S02_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA + .S02_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB + .S02_AXI_WLAST (0), // input S01_AXI_WLAST + .S02_AXI_WVALID (0), // input S01_AXI_WVALID + .S02_AXI_WREADY (), // output S01_AXI_WREADY + .S02_AXI_BID (), // output [0 : 0] S01_AXI_BID + .S02_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP + .S02_AXI_BVALID (), // output S01_AXI_BVALID + .S02_AXI_BREADY (1), // input S01_AXI_BREADY + .S02_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID + .S02_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR + .S02_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN + .S02_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE + .S02_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST + .S02_AXI_ARLOCK (0), // input S01_AXI_ARLOCK + .S02_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE + .S02_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT + .S02_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS + .S02_AXI_ARVALID (0), // input S01_AXI_ARVALID + .S02_AXI_ARREADY (), // output S01_AXI_ARREADY + .S02_AXI_RID (), // output [0 : 0] S01_AXI_RID + .S02_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA + .S02_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP + .S02_AXI_RLAST (), // output S01_AXI_RLAST + .S02_AXI_RVALID (), // output S01_AXI_RVALID + .S02_AXI_RREADY (1), // input S01_AXI_RREADY + // + .S03_AXI_ACLK (dma_engine_clk), // input S00_AXI_ACLK + .S03_AXI_ARESETN (~ddr3_axi_rst), // input S00_AXI_ARESETN + .S03_AXI_AWID (dma_axi_wr.addr.id), // input [0 : 0] S00_AXI_AWID + .S03_AXI_AWADDR (dma_axi_wr.addr.addr), // input [31 : 0] S00_AXI_AWADDR + .S03_AXI_AWLEN (dma_axi_wr.addr.len), // input [7 : 0] S00_AXI_AWLEN + .S03_AXI_AWSIZE (dma_axi_wr.addr.size), // input [2 : 0] S00_AXI_AWSIZE + .S03_AXI_AWBURST (dma_axi_wr.addr.burst), // input [1 : 0] S00_AXI_AWBURST + .S03_AXI_AWLOCK (dma_axi_wr.addr.lock), // input S00_AXI_AWLOCK + .S03_AXI_AWCACHE (dma_axi_wr.addr.cache), // input [3 : 0] S00_AXI_AWCACHE + .S03_AXI_AWPROT (dma_axi_wr.addr.prot), // input [2 : 0] S00_AXI_AWPROT + .S03_AXI_AWQOS (dma_axi_wr.addr.qos), // input [3 : 0] S00_AXI_AWQOS + .S03_AXI_AWVALID (dma_axi_wr.addr.valid), // input S00_AXI_AWVALID + .S03_AXI_AWREADY (dma_axi_wr.addr.ready), // output S00_AXI_AWREADY + .S03_AXI_WDATA (dma_axi_wr.data.data ^ forced_bit_err), // input [63 : 0] S00_AXI_WDATA + .S03_AXI_WSTRB (dma_axi_wr.data.strb), // input [7 : 0] S00_AXI_WSTRB + .S03_AXI_WLAST (dma_axi_wr.data.last), // input S00_AXI_WLAST + .S03_AXI_WVALID (dma_axi_wr.data.valid), // input S00_AXI_WVALID + .S03_AXI_WREADY (dma_axi_wr.data.ready), // output S00_AXI_WREADY + .S03_AXI_BID (dma_axi_wr.resp.id), // output [0 : 0] S00_AXI_BID + .S03_AXI_BRESP (dma_axi_wr.resp.resp), // output [1 : 0] S00_AXI_BRESP + .S03_AXI_BVALID (dma_axi_wr.resp.valid), // output S00_AXI_BVALID + .S03_AXI_BREADY (dma_axi_wr.resp.ready), // input S00_AXI_BREADY + .S03_AXI_ARID (dma_axi_rd.addr.id), // input [0 : 0] S00_AXI_ARID + .S03_AXI_ARADDR (dma_axi_rd.addr.addr), // input [31 : 0] S00_AXI_ARADDR + .S03_AXI_ARLEN (dma_axi_rd.addr.len), // input [7 : 0] S00_AXI_ARLEN + .S03_AXI_ARSIZE (dma_axi_rd.addr.size), // input [2 : 0] S00_AXI_ARSIZE + .S03_AXI_ARBURST (dma_axi_rd.addr.burst), // input [1 : 0] S00_AXI_ARBURST + .S03_AXI_ARLOCK (dma_axi_rd.addr.lock), // input S00_AXI_ARLOCK + .S03_AXI_ARCACHE (dma_axi_rd.addr.cache), // input [3 : 0] S00_AXI_ARCACHE + .S03_AXI_ARPROT (dma_axi_rd.addr.prot), // input [2 : 0] S00_AXI_ARPROT + .S03_AXI_ARQOS (dma_axi_rd.addr.qos), // input [3 : 0] S00_AXI_ARQOS + .S03_AXI_ARVALID (dma_axi_rd.addr.valid), // input S00_AXI_ARVALID + .S03_AXI_ARREADY (dma_axi_rd.addr.ready), // output S00_AXI_ARREADY + .S03_AXI_RID (dma_axi_rd.data.id), // output [0 : 0] S00_AXI_RID + .S03_AXI_RDATA (dma_axi_rd.data.data), // output [63 : 0] S00_AXI_RDATA + .S03_AXI_RRESP (dma_axi_rd.data.resp), // output [1 : 0] S00_AXI_RRESP + .S03_AXI_RLAST (dma_axi_rd.data.last), // output S00_AXI_RLAST + .S03_AXI_RVALID (dma_axi_rd.data.valid), // output S00_AXI_RVALID + .S03_AXI_RREADY (dma_axi_rd.data.ready), // input S00_AXI_RREADY + // + .M00_AXI_ACLK (ddr3_axi_clk), // input M00_AXI_ACLK + .M00_AXI_ARESETN (~ddr3_axi_rst), // input M00_AXI_ARESETN + .M00_AXI_AWID (mig_axi_wr.addr.id), // output [3 : 0] M00_AXI_AWID + .M00_AXI_AWADDR (mig_axi_wr.addr.addr), // output [31 : 0] M00_AXI_AWADDR + .M00_AXI_AWLEN (mig_axi_wr.addr.len), // output [7 : 0] M00_AXI_AWLEN + .M00_AXI_AWSIZE (mig_axi_wr.addr.size), // output [2 : 0] M00_AXI_AWSIZE + .M00_AXI_AWBURST (mig_axi_wr.addr.burst), // output [1 : 0] M00_AXI_AWBURST + .M00_AXI_AWLOCK (mig_axi_wr.addr.lock), // output M00_AXI_AWLOCK + .M00_AXI_AWCACHE (mig_axi_wr.addr.cache), // output [3 : 0] M00_AXI_AWCACHE + .M00_AXI_AWPROT (mig_axi_wr.addr.prot), // output [2 : 0] M00_AXI_AWPROT + .M00_AXI_AWQOS (mig_axi_wr.addr.qos), // output [3 : 0] M00_AXI_AWQOS + .M00_AXI_AWVALID (mig_axi_wr.addr.valid), // output M00_AXI_AWVALID + .M00_AXI_AWREADY (mig_axi_wr.addr.ready), // input M00_AXI_AWREADY + .M00_AXI_WDATA (mig_axi_wr.data.data), // output [127 : 0] M00_AXI_WDATA + .M00_AXI_WSTRB (mig_axi_wr.data.strb), // output [15 : 0] M00_AXI_WSTRB + .M00_AXI_WLAST (mig_axi_wr.data.last), // output M00_AXI_WLAST + .M00_AXI_WVALID (mig_axi_wr.data.valid), // output M00_AXI_WVALID + .M00_AXI_WREADY (mig_axi_wr.data.ready), // input M00_AXI_WREADY + .M00_AXI_BID (mig_axi_wr.resp.id), // input [3 : 0] M00_AXI_BID + .M00_AXI_BRESP (mig_axi_wr.resp.resp), // input [1 : 0] M00_AXI_BRESP + .M00_AXI_BVALID (mig_axi_wr.resp.valid), // input M00_AXI_BVALID + .M00_AXI_BREADY (mig_axi_wr.resp.ready), // output M00_AXI_BREADY + .M00_AXI_ARID (mig_axi_rd.addr.id), // output [3 : 0] M00_AXI_ARID + .M00_AXI_ARADDR (mig_axi_rd.addr.addr), // output [31 : 0] M00_AXI_ARADDR + .M00_AXI_ARLEN (mig_axi_rd.addr.len), // output [7 : 0] M00_AXI_ARLEN + .M00_AXI_ARSIZE (mig_axi_rd.addr.size), // output [2 : 0] M00_AXI_ARSIZE + .M00_AXI_ARBURST (mig_axi_rd.addr.burst), // output [1 : 0] M00_AXI_ARBURST + .M00_AXI_ARLOCK (mig_axi_rd.addr.lock), // output M00_AXI_ARLOCK + .M00_AXI_ARCACHE (mig_axi_rd.addr.cache), // output [3 : 0] M00_AXI_ARCACHE + .M00_AXI_ARPROT (mig_axi_rd.addr.prot), // output [2 : 0] M00_AXI_ARPROT + .M00_AXI_ARQOS (mig_axi_rd.addr.qos), // output [3 : 0] M00_AXI_ARQOS + .M00_AXI_ARVALID (mig_axi_rd.addr.valid), // output M00_AXI_ARVALID + .M00_AXI_ARREADY (mig_axi_rd.addr.ready), // input M00_AXI_ARREADY + .M00_AXI_RID (mig_axi_rd.data.id), // input [3 : 0] M00_AXI_RID + .M00_AXI_RDATA (mig_axi_rd.data.data), // input [127 : 0] M00_AXI_RDATA + .M00_AXI_RRESP (mig_axi_rd.data.resp), // input [1 : 0] M00_AXI_RRESP + .M00_AXI_RLAST (mig_axi_rd.data.last), // input M00_AXI_RLAST + .M00_AXI_RVALID (mig_axi_rd.data.valid), // input M00_AXI_RVALID + .M00_AXI_RREADY (mig_axi_rd.data.ready) // output M00_AXI_RREADY + ); + + //--------------------------------------------------- + // MIG + //--------------------------------------------------- + ddr3_32bit ddr_mig_i ( + // Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .init_calib_complete (init_calib_complete), + + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + // Application interface ports + .ui_clk (ddr3_axi_clk), // 150MHz clock out + .ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 150MHz + .aresetn (ddr3_axi_rst_reg_n), + .app_sr_req (1'b0), + .app_sr_active (), + .app_ref_req (1'b0), + .app_ref_ack (), + .app_zq_req (1'b0), + .app_zq_ack (), + + // Slave Interface Write Address Ports + .s_axi_awid (mig_axi_wr.addr.id), + .s_axi_awaddr (mig_axi_wr.addr.addr), + .s_axi_awlen (mig_axi_wr.addr.len), + .s_axi_awsize (mig_axi_wr.addr.size), + .s_axi_awburst (mig_axi_wr.addr.burst), + .s_axi_awlock (mig_axi_wr.addr.lock), + .s_axi_awcache (mig_axi_wr.addr.cache), + .s_axi_awprot (mig_axi_wr.addr.prot), + .s_axi_awqos (mig_axi_wr.addr.qos), + .s_axi_awvalid (mig_axi_wr.addr.valid), + .s_axi_awready (mig_axi_wr.addr.ready), + // Slave Interface Write Data Ports + .s_axi_wdata (mig_axi_wr.data.data), + .s_axi_wstrb (mig_axi_wr.data.strb), + .s_axi_wlast (mig_axi_wr.data.last), + .s_axi_wvalid (mig_axi_wr.data.valid), + .s_axi_wready (mig_axi_wr.data.ready), + // Slave Interface Write Response Ports + .s_axi_bid (mig_axi_wr.resp.id), + .s_axi_bresp (mig_axi_wr.resp.resp), + .s_axi_bvalid (mig_axi_wr.resp.valid), + .s_axi_bready (mig_axi_wr.resp.ready), + // Slave Interface Read Address Ports + .s_axi_arid (mig_axi_rd.addr.id), + .s_axi_araddr (mig_axi_rd.addr.addr), + .s_axi_arlen (mig_axi_rd.addr.len), + .s_axi_arsize (mig_axi_rd.addr.size), + .s_axi_arburst (mig_axi_rd.addr.burst), + .s_axi_arlock (mig_axi_rd.addr.lock), + .s_axi_arcache (mig_axi_rd.addr.cache), + .s_axi_arprot (mig_axi_rd.addr.prot), + .s_axi_arqos (mig_axi_rd.addr.qos), + .s_axi_arvalid (mig_axi_rd.addr.valid), + .s_axi_arready (mig_axi_rd.addr.ready), + // Slave Interface Read Data Ports + .s_axi_rid (mig_axi_rd.data.id), + .s_axi_rdata (mig_axi_rd.data.data), + .s_axi_rresp (mig_axi_rd.data.resp), + .s_axi_rlast (mig_axi_rd.data.last), + .s_axi_rvalid (mig_axi_rd.data.valid), + .s_axi_rready (mig_axi_rd.data.ready), + // System Clock Ports + .sys_clk_p (sys_clk_p), // From external 100MHz source. + .sys_clk_n (sys_clk_n), // From external 100MHz source. + .clk_ref_i (bus_clk), + .sys_rst (sys_rst_n) // IJB. Poorly named active low. Should change RST_ACT_LOW. + ); + + //--------------------------------------------------- + // DDR3 SDRAM Models + //--------------------------------------------------- + ddr3_model #( + .DEBUG(0) //Disable verbose prints + ) sdram_i0 ( + .rst_n (ddr3_reset_n), + .ck (ddr3_ck_p), + .ck_n (ddr3_ck_n), + .cke (ddr3_cke), + .cs_n (ddr3_cs_n), + .ras_n (ddr3_ras_n), + .cas_n (ddr3_cas_n), + .we_n (ddr3_we_n), + .dm_tdqs (ddr3_dm[1:0]), + .ba (ddr3_ba), + .addr (ddr3_addr), + .dq (ddr3_dq[15:0]), + .dqs (ddr3_dqs_p[1:0]), + .dqs_n (ddr3_dqs_n[1:0]), + .tdqs_n (), // Unused on x16 + .odt (ddr3_odt) + ); + + ddr3_model #( + .DEBUG(0) //Disable verbose prints + ) sdram_i1 ( + .rst_n (ddr3_reset_n), + .ck (ddr3_ck_p), + .ck_n (ddr3_ck_n), + .cke (ddr3_cke), + .cs_n (ddr3_cs_n), + .ras_n (ddr3_ras_n), + .cas_n (ddr3_cas_n), + .we_n (ddr3_we_n), + .dm_tdqs (ddr3_dm[3:2]), + .ba (ddr3_ba), + .addr (ddr3_addr), + .dq (ddr3_dq[31:16]), + .dqs (ddr3_dqs_p[3:2]), + .dqs_n (ddr3_dqs_n[3:2]), + .tdqs_n (), // Unused on x16 + .odt (ddr3_odt) + ); + +endmodule diff --git a/fpga/usrp3/top/n3xx/sim/dram_fifo/dram_fifo_tb.sv b/fpga/usrp3/top/n3xx/sim/dram_fifo/dram_fifo_tb.sv new file mode 100644 index 000000000..2979aefb7 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/dram_fifo/dram_fifo_tb.sv @@ -0,0 +1,163 @@ +// +// Copyright 2016 Ettus Research +// + + +`timescale 1ns/1ps +`define SIM_TIMEOUT_US 120 +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 7 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +module dram_fifo_tb(); + `TEST_BENCH_INIT("dram_fifo_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_DIFF_CLK(sys_clk_p, sys_clk_n, 10, 50) //100MHz differential sys_clk to generate DDR3 clocking + `DEFINE_CLK(bus_clk, 1000/200, 50) //200MHz bus_clk + `DEFINE_CLK(dma_engine_clk, 1000.0/305.0, 50) //305MHz dma_engine_clk + `DEFINE_RESET(bus_rst, 0, 100) //100ns for GSR to deassert + `DEFINE_RESET_N(sys_rst_n, 0, 100) //100ns for GSR to deassert + + settings_bus_master #(.SR_AWIDTH(8),.SR_DWIDTH(32)) tst_set (.clk(bus_clk)); + cvita_master chdr_i (.clk(bus_clk)); + cvita_slave chdr_o (.clk(bus_clk)); + + // Initialize DUT + wire calib_complete; + + axis_dram_fifo_single dut_single ( + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .sys_clk_p(sys_clk_p),//use differential clock on N310 + .sys_clk_n(sys_clk_n), + .sys_rst_n(sys_rst_n), + .dma_engine_clk(dma_engine_clk), + + .i_tdata(chdr_i.axis.tdata), + .i_tlast(chdr_i.axis.tlast), + .i_tvalid(chdr_i.axis.tvalid), + .i_tready(chdr_i.axis.tready), + + .o_tdata(chdr_o.axis.tdata), + .o_tlast(chdr_o.axis.tlast), + .o_tvalid(chdr_o.axis.tvalid), + .o_tready(chdr_o.axis.tready), + + .set_stb(tst_set.settings_bus.set_stb), + .set_addr(tst_set.settings_bus.set_addr), + .set_data(tst_set.settings_bus.set_data), + .rb_data(), + + .forced_bit_err(64'h0), + .init_calib_complete(calib_complete) + ); + + //Testbench variables + cvita_hdr_t header; + cvita_pkt_t pkt_out; + integer i; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + string s; + + `TEST_CASE_START("Wait for reset"); + while (bus_rst) @(posedge bus_clk); + while (~sys_rst_n) @(posedge sys_clk_p); + `TEST_CASE_DONE((~bus_rst & sys_rst_n)); + + `TEST_CASE_START("Wait for initial calibration to complete"); + while (calib_complete !== 1'b1) @(posedge bus_clk); + `TEST_CASE_DONE(calib_complete); + + `TEST_CASE_START("Clear FIFO"); + tst_set.write(1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b1}); + repeat (200) @(posedge bus_clk); + tst_set.write(1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b0}); + repeat (200) @(posedge bus_clk); + `TEST_CASE_DONE(1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Fill up empty FIFO then drain (short packet)"); + chdr_i.push_ramp_pkt(16, 64'd0, 64'h100, header); + chdr_o.pull_pkt(pkt_out); + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",16,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==16, s); + $sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x", + {header.src_sid,header.dst_sid},{pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}); + `ASSERT_ERROR({header.src_sid,header.dst_sid}=={pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}, s); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Fill up empty FIFO then drain (long packet)"); + chdr_i.push_ramp_pkt(1024, 64'd0, 64'h100, header); + chdr_o.pull_pkt(pkt_out); + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",1024,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==1024, s); + $sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x", + {header.src_sid,header.dst_sid},{pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}); + `ASSERT_ERROR({header.src_sid,header.dst_sid}=={pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}, s); + `TEST_CASE_DONE(1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Concurrent read and write (single packet)"); + fork + begin + chdr_i.push_ramp_pkt(20, 64'd0, 64'h100, header); + end + begin + chdr_o.pull_pkt(pkt_out); + end + join + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",20,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==20, s); + i = 0; + repeat (20) begin + $sformat(s, "Bad packet: Wrong payload. Index: %d, Expected: %08x, Actual: %08x", + i,(i * 64'h100),pkt_out.payload[i]); + `ASSERT_ERROR(pkt_out.payload[i]==(i * 64'h100), s); + end + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Concurrent read and write (multiple packets)"); + fork + begin + repeat (10) begin + chdr_i.push_ramp_pkt(20, 64'd0, 64'h100, header); + repeat (30) @(posedge bus_clk); + end + end + begin + repeat (10) begin + chdr_o.pull_pkt(pkt_out); + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",20,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==20, s); + i = 0; + repeat (20) begin + $sformat(s, "Bad packet: Wrong payload. Index: %d, Expected: %08x, Actual: %08x", + i,(i * 64'h100),pkt_out.payload[i]); + `ASSERT_ERROR(pkt_out.payload[i]==(i * 64'h100), s); + end + end + end + join + `TEST_CASE_DONE(1); + + `TEST_BENCH_DONE; + + end + +endmodule diff --git a/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/Makefile b/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/Makefile new file mode 100644 index 000000000..49e673dc4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/Makefile @@ -0,0 +1,70 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID = xc7z100/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/ddr3_32bit/Makefile.inc +include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_DDR3_32BIT_SRCS) \ +$(IP_AXI_INTERCON_4X64_256_SRCS) \ +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = dram_fifo_bist_tb + +SIM_SRCS = \ +$(abspath dram_fifo_bist_tb.sv) \ +$(abspath ../dram_fifo/axis_dram_fifo_single.sv) \ +$(IP_DDR3_32BIT_SIM_OUTS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/dram_fifo_bist_tb.sv b/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/dram_fifo_bist_tb.sv new file mode 100644 index 000000000..96a60de6e --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/dram_fifo_bist_tb.sv @@ -0,0 +1,348 @@ +// +// Copyright 2015 Ettus Research LLC +// + + +`timescale 1ns/1ps +`define SIM_RUNTIME_US 3000 +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 8 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +module dram_fifo_bist_tb(); + `TEST_BENCH_INIT("dram_fifo_bist_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_DIFF_CLK(sys_clk_p, sys_clk_n, 10, 50) //100MHz differential sys_clk to generate DDR3 clocking + `DEFINE_CLK(bus_clk, 1000/200, 50) //200MHz bus_clk + `DEFINE_CLK(dma_engine_clk, 1000/300, 50) //300MHz dma_engine_clk + `DEFINE_RESET(bus_rst, 0, 100) //100ns for GSR to deassert + `DEFINE_RESET_N(sys_rst_n, 0, 100) //100ns for GSR to deassert + + localparam EXTENDED_TEST = 0; + + // Initialize DUT + wire calib_complete; + wire running, done; + wire [1:0] error; + wire [31:0] rb_data; + reg [63:0] forced_bit_err; + + settings_bus_master #(.SR_AWIDTH(8),.SR_DWIDTH(32)) tst_set (.clk(bus_clk)); + cvita_master cvita_fifo_in (.clk(bus_clk)); + cvita_slave cvita_fifo_out (.clk(bus_clk)); + + // AXI DRAM FIFO Topology (Inline production BIST for DRAM FIFO): + // + // User Data ====> |---------| |---------------| |-----------| ====> User Data Out + // | AXI MUX | ====> | AXI DRAM FIFO | ====> | AXI DEMUX | + // BIST Data ====> |---------| |---------------| |-----------| ====> BIST Data Out + // || + // |--------------| + // | MIG (D/S)RAM | + // |--------------| + + localparam SR_FIFO_BASE = 0; + localparam SR_BIST_BASE = SR_FIFO_BASE + 4; + + axis_dram_fifo_single dut_single ( + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .sys_clk_p(sys_clk_p),//use differential clock on N310 + .sys_clk_n(sys_clk_n), + .sys_rst_n(sys_rst_n), + .dma_engine_clk(dma_engine_clk), + + .i_tdata(cvita_fifo_in.axis.tdata), + .i_tlast(cvita_fifo_in.axis.tlast), + .i_tvalid(cvita_fifo_in.axis.tvalid), + .i_tready(cvita_fifo_in.axis.tready), + + .o_tdata(cvita_fifo_out.axis.tdata), + .o_tlast(cvita_fifo_out.axis.tlast), + .o_tvalid(cvita_fifo_out.axis.tvalid), + .o_tready(cvita_fifo_out.axis.tready), + + .set_stb(tst_set.settings_bus.set_stb), + .set_addr(tst_set.settings_bus.set_addr), + .set_data(tst_set.settings_bus.set_data), + .rb_data(rb_data), + + .forced_bit_err(forced_bit_err), + .init_calib_complete(calib_complete) + ); + + assign {error, done, running} = rb_data[3:0]; + + //Testbench variables + cvita_hdr_t header; + cvita_pkt_t pkt_out; + integer i; + integer single_run_time; + integer xfer_cnt, cyc_cnt; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + string s; + + `TEST_CASE_START("Wait for reset"); + while (bus_rst) @(posedge bus_clk); + while (~sys_rst_n) @(posedge sys_clk_p); + `TEST_CASE_DONE(~bus_rst & sys_rst_n); + + forced_bit_err <= 64'h0; + repeat (200) @(posedge sys_clk_p); + + `TEST_CASE_START("Wait for initial calibration to complete"); + while (calib_complete !== 1'b1) @(posedge bus_clk); + `TEST_CASE_DONE(calib_complete); + + `TEST_CASE_START("Clear FIFO"); + tst_set.write(SR_FIFO_BASE + 1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b1}); + repeat (200) @(posedge bus_clk); + tst_set.write(SR_FIFO_BASE + 1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b0}); + repeat (200) @(posedge bus_clk); + `TEST_CASE_DONE(1); + + //Select BIST status as the readback output + tst_set.write(SR_FIFO_BASE + 0, 3'd1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Fill up empty FIFO then drain (long packet)"); + cvita_fifo_in.push_ramp_pkt(100, 64'd0, 64'h100, header); + cvita_fifo_out.pull_pkt(pkt_out); + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",100,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==100, s); + $sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x", + {header.src_sid,header.dst_sid},{pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}); + `ASSERT_ERROR({header.src_sid,header.dst_sid}=={pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}, s); + i = 0; + repeat (100) begin + $sformat(s, "Bad packet: Wrong payload. Index: %d, Expected: %08x, Actual: %08x", + i,(i * 64'h100),pkt_out.payload[i]); + `ASSERT_ERROR(pkt_out.payload[i]==(i * 64'h100), s); + end + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Setup BIST: 10 x 40byte packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h01234567); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd40, 18'd10}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd3, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Run BIST ... again (should fail)"); + forced_bit_err <= 64'h8000000000000000; + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b01, "BIST passed when it should have failed!"); + forced_bit_err <= 64'h0; + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Run BIST ... and again (should pass)"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + if (EXTENDED_TEST) begin // Extended test mode + `TEST_CASE_START("Setup BIST: 8000 x 40byte ramping packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h01234567); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b1, 13'd40, 18'd8000}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd3, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Setup BIST: 256 x 1000byte packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h0ABCDEF0); + tst_set.write(SR_BIST_BASE + 2, {8'd4, 16'd256}); + tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd1000, 18'd256}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd1, 2'd0, 1'b0, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("User Data: Concurrent read and write"); + cvita_fifo_out.axis.tready = 1; + fork + begin + cvita_fifo_in.push_ramp_pkt(20, 64'd0, 64'h100, header); + end + begin + cvita_fifo_out.pull_pkt(pkt_out); + end + join + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",20,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==20, s); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Setup BIST: 256 x 600byte ramping packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h01234567); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b1, 13'd600, 18'd256}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Setup BIST: 30 x 8000byte packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h0ABCDEF0); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd8000, 18'd30}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd1, 2'd0, 1'b0, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Setup BIST: 100 x 8000byte ramping packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h0ABCDEF0); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b1, 13'd8000, 18'd100}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd1, 2'd0, 1'b0, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Validate Throughput"); + tst_set.write(SR_FIFO_BASE + 0, 3'd2); + xfer_cnt = rb_data; + tst_set.write(SR_FIFO_BASE + 0, 3'd3); + cyc_cnt = rb_data; + `ASSERT_ERROR(xfer_cnt>0, "Transfer count was not >0"); + `ASSERT_ERROR(cyc_cnt>0, "Cycle count was not >0"); + $display("Measured Throughput = %0d%% of bus_clk throughput", ((xfer_cnt*100)/cyc_cnt)); + `ASSERT_ERROR(((xfer_cnt*100)/cyc_cnt)>80, "Throughput was less than 80%%"); + tst_set.write(SR_FIFO_BASE + 0, 3'd1); //Restore + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Setup BIST: 10 x 256byte packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'hFFFFFFFF); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd256, 18'd30}); + `TEST_CASE_DONE(~done & ~running); + + fork + begin + integer curr_time = $time; + `TEST_CASE_START("Run BIST Continuous (Early interrupt)"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + single_run_time = $time - curr_time; + `TEST_CASE_DONE(done & ~running); + end + begin + //Wait then clear + #2000; + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + end + join + + fork + begin + `TEST_CASE_START("Run BIST Continuous (Force error)"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b01, "BIST passed when it should have failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + end + begin + //Wait then force error + #10000; + forced_bit_err <= 64'h1; + end + join + //Recover from failure + forced_bit_err <= 64'h0; + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + repeat (2000) @(posedge bus_clk); + + fork + begin + integer curr_time = $time; + `TEST_CASE_START("Run BIST Continuous"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `ASSERT_ERROR((($time - curr_time) > 2 * single_run_time), "Continuous test most likely stopped early!"); + `TEST_CASE_DONE(done & ~running); + end + begin + //Wait then clear + #100000; + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + end + join + + `TEST_CASE_START("Validate Throughput"); + tst_set.write(SR_FIFO_BASE + 0, 3'd2); + xfer_cnt = rb_data; + tst_set.write(SR_FIFO_BASE + 0, 3'd3); + cyc_cnt = rb_data; + `ASSERT_ERROR(xfer_cnt>0, "Transfer count was not >0"); + `ASSERT_ERROR(cyc_cnt>0, "Cycle count was not >0"); + $display("Measured Throughput = %0d%% of bus_clk throughput", ((xfer_cnt*100)/cyc_cnt)); + `ASSERT_ERROR(((xfer_cnt*100)/cyc_cnt)>80, "Throughput was less than 80%%"); + tst_set.write(SR_FIFO_BASE + 0, 3'd1); //Restore + `TEST_CASE_DONE(done & ~running); + end + + `TEST_BENCH_DONE; + + end +endmodule diff --git a/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/Makefile b/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/Makefile new file mode 100644 index 000000000..77c7c58c5 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/Makefile @@ -0,0 +1,78 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID = xc7z100/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/simple_gemac/Makefile.srcs +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +$(SIMPLE_GEMAC_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/one_gig_eth_pcs_pma/Makefile.inc +#include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_ONE_GIGE_PHY_XCI_SRCS) \ +$(ONE_GIGE_PHY_SRCS) \ +$(IP_AXI64_8K_2CLK_FIFO_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +include $(BASE_DIR)/../sim/general/Makefile.srcs +include $(BASE_DIR)/../sim/control/Makefile.srcs +include $(BASE_DIR)/../sim/axi/Makefile.srcs + +# Define only one toplevel module +SIM_TOP = one_gig_eth_loopback_tb +# Simulation runtime in microseconds +SIM_RUNTIME_US = 30000 + +SIM_SRCS = \ +$(abspath one_gig_eth_loopback_tb.sv) \ +$(SIM_GENERAL_SRCS) \ +$(SIM_CONTROL_SRCS) \ +$(SIM_AXI_SRCS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/demo_one_gig_pcs_pma_mdio.v b/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/demo_one_gig_pcs_pma_mdio.v new file mode 100644 index 000000000..cd24e14a8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/demo_one_gig_pcs_pma_mdio.v @@ -0,0 +1,489 @@ +//------------------------------------------------------------------------------ +// File : demo_tb.v +// Author : Xilinx Inc. +//------------------------------------------------------------------------------ +// (c) Copyright 2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//------------------------------------------------------------------------------ +// Description: This testbench will exercise the ports of the Ethernet +// 1000BASE-X PCS/PMA core's example design to perform the following +// operations: +// +//---------------- +// Configuration +//---------------- +// The core will be reset, then Auto-Negotiation (if present) will +// be disabled and and the core will be taken out of the Isolate +// state. +// +//---------------- +// Transmitter +//---------------- +// Four frames are generated by the Tx Stimulus and pushed into the +// GMII transmitter. +// +// The PHY side transmitter interface data is captured, 8B10B decoded +// and the Tx Monitor checks that the captured data matches that +// injected. +// +//---------------- +// Receiver +//---------------- +// Four frames are generated by the Rx Stimulus, 8B10B encoded and +// pushed into the PHY side receiver interface. +// +// The GMII side receiver interface data is captured and the +// Rx Monitor checks that the captured data matches that injected. +// +// +//---------------------------------------------------------------------- +// Demonstration Test Fixture | +// | +// | +// -------------------------- | +// | Example Design | | +// | (DUT) | | +// | | | +// | | | +// | | | +// Tx | | 8B10B decode, Tx | +// Generate -------> --------> Monitor | +// Frames | | Frames | +// |GMII PHY | | +// | I/F I/F | | +// | | | +// | | | +// | | | +// Rx | | 8B10B encode, Rx | +// Monitor <-------- <-------- Generate | +// Frames | | Frames | +// | | | +// ------------^------------- | +// | | +// | | +// Stimulate | +// MDIO I/F | +// (if present) | +// | +//---------------------------------------------------------------------- + +`timescale 1 ps/1 ps + + +// To use this testbench copy it over the demo_tb.v in the example testbench +// provided by xilinx + +// This module is a modified version of the demonstration testbench provided +// by Xilinx. It has the mdio_master along with the one_gig dut. +// It uses the configuration vector to control the phy +// Can be used to debug mdio_master +module demo_tb; + + + //---------------------------------------------------------------------------- + // Stimulus - Management Frame data + //---------------------------------------------------------------------------- + // Create management frame + reg [0:63] mdio_data; + + initial + begin + + mdio_data[0:31] = 32'hffffffff; // preamble field + mdio_data[32:33] = 2'h1; // start opcode + mdio_data[34:35] = 2'h1; // write opcode + mdio_data[36:40] = 5'd1; // phyad (write to this device) + mdio_data[41:45] = 5'h0; // regad (write to Configuration Register) + mdio_data[46:47] = 2'h2; // Turn-around cycles + + // DATA FIELD + + mdio_data[48] = 1'b0; // Do not assert Reset + mdio_data[49] = 1'b0; // No loopback + mdio_data[50] = 1'b0; // Speed selection + mdio_data[51] = 1'b0; // Disable Auto-Negotiation + mdio_data[52] = 1'b0; // Disable Power Down + mdio_data[53] = 1'b0; // Disable Isolate GMII + mdio_data[54] = 1'b0; // Disable Auto-Negotiation Restart + mdio_data[55] = 1'b1; // Full Duplex Mode + mdio_data[56] = 1'b0; // Disable Collision Test + mdio_data[57] = 1'b0; // Speed selection + mdio_data[58:63] = 6'h0; // Reserved + + end + + + + //---------------------------------------------------------------------------- + // testbench signals + //---------------------------------------------------------------------------- + + // testbench control semaphores + reg configuration_finished; + wire tx_monitor_finished; + wire rx_monitor_finished; + wire simulation_finished; + + + //---------------------------------------------------------------------------- + // DUT signals + //---------------------------------------------------------------------------- + + // An independent clock source used as the reference clock for an + // IDELAYCTRL (if present) and for the main GT transceiver reset logic. + // This example design assumes that this is of frequency 200MHz. + reg independent_clock; + + // System Reset + reg reset; + + // Transceiver Interface + //---------------------- + reg gtrefclk_p; + reg gtrefclk_n; + wire rxuserclk2; + wire txp; + wire txn; + wire rxp; + wire rxn; + + // GMII Interface + //--------------- + wire gmii_tx_clk; + wire gmii_rx_clk; + wire [7:0] gmii_txd; + wire gmii_tx_en; + wire gmii_tx_er; + wire [7:0] gmii_rxd; + wire gmii_rx_dv; + wire gmii_rx_er; + + // Management: MDIO Interface + //--------------------------- + wire mdc; + wire mdio_i; + wire mdio_o; + wire mdio_t; + reg [4:0] configuration_vector; + reg configuration_valid; + wire signal_detect; + wire [15:0] status_vector; + + parameter [13:0] REG_BASE = 14'h0; + parameter REG_DWIDTH = 32; + parameter REG_AWIDTH = 14; + + reg reg_wr_req; + reg [REG_AWIDTH-1:0] reg_wr_addr; + reg [31:0] reg_wr_data; + reg reg_rd_req; + reg [REG_AWIDTH-1:0] reg_rd_addr; + wire reg_rd_resp; + wire [31:0] reg_rd_data; + + //---------------------------------------------------------------------------- + // Create clock sources + //---------------------------------------------------------------------------- + + // An independent clock source used as the reference clock for an + // IDELAYCTRL (if present) and for the main GT transceiver reset logic. + // This testbench uses the frequency of 200MHz. + initial + begin + independent_clock <= 1'b0; + forever + begin + independent_clock <= 1'b0; + #2500; + independent_clock <= 1'b1; + #2500; + end + end + + + + // Create the transceiver Reference clock (125 MHz) + initial + begin + gtrefclk_p <= 1'b0; + gtrefclk_n <= 1'b1; + forever + begin + gtrefclk_p <= 1'b0; + gtrefclk_n <= 1'b1; + #4000; + gtrefclk_p <= 1'b1; + gtrefclk_n <= 1'b0; + #4000; + end + end + + // MDIO Master + mdio_master #( + .REG_BASE (REG_BASE + 32'h10), + .REG_AWIDTH (REG_AWIDTH), + .MDC_DIVIDER (8'd200) + ) mdio_master_i ( + .clk (independent_clock), + .rst (reset), + .mdc (mdc), + .mdio_in (mdio_o), + .mdio_out (mdio_i), + .mdio_tri (mdio_t), + .reg_wr_req (reg_wr_req), + .reg_wr_addr(reg_wr_addr), + .reg_wr_data(reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr(reg_rd_addr), + .reg_rd_data(reg_rd_data), + .reg_rd_resp(reg_rd_resp) + ); + + //---------------------------------------------------------------------------- + // Wire up Device Under Test + //---------------------------------------------------------------------------- + one_gig_eth_pcs_pma_example_design dut + ( + .independent_clock (independent_clock), + .gtrefclk_p (gtrefclk_p), + .gtrefclk_n (gtrefclk_n), + .rxuserclk2 (rxuserclk2), + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + .gmii_tx_clk (gmii_tx_clk), + .gmii_rx_clk (gmii_rx_clk), + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd), + .gmii_rx_dv (gmii_rx_dv), + .gmii_rx_er (gmii_rx_er), + .mdc (mdc), + .mdio_i (mdio_i), + .mdio_o (mdio_o), + .mdio_t (mdio_t), + .configuration_vector (configuration_vector), + .configuration_valid (configuration_valid), + .status_vector (status_vector), + .reset (reset), + .signal_detect (signal_detect) + ); + + + + //---------------------------------------------------------------------------- + // Instantiate a Stimulus module for the core + //---------------------------------------------------------------------------- + stimulus_tb stimulus + ( + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + + .gmii_tx_clk (gmii_tx_clk), + .gmii_rx_clk (gmii_rx_clk), + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd), + .gmii_rx_dv (gmii_rx_dv), + .gmii_rx_er (gmii_rx_er), + + .configuration_finished (configuration_finished), + .tx_monitor_finished (tx_monitor_finished), + .rx_monitor_finished (rx_monitor_finished) + ); + + + + //---------------------------------------------------------------------------- + // Simulate that PMD sublayer has detected and optical input. + //---------------------------------------------------------------------------- + assign signal_detect = 1'b1; + + + + + //---------------------------------------------------------------------------- + // Set the PHYAD for the core + //---------------------------------------------------------------------------- + + + //---------------------------------------------------------------------------- + // Configuration process. This process will reset the core, then write + // to configuration register 0 to turn off autonegotiation and take + // the core out of the isolate state. + //---------------------------------------------------------------------------- + + // drives MDC at 2.5 MHz + //initial + //begin + // mdc <= 1'b0; + // forever + // begin + // mdc <= 1'b0; + // #200000; + // mdc <= 1'b1; + // #200000; + // end + //end + + + // Main configuration process + initial + begin : p_configuration + integer MDIO_BIT; // Bit counter within MDIO frame + + $display("** Note: Timing checks are not valid"); + + configuration_finished <= 0; + configuration_vector <= 5'b00000; + // Not doing any MDIO write, so configure the Register 0 using + // Configuration Vector + configuration_valid <= 1'b1; + //mdio_i <= 1'b1; + + // reset the core + $display("Resetting core..."); + reset <= 1'b1; + #1000000 + @(posedge gtrefclk_p) + reset <= 1'b0; + // wait for core to obtain synchronisation + + #2000000000 + #1000000000 + + #250000000 + + // Write to PCS Management configuration register 0. + $display("Writing to Control Register in PCS sublayer...."); + + // Write REG_MDIO_OP to Read MDIO Phy Addr 1, Reg Addr 1 + @(posedge independent_clock) + reg_wr_addr <= 14'h18; + reg_wr_data <= 16'h822; + reg_wr_req <= 1'b1; + @(posedge independent_clock) + reg_wr_req <= 1'b0; + #4000000 + + // Write REG_MDIO_CTRL_STATUS to turn on mdio_running + @(posedge independent_clock) + reg_wr_addr <= 14'h1c; + reg_wr_data <= 32'h1; + reg_wr_req <= 1'b1; + @(posedge independent_clock) + reg_wr_req <= 1'b0; + #4000000 + + // Write REG_MDIO_OP to Read MDIO Phy Addr 1, Reg Addr 0 + @(posedge independent_clock) + reg_wr_addr <= 14'h18; + reg_wr_data <= 32'h820; + reg_wr_req <= 1'b1; + @(posedge independent_clock) + reg_wr_req <= 1'b0; + #4000000 + //@(negedge mdc) // centre MDIO around MDC rising edge + + //MDIO_BIT = 0; + + //// transmit serial management frame + //while(MDIO_BIT !== 64) + //begin + // @(negedge mdc); + // mdio_i <= mdio_data[MDIO_BIT]; + // MDIO_BIT = MDIO_BIT + 1; + //end + + //@(negedge mdc) + //mdio_i <= 1'b1; // simulate tri-state with pullup + #10000000 + // wait for core to obtain synchronisation + wait (status_vector[1] == 1); + #8000000 + + configuration_finished <= 1; + end // p_configuration + + + + //---------------------------------------------------------------------------- + // End the simulation. + //---------------------------------------------------------------------------- + + assign simulation_finished = tx_monitor_finished & rx_monitor_finished; + + + initial + begin : p_end_simulation + fork: sim_in_progress + @(posedge simulation_finished) disable sim_in_progress; + #2000000000 + #2000000000 + #500000000 + disable sim_in_progress; + + join + if (simulation_finished) begin + #1000000 + $display("Test completed successfully"); + $display("Simulation Complete."); + end + else + $display("** Error: Testbench timed out"); + $stop; + end // p_end_simulation + + +endmodule + diff --git a/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv b/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv new file mode 100644 index 000000000..759ea2872 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv @@ -0,0 +1,381 @@ +// +// Copyright 2016 Ettus Research LLC +// + + +`timescale 1ns/1ps +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 13 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +module one_gig_eth_loopback_tb(); + `TEST_BENCH_INIT("one_gig_eth_loopback_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_CLK(ETH_CLK_P, 1000/125, 50) //125MHz GT transceiver clock + `DEFINE_RESET(GSR, 0, 100) //100ns for GSR to deassert + + wire ETH_CLK_N = ~ETH_CLK_P; + wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N; + + //localparam PACKET_MODE = 0; + localparam PORTNUM = 8'd0; + + // One_gigE Loopback Topology: + // + // TB Simulus ====> |------------| |----------------| + // | gigE MAC | <===> | gigE PCS/PMA | <====>|| + // TB Checker <==== |------------| |----------------| || Loopback through + // || + // ====> |------------| |----------------| || perfect serial channel + // Loopback | | gigE MAC | <===> | gigE PCS/PMA | <====>|| + // <==== |------------| |----------------| + + // Initialize DUT + wire gige_refclk, gige_refclk_bufg; + wire m_user_clk, s_user_clk; + wire m_channel_up, s_channel_up; + wire [7:0] m_gmii_txd, m_gmii_rxd; + wire m_gmii_tx_en, m_gmii_tx_er, m_gmii_rx_dv, m_gmii_rx_er; + wire m_gmii_clk; + wire [7:0] s_gmii_txd, s_gmii_rxd; + wire s_gmii_tx_en, s_gmii_tx_er, s_gmii_rx_dv, s_gmii_rx_er; + wire s_gmii_clk; + wire [15:0] m_phy_status; + wire [15:0] s_phy_status; + wire [63:0] loop_tdata; + wire loop_tlast, loop_tvalid, loop_tready; + + + reg independent_clock; + assign m_channel_up = m_phy_status[0]; + assign s_channel_up = s_phy_status[0]; + //assign m_user_clk = gmii_clk; + //assign s_user_clk = gmii_clk; + assign m_user_clk = independent_clock; + assign s_user_clk = independent_clock; + wire gt0_qplloutclk, gt0_qplloutrefclk, pma_reset; + + one_gige_phy_clk_gen gige_clk_gen_i ( + .areset(GSR), + .refclk_p(ETH_CLK_P), + .refclk_n(ETH_CLK_N), + .refclk(gige_refclk), + .refclk_bufg(gige_refclk_bufg) + ); + + cvita_master m_tx_chdr (.clk(m_user_clk)); + cvita_slave s_rx_chdr (.clk(s_user_clk)); + initial + begin + independent_clock <= 1'b0; + forever + begin + independent_clock <= 1'b0; + #0.5; + independent_clock <= 1'b1; + #0.5; + end + end + + //----------------------------------------------------------------- + // MDIO Master + //----------------------------------------------------------------- + wire mdc, mdio_m2s, mdio_s2m; + + mdio_master #( + .MDC_DIVIDER (8'd200) + ) mdio_master_i ( + .clk (m_user_clk), + .rst (GSR), + .mdc (mdc), + .mdio_in (mdio_s2m), + .mdio_out (mdio_m2s), + .mdio_tri (), + .reg_wr_req (/*reg_wr_req*/), + .reg_wr_addr(/*reg_wr_addr*/), + .reg_wr_data(/*reg_wr_data*/), + .reg_rd_req (/*reg_rd_req*/), + .reg_rd_addr(/*reg_rd_addr*/), + .reg_rd_data(/*reg_rd_data*/), + .reg_rd_resp(/*reg_rd_resp*/) + ); + + //GT COMMON + one_gig_eth_pcs_pma_gt_common core_gt_common_i + ( + .GTREFCLK0_IN (gige_refclk) , + .QPLLLOCK_OUT (), + .QPLLLOCKDETCLK_IN (independent_clock), + .QPLLOUTCLK_OUT (gt0_qplloutclk), + .QPLLOUTREFCLK_OUT (gt0_qplloutrefclk), + .QPLLREFCLKLOST_OUT (), + .QPLLRESET_IN (pma_reset) + ); + + one_gige_phy one_gige_phy_master_i + ( + .reset(GSR), // Asynchronous reset for entire core. + .independent_clock(independent_clock), + .pma_reset_out(pma_reset), + .gt0_qplloutclk_in(gt0_qplloutclk), + .gt0_qplloutrefclk_in(gt0_qplloutrefclk), + // Tranceiver Interface + .gtrefclk(gige_refclk), // Reference clock for MGT: 125MHz, very high quality. + .gtrefclk_bufg(gige_refclk_bufg), // Reference clock routed through a BUFG + .txp(SFP_LN1_P), // Differential +ve of serial transmission from PMA to PMD. + .txn(SFP_LN1_N), // Differential -ve of serial transmission from PMA to PMD. + .rxp(SFP_LN0_P), // Differential +ve for serial reception from PMD to PMA. + .rxn(SFP_LN0_N), // Differential -ve for serial reception from PMD to PMA. + // GMII Interface (client MAC <=> PCS) + .gmii_clk(m_gmii_clk), // Clock to client MAC. + .gmii_txd(m_gmii_txd), // Transmit data from client MAC. + .gmii_tx_en(m_gmii_tx_en), // Transmit control signal from client MAC. + .gmii_tx_er(m_gmii_tx_er), // Transmit control signal from client MAC. + .gmii_rxd(m_gmii_rxd), // Received Data to client MAC. + .gmii_rx_dv(m_gmii_rx_dv), // Received control signal to client MAC. + .gmii_rx_er(m_gmii_rx_er), // Received control signal to client MAC. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_i(mdio_m2s), // Management Data In + .mdio_o(mdio_s2m), // Management Data Out + .mdio_t(), // Management Data Tristate + .configuration_vector(5'd0), // Alternative to MDIO interface. + .configuration_valid(1'b1), // Validation signal for Config vector (MUST be 1 for proper functionality...undocumented) + // General IO's + .status_vector(m_phy_status), // Core status. + .signal_detect(1'b1 /*Optical module not supported*/) // Input from PMD to indicate presence of optical input. + ); + + simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_master_i + ( + .clk125(m_gmii_clk), + .reset(GSR), + + .GMII_GTX_CLK(), + .GMII_TX_EN(m_gmii_tx_en), + .GMII_TX_ER(m_gmii_tx_er), + .GMII_TXD(m_gmii_txd), + .GMII_RX_CLK(m_gmii_clk), + .GMII_RX_DV(m_gmii_rx_dv), + .GMII_RX_ER(m_gmii_rx_er), + .GMII_RXD(m_gmii_rxd), + + .sys_clk(m_user_clk), + .rx_tdata(s_rx_chdr.axis.tdata), + .rx_tuser(/*s_rx_chdr.axis.tuser*/), + .rx_tlast(s_rx_chdr.axis.tlast), + .rx_tvalid(s_rx_chdr.axis.tvalid), + .rx_tready(s_rx_chdr.axis.tready), + .tx_tdata(m_tx_chdr.axis.tdata), + .tx_tuser(/*m_tx_chdr.axis_tuser*/), + .tx_tlast(m_tx_chdr.axis.tlast), + .tx_tvalid(m_tx_chdr.axis.tvalid), + .tx_tready(m_tx_chdr.axis.tready), + // Debug + .debug_tx(), .debug_rx() + ); + + one_gige_phy one_gige_phy_slave_i + ( + .reset(GSR), // Asynchronous reset for entire core. + .independent_clock(independent_clock), + .pma_reset_out(), + .gt0_qplloutclk_in(gt0_qplloutclk), + .gt0_qplloutrefclk_in(gt0_qplloutrefclk), + // Tranceiver Interface + .gtrefclk(gige_refclk), // Reference clock for MGT: 125MHz, very high quality. + .gtrefclk_bufg(gige_refclk_bufg), // Reference clock routed through a BUFG + .txp(SFP_LN0_P), // Differential +ve of serial transmission from PMA to PMD. + .txn(SFP_LN0_N), // Differential -ve of serial transmission from PMA to PMD. + .rxp(SFP_LN1_P), // Differential +ve for serial reception from PMD to PMA. + .rxn(SFP_LN1_N), // Differential -ve for serial reception from PMD to PMA. + // GMII Interface (client MAC <=> PCS) + .gmii_clk(s_gmii_clk), // Clock to client MAC. + .gmii_txd(s_gmii_txd), // Transmit data from client MAC. + .gmii_tx_en(s_gmii_tx_en), // Transmit control signal from client MAC. + .gmii_tx_er(s_gmii_tx_er), // Transmit control signal from client MAC. + .gmii_rxd(s_gmii_rxd), // Received Data to client MAC. + .gmii_rx_dv(s_gmii_rx_dv), // Received control signal to client MAC. + .gmii_rx_er(s_gmii_rx_er), // Received control signal to client MAC. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_i(mdio_m2s), // Management Data In + .mdio_o(mdio_s2m), // Management Data Out + .mdio_t(), // Management Data Tristate + .configuration_vector(5'd0), // Alternative to MDIO interface. + .configuration_valid(1'b1), // Validation signal for Config vector (MUST be 1 for proper functionality...undocumented) + // General IO's + .status_vector(s_phy_status), // Core status. + .signal_detect(1'b1 /*Optical module not supported*/) // Input from PMD to indicate presence of optical input. + ); + + simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_slave_i + ( + .clk125(s_gmii_clk), + .reset(GSR), + + .GMII_GTX_CLK(), + .GMII_TX_EN(s_gmii_tx_en), + .GMII_TX_ER(s_gmii_tx_er), + .GMII_TXD(s_gmii_txd), + .GMII_RX_CLK(s_gmii_clk), + .GMII_RX_DV(s_gmii_rx_dv), + .GMII_RX_ER(s_gmii_rx_er), + .GMII_RXD(s_gmii_rxd), + + .sys_clk(s_user_clk), + .rx_tdata(loop_tdata), + .rx_tuser(), + .rx_tlast(loop_tlast), + .rx_tvalid(loop_tvalid), + .rx_tready(loop_tready), + .tx_tdata(loop_tdata), + .tx_tuser(), + .tx_tlast(loop_tlast), + .tx_tvalid(loop_tvalid), + .tx_tready(loop_tready), + // Debug + .debug_tx(), .debug_rx() + ); + + //Testbench variables + cvita_hdr_t header, header_out; + cvita_stats_t stats; + logic [63:0] crc_cache; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + `TEST_CASE_START("Wait for reset"); + while (GSR) @(posedge ETH_CLK_P); + `TEST_CASE_DONE((~GSR)); + + m_tx_chdr.push_bubble(); + + `TEST_CASE_START("Wait for master channel to come up"); + while (m_channel_up !== 1'b1) @(posedge m_user_clk); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Wait for slave channel to come up"); + while (s_channel_up !== 1'b1) @(posedge s_user_clk); + `TEST_CASE_DONE(1'b1); + + // `TEST_CASE_START("Run PRBS15 BIST"); + // s_bist_loopback <= PACKET_MODE; + // @(posedge m_user_clk); + // m_bist_gen <= 1'b1; + // m_bist_check <= 1'b1; + // @(posedge m_user_clk); + // while (m_bist_locked !== 1'b1) @(posedge m_user_clk); + // repeat (512) @(posedge m_user_clk); + // `ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + // `ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + // @(posedge m_user_clk); + // m_bist_gen <= 1'b0; + // repeat (256) @(posedge m_user_clk); + // m_bist_check <= 1'b0; + // `TEST_CASE_DONE(1'b1); + + repeat(1000) @(posedge m_user_clk); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Fill up empty FIFO then drain (short packet)"); + s_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(16, 64'd0, 64'h100, header); + s_rx_chdr.axis.tready = 1; + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==16, "Bad packet: Length mismatch"); + `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID"); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Fill up empty FIFO then drain (long packet)"); + s_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(256, 64'd0, 64'h100, header); + s_rx_chdr.axis.tready = 1; + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==256, "Bad packet: Length mismatch"); + `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID"); + `TEST_CASE_DONE(1); + + header = '{ + pkt_type:DATA, has_time:1, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Concurrent read and write (single packet)"); + s_rx_chdr.axis.tready = 1; + fork + begin + m_tx_chdr.push_ramp_pkt(1000, 64'd0, 64'h100, header); + end + begin + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + end + join + crc_cache = stats.crc; //Cache CRC for future test cases + `ASSERT_ERROR(stats.count==1000, "Bad packet: Length mismatch"); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Concurrent read and write (multiple packets)"); + s_rx_chdr.axis.tready = 1; + fork + begin + repeat (20) begin + m_tx_chdr.push_ramp_pkt(20, 64'd0, 64'h100, header); + m_tx_chdr.push_bubble(); + end + end + begin + repeat (20) begin + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==20, "Bad packet: Length mismatch"); + `ASSERT_ERROR(crc_cache==stats.crc, "Bad packet: Wrong CRC"); + end + end + join + `TEST_CASE_DONE(1); + + //`TEST_CASE_START("Validate no drops (master)"); + //`TEST_CASE_DONE((m_overruns === 32'd0)); + + //`TEST_CASE_START("Validate no drops (slave)"); + //`TEST_CASE_DONE((s_overruns === 32'd0)); + + //s_bist_loopback <= 1'b1; + + //`TEST_CASE_START("Run PRBS15 BIST (Loopback Mode)"); + //@(posedge m_user_clk); + //m_bist_gen <= 1'b1; + //m_bist_rate <= 5'd4; + //m_bist_check <= 1'b1; + //@(posedge m_user_clk); + //while (m_bist_locked !== 1'b1) @(posedge m_user_clk); + //repeat (512) @(posedge m_user_clk); + //`ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + //`ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + //@(posedge m_user_clk); + //m_bist_gen <= 1'b0; + //repeat (256) @(posedge m_user_clk); + //m_bist_check <= 1'b0; + //`TEST_CASE_DONE(1'b1); + + //s_bist_loopback <= 1'b0; + + //`TEST_CASE_START("Validate no drops (master)"); + //`TEST_CASE_DONE((m_overruns === 32'd0)); + + //`TEST_CASE_START("Validate no drops (slave)"); + //`TEST_CASE_DONE((s_overruns === 32'd0)); + + end + +endmodule diff --git a/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/Makefile b/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/Makefile new file mode 100644 index 000000000..c1271a40b --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/Makefile @@ -0,0 +1,84 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID = xc7z100/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs +include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs +include $(BASE_DIR)/../lib/xge/Makefile.srcs +include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/ten_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(XGE_SRCS) \ +$(XGE_INTERFACE_SRCS) \ +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_TEN_GIGE_PHY_XCI_SRCS) \ +$(TEN_GIGE_PHY_SRCS) \ +$(IP_AXI64_8K_2CLK_FIFO_SRCS) \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(PACKET_PROC_SRCS) \ +) +#$(IP_FIFO_SHORT_2CLK_SRCS) \ + + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +#include $(BASE_DIR)/../sim/general/Makefile.srcs +#include $(BASE_DIR)/../sim/control/Makefile.srcs +#include $(BASE_DIR)/../sim/axi/Makefile.srcs + +# Define only one toplevel module +SIM_TOP = ten_gig_eth_loopback_tb +# Simulation runtime in microseconds +SIM_RUNTIME_US = 30000 + +SIM_SRCS = \ +$(abspath ten_gig_eth_loopback_tb.sv) \ +$(SIM_GENERAL_SRCS) \ +$(SIM_CONTROL_SRCS) \ +$(SIM_AXI_SRCS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv b/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv new file mode 100644 index 000000000..b0233a339 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv @@ -0,0 +1,527 @@ +// +// Copyright 2016 Ettus Research LLC +// + + +`timescale 1ns/1ps +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 13 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axis_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +module ten_gig_eth_loopback_tb(); + `TEST_BENCH_INIT("ten_gig_eth_loopback_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_CLK(XG_CLK_P, 1000/156.25, 50) //156.25MHz GT transceiver clock + `DEFINE_RESET(GSR, 0, 100) //100ns for GSR to deassert + + wire XG_CLK_N = ~XG_CLK_P; + wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N; + + //localparam PACKET_MODE = 0; + localparam PORTNUM = 8'd0; + + // Ten_gigE Loopback Topology: + // + // TB Simulus ====> |------------| |----------------| + // | XgigE MAC | <===> | XgigE PCS/PMA | <====>|| + // TB Checker <==== |------------| |----------------| || Loopback through + // || + // ====> |------------| |----------------| || perfect serial channel + // Loopback | | XgigE MAC | <===> | XgigE PCS/PMA | <====>|| + // <==== |------------| |----------------| + + // Initialize DUT + wire xgige_refclk, xgige_clk156, xgige_dclk; + wire m_user_clk, s_user_clk; + wire m_channel_up, s_channel_up; + + wire [63:0] m_xgmii_txd; + wire [7:0] m_xgmii_txc; + wire [63:0] m_xgmii_rxd; + wire [7:0] m_xgmii_rxc; + wire [63:0] s_xgmii_txd; + wire [7:0] s_xgmii_txc; + wire [63:0] s_xgmii_rxd; + wire [7:0] s_xgmii_rxc; + wire [7:0] m_xgmii_status; + wire [7:0] s_xgmii_status; + wire m_xge_phy_resetdone; + wire s_xge_phy_resetdone; + wire m_mdc, m_mdio_in, m_mdio_out; + wire s_mdc, s_mdio_in, s_mdio_out; + wire sfpp_rxlos,sfpp_tx_fault,sfpp_tx_disable; + + + wire [15:0] m_phy_status; + wire [15:0] s_phy_status; + wire [63:0] loop_tdata; + wire [3:0] loop_tuser; + wire loop_tlast, loop_tvalid, loop_tready; + + wire [7:0] wb_adr_i; + wire wb_cyc_i; + wire [31:0] wb_dat_i; + wire wb_stb_i; + wire wb_we_i; + wire wb_ack_o; + wire [31:0] wb_dat_o; + wire wb_int_o; + //`ifdef USE_ARM_FRAMER + //wire [63:0] c2e_tdata_int; + //wire [3:0] c2e_tuser_int; + //wire c2e_tlast_int; + //wire c2e_tvalid_int; + //wire c2e_tready_int; + //wire [63:0] c2e_tdata; + //wire [3:0] c2e_tuser; + //wire c2e_tlast; + //wire c2e_tvalid; + //wire c2e_tready; + //`endif + + reg independent_clock; + assign m_channel_up = m_phy_status[0]; + assign s_channel_up = s_phy_status[0]; + //assign m_user_clk = xgige_refclk; + //assign s_user_clk = xgige_refclk; + assign m_user_clk = independent_clock; + assign s_user_clk = independent_clock; + + ten_gige_phy_clk_gen xgige_clk_gen_i ( + .areset(GSR), + .refclk_p(XG_CLK_P), + .refclk_n(XG_CLK_N), + .refclk(xgige_refclk), + .clk156(xgige_clk156), + .dclk(xgige_dclk) + ); + + cvita_master m_tx_chdr (.clk(m_user_clk)); + cvita_slave s_rx_chdr (.clk(s_user_clk)); + // Use this to send axi-stream with arm_framer + //`ifdef USE_ARM_FRAMER + //axis_master #(.DWIDTH(68)) m_axis (.clk(m_user_clk)); + //axis_slave #(.DWIDTH(68)) s_axis (.clk(s_user_clk)); + //`endif + initial + begin + independent_clock <= 1'b0; + forever + begin + independent_clock <= 1'b0; + #2.5; + independent_clock <= 1'b1; + #2.5; + end + end + + assign sfpp_rxlos = 1'b0; + assign sfpp_tx_fault = 1'b0; + + // Instantiate the 10GBASER/KR GT Common block + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") ) //Does not affect hardware + ten_gig_eth_pcs_pma_gt_common_block + ( + .refclk(xgige_refclk), + .qpllreset(qpllreset), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclksel(3'b001 /*3'b101*GTSOUTHREFCLK0*/) + ); + + ten_gige_phy ten_gige_phy_master_i + ( + // Clocks and Reset + .areset(GSR), // Asynchronous reset for entire core. + .refclk(xgige_refclk), // Transciever reference clock: 156.25MHz + .clk156(xgige_clk156), // Globally buffered core clock: 156.25MHz + .dclk(xgige_dclk), // Management/DRP clock: 78.125MHz + .sim_speedup_control(~GSR), + // GMII Interface (client MAC <=> PCS) + .xgmii_txd(m_xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(m_xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(m_xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(m_xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(SFP_LN0_P), // Differential +ve of serial transmission from PMA to PMD. + .txn(SFP_LN0_N), // Differential -ve of serial transmission from PMA to PMD. + .rxp(SFP_LN1_P), // Differential +ve for serial reception from PMD to PMA. + .rxn(SFP_LN1_N), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(m_mdc), // Management Data Clock + .mdio_in(m_mdio_in), // Management Data In + .mdio_out(m_mdio_out), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(5'd4), // MDIO address is 4 + // General IO's + .core_status(m_xgmii_status), // Core status + .resetdone(m_xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), //FIXME // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), //FIXME + .tx_disable(/*sfpp_tx_disable*/), //FIXME + .qpllreset(qpllreset1), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk) + + ); + + n310_xge_mac_wrapper #(.PORTNUM(PORTNUM)) xge_mac_wrapper_master_i + ( + // XGMII + .xgmii_clk(xgige_clk156), + .xgmii_txd(m_xgmii_txd), + .xgmii_txc(m_xgmii_txc), + .xgmii_rxd(m_xgmii_rxd), + .xgmii_rxc(m_xgmii_rxc), + // Client FIFO Interfaces + .sys_clk(m_user_clk), + .sys_rst(GSR), + //`ifdef USE_ARM_FRAMER + //.rx_tdata(s_axis.axis.tdata[63:0]), + //.rx_tuser(s_axis.axis.tdata[67:64]), + //.rx_tlast(s_axis.axis.tlast), + //.rx_tvalid(s_axis.axis.tvalid), + //.rx_tready(/*s_axis.axis.tready*/1'b1), + //.tx_tdata(c2e_tdata), + //.tx_tuser(c2e_tuser), + //.tx_tlast(c2e_tlast), + //.tx_tvalid(c2e_tvalid), + //.tx_tready(c2e_tready), + //`endif + .rx_tdata(s_rx_chdr.axis.tdata), + .rx_tuser(), + .rx_tlast(s_rx_chdr.axis.tlast), + .rx_tvalid(s_rx_chdr.axis.tvalid), + .rx_tready(s_rx_chdr.axis.tready), + .tx_tdata(m_tx_chdr.axis.tdata), + .tx_tuser(4'd4), // Bit[3] (error) is ignored for now. + .tx_tlast(m_tx_chdr.axis.tlast), + .tx_tvalid(m_tx_chdr.axis.tvalid), + .tx_tready(m_tx_chdr.axis.tready), + // Other + .phy_ready(m_xge_phy_resetdone), + .ctrl_tx_enable (/*mac_ctrl_reg[0]*/1'b1), //FIXME: Remove hardcoded value + .status_crc_error (), + .status_fragment_error (), + .status_txdfifo_ovflow (), + .status_txdfifo_udflow (), + .status_rxdfifo_ovflow (), + .status_rxdfifo_udflow (), + .status_pause_frame_rx (), + .status_local_fault (), + .status_remote_fault () + ); + + assign m_phy_status = {8'h00, m_xgmii_status}; + + //`ifdef USE_ARM_FRAMER + // arm_framer inst_arm_framer ( + // .clk (m_user_clk), + // .reset (GSR), + // .clear (clear), + // .s_axis_tdata (m_axis.axis.tdata[63:0]), + // .s_axis_tuser (m_axis.axis.tdata[67:64]), + // .s_axis_tlast (m_axis.axis.tlast), + // .s_axis_tvalid (m_axis.axis.tvalid), + // .s_axis_tready (m_axis.axis.tready), + // .m_axis_tdata (c2e_tdata_int), + // .m_axis_tuser (c2e_tuser_int), + // .m_axis_tlast (c2e_tlast_int), + // .m_axis_tvalid (c2e_tvalid_int), + // .m_axis_tready (c2e_tready_int) + // ); + + // axi_mux4 #(.PRIO(0), .WIDTH(68)) eth_mux + // (.clk(m_user_clk), .reset(GSR), .clear(clear), + // .i0_tdata({c2e_tuser_int,c2e_tdata_int}), .i0_tlast(c2e_tlast_int), .i0_tvalid(c2e_tvalid_int), .i0_tready(c2e_tready_int), + // .i1_tdata(), .i1_tlast(), .i1_tvalid(), .i1_tready(), + // .i2_tdata(), .i2_tlast(), .i2_tvalid(), .i2_tready(), + // .i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(), + // .o_tdata({c2e_tuser,c2e_tdata}), .o_tlast(c2e_tlast), .o_tvalid(c2e_tvalid), .o_tready(c2e_tready)); + //`endif + + ten_gige_phy ten_gige_phy_slave_i + ( + // Clocks and Reset + .areset(GSR), // Asynchronous reset for entire core. + .refclk(xgige_refclk), // Transciever reference clock: 156.25MHz + .clk156(xgige_clk156), // Globally buffered core clock: 156.25MHz + .dclk(xgige_dclk), // Management/DRP clock: 78.125MHz + .sim_speedup_control(~GSR), + // GMII Interface (client MAC <=> PCS) + .xgmii_txd(s_xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(s_xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(s_xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(s_xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(SFP_LN1_P), // Differential +ve of serial transmission from PMA to PMD. + .txn(SFP_LN1_N), // Differential -ve of serial transmission from PMA to PMD. + .rxp(SFP_LN0_P), // Differential +ve for serial reception from PMD to PMA. + .rxn(SFP_LN0_N), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(s_mdc), // Management Data Clock + .mdio_in(s_mdio_in), // Management Data In + .mdio_out(s_mdio_out), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(5'd4), // MDIO address is 4 + // General IO's + .core_status(s_xgmii_status), // Core status + .resetdone(s_xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), //FIXME // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), //FIXME + .tx_disable(/*sfpp_tx_disable*/), //FIXME + .qpllreset(qpllreset2), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk) + ); + + n310_xge_mac_wrapper #(.PORTNUM(PORTNUM)) xge_mac_wrapper_slave_i + ( + // XGMII + .xgmii_clk(xgige_clk156), + .xgmii_txd(s_xgmii_txd), + .xgmii_txc(s_xgmii_txc), + .xgmii_rxd(s_xgmii_rxd), + .xgmii_rxc(s_xgmii_rxc), + // Client FIFO Interfaces + .sys_clk(s_user_clk), + .sys_rst(GSR), + .rx_tdata(loop_tdata), + .rx_tuser(loop_tuser), + .rx_tlast(loop_tlast), + .rx_tvalid(loop_tvalid), + .rx_tready(loop_tready), + .tx_tdata(loop_tdata), + .tx_tuser(loop_tuser), // Bit[3] (error) is ignored for now. + .tx_tlast(loop_tlast), + .tx_tvalid(loop_tvalid), + .tx_tready(loop_tready), + // Other + .phy_ready(s_xge_phy_resetdone), + .ctrl_tx_enable (/*mac_ctrl_reg[0]*/1'b1), //FIXME: Remove hardcoded value + .status_crc_error (), + .status_fragment_error (), + .status_txdfifo_ovflow (), + .status_txdfifo_udflow (), + .status_rxdfifo_ovflow (), + .status_rxdfifo_udflow (), + .status_pause_frame_rx (), + .status_local_fault (), + .status_remote_fault () + ); + + assign s_phy_status = {8'h00, s_xgmii_status}; + + //Testbench variables + cvita_hdr_t header, header_out; + cvita_stats_t stats; + logic [63:0] crc_cache; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + `TEST_CASE_START("Wait for reset"); + // `ifdef USE_ARM_FRAMER + // m_axis.reset; + // `endif + while (GSR) @(posedge XG_CLK_P); + `TEST_CASE_DONE((~GSR)); + + m_tx_chdr.push_bubble(); + // `ifdef USE_ARM_FRAMER + //m_axis.push_bubble(); + // `endif + + `TEST_CASE_START("Wait for master channel to come up"); + while (m_channel_up !== 1'b1) @(posedge m_user_clk); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Wait for slave channel to come up"); + while (s_channel_up !== 1'b1) @(posedge s_user_clk); + `TEST_CASE_DONE(1'b1); + + // `TEST_CASE_START("Run PRBS15 BIST"); + // s_bist_loopback <= PACKET_MODE; + // @(posedge m_user_clk); + // m_bist_gen <= 1'b1; + // m_bist_check <= 1'b1; + // @(posedge m_user_clk); + // while (m_bist_locked !== 1'b1) @(posedge m_user_clk); + // repeat (512) @(posedge m_user_clk); + // `ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + // `ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + // @(posedge m_user_clk); + // m_bist_gen <= 1'b0; + // repeat (256) @(posedge m_user_clk); + // m_bist_check <= 1'b0; + // `TEST_CASE_DONE(1'b1); + + repeat(2000) @(posedge m_user_clk); + + //`TEST_CASE_START("Test Ethernet packet"); + // s_axis.axis.tready = 0; + // m_axis.push_word({4'b0, 64'h0000_0000_0000_ffff}, 1'b0); + // s_axis.axis.tready = 1; + // m_axis.push_word({4'b0, 64'hffff_ffff_ce20_ad1b}, 1'b0); + // m_axis.push_word({4'b0, 64'hc57a_0806_0001_0800}, 1'b0); + // m_axis.push_word({4'b0, 64'h0604_0001_ce20_ad1b}, 1'b0); + // m_axis.push_word({4'b0, 64'hc57a_c0a8_0a64_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_c0a8_0a0a}, 1'b1); + //`TEST_CASE_DONE(1'b1); + + // repeat(2000) @(posedge m_user_clk); + //`TEST_CASE_START("Test Ethernet packet"); + // s_axis.axis.tready = 0; + // m_axis.push_word({4'b0, 64'hffff_ffff_ffff_9aa9}, 1'b0); + // s_axis.axis.tready = 1; + // m_axis.push_word({4'b0, 64'h6400_e341_0800_4500}, 1'b0); + // m_axis.push_word({4'b0, 64'h0148_0000_0000_4011}, 1'b0); + // m_axis.push_word({4'b0, 64'h79a6_0000_0000_ffff}, 1'b0); + // m_axis.push_word({4'b0, 64'hffff_0044_0043_0134}, 1'b0); + // m_axis.push_word({4'b0, 64'h90be_0101_0600_d2ab}, 1'b0); + // m_axis.push_word({4'b0, 64'h9f01_0007_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_9aa9}, 1'b0); + // m_axis.push_word({4'b0, 64'h6400_e341_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_6382}, 1'b0); + // m_axis.push_word({4'b0, 64'h5363_3501_013d_0701}, 1'b0); + // m_axis.push_word({4'b0, 64'h9aa9_6400_e341_3902}, 1'b0); + // m_axis.push_word({4'b0, 64'h0240_3707_0103_060c}, 1'b0); + // m_axis.push_word({4'b0, 64'h0f1c_2a3c_0c75_6468}, 1'b0); + // m_axis.push_word({4'b0, 64'h6370_2031_2e32_342e}, 1'b0); + // m_axis.push_word({4'b0, 64'h31ff_0000_0000_0000}, 1'b0); + // m_axis.push_word({5'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'd6, 64'h0000_0000_1234_0000}, 1'b1); + + //`TEST_CASE_DONE(1'b1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Fill up empty FIFO then drain (short packet)"); + s_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(16, 64'd0, 64'h100, header); + s_rx_chdr.axis.tready = 1; + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==16, "Bad packet: Length mismatch"); + `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID"); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Fill up empty FIFO then drain (long packet)"); + s_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(256, 64'd0, 64'h100, header); + s_rx_chdr.axis.tready = 1; + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==256, "Bad packet: Length mismatch"); + `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID"); + `TEST_CASE_DONE(1); + + header = '{ + pkt_type:DATA, has_time:1, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Concurrent read and write (single packet)"); + s_rx_chdr.axis.tready = 1; + fork + begin + m_tx_chdr.push_ramp_pkt(1000, 64'd0, 64'h100, header); + end + begin + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + end + join + crc_cache = stats.crc; //Cache CRC for future test cases + `ASSERT_ERROR(stats.count==1000, "Bad packet: Length mismatch"); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Concurrent read and write (multiple packets)"); + s_rx_chdr.axis.tready = 1; + fork + begin + repeat (20) begin + m_tx_chdr.push_ramp_pkt(20, 64'd0, 64'h100, header); + m_tx_chdr.push_bubble(); + end + end + begin + repeat (20) begin + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==20, "Bad packet: Length mismatch"); + `ASSERT_ERROR(crc_cache==stats.crc, "Bad packet: Wrong CRC"); + end + end + join + `TEST_CASE_DONE(1); + + //`TEST_CASE_START("Validate no drops (master)"); + //`TEST_CASE_DONE((m_overruns === 32'd0)); + + //`TEST_CASE_START("Validate no drops (slave)"); + //`TEST_CASE_DONE((s_overruns === 32'd0)); + + //s_bist_loopback <= 1'b1; + + //`TEST_CASE_START("Run PRBS15 BIST (Loopback Mode)"); + //@(posedge m_user_clk); + //m_bist_gen <= 1'b1; + //m_bist_rate <= 5'd4; + //m_bist_check <= 1'b1; + //@(posedge m_user_clk); + //while (m_bist_locked !== 1'b1) @(posedge m_user_clk); + //repeat (512) @(posedge m_user_clk); + //`ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + //`ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + //@(posedge m_user_clk); + //m_bist_gen <= 1'b0; + //repeat (256) @(posedge m_user_clk); + //m_bist_check <= 1'b0; + //`TEST_CASE_DONE(1'b1); + + //s_bist_loopback <= 1'b0; + + //`TEST_CASE_START("Validate no drops (master)"); + //`TEST_CASE_DONE((m_overruns === 32'd0)); + + //`TEST_CASE_START("Validate no drops (slave)"); + //`TEST_CASE_DONE((s_overruns === 32'd0)); + + end + +endmodule -- cgit v1.2.3