From c6bb9924e56664ccb337694f8ef485ba8245edfd Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Wed, 26 Aug 2020 13:51:51 -0500 Subject: fpga: n3xx: Update AXI interconnect address range This change allows the entire 2 GiB address space to be accessed on each memory port. --- .../axi_intercon_2x64_256_bd.bd | 1554 +++++---- .../axi_intercon_2x64_256_bd.bxml | 23 +- .../axi_intercon_4x64_256_bd.bd | 3559 ++++++++------------ .../axi_intercon_4x64_256_bd.bxml | 9 +- 4 files changed, 2217 insertions(+), 2928 deletions(-) (limited to 'fpga/usrp3/top/n3xx/ip') diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd index 121829558..c2249e1fa 100644 --- a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd @@ -1,715 +1,839 @@ - - - - - xilinx.com - BlockDiagram - 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"s01_width_conv/m_axi_aclk", + "s00_width_conv/m_axi_aclk" + ] + }, + "M00_AXI_ARESETN_1": { + "ports": [ + "M00_AXI_ARESETN", + "xbar/aresetn", + "m00_rs/aresetn", + "s00_rs_256/aresetn", + "s01_rs_256/aresetn", + "s01_width_conv/m_axi_aresetn", + "s00_width_conv/m_axi_aresetn" + ] + }, + "S00_AXI_ACLK_1": { + "ports": [ + "S00_AXI_ACLK", + "s00_rs/aclk", + "s00_width_conv/s_axi_aclk" + ] + }, + "S00_AXI_ARESETN_1": { + "ports": [ + "S00_AXI_ARESETN", + "s00_rs/aresetn", + "s00_width_conv/s_axi_aresetn" + ] + }, + "S01_AXI_ACLK_1": { + "ports": [ + "S01_AXI_ACLK", + "s01_rs/aclk", + "s01_width_conv/s_axi_aclk" + ] + }, + "S01_AXI_ARESETN_1": { + "ports": [ + "S01_AXI_ARESETN", + "s01_rs/aresetn", + "s01_width_conv/s_axi_aresetn" + ] + } + }, + "addressing": { + "/": { + "address_spaces": { + "S00_AXI": { + "range": "4G", + "width": "32", + "segments": { + "SEG_M00_AXI_Reg": { + "address_block": "/M00_AXI/Reg", + "offset": "0x00000000", + "range": "2G" + } + } + }, + "S01_AXI": { + "range": "4G", + "width": "32", + "segments": { + "SEG_M00_AXI_Reg": { + "address_block": "/M00_AXI/Reg", + "offset": "0x00000000", + "range": "2G" + } + } + } + }, + "memory_maps": { + "M00_AXI": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "64K", + "width": "32", + "usage": "register" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml index 5e3a0c83e..4cddd3510 100644 --- a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml @@ -1,18 +1,12 @@ - + Composite Fileset - - - + + + + - - - - - - - @@ -77,13 +71,6 @@ - - - - - - - diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd 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"m00_rs/S_AXI", + "xbar/M00_AXI" + ] + }, + "s00_width_conv_M_AXI": { + "interface_ports": [ + "s00_width_conv/M_AXI", + "s00_rs_256/S_AXI" + ] + }, + "s03_rs_256_M_AXI": { + "interface_ports": [ + "s03_rs_256/M_AXI", + "xbar/S03_AXI" + ] + }, + "s02_rs_M_AXI": { + "interface_ports": [ + "s02_rs/M_AXI", + "s02_width_conv/S_AXI" + ] + }, + "s03_rs_M_AXI": { + "interface_ports": [ + "s03_rs/M_AXI", + "s03_width_conv/S_AXI" + ] + }, + "s00_rs_M_AXI": { + "interface_ports": [ + "s00_rs/M_AXI", + "s00_width_conv/S_AXI" + ] + }, + "s02_rs_256_M_AXI": { + "interface_ports": [ + "s02_rs_256/M_AXI", + "xbar/S02_AXI" + ] + }, + "s01_width_conv_M_AXI": { + "interface_ports": [ + "s01_width_conv/M_AXI", + "s01_rs_256/S_AXI" + ] + }, + "s02_width_conv_M_AXI": { + "interface_ports": [ + "s02_width_conv/M_AXI", + "s02_rs_256/S_AXI" + ] + }, + "S03_AXI_1": { + "interface_ports": [ + "S03_AXI", + "s03_rs/S_AXI" + ] + }, + "m00_rs_M_AXI": { + "interface_ports": [ + "M00_AXI", + "m00_rs/M_AXI" + ] + }, + "S02_AXI_1": { + "interface_ports": [ + "S02_AXI", + "s02_rs/S_AXI" + ] + }, + "S01_AXI_1": { + "interface_ports": [ + "S01_AXI", + "s01_rs/S_AXI" + ] + } + }, + "nets": { + "M00_AXI_ACLK_1": { + "ports": [ + "M00_AXI_ACLK", + "xbar/aclk", + "m00_rs/aclk", + "s00_rs_256/aclk", + "s01_rs_256/aclk", + "s01_width_conv/m_axi_aclk", + "s00_width_conv/m_axi_aclk", + "s02_width_conv/m_axi_aclk", + "s03_width_conv/m_axi_aclk", + "s02_rs_256/aclk", + "s03_rs_256/aclk" + ] + }, + "M00_AXI_ARESETN_1": { + "ports": [ + "M00_AXI_ARESETN", + "xbar/aresetn", + "m00_rs/aresetn", + "s00_rs_256/aresetn", + "s01_rs_256/aresetn", + "s01_width_conv/m_axi_aresetn", + "s00_width_conv/m_axi_aresetn", + "s02_width_conv/m_axi_aresetn", + "s03_width_conv/m_axi_aresetn", + "s02_rs_256/aresetn", + "s03_rs_256/aresetn" + ] + }, + "S00_AXI_ACLK_1": { + "ports": [ + "S00_AXI_ACLK", + "s00_rs/aclk", + "s00_width_conv/s_axi_aclk" + ] + }, + "S00_AXI_ARESETN_1": { + "ports": [ + "S00_AXI_ARESETN", + "s00_rs/aresetn", + "s00_width_conv/s_axi_aresetn" + ] + }, + "S01_AXI_ACLK_1": { + "ports": [ + "S01_AXI_ACLK", + "s01_rs/aclk", + "s01_width_conv/s_axi_aclk" + ] + }, + "S01_AXI_ARESETN_1": { + "ports": [ + "S01_AXI_ARESETN", + "s01_rs/aresetn", + "s01_width_conv/s_axi_aresetn" + ] + }, + "S02_AXI_ACLK_1": { + "ports": [ + "S02_AXI_ACLK", + "s02_rs/aclk", + "s02_width_conv/s_axi_aclk" + ] + }, + "S02_AXI_ARESETN_1": { + "ports": [ + "S02_AXI_ARESETN", + "s02_rs/aresetn", + "s02_width_conv/s_axi_aresetn" + ] + }, + "S03_AXI_ACLK_1": { + "ports": [ + "S03_AXI_ACLK", + "s03_rs/aclk", + "s03_width_conv/s_axi_aclk" + ] + }, + "S03_AXI_ARESETN_1": { + "ports": [ + "S03_AXI_ARESETN", + "s03_rs/aresetn", + "s03_width_conv/s_axi_aresetn" + ] + } + }, + "addressing": { + "/": { + "address_spaces": { + "S00_AXI": { + "range": "4G", + "width": "32", + "segments": { + "SEG_M00_AXI_Reg": { + "address_block": "/M00_AXI/Reg", + "offset": "0x00000000", + "range": "2G" + } + } + }, + "S01_AXI": { + "range": "4G", + "width": "32", + "segments": { + "SEG_M00_AXI_Reg": { + "address_block": "/M00_AXI/Reg", + "offset": "0x00000000", + "range": "2G" + } + } + }, + "S02_AXI": { + "range": "4G", + "width": "32", + "segments": { + "SEG_M00_AXI_Reg": { + "address_block": "/M00_AXI/Reg", + "offset": "0x00000000", + "range": "2G" + } + } + }, + "S03_AXI": { + "range": "4G", + "width": "32", + "segments": { + "SEG_M00_AXI_Reg": { + "address_block": "/M00_AXI/Reg", + "offset": "0x00000000", + "range": "2G" + } + } + } + }, + "memory_maps": { + "M00_AXI": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "64K", + "width": "32", + "usage": "register" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml index 217597784..a5bded5c4 100644 --- a/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml @@ -1,10 +1,11 @@ - + Composite Fileset - - - + + + + -- cgit v1.2.3