From ae2b9bf7aeea6f8f98f6dacffdfc018d87107927 Mon Sep 17 00:00:00 2001 From: steviez Date: Fri, 31 Jul 2020 12:08:19 -0500 Subject: fpga: n320: Add BIST (AA) image files This adds new image files which come with a DRAM FIFO. The addition of an N320 image with a DRAM FIFO allows DDR3 BIST to be run on an assembled (motherboard + daughterboard) N320. This image is intentionally very similar to the N300_AA and N310_AA targets which serve the same purpose of providing an image with a DRAM FIFO for their respective devices. --- fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AA.dts | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AA.dts (limited to 'fpga/usrp3/top/n3xx/dts') diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AA.dts new file mode 100644 index 000000000..26177537e --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AA.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n320-fpga.dtsi" + +&fpga_full { + uio@40004000 { + compatible = "usrp-uio"; + reg = <0x40004000 0x1000>; + reg-names = "misc-auro-regs0"; + status = "okay"; + }; + + + uio@4000c000 { + compatible = "usrp-uio"; + reg = <0x4000c000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; +}; + +#include "n320-common.dtsi" +#include "dma-common.dtsi" -- cgit v1.2.3