From 6f038dc2f69b38e715206b2e700fdd3a1bbc638e Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Thu, 9 Dec 2021 14:30:30 -0600
Subject: fpga: Use PROTOVER and CHDR_W from RFNoC image builder

This updates all RFNoC devices so that they get the RFNoC protocol
version and CHDR width in the same way, from the output generated by
the RFNoC image builder.
---
 fpga/usrp3/top/n3xx/dboards/mg/n3xx.v | 19 ++++++++++++++++++-
 fpga/usrp3/top/n3xx/dboards/rh/n3xx.v | 19 ++++++++++++++++++-
 2 files changed, 36 insertions(+), 2 deletions(-)

(limited to 'fpga/usrp3/top/n3xx/dboards')

diff --git a/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v b/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v
index d9104f412..daa3ca90e 100644
--- a/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v
+++ b/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v
@@ -315,6 +315,22 @@ module n3xx (
 `endif
 );
 
+  // Include the RFNoC image core header file
+  `ifdef RFNOC_IMAGE_CORE_HDR
+    `include `"`RFNOC_IMAGE_CORE_HDR`"
+  `else
+    ERROR_RFNOC_IMAGE_CORE_HDR_not_defined();
+    `define CHDR_WIDTH     64
+    `define RFNOC_PROTOVER { 8'd1, 8'd0 }
+  `endif
+  localparam CHDR_W         = `CHDR_WIDTH;
+  localparam RFNOC_PROTOVER = `RFNOC_PROTOVER;
+
+  // This USRP currently only supports 64-bit CHDR width
+  if (CHDR_W != 64) begin : gen_chdr_w_error
+    CHDR_W_must_be_64_for_this_USRP();
+  end
+
   localparam N_AXILITE_SLAVES = 4;
   localparam REG_AWIDTH = 14; // log2(0x4000)
   localparam QSFP_REG_AWIDTH = 17; // log2(0x20000)
@@ -332,7 +348,6 @@ module n3xx (
   localparam NUM_DBOARDS = 1;
 `endif
   localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO;
-  localparam [15:0] RFNOC_PROTOVER  = {8'd1, 8'd0};
 
   // Internal connections to PS
   // HP0 -- High Performance port 0, FPGA is the master
@@ -3517,6 +3532,8 @@ module n3xx (
     .NUM_CHANNELS_PER_RADIO(NUM_CHANNELS_PER_RADIO),
     .NUM_CHANNELS(NUM_CHANNELS),
     .NUM_DBOARDS(NUM_DBOARDS),
+    .CHDR_W(CHDR_W),
+    .RFNOC_PROTOVER(RFNOC_PROTOVER),
   `ifdef USE_REPLAY
     .USE_REPLAY(1)
   `else
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v b/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v
index 9eedd55b9..e5238f135 100644
--- a/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v
+++ b/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v
@@ -307,6 +307,22 @@ module n3xx (
   output        DBB_LED_TX
 );
 
+  // Include the RFNoC image core header file
+  `ifdef RFNOC_IMAGE_CORE_HDR
+    `include `"`RFNOC_IMAGE_CORE_HDR`"
+  `else
+    ERROR_RFNOC_IMAGE_CORE_HDR_not_defined();
+    `define CHDR_WIDTH     64
+    `define RFNOC_PROTOVER { 8'd1, 8'd0 }
+  `endif
+  localparam CHDR_W         = `CHDR_WIDTH;
+  localparam RFNOC_PROTOVER = `RFNOC_PROTOVER;
+
+  // This USRP currently only supports 64-bit CHDR width
+  if (CHDR_W != 64) begin : gen_chdr_w_error
+    CHDR_W_must_be_64_for_this_USRP();
+  end
+
   localparam N_AXILITE_SLAVES = 4;
   localparam REG_AWIDTH = 14; // log2(0x4000)
   localparam QSFP_REG_AWIDTH = 17; // log2(0x20000)
@@ -320,7 +336,6 @@ module n3xx (
   localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO;
   localparam CHANNEL_WIDTH = 32;
 
-
   // Internal connections to PS
   // HP0 -- High Performance port 0, FPGA is the master
   wire [31:0] S_AXI_HP0_AWADDR;
@@ -3447,6 +3462,8 @@ module n3xx (
     .NUM_DBOARDS(NUM_DBOARDS),
     .NUM_SPI_PER_DBOARD(4),
     .USE_CORRECTION(1),
+    .CHDR_W(CHDR_W),
+    .RFNOC_PROTOVER(RFNOC_PROTOVER),
   `ifdef USE_REPLAY
     .USE_REPLAY(1)
   `else
-- 
cgit v1.2.3