From e94a209c5b2559348593a6732d694fd49ab59ad0 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Mon, 17 Aug 2020 21:07:30 -0500 Subject: fpga: n3xx: Fix timeout for timekeeper registers This implements the same change that was made for E31x. The same issue wasn't reproduced on N3xx, however this change keeps the code consistent and eliminates the potential for the same problem. --- fpga/usrp3/top/n3xx/dboards/mg/n3xx.v | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'fpga/usrp3/top/n3xx/dboards/mg/n3xx.v') diff --git a/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v b/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v index e09e44741..d9104f412 100644 --- a/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v +++ b/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v @@ -904,8 +904,6 @@ module n3xx ( wire reg_rd_resp_npio, reg_rd_resp_npio0, reg_rd_resp_npio1; wire [REG_DWIDTH-1:0] reg_rd_data_npio, reg_rd_data_npio0, reg_rd_data_npio1; - localparam NPIO_REG_BASE = 14'h0200; - regport_resp_mux #( .WIDTH (REG_DWIDTH), .NUM_SLAVES (2) @@ -1360,7 +1358,7 @@ module n3xx ( n3xx_mgt_io_core #( .PROTOCOL ("Aurora"), - .REG_BASE (NPIO_REG_BASE + 14'h00), + .REG_BASE (14'h00), // Base offset removed by n3xx_core .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) .REG_AWIDTH (REG_AWIDTH), // Width of the address bus .PORTNUM (8'd2), @@ -1417,7 +1415,7 @@ module n3xx ( n3xx_mgt_io_core #( .PROTOCOL ("Aurora"), - .REG_BASE (NPIO_REG_BASE + 14'h40), + .REG_BASE (14'h40), // Base offset removed by n3xx_core .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) .REG_AWIDTH (REG_AWIDTH), // Width of the address bus .PORTNUM (8'd3), -- cgit v1.2.3