From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Thu, 23 Jan 2020 16:10:22 -0800 Subject: Merge FPGA repository back into UHD repository MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams Co-authored-by: Andrej Rode Co-authored-by: Ashish Chaudhari Co-authored-by: Ben Hilburn Co-authored-by: Ciro Nishiguchi Co-authored-by: Daniel Jepson Co-authored-by: Derek Kozel Co-authored-by: EJ Kreinar Co-authored-by: Humberto Jimenez Co-authored-by: Ian Buckley Co-authored-by: Jörg Hofrichter Co-authored-by: Jon Kiser Co-authored-by: Josh Blum Co-authored-by: Jonathon Pendlum Co-authored-by: Martin Braun Co-authored-by: Matt Ettus Co-authored-by: Michael West Co-authored-by: Moritz Fischer Co-authored-by: Nick Foster Co-authored-by: Nicolas Cuervo Co-authored-by: Paul Butler Co-authored-by: Paul David Co-authored-by: Ryan Marlow Co-authored-by: Sugandha Gupta Co-authored-by: Sylvain Munaut Co-authored-by: Trung Tran Co-authored-by: Vidush Vishwanath Co-authored-by: Wade Fife --- fpga/usrp3/top/e320/dts/dma-common.dtsi | 358 ++++++++++++++++++++++++++ fpga/usrp3/top/e320/dts/e320-common.dtsi | 46 ++++ fpga/usrp3/top/e320/dts/e320-fpga.dtsi | 8 + fpga/usrp3/top/e320/dts/usrp_e320_fpga_1G.dts | 47 ++++ fpga/usrp3/top/e320/dts/usrp_e320_fpga_AA.dts | 22 ++ fpga/usrp3/top/e320/dts/usrp_e320_fpga_XG.dts | 47 ++++ 6 files changed, 528 insertions(+) create mode 100644 fpga/usrp3/top/e320/dts/dma-common.dtsi create mode 100644 fpga/usrp3/top/e320/dts/e320-common.dtsi create mode 100644 fpga/usrp3/top/e320/dts/e320-fpga.dtsi create mode 100644 fpga/usrp3/top/e320/dts/usrp_e320_fpga_1G.dts create mode 100644 fpga/usrp3/top/e320/dts/usrp_e320_fpga_AA.dts create mode 100644 fpga/usrp3/top/e320/dts/usrp_e320_fpga_XG.dts (limited to 'fpga/usrp3/top/e320/dts') diff --git a/fpga/usrp3/top/e320/dts/dma-common.dtsi b/fpga/usrp3/top/e320/dts/dma-common.dtsi new file mode 100644 index 000000000..0f3dde41d --- /dev/null +++ b/fpga/usrp3/top/e320/dts/dma-common.dtsi @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +&fpga_full { + tx_dma0: dma@43CA0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CA0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma1: dma@43CB0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CB0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma2: dma@43CC0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CC0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma3: dma@43CD0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CD0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma4: dma@43CE0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CE0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma5: dma@43CF0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CF0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma0: dma@43C00000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C00000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma1: dma@43C10000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C10000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma2: dma@43C20000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C20000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma3: dma@43C30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C30000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma4: dma@43C40000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C40000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma5: dma@43C50000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C50000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + + usrp_rx_dma0: usrp-rx-dma@43c00000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma0 0>; + dma-names = "dma"; + port-id = <0>; + status = "okay"; + + regmap = <&dma_conf0>; + offset = <0x0>; + }; + + usrp_rx_dma1: usrp-rx-dma@43c10000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma1 0>; + dma-names = "dma"; + port-id = <1>; + + regmap = <&dma_conf0>; + offset = <0x4>; + }; + + usrp_rx_dma2: usrp-rx-dma@43c20000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma2 0>; + dma-names = "dma"; + port-id = <2>; + + regmap = <&dma_conf0>; + offset = <0x8>; + }; + + usrp_rx_dma3: usrp-rx-dma@43c30000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma3 0>; + dma-names = "dma"; + port-id = <3>; + + regmap = <&dma_conf0>; + offset = <0xc>; + }; + + usrp_rx_dma4: usrp-rx-dma@43c40000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma4 0>; + dma-names = "dma"; + port-id = <4>; + + regmap = <&dma_conf0>; + offset = <0x10>; + }; + + usrp_rx_dma5: usrp-rx-dma@43c50000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma5 0>; + dma-names = "dma"; + port-id = <5>; + + regmap = <&dma_conf0>; + offset = <0x14>; + }; + + usrp_tx_dma0: usrp-tx-dma@43ca0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma0 0>; + dma-names = "dma"; + port-id = <0>; + }; + + usrp_tx_dma1: usrp-tx-dma@43cb0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma1 0>; + dma-names = "dma"; + port-id = <1>; + }; + + usrp_tx_dma2: usrp-tx-dma@43cc0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma2 0>; + dma-names = "dma"; + port-id = <2>; + status = "okay"; + }; + + usrp_tx_dma3: usrp-tx-dma@43cd0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma3 0>; + dma-names = "dma"; + port-id = <3>; + }; + + usrp_tx_dma4: usrp-tx-dma@43ce0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma4 0>; + dma-names = "dma"; + port-id = <4>; + status = "okay"; + }; + + usrp_tx_dma5: usrp-tx-dma@43cf0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma5 0>; + dma-names = "dma"; + port-id = <5>; + }; + + dma_conf0: dma_conf0@42080000 { + compatible = "syscon"; + reg = <0x42080000 0x1000>; + status = "okay"; + }; +}; diff --git a/fpga/usrp3/top/e320/dts/e320-common.dtsi b/fpga/usrp3/top/e320/dts/e320-common.dtsi new file mode 100644 index 000000000..470596f33 --- /dev/null +++ b/fpga/usrp3/top/e320/dts/e320-common.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +&fpga_full { + uio@40010000 { + compatible = "usrp-uio"; + reg = <0x40010000 0x2000>; + reg-names = "mboard-regs"; + status = "okay"; + }; + + uio@40014000 { + compatible = "usrp-uio"; + reg = <0x40014000 0x4000>; + reg-names = "dboard-regs"; + status = "okay"; + }; +}; + +&spi0 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 62 0>; + + spidev0: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; + +&spi1 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 63 0>; + + spidev1: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; diff --git a/fpga/usrp3/top/e320/dts/e320-fpga.dtsi b/fpga/usrp3/top/e320/dts/e320-fpga.dtsi new file mode 100644 index 000000000..3f245d0a2 --- /dev/null +++ b/fpga/usrp3/top/e320/dts/e320-fpga.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +&fpga_full { + firmware-name = "e320.bin"; +}; diff --git a/fpga/usrp3/top/e320/dts/usrp_e320_fpga_1G.dts b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_1G.dts new file mode 100644 index 000000000..c1d76ae4f --- /dev/null +++ b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_1G.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "e320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + /* 114 = 54 (MIOs) + 60 (EMIO 60) */ + link-gpios = <&gpio0 114 0>; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; // FIXME: Addresses + reg-names = "misc-enet-regs"; + status = "okay"; + }; +}; + +#include "e320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/e320/dts/usrp_e320_fpga_AA.dts b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_AA.dts new file mode 100644 index 000000000..04f67d002 --- /dev/null +++ b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_AA.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "e320-fpga.dtsi" + +&fpga_full { + uio@40004000 { + compatible = "usrp-uio"; + reg = <0x40004000 0x1000>; //FIXME + reg-names = "misc-auro-regs"; + status = "okay"; + }; +}; + +#include "e320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/e320/dts/usrp_e320_fpga_XG.dts b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_XG.dts new file mode 100644 index 000000000..3c64cfbf7 --- /dev/null +++ b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_XG.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "e320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; //FIXME + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; //FIXME + reg-names = "misc-enet-regs"; + status = "okay"; + }; +}; + +#include "e320-common.dtsi" +#include "dma-common.dtsi" -- cgit v1.2.3