From e962cc4a5e51e2326eb656ee2a779ea26774687b Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Thu, 2 Jul 2020 13:50:23 -0500 Subject: fpga: rfnoc: Fix testbenches to run under ModelSim This updates the makefiles for the testbenches so they can be run using "make modelsim" without any additional hacks. The "xsim" and "vsim" simulation targets also still work. --- fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'fpga/usrp3/top/e31x') diff --git a/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile b/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile index bf4922c21..956c1f211 100644 --- a/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile +++ b/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile @@ -25,11 +25,12 @@ DESIGN_SRCS = $(abspath ../../e310_io.v) \ #------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module -SIM_TOP = e310_io_tb +# Define toplevel module +SIM_TOP = e310_io_tb glbl SIM_SRCS = \ -$(abspath e310_io_tb.sv) +$(abspath e310_io_tb.sv) \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ #------------------------------------------------- # Bottom-of-Makefile -- cgit v1.2.3