From 6f038dc2f69b38e715206b2e700fdd3a1bbc638e Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Thu, 9 Dec 2021 14:30:30 -0600
Subject: fpga: Use PROTOVER and CHDR_W from RFNoC image builder

This updates all RFNoC devices so that they get the RFNoC protocol
version and CHDR width in the same way, from the output generated by
the RFNoC image builder.
---
 fpga/usrp3/top/e31x/Makefile.e31x.inc |  3 ++-
 fpga/usrp3/top/e31x/e31x.v            | 20 +++++++++++++++++++-
 fpga/usrp3/top/e31x/e31x_core.v       |  7 ++++---
 3 files changed, 25 insertions(+), 5 deletions(-)

(limited to 'fpga/usrp3/top/e31x')

diff --git a/fpga/usrp3/top/e31x/Makefile.e31x.inc b/fpga/usrp3/top/e31x/Makefile.e31x.inc
index 4e017ca0c..871dd5318 100644
--- a/fpga/usrp3/top/e31x/Makefile.e31x.inc
+++ b/fpga/usrp3/top/e31x/Makefile.e31x.inc
@@ -107,13 +107,14 @@ $(RFNOC_BLOCK_EXAMPLE_SRCS) \
 $(abspath $(MB_XDC))
 
 EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
+IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
 
 ##################################################
 # Dependency Targets
 ##################################################
 .SECONDEXPANSION:
 
-VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF)
+VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
 
 # DESIGN_SRCS and VERILOG_DEFS must be defined
 bin: .prereqs $$(DESIGN_SRCS) ip
diff --git a/fpga/usrp3/top/e31x/e31x.v b/fpga/usrp3/top/e31x/e31x.v
index 57c1346ff..9ca3db62e 100644
--- a/fpga/usrp3/top/e31x/e31x.v
+++ b/fpga/usrp3/top/e31x/e31x.v
@@ -136,6 +136,22 @@ module e31x (
   inout [5:0]   PL_GPIO
 );
 
+  // Include the RFNoC image core header file
+  `ifdef RFNOC_IMAGE_CORE_HDR
+    `include `"`RFNOC_IMAGE_CORE_HDR`"
+  `else
+    ERROR_RFNOC_IMAGE_CORE_HDR_not_defined();
+    `define CHDR_WIDTH     64
+    `define RFNOC_PROTOVER { 8'd1, 8'd0 }
+  `endif
+  localparam CHDR_W         = `CHDR_WIDTH;
+  localparam RFNOC_PROTOVER = `RFNOC_PROTOVER;
+
+  // This USRP currently only supports 64-bit CHDR width
+  if (CHDR_W != 64) begin : gen_chdr_w_error
+    CHDR_W_must_be_64_for_this_USRP();
+  end
+
   // Constants
   localparam REG_AWIDTH = 14; // log2(0x4000)
   localparam REG_DWIDTH = 32;
@@ -846,7 +862,9 @@ module e31x (
     .NUM_DBOARDS(NUM_DBOARDS),
     .NUM_CHANNELS_PER_DBOARD(NUM_CHANNELS_PER_RADIO),
     .FP_GPIO_WIDTH(FP_GPIO_WIDTH),
-    .DB_GPIO_WIDTH(DB_GPIO_WIDTH)
+    .DB_GPIO_WIDTH(DB_GPIO_WIDTH),
+    .CHDR_W(CHDR_W),
+    .RFNOC_PROTOVER(RFNOC_PROTOVER)
   ) e31x_core_inst (
 
     //Clocks and resets
diff --git a/fpga/usrp3/top/e31x/e31x_core.v b/fpga/usrp3/top/e31x/e31x_core.v
index 99675262b..43bb59799 100644
--- a/fpga/usrp3/top/e31x/e31x_core.v
+++ b/fpga/usrp3/top/e31x/e31x_core.v
@@ -26,7 +26,7 @@ module e31x_core #(
   parameter NUM_CHANNELS_PER_DBOARD = 2,
   parameter FP_GPIO_WIDTH = 8,  // Front panel GPIO width
   parameter DB_GPIO_WIDTH = 16,  // Daughterboard GPIO width
-  parameter CHDR_WIDTH  = 16'd64 ,
+  parameter CHDR_W = 64,
   parameter RFNOC_PROTOVER  = {8'd1, 8'd0}
 )(
   // Clocks and resets
@@ -414,7 +414,7 @@ module e31x_core #(
             cp_glob_resp_data <= {16'd0, device_id};
 
           REG_RFNOC_INFO:
-            cp_glob_resp_data <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]};
+            cp_glob_resp_data <= {CHDR_W[15:0], RFNOC_PROTOVER[15:0]};
 
           REG_COMPAT_NUM:
             cp_glob_resp_data <= {COMPAT_MAJOR[15:0], COMPAT_MINOR[15:0]};
@@ -812,7 +812,8 @@ module e31x_core #(
   /////////////////////////////////////////////////////////////////////////////
 
   rfnoc_image_core #(
-    .PROTOVER(RFNOC_PROTOVER)
+    .CHDR_W   (CHDR_W),
+    .PROTOVER (RFNOC_PROTOVER)
   ) rfnoc_image_core_i (
     .chdr_aclk               (bus_clk    ),
     .ctrl_aclk               (clk40      ),
-- 
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