From 3f823004600472c7f4b173a0da83a3bd53968c40 Mon Sep 17 00:00:00 2001 From: RobertWalstab Date: Tue, 2 Jun 2020 16:37:56 +0200 Subject: e31x: Swap out liberio for internal Ethernet --- fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl | 426 +++++++++++++++++++---- 1 file changed, 355 insertions(+), 71 deletions(-) (limited to 'fpga/usrp3/top/e31x/ip/e31x_ps_bd') diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl index b6b3cb1e5..55ab5fad9 100644 --- a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl +++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl @@ -1,6 +1,60 @@ + +################################################################ +# This is a generated script based on design: e31x_ps_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2019.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source e31x_ps_bd_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7z020clg484-3 +} + + # CHANGE DESIGN NAME HERE +variable design_name set design_name e31x_ps_bd +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + # Creating design if needed set errMsg "" set nRet 0 @@ -8,25 +62,216 @@ set nRet 0 set cur_design [current_bd_design -quiet] set list_cells [get_bd_cells -quiet] -create_bd_design $design_name -current_bd_design $design_name +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - puts $errMsg + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} return $nRet } -set scriptDir [file dirname [info script]] +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:processing_system7:5.5\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:xlslice:1.0\ +xilinx.com:ip:axi_dma:7.1\ +xilinx.com:ip:axi_protocol_converter:2.1\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} ################################################################## # DESIGN PROCs ################################################################## -source "$scriptDir/chdr_dma_top.tcl" + + +# Hierarchical cell: dma +proc create_hier_cell_dma { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_dma() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_DMA_SG + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_dmac + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma + + + # Create pins + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O rx_irq + create_bd_pin -dir O tx_irq + + # Create instance: axi_dma_eth_internal, and set properties + set axi_dma_eth_internal [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_eth_internal ] + set_property -dict [ list \ + CONFIG.c_enable_multi_channel {0} \ + CONFIG.c_include_mm2s_dre {1} \ + CONFIG.c_include_s2mm_dre {1} \ + CONFIG.c_m_axi_mm2s_data_width {64} \ + CONFIG.c_m_axis_mm2s_tdata_width {64} \ + CONFIG.c_mm2s_burst_size {16} \ + CONFIG.c_num_mm2s_channels {1} \ + CONFIG.c_num_s2mm_channels {1} \ + CONFIG.c_s2mm_burst_size {16} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + ] $axi_dma_eth_internal + + # Create instance: axi_protocol_convert_rx, and set properties + set axi_protocol_convert_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_rx ] + set_property -dict [ list \ + CONFIG.TRANSLATION_MODE {0} \ + ] $axi_protocol_convert_rx + + # Create instance: axi_protocol_convert_tx, and set properties + set axi_protocol_convert_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_tx ] + set_property -dict [ list \ + CONFIG.TRANSLATION_MODE {0} \ + ] $axi_protocol_convert_tx + + # Create interface connections + connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins m_axis_dma] [get_bd_intf_pins axi_dma_eth_internal/M_AXIS_MM2S] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_eth_internal/M_AXI_MM2S] [get_bd_intf_pins axi_protocol_convert_tx/S_AXI] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_eth_internal/M_AXI_S2MM] [get_bd_intf_pins axi_protocol_convert_rx/S_AXI] + connect_bd_intf_net -intf_net axi_dma_eth_internal_M_AXI_SG [get_bd_intf_pins M_AXI_DMA_SG] [get_bd_intf_pins axi_dma_eth_internal/M_AXI_SG] + connect_bd_intf_net -intf_net axi_protocol_convert_0_M_AXI [get_bd_intf_pins M_AXI_TX_DMA] [get_bd_intf_pins axi_protocol_convert_tx/M_AXI] + connect_bd_intf_net -intf_net axi_protocol_convert_1_M_AXI [get_bd_intf_pins M_AXI_RX_DMA] [get_bd_intf_pins axi_protocol_convert_rx/M_AXI] + connect_bd_intf_net -intf_net s_axi_dmac_1 [get_bd_intf_pins s_axi_dmac] [get_bd_intf_pins axi_dma_eth_internal/S_AXI_LITE] + connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_pins s_axis_dma] [get_bd_intf_pins axi_dma_eth_internal/S_AXIS_S2MM] + + # Create port connections + connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins tx_irq] [get_bd_pins axi_dma_eth_internal/mm2s_introut] + connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins rx_irq] [get_bd_pins axi_dma_eth_internal/s2mm_introut] + connect_bd_net -net axi_dma_0_s2mm_prmry_reset_out_n [get_bd_pins axi_dma_eth_internal/s2mm_prmry_reset_out_n] [get_bd_pins axi_protocol_convert_rx/aresetn] + connect_bd_net -net axi_dma_eth_internal_mm2s_prmry_reset_out_n [get_bd_pins axi_dma_eth_internal/mm2s_prmry_reset_out_n] [get_bd_pins axi_protocol_convert_tx/aresetn] + connect_bd_net -net bus_clk_1 [get_bd_pins bus_clk] [get_bd_pins axi_dma_eth_internal/m_axi_mm2s_aclk] [get_bd_pins axi_dma_eth_internal/m_axi_s2mm_aclk] [get_bd_pins axi_dma_eth_internal/m_axi_sg_aclk] [get_bd_pins axi_protocol_convert_rx/aclk] [get_bd_pins axi_protocol_convert_tx/aclk] + connect_bd_net -net clk40_1 [get_bd_pins clk40] [get_bd_pins axi_dma_eth_internal/s_axi_lite_aclk] + connect_bd_net -net clk40_rstn_1 [get_bd_pins clk40_rstn] [get_bd_pins axi_dma_eth_internal/axi_resetn] + + # Restore current instance + current_bd_instance $oldCurInst +} + # Procedure to create entire design; Provide argument to make # procedure reusable. If parentCell is "", will use root. proc create_root_design { parentCell } { + variable script_folder + variable design_name + if { $parentCell eq "" } { set parentCell [get_bd_cells /] } @@ -34,14 +279,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - puts "ERROR: Unable to find parent cell <$parentCell>!" + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -54,14 +299,27 @@ proc create_root_design { parentCell } { # Create interface ports set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0 ] - set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ] - set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ] + + set USBIND_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:usbctrl_rtl:1.0 USBIND_0 ] + + set m_axi_eth_internal [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_internal ] set_property -dict [ list \ - CONFIG.HAS_TLAST 1 \ - CONFIG.TDATA_NUM_BYTES 8 \ - CONFIG.TDEST_WIDTH 4 \ - ] $s_axis_dma + CONFIG.ADDR_WIDTH {31} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_eth_internal + set m_axi_pmu [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_pmu ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {32} \ @@ -77,6 +335,7 @@ proc create_root_design { parentCell } { CONFIG.NUM_WRITE_OUTSTANDING {2} \ CONFIG.PROTOCOL {AXI4LITE} \ ] $m_axi_pmu + set m_axi_xbar [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_xbar ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {32} \ @@ -92,7 +351,26 @@ proc create_root_design { parentCell } { CONFIG.NUM_WRITE_OUTSTANDING {2} \ CONFIG.PROTOCOL {AXI4LITE} \ ] $m_axi_xbar - set USBIND_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:usbctrl_rtl:1.0 USBIND_0 ] + + set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + ] $m_axis_dma + + set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {8} \ + CONFIG.TDEST_WIDTH {4} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $s_axis_dma + # Create ports set DDR_VRN [ create_bd_port -dir IO DDR_VRN ] @@ -154,7 +432,7 @@ proc create_root_design { parentCell } { set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ] set clk40 [ create_bd_port -dir I -type clk clk40 ] set_property -dict [ list \ - CONFIG.ASSOCIATED_BUSIF {m_axi_xbar:m_axi_pmu} \ + CONFIG.ASSOCIATED_BUSIF {m_axi_pmu:m_axi_xbar:m_axi_eth_internal} \ CONFIG.ASSOCIATED_RESET {clk40_rstn} \ CONFIG.FREQ_HZ {40000000} \ ] $clk40 @@ -164,16 +442,16 @@ proc create_root_design { parentCell } { set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] set_property -dict [ list \ CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ - CONFIG.NUM_MI {5} \ + CONFIG.NUM_MI {4} \ ] $axi_interconnect_0 # Create instance: dma - create_hier_cell_dma [current_bd_instance .] dma 5 + create_hier_cell_dma [current_bd_instance .] dma # Create instance: processing_system7_0, and set properties set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] set_property -dict [ list \ - CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {866.666687} \ CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ @@ -188,23 +466,23 @@ proc create_root_design { parentCell } { CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \ CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ - CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ - CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ - CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ - CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ - CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ - CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {144.444443} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {144.444443} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {144.444443} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {144.444443} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {144.444443} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {144.444443} \ CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ - CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {144.444443} \ CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {1000} \ - CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {52} \ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ CONFIG.PCW_CLK0_FREQ {100000000} \ CONFIG.PCW_CLK1_FREQ {40000000} \ CONFIG.PCW_CLK2_FREQ {166666672} \ CONFIG.PCW_CLK3_FREQ {200000000} \ - CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1733.333} \ CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ @@ -216,7 +494,7 @@ proc create_root_design { parentCell } { CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ - CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {16} \ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ @@ -252,13 +530,13 @@ proc create_root_design { parentCell } { CONFIG.PCW_EN_UART1 {1} \ CONFIG.PCW_EN_USB0 {1} \ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ - CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ - CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {10} \ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \ - CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {3} \ - CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {2} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {4} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {3} \ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {5} \ - CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {2} \ CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \ CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \ @@ -284,11 +562,11 @@ proc create_root_design { parentCell } { CONFIG.PCW_I2C1_I2C1_IO {} \ - CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \ - CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ + CONFIG.PCW_IOPLL_CTRL_FBDIV {60} \ + CONFIG.PCW_IO_IO_PLL_FREQMHZ {2000.000} \ CONFIG.PCW_IRQ_F2P_INTR {1} \ CONFIG.PCW_MIO_0_DIRECTION {inout} \ CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 1.8V} \ @@ -508,7 +786,7 @@ proc create_root_design { parentCell } { CONFIG.PCW_MIO_9_SLEW {slow} \ CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#USB Reset#GPIO#ENET Reset#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#I2C 0#I2C 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \ CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#gpio[8]#reset#gpio[10]#reset#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#scl#sda#tx#rx#gpio[50]#gpio[51]#mdc#mdio} \ - CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {10} \ CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_PJTAG_PJTAG_IO {